TWI434380B - 內層散熱板結構暨具內層散熱之多晶片堆疊封裝結構及其製法 - Google Patents

內層散熱板結構暨具內層散熱之多晶片堆疊封裝結構及其製法 Download PDF

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TWI434380B
TWI434380B TW100106829A TW100106829A TWI434380B TW I434380 B TWI434380 B TW I434380B TW 100106829 A TW100106829 A TW 100106829A TW 100106829 A TW100106829 A TW 100106829A TW I434380 B TWI434380 B TW I434380B
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Prior art keywords
wafer
heat dissipation
package structure
dissipation plate
metal plate
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TW100106829A
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English (en)
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TW201238015A (en
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黃惠暖
黃品誠
盧俊宏
趙俊杰
邱啟新
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矽品精密工業股份有限公司
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Priority to TW100106829A priority Critical patent/TWI434380B/zh
Priority to US13/112,253 priority patent/US8520391B2/en
Publication of TW201238015A publication Critical patent/TW201238015A/zh
Priority to US13/964,488 priority patent/US20130326873A1/en
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Publication of TWI434380B publication Critical patent/TWI434380B/zh

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
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Description

內層散熱板結構暨具內層散熱之多晶片堆疊封裝結構及其製法
本發明係有關於一種內層散熱板結構暨具該內層散熱板之多晶片堆疊封裝結構及其製法，尤指一種在堆疊結構內層提供散熱途徑及增加整體結構剛性之多晶片堆疊封裝結構及其製法。
按，隨著科技的快速發展，各種新的產品不斷推陳出新，為了滿足消費著方便使用及攜帶容易之需求，現今各式電子產品無不朝向輕、薄、短、小發展。
而現今之電子產品除了要有輕、薄、短、小之特性外，亦希望電子產品能兼具高效能、低耗電、多功能等產品特性，故業界遂發展出於一電路板或封裝基板上接置複數半導體晶片，藉以增加電性功能，惟在單一電路板或封裝基板上接置複數半導體晶片，則因該封裝基板之使用面積有限，而限制接置半導體晶片之數量，且以平面接置半導體晶片之封裝結構無法有效縮小體積，難以達到薄小之目的；因而嗣後發展出將半導體晶片堆疊整合之封裝結構，其目前研究方向為將複數半導體晶片予以堆疊，而該經堆疊之半導體晶片之封裝結構則因傳輸路徑短，且經立體堆疊，故具有高效能、低耗電、多功能等特性，此外，相較傳統單一半導體晶片逐一接置於封裝基板上，是種半導體晶片之堆疊結構亦可大幅減少封裝基板之使用面積。
請參閱第1圖，係為習知多晶片堆疊封裝結構；如圖所示，係於一封裝基板10上以錫球110電性連接第一半導體晶片11，且該第一半導體晶片11上疊置有第二半導體晶片12，又於該第二半導體晶片12上疊置一第三半導體晶片13，而該第二半導體晶片12及第三半導體晶片13係以打線方式之銲線14電性連接至該封裝基板10。
惟，該習知多晶片堆疊封裝結構為配合打線之電性連接方式，位於上方之第二半導體晶片12必須小於下方之第一半導體晶片11，且該第三半導體晶片13又必須小於下方之第二半導體晶片12，方能提供是種多晶片堆疊結構，並打線電性連接，但也限制了晶片之堆疊數量，導致電性功能有限，亦無法有效提昇電性傳輸效能。且以打線方式進行半導體晶片與封裝基板10之電性連接，其銲線具有一線弧高度，故無法有效縮小多晶片堆疊封裝結構體積。
為解決前述習知技術缺失，且進一步提昇之電性功能及傳輸效能，且因應電子產品功能整合的趨勢，半導體界遂開發出將能垂直電性垂直連接之具矽穿孔(Through-Silicon Via,TSV)的多晶片堆疊技術(其中該些矽穿孔中填充有導電材料)，以俾將複數晶片進行多晶片垂直堆疊結構，以並結合該堆疊結構於同一封裝基板上，以構成一半導體封裝結構。該半導體封裝結構不僅具有高電性功能，亦可大幅提升電性傳輸效能，而能符合高階終端電子產品之使用需求。
請參閱第2A圖，係為習知具矽穿孔之多晶片堆疊封裝結構，如圖所示，係於一封裝基板20上以錫球210電性連接經堆疊之複數TSV晶片21，且於該最頂層之TSV晶片21上接置一般之半導體晶片22。
惟，該些堆疊之TSV晶片21，因該些TSV晶片21作動頻率高，且位處中間位置之TSV晶片21，由於複數晶片堆疊後彼此的間隙狹小，故會發生熱逸散困難、散熱效率不佳等問題，輕則發生該些TSV晶片21降頻運作，重則會導致該些TSV晶片21燒毀，使得終端電子產品損毀。
請參閱第2B圖，而為解決位處中間位置之TSV晶片21散熱不易的問題，係於最頂層之半導體晶片22裸露於外界環境之表面上黏貼一金屬散熱片23，以將位於中間位置之TSV晶片21所產生之熱經由堆疊TSV晶片21間之錫球210及矽穿孔中之導電材，逐一傳導至頂層的金屬散熱片23。
然而，該位處中間位置之TSV晶片21須經長距之傳導路徑始能將熱傳導至金屬散熱片23，因而散熱效率不佳；其次接置於最頂層之半導體晶片22上之金屬散熱片23的面積不可超過該半導體晶片22之面積過多，否則易有黏接及應力方面等問題，容易導致該半導體晶片22碎裂。
因此，鑒於上述之問題，如何提供一種能使用於多晶片堆疊封裝結構中，具製作成本低廉、製作方式簡單、能大幅提升散熱效率、且可增加多晶片堆疊封裝結構之整體剛性，實已成為目前亟欲解決之課題。
鑑於上述習知技術之種種缺失，本發明揭露一種內層散熱板結構，係包括：金屬板體及複數貫穿該金屬板體之導電通孔，各該導電通孔係包括具有複數奈米孔洞之氧化塊及填入該奈米孔洞中之奈米線。
所述之形成該金屬板體之材料係為鋁；形成該氧化塊之材料係為氧化鋁。
該內層散熱板結構復可包括第一凸塊，係設於該導電通孔之端面上。
該內層散熱板結構之各該奈米線之寬度係小於或等於100奈米，或者各該奈米線之深寬比大於1000。其中，該奈米線之材質為銅、鎳、鉑或金。
本發明復提供一種多晶片堆疊封裝結構，係包括：具有相對之第一表面及第二表面之本發明內層散熱板；接置於該內層散熱板之第一表面上之第一晶片；以及接置於該內層散熱板之第二表面上之電子元件。
所述之電子元件可為電路板或第二晶片。
所述之第一晶片及電子元件分別具有複數接置其上之第二凸塊，以藉由各該第二凸塊對應電性連接至該內層散熱板之導電通孔端面的各該第一凸塊。
又，該多晶片堆疊封裝結構中，該電子元件為第二晶片，且該第二晶片係以其頂面接置於該內層散熱板上，又該多晶片堆疊封裝結構復包括一電路板，係接置在該第二晶片底面下。
所述之多晶片堆疊封裝結構復可包括底膠材料，係形成於該內層散熱板與第一晶片之間、該內層散熱板與第二晶片之間以及該電路板與第二晶片之間，且包覆該第一凸塊及第二凸塊。
該多晶片堆疊封裝結構之各該奈米線之寬度係小於或等於100奈米，或者各該奈米線之深寬比大於1000。其中，該奈米線之材質為銅、鎳、鉑或金。
本發明復提供一種多晶片堆疊封裝結構之製法，係包括：提供一具有相對之第一表面及第二表面之內層散熱板，其中，該內層散熱板包括金屬板體、及複數貫穿該金屬板體之導電通孔，且該導電通孔係包括形成有複數奈米孔洞之氧化塊及填入該奈米孔洞中之奈米線；以及於該內層散熱板之第一表面及第二表面上分別接置第一晶片及電子元件，並電性連接該第一晶片及電子元件至該導電通孔。
依上所述，該導電通孔之製法，係包括：於該金屬板體之一表面上形成具有複數開孔之阻層，以令部份之金屬板體外露於該開孔中；對該外露於開孔中之金屬板體進行氧化處理，使該金屬板體對應該開孔之部位的金屬氧化而形成為氧化塊；進行圖案化製程以蝕刻該氧化塊，以於該氧化塊中形成複數奈米孔洞；於該奈米孔洞中形成奈米線；以及使該氧化塊及奈米線皆露出該金屬板體，以形成導電通孔。
前述之製法中，復可包括於使該氧化塊及奈米線皆露出該金屬板體之前或之後，移除該阻層。再者，本發明係以研磨或蝕刻該未具有阻層之另一金屬板體表面，以露出該氧化塊及奈米線。此外，復包括形成複數第一凸塊，例如，於露出該氧化塊及奈米線後，再於各該導電通孔的端面上形成第一凸塊。
在前述之多晶片堆疊封裝結構中，所述之第一晶片及電子元件分別復包括複數接置其上之第二凸塊，以藉由各該第二凸塊對應電性連接至該內層散熱板之導電通孔端面的各該第一凸塊。
是以，本發明多晶片堆疊封裝結構之製法中，該第一晶片及電子元件分別以複數第二凸塊對應電性連接至該內層散熱板之導電通孔端面的各該第一凸塊。
所述之電子元件可為第二晶片，且該第二晶片係以其頂面接置於該內層散熱板上，且該多晶片堆疊封裝結構及其製法復可包括將一電路板接置在該第二晶片底面下。
所述之多晶片堆疊封裝結構之製法復可包括形成底膠材料於該內層散熱板與第一晶片之間、該內層散熱板與第二晶片之間以及該電路板與第二晶片之間，且包覆該第一凸塊及第二凸塊。
於本發明之另一實施態樣中，復包括將該電子元件以其底面疊接於另一內層散熱板上，且同樣地，該內層散熱板底面復可疊接有另一電子元件，例如，第三晶片，而該第三另一晶片底面亦可接置於電路板上。
由上可知，本發明之多晶片堆疊封裝結構及其製法，係提供一具有相對之兩表面及複數貫穿該兩表面之導電通孔的內層散熱板，且於該導電通孔中佈設有複述奈米線。於該內層散熱板之兩表面上分別接置至少一晶片，且各該晶片電性連接至該導電通孔，俾於該些堆疊之晶片中夾設該內層散熱板，以藉由該內層散熱板提供位處中間位置之晶片的快速散熱途徑，以免除夾設於中間層之晶片逐層傳熱，導致散熱不佳之缺失；此外，本發明係以具有氧化塊之金屬板體作為散熱板，亦可提供該多晶片堆疊封裝結構之整體剛性提升，以避免習知多晶片堆疊封裝結構之半導體晶片裂損可能性。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“頂面”、“底面”“一”、“上”及“下”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
為得到本發明之多晶片堆疊封裝結構，請參閱第3A至3G圖，係揭露本發明之內層散熱板結構之製法。
如第3A圖所示，首先，提供一例如為鋁之金屬板體30。
如第3B圖所示，於該金屬板體30之一表面上形成阻層31，且該阻層31經圖案化製程以形成複數開孔310，以令部份之金屬板體30外露於該開孔310中。
如第3C圖所示，之後，對該開孔310中之金屬板體30進行陽極氧化處理，使該金屬板體30對應該開孔310之部位的金屬氧化而形成為氧化塊301，且該氧化塊301可穿透或如本實施例之未穿透該金屬板體30，而該氧化塊301之材質為氧化鋁。
如第3D及3D-1圖所示，以乾式或濕式蝕刻的方式蝕刻該氧化塊301，以於該氧化塊301中形成複數奈米孔洞301a。
如第3E及3E-1圖所示，於該奈米孔洞301a中以例如電鍍或化學沉積方式形成奈米線301b。前述之奈米線301b於物理學界中可以被定義為一種具有在橫向尺寸上被限制在100奈米以下(縱向尺寸沒有限制)，例如，各該奈米線之寬度W係小於或等於100奈米，或是深寬(H/W)比大於1000的結構，該奈米線係為金屬材質，例如銅、鎳、鉑或金。
如第3F及3F-1圖所示，使該氧化塊301及奈米線301b兩端面皆露出該金屬板體30，以形成導電通孔32。具體而言，形成該導電通孔32之方式主要可透過研磨或蝕刻該與形成該阻層31表面相對之金屬板體30表面，亦即移除該金屬板體30未形成該阻層31之表面，以露出該氧化塊301及奈米線301b而形成導電通孔32。此外，本實施例之製法復包括於露出該氧化塊301及奈米線301b之前，移除該阻層31，舉例而言，如第3E圖所示，係於使該氧化塊301及奈米線301b兩端面皆露出該金屬板體30之步驟前，移除該阻層31；或者於研磨或蝕刻金屬板體30表面之後，再移除該阻層31。
如第3G圖所示，於各該導電通孔32的端面上形成係如銲錫之第一凸塊33a，俾使各該導電通孔32之兩端面上具有第一凸塊33a。該第一凸塊33a亦可為於導電通孔32之兩端面上先形成銅柱後，再於銅柱頂面形成銲錫(圖未示)。
根據前述之製法，本發明提供一種內層散熱板結構，係包括：材料例如為鋁之金屬板體30；複數導電通孔32，係貫穿該金屬板體30上下表面，而該導電通孔32包括具有複數奈米孔洞301a之氧化塊301及填入該奈米孔洞301a中之之奈米線301b。
以上所述，該內層散熱板結構復可包括分別設於該些導電通孔32之端面上之複數第一凸塊33a。
請參閱第3H至3I圖，係為具有本發明內層散熱板3之多晶片堆疊封裝結構及其製法示意圖。
如第3H圖所示，於該內層散熱板3之第一表面3a及第二表面3b上分別接置第一晶片34a及如第二晶片34b之電子元件。該電子元件不限為第二晶片，其亦可為電路板。又，該第一及第二晶片34a,34b可為具有TSV設計之晶片，或上下表面皆設有線路之晶片，且各自電性連接至該導電通孔32。具體而言，該第一晶片34a及第二晶片34b皆以接置導電元件方式，例如透過係為錫球之第二凸塊33b電性連接該內層散熱板3之導電通孔32端面的第一凸塊33a。此外，該導電元件可包括金屬柱及形成於該金屬柱上且材質例如為錫球之金屬凸塊，舉例而言，如第二晶片34b底面電極墊331上之金屬柱33d及形成於該金屬柱33d上之第三凸塊33c。當然，是種導電元件的結構亦可應用於其他晶片或內層散熱板。通常，接置在內層散熱板3之第一表面3a及第二表面3b上的晶片之兩晶片表面上具有相對應之電極墊331，例如，該第一晶片34a之底面具有電極墊331，以電性連接該內層散熱板3之導電通孔32；該第二晶片34b之頂面具有電極墊331，以電性連接該內層散熱板3之導電通孔32，至於該第二晶片34b底面的電極墊331則可再接置並電性連接其他內層散熱板或電子元件，例如電路板或晶片等。而該內層散熱板3則可於多晶片堆疊結構內層提供快速散熱途徑，以避免夾設於中間層之晶片逐層傳熱，導致散熱不佳之缺失；此外，本發明係以具有氧化塊之金屬板體作為內層散熱板，亦可提供該多晶片堆疊封裝結構之整體結構剛性提升，以避免多晶片堆疊封裝結構之壓損可能性。
此外，復可包括形成底膠材料36於該內層散熱板3與第一晶片34a之間和該內層散熱板3與第二晶片34b之間，且包覆該第一凸塊33a及第二凸塊33b。
復參閱第3I及3I’圖，係舉例說明本發明多晶片堆疊封裝結構之延伸堆疊態樣，但不以此為限。例如，如第二晶片34b之電子元件係以其頂面接置於該內層散熱板3上，且該第二晶片34b係以其底面透過例如為錫球之第三凸塊33c堆疊接置於一電路板35上，如第3I圖所示；或該第二晶片34b係以其底面疊接於另一內層散熱板3’上，且該內層散熱板3’底面疊接有另一電子元件，如第三晶片34b’，而該第三晶片34b’底面透過例如為錫球之第三凸塊33c接置於電路板35上，如第3I’圖所示；其中，該電路板35可為主機板或封裝基板。
此外，復可包括形成底膠材料36於該電路板35與第二晶片34b之間，或電路板35與第三晶片34b’之間；或內層散熱板3’與第三晶片34b’及第二晶片34b之間，且其材質可與該內層散熱板3與第一晶片34a之間和該內層散熱板3與第二晶片34b之間的底膠材料36相同或不相同。
根據前述之製法，本發明復提供一種具內層散熱之多晶片堆疊封裝結構，係包括：內層散熱板3，係具有相對相對之第一表面3a及第二表面3b，且該內層散熱板3包括金屬板體30及貫穿該金屬板體30之複數導電通孔32，各該導電通孔32包括形成有複數奈米孔洞301a之氧化塊301，以及填入該奈米孔洞301a中之奈米線301b；第一晶片34a，係接置於該內層散熱板3之第一表面3a上；以及如第二晶片34b之電子元件，係接置於該內層散熱板3之第二表面3b上，並電性連接該第一晶片34a及第二晶片34b至該導電通孔。
所述之內層散熱板3之材料係例如鋁之金屬板體30；該氧化塊301之材料係例如氧化鋁。
此外，該內層散熱板3復包括第一凸塊33a，係設於該導電通孔32之端面上。該第一晶片34a及第二晶片34b分別具有複數接置其上之第二凸塊33b，以藉由各該第二凸塊33b對應電性連接至該內層散熱板3之導電通孔32端面的各該第一凸塊33a。此外，如第二晶片34b之電子元件係以其頂面接置於該內層散熱板3上，且該多晶片堆疊封裝結構復可包括一電路板35，係接置在該第二晶片34b底面下。
所述之多晶片堆疊封裝結構，復包括底膠材料36，係形成於該內層散熱板3與第一晶片34a之間、該內層散熱板3與第二晶片34b之間以及該電路板35與第二晶片34b之間，且包覆該第一凸塊33a及第二凸塊33b。
或者，如第二晶片34b之電子元件係以其頂面接置於該內層散熱板3上，又該第二晶片34b係可以其底面疊接於另一內層散熱板3’上，且該內層散熱板3’底面復可疊接有另一電子元件，如第三晶片34b’，而該第三晶片34b’底面透係如錫球之第三凸塊33c接置於電路板35上，其中，該電路板35可為主機板或封裝基板。
本發明之內層散熱板結構暨具內層散熱之多晶片堆疊封裝結構及其製法，係提供一具有相對之兩表面及複數導電通孔的內層散熱板，且於該導電通孔中佈設有複述奈米線。於該內層散熱板之兩表面上分別接置至少一晶片，且各該晶片電性連接至該導電通孔，俾於該些堆疊之晶片中夾設該內層散熱板，以藉由該內層散熱板提供位處中間位置之晶片的快速散熱途徑，以免除夾設於中間層之晶片逐層傳熱，導致散熱不佳之缺失；此外，本發明係以具有氧化塊之金屬板體作為散熱板，亦可提供該多晶片堆疊封裝結構之整體剛性提升，以避免多晶片堆疊封裝結構之半導體晶片裂損可能性。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
10．．．封裝基板
110．．．錫球
11．．．第一半導體晶片
12．．．第二半導體晶片
13．．．第三半導體晶片
14．．．銲線
20．．．封裝基板
21．．．TSV晶片
210．．．錫球
22．．．半導體晶片
23．．．金屬散熱片
3、3’．．．內層散熱板
3a．．．第一表面
3b．．．第二表面
30．．．金屬板體
300．．．穿孔
301．．．氧化塊
301a．．．奈米孔洞
301b．．．奈米線
31．．．阻層
310．．．開孔
32．．．導電通孔
331．．．電極墊
33a．．．第一凸塊
33b．．．第二凸塊
33c．．．第三凸塊
33d．．．金屬柱
34a．．．第一晶片
34b．．．第二晶片
34b’．．．第三晶片
35．．．電路板
36．．．底膠材料
第1圖係為習知半導體晶片之堆疊封裝結構的剖視示意圖；
第2A及2B圖係為習知堆疊穿孔晶片之封裝結構的剖視示意圖；其中，該第2B圖係為第2A圖之另一實施態樣；以及
第3A至3I圖係為本發明內層散熱板結構及具內層散熱之多晶片堆疊封裝結構的製法剖視示意圖；其中，第3D-1、3E-1及3F-1分別為第3D、3E及3F圖之局部放大圖；第3I’圖係為第3I圖之另一實施態樣。
3a．．．第一表面
3b．．．第二表面
32．．．導電通孔
33c．．．第三凸塊
34a．．．第一晶片
34b．．．第二晶片
35．．．電路板
36．．．底膠材料

Claims (26)

  1. 一種內層散熱板結構，係包括：金屬板體；以及複數導電通孔，係貫穿該金屬板體，各該導電通孔係包括具有複數奈米孔洞之氧化塊及填入該奈米孔洞中之奈米線。
  2. 如申請專利範圍第1項所述之內層散熱板結構，其中，形成該金屬板體之材料係為鋁，形成該氧化塊之材料係為氧化鋁。
  3. 如申請專利範圍第1項所述之內層散熱板結構，復包括複數第一凸塊，係分別設於該導電通孔之端面上。
  4. 如申請專利範圍第1項所述之內層散熱板結構，其中，各該奈米線之寬度係小於或等於100奈米，或者各該奈米線之深寬比大於1000。
  5. 如申請專利範圍第1項所述之內層散熱板結構，其中，該奈米線之材質為銅、鎳、鉑或金。
  6. 一種多晶片堆疊封裝結構，係包括：內層散熱板，係具有相對之第一表面及第二表面，且係包括金屬板體及貫穿該金屬板體之複數導電通孔，各該導電通孔包括具有複數奈米孔洞之氧化塊及填入該奈米孔洞中之奈米線；第一晶片，係接置於該內層散熱板之第一表面上；以及電子元件，係接置於該內層散熱板之第二表面上。
  7. 如申請專利範圍第6項所述之多晶片堆疊封裝結構，其中，形成該金屬板體之材料係為鋁，形成該氧化塊之材料係為氧化鋁。
  8. 如申請專利範圍第6項所述之多晶片堆疊封裝結構，其中，該內層散熱板復包括第一凸塊，係設於該導電通孔之端面上。
  9. 如申請專利範圍第8項所述之多晶片堆疊封裝結構，其中，該第一晶片及電子元件分別具有複數接置其上之第二凸塊，以藉由各該第二凸塊對應電性連接至該內層散熱板之導電通孔端面的各該第一凸塊。
  10. 如申請專利範圍第6項所述之多晶片堆疊封裝結構，其中，該電子元件為電路板或第二晶片。
  11. 如申請專利範圍第10項所述之多晶片堆疊封裝結構，其中，該電子元件為第二晶片，且該第二晶片係以其頂面接置於該內層散熱板上，且該多晶片堆疊封裝結構復包括一電路板，係接置在該第二晶片底面下。
  12. 如申請專利範圍第11項所述之多晶片堆疊封裝結構，復包括底膠材料，係形成於該內層散熱板與第一晶片之間、該內層散熱板與第二晶片之間以及該電路板與第二晶片之間。
  13. 如申請專利範圍第6項所述之多晶片堆疊封裝結構，復包括另一內層散熱板，係疊接在該電子元件之底面下。
  14. 如申請專利範圍第6項所述之多晶片堆疊封裝結構，其中，各該奈米線之寬度係小於或等於100奈米，或者各 該奈米線之深寬比大於1000。
  15. 如申請專利範圍第6項所述之多晶片堆疊封裝結構，其中，該奈米線之材質為銅、鎳、鉑或金。
  16. 一種多晶片堆疊封裝結構之製法，係包括：提供一具有相對之第一表面及第二表面之內層散熱板，其中，該內層散熱板包括金屬板體、及複數貫穿該金屬板體之導電通孔，且該導電通孔係包括形成有複數奈米孔洞之氧化塊及填入該奈米孔洞中之奈米線；以及於該內層散熱板之第一表面及第二表面上分別接置第一晶片及電子元件，並電性連接該第一晶片及電子元件至該導電通孔。
  17. 如申請專利範圍第16項所述之多晶片堆疊封裝結構之製法，其中，形成該金屬板體之材料係為鋁，形成該氧化塊之材料係為氧化鋁。
  18. 如申請專利範圍第16項所述之多晶片堆疊封裝結構之製法，其中，該導電通孔之製法，係包括：於該金屬板體之一表面上形成具有複數開孔之阻層，以令部份之金屬板體外露於該開孔中；對該外露於開孔中之金屬板體進行氧化處理，使該金屬板體對應該開孔之部位的金屬氧化而形成為氧化塊；進行圖案化製程以蝕刻該氧化塊，以於該氧化塊中形成複數奈米孔洞； 於該奈米孔洞中形成奈米線；以及使該氧化塊及奈米線皆露出該金屬板體，以形成導電通孔。
  19. 如申請專利範圍第18項所述之多晶片堆疊封裝結構之製法，復包括於使該氧化塊及奈米線皆露出該金屬板體之前或之後，移除該阻層。
  20. 如申請專利範圍第18項所述之多晶片堆疊封裝結構之製法，其中，使該氧化塊及奈米線露出該金屬板體之步驟係以研磨或蝕刻該未具有阻層之另一金屬板體表面，以露出該氧化塊及奈米線。
  21. 如申請專利範圍第18項所述之多晶片堆疊封裝結構之製法，復包括於各該導電通孔的端面上形成第一凸塊。
  22. 如申請專利範圍第20項所述之多晶片堆疊封裝結構之製法，其中，該第一晶片及電子元件分別以複數第二凸塊對應電性連接至該內層散熱板之導電通孔端面的各該第一凸塊。
  23. 如申請專利範圍第16項所述之多晶片堆疊封裝結構之製法，其中，該電子元件為電路板或第二晶片。
  24. 如申請專利範圍第23項所述之多晶片堆疊封裝結構之製法，其中，該電子元件為第二晶片，且該第二晶片係以其頂面接置於該內層散熱板上，且復包括將一電路板接置在該第二晶片底面下。
  25. 如申請專利範圍第24項所述之多晶片堆疊封裝結構之製法，復包括形成底膠材料於該內層散熱板與第一晶片 之間、該內層散熱板與第二晶片之間以及該電路板與第二晶片之間。
  26. 如申請專利範圍第16項所述之多晶片堆疊封裝結構之製法，復包括將該電子元件以其底面疊接於另一內層散熱板上。
TW100106829A 2011-03-02 2011-03-02 內層散熱板結構暨具內層散熱之多晶片堆疊封裝結構及其製法 TWI434380B (zh)

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