TWI433095B

TWI433095B - Dual resolution display apparatus and driving method applicalbe thereto

Info

Publication number: TWI433095B
Application number: TW100102169A
Authority: TW
Inventors: Yi Cheng Tsai
Original assignee: Innolux Corp
Priority date: 2011-01-20
Filing date: 2011-01-20
Publication date: 2014-04-01
Also published as: TW201232501A

Description

支援雙解析度顯示之顯示裝置與其驅動方法 Display device supporting dual resolution display and driving method thereof

本發明是有關於一種移位暫存器電路，且特別是有關於一種能支援雙解析度顯示的GOP(gate on panel，閘極面極)顯示系統。 The present invention relates to a shift register circuit, and more particularly to a GOP (gate on panel) display system capable of supporting dual resolution display.

液晶顯示面板具有重量輕、壽命長及高畫質等優點，使得液晶顯示面板廣泛的應用於各式電子裝置中。例如行動電話、電視、電腦螢幕等。傳統上，將閘極驅動電路形成於外部硬式印刷電路板上。 The liquid crystal display panel has the advantages of light weight, long life and high image quality, and the liquid crystal display panel is widely used in various electronic devices. For example, mobile phones, televisions, computer screens, etc. Conventionally, a gate drive circuit is formed on an external hard printed circuit board.

為可簡化外部閘極驅動積體電路複雜性及減少體積，降低面板生產成本，本發明實施例利用薄膜電晶體陣列製程將驅動掃描線的部份閘極驅動電路一併形成於液晶顯示面板之基板上，此技術稱為GOP(Gate on Panel)。 In order to simplify the complexity of the external gate driving integrated circuit and reduce the volume and reduce the panel production cost, the embodiment of the present invention uses a thin film transistor array process to form a part of the gate driving circuit for driving the scan line to be formed on the liquid crystal display panel. On the substrate, this technique is called GOP (Gate on Panel).

顯示模組利用時序控制器及驅動電路，即可達成雙解析度(包括正常解析度與低解析度)可切換的效果，可提升顯示設計上的彈性，以及減低成本。以有PMOS及NMOS邏輯電路之薄膜電晶體陣列製程而言，其設計是較容易達成的，但成本較a-Si的GOP製程高。然而，以目前a-Si的GOP技術而言，尚無以單一驅動電路同時支援雙解析度顯示的設計。 The display module can realize the double-resolution (including normal resolution and low resolution) switchable effect by using the timing controller and the driving circuit, thereby improving the flexibility of the display design and reducing the cost. In the case of a thin film transistor array process with PMOS and NMOS logic circuits, the design is relatively easy to achieve, but the cost is higher than that of the a-Si GOP process. However, with the current a-Si GOP technology, there is no design that supports a dual resolution display with a single drive circuit.

本發明係有關於一種支援雙解析度顯示之顯示裝置與其驅動方法。於低解析度顯示時，以相同時脈信號來驅動位於玻璃基板上之GOP驅動電路中之複數移位暫存器中之至少二個相對應移位暫存器，以使得該些相對應移位暫存器輸出相同相位的輸出信號來驅動至少二相對應掃描線。 The present invention relates to a display device and a driving method thereof that support dual resolution display. Driving a plurality of shift registers in a GOP driving circuit on a glass substrate with the same clock signal at low resolution display At least two of the corresponding shift registers are such that the corresponding shift register outputs an output signal of the same phase to drive at least two corresponding scan lines.

本發明一實施例提出一種支援雙解析度顯示之顯示裝置，包括：一顯示面板，具有一薄膜電晶體陣列基板；複數條掃描線，形成於該薄膜電晶體陣列基板上；一時序控制器，輸出一起始信號與複數時脈信號；以及一驅動電路，形成於該薄膜電晶體陣列基板上，該驅動電路包括複數個移位暫存器，該些移位暫存器接收該起始信號與該些時脈信號，該些移位暫存器輸出個別第一輸出信號以驅動該些掃描線，該些移位暫存器之一第(i)級移位暫存器輸出一第二輸出信號以起始該些移位暫存器之一第(i+j)級移位暫存器，i與j為正整數且j大於等於2。於低解析度顯示下，該時序控制器輸出相同相位之j個時脈信號以驅動該些移位暫存器之該第(i)級至一第(i+j-1)級移位暫存器，以使得該第(i)級至該第(i+j-1)級移位暫存器所輸出之該些第一輸出信號具有相同相位來驅動相對應掃描線。 An embodiment of the present invention provides a display device supporting a dual-resolution display, comprising: a display panel having a thin film transistor array substrate; a plurality of scan lines formed on the thin film transistor array substrate; and a timing controller And outputting a start signal and a complex clock signal; and a driving circuit formed on the thin film transistor array substrate, the driving circuit includes a plurality of shift registers, and the shift registers receive the start signal and The clock signals, the shift register outputs an individual first output signal to drive the scan lines, and one of the shift registers (i) stage shift register outputs a second output The signal starts the (i+j)th stage shift register of one of the shift registers, i and j are positive integers and j is greater than or equal to 2. In the low-resolution display, the timing controller outputs j clock signals of the same phase to drive the (i)th to (i+j-1)th shifts of the shift registers. And storing the first output signals outputted by the (i)th stage to the (i+j-1)th stage shift register to have the same phase to drive the corresponding scan lines.

本發明另一實施例提出一種驅動方法，應用於支援雙解析度顯示之一顯示裝置。該驅動方法包括：於正常顯示下，以不同相位之複數時脈信號驅動該顯示裝置之一驅動電路之複數移位暫存器，以使得該些移位暫存器之個別第一輸出信號為不同相位來驅動該顯示裝置之複數掃描線；於低解析度顯示下，以相同相位之j個時脈信號驅動該些移位暫存器之該第(i)級至一第(i+j-1)級移位暫存器，以使得該該第(i)級至該第(i+j-1)級移位暫存器所輸出之該些第一輸出信號具有相同相位來驅動相對應掃描線，該些移位暫存器之一第(i)級移位暫存器輸出一第二輸出信號以起始該些移位暫存器之一第(i+j)級移位暫存器，i與j為正整數且j大於等於2，該些移位暫存器之該第(i+j)級移位暫存器所輸出之該第一輸出信號更重置該些移位暫存器之該第(i)級移位暫存器。 Another embodiment of the present invention provides a driving method for one display device supporting dual resolution display. The driving method includes: driving, after a normal display, a plurality of shift registers of a driving circuit of one of the display devices with complex clock signals of different phases, so that the individual first output signals of the shift registers are Driving the plurality of scan lines of the display device with different phases; driving the (i)th to the first (i+j) of the shift registers with j clock signals of the same phase under low resolution display -1) a stage shift register such that the output of the (i)th stage to the (i+j-1)th stage shift register is output The first output signals have the same phase to drive the corresponding scan lines, and one of the shift registers, the (i)th stage shift register outputs a second output signal to start the shift registers. One (i+j)th stage shift register, i and j are positive integers and j is greater than or equal to 2, and the output of the (i+j)th stage shift register of the shift registers is output. The first output signal further resets the (i)th stage shift register of the shift registers.

為了對本發明之上述及其他方面有更佳的瞭解，下文特舉實施例，並配合所附圖式，作詳細說明如下： In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

於本發明多個實施例中，在同一個顯示面板，透過時序控制器的功能設定變更，並設計GOP線路(比如，移位暫存器)，以支援雙解析度顯示：正常解析度顯示與低解析度顯示。於正常解析度顯示下，一次掃描一條掃描線，也就是說，一個掃描信號輸入給一條掃描線。於低解析度顯示下，一次掃描N條掃描線(N為大於1的正整數)，也就是說，同一個掃描信號輸入給N條掃描線。 In various embodiments of the present invention, in the same display panel, the function setting of the timing controller is changed, and a GOP line (for example, a shift register) is designed to support dual resolution display: normal resolution display and Low resolution display. Under the normal resolution display, one scan line is scanned at a time, that is, one scan signal is input to one scan line. Under low-resolution display, N scan lines are scanned at a time (N is a positive integer greater than 1), that is, the same scan signal is input to N scan lines.

第一實施例 First embodiment

請參照第1圖，其繪示利用GOP技術之顯示面板的示意圖。顯示面板10包括薄膜電晶體陣列基板11、多條掃描線13、GOP驅動電路14、外部準位轉換電路15、以及時序控制器(Timing Controller)16。薄膜電晶體陣列基板11具有畫素區域(Active Area)12，各條掃描線13係分別部分地設置於畫素區域12內。GOP驅動電路14係設置於玻璃基板11上之一側。GOP驅動電路14包括多個移位暫存器，此些移位暫存器電性連接於該些掃描線13，以驅動該些掃描線13。時序控制器16係輸出多種控制信號與多種時脈信號，該些信號經由外部準位轉換電路15升壓過後，送至GOP驅動電路14，來驅動此些掃描線13，以進行畫面顯示。時序控制器16及外部準位轉換電路15並非形成於薄膜電晶體陣列基板11上，而是形成於比如硬式印刷電路板上，COF(薄膜覆晶，Chip on Film)用以連結此硬式印刷電路板與玻璃基板，使得由時序控制器16所輸出的該些控制信號與該些時脈信號透過COF傳送信號給薄膜電晶體陣列基板11上的GOP驅動電路14。 Please refer to FIG. 1 , which shows a schematic diagram of a display panel using GOP technology. The display panel 10 includes a thin film transistor array substrate 11, a plurality of scanning lines 13, a GOP driving circuit 14, an external level conversion circuit 15, and a timing controller 16. The thin film transistor array substrate 11 has a pixel area (Active Area) 12, and each of the scanning lines 13 is partially disposed in the pixel area 12, respectively. The GOP driving circuit 14 is disposed on one side of the glass substrate 11. GOP drive circuit 14 includes multiple The shift register is electrically connected to the scan lines 13 to drive the scan lines 13. The timing controller 16 outputs a plurality of control signals and a plurality of clock signals. The signals are boosted by the external level conversion circuit 15, and then sent to the GOP driving circuit 14 to drive the scan lines 13 for screen display. The timing controller 16 and the external level conversion circuit 15 are not formed on the thin film transistor array substrate 11, but are formed on, for example, a hard printed circuit board, and COF (Chip on Film) is used to connect the hard printed circuit. The board and the glass substrate are such that the control signals output by the timing controller 16 and the clock signals are transmitted to the GOP driving circuit 14 on the thin film transistor array substrate 11 through the COF.

於本發明第一實施例中，顯示面板10可支援雙解析度顯示，亦即，正常解析度顯示與1/2解析度顯示。請參考第2圖，其顯示根據本發明第一實施例之多個移位暫存器之連接關係，第3A圖顯示根據本發明第一實施例處於正常解析度顯示模式之時序圖，第3B圖顯示根據本發明第一實施例處於1/2解析度顯示模式之時序圖。 In the first embodiment of the present invention, the display panel 10 can support dual resolution display, that is, normal resolution display and 1/2 resolution display. Please refer to FIG. 2, which shows the connection relationship of a plurality of shift registers according to the first embodiment of the present invention, and FIG. 3A shows a timing chart of the normal resolution display mode according to the first embodiment of the present invention, FIG. 3B. The figure shows a timing chart in the 1/2 resolution display mode according to the first embodiment of the present invention.

如第2圖所示，GOP驅動電路14包括複數個移位暫存器SR。雖然第2圖中只顯示出4個移位暫存器SR1~SR4，但知本發明並不受限於此。時脈信號CK1~CK6、起始信號STV(Start Pulse)由時序控制器16所輸出並經由外部準位轉換電路15升壓後輸出給移位暫存器SR1~SR4。 As shown in FIG. 2, the GOP drive circuit 14 includes a plurality of shift registers SR. Although only four shift registers SR1 to SR4 are shown in Fig. 2, the present invention is not limited thereto. The clock signals CK1 to CK6 and the start signal STV (Start Pulse) are output from the timing controller 16 and boosted via the external level conversion circuit 15 and output to the shift registers SR1 to SR4.

第一級移位暫存器SR1與第二級移位暫存器SR2可以接收相同的起始信號或是接收不同的起始信號。在此以第一級移位暫存器SR1與第二級移位暫存器SR2接收相同的起始信號為例做說明。至於第一級移位暫存器SR1與第二級移位暫存器SR2接收不同的起始信號的細節可依此類推，於此不重述。 The first stage shift register SR1 and the second stage shift register SR2 can receive the same start signal or receive different start signals. Here, the phase is received by the first stage shift register SR1 and the second stage shift register SR2. The same starting signal is taken as an example for explanation. The details of receiving the different start signals for the first stage shift register SR1 and the second stage shift register SR2 can be deduced by analogy and will not be repeated here.

第一級移位暫存器SR1接收由時序控制器所輸出的起始信號STV、時脈信號CK1、CK3與CK5。第一級移位暫存器SR1的傳送信號Carry做為第三級移位暫存器SR3的起始信號。第一級移位暫存器SR1的輸出信號Output1輸出給相對應的掃描線。第三級移位暫存器SR3的輸出信號Output3作為重置信號，回授給第一級移位暫存器SR1的重置端RT，以將第一級移位暫存器SR1的輸出信號Output1重置(拉至低準位)。於本揭露內容中，輸出信號Output可視為為各移位暫存器的第一輸出信號，而傳送信號Carry則可視為各移位暫存器的第二輸出信號，以下類推。 The first stage shift register SR1 receives the start signal STV and the clock signals CK1, CK3, and CK5 outputted by the timing controller. The transmission signal Carry of the first stage shift register SR1 serves as the start signal of the third stage shift register SR3. The output signal Output1 of the first stage shift register SR1 is output to the corresponding scan line. The output signal Output3 of the third stage shift register SR3 is returned as a reset signal to the reset terminal RT of the first stage shift register SR1 to shift the output signal of the first stage shift register SR1. Output1 is reset (pushed to low level). In the disclosure, the output signal Output can be regarded as the first output signal of each shift register, and the transmit signal Carry can be regarded as the second output signal of each shift register, and so on.

相似地，第二級移位暫存器SR2接收由時序控制器所輸出的起始信號STV、時脈信號CK2、CK4與CK6。第二級移位暫存器SR2的傳送信號Carry做為第四級移位暫存器SR4的起始信號。第二級移位暫存器SR2的輸出信號Output2輸出給相對應的掃描線。第四級移位暫存器SR4的輸出信號Output4作為重置信號，回授給第二級移位暫存器SR2的重置端RT，以將第二級移位暫存器SR2的輸出信號Output2重置(拉至低準位)。 Similarly, the second stage shift register SR2 receives the start signal STV, clock signals CK2, CK4, and CK6 output by the timing controller. The transmission signal Carry of the second stage shift register SR2 serves as the start signal of the fourth stage shift register SR4. The output signal Output2 of the second stage shift register SR2 is output to the corresponding scan line. The output signal Output4 of the fourth stage shift register SR4 is sent as a reset signal to the reset terminal RT of the second stage shift register SR2 to shift the output signal of the second stage shift register SR2. Output2 reset (pushed to low level).

第三級移位暫存器SR3的起始信號乃是第一級移位暫存器SR1的傳送信號Carry，而第三級移位暫存器SR3接收由時序控制器所輸出的時脈信號CK1、CK3與CK5。第四級移位暫存器SR4的起始信號乃是第二級移位暫存器SR2的傳送信號Carry，而第四級移位暫存器SR4接收由時序控制器所輸出的時脈信號CK2、CK4與CK6。也就是說，第i級移位暫存器的傳送信號Carry做為第(i+2)級移位暫存器的起始信號，第(i+2)級移位暫存器的輸出信號Output(i)做為第i級移位暫存器的重置信號，i為正整數。其他級移位暫存器的電路連接關係可依此類推，於此不重述。STV、CK1~CK6的最高準位與最低準位為VGH與VSS2；另外VSS1≧VSS2。輸出信號Output1~Output4為傳送給相對應掃描線的掃描信號。 The start signal of the third stage shift register SR3 is the transfer signal Carry of the first stage shift register SR1, and the third stage shift register SR3 receives the clock signal output by the timing controller. CK1, CK3 and CK5. The start signal of the fourth stage shift register SR4 is the transfer signal Carry of the second stage shift register SR2, and the fourth stage shift register SR4 receives the clock signal output by the timing controller. CK2, CK4 and CK6. That is to say, the transmission signal Carry of the i-th stage shift register is used as the start signal of the (i+2)th stage shift register, and the output signal of the (i+2)th stage shift register Output(i) is used as the reset signal of the i-th shift register, and i is a positive integer. The circuit connection relationship of other stages of the shift register can be deduced by analogy, and will not be repeated here. The highest level and lowest level of STV, CK1~CK6 are VGH and VSS2; in addition, VSS1 ≧ VSS2. The output signals Output1~Output4 are scan signals transmitted to the corresponding scan lines.

請參考第2圖與第3A圖。於正常解析度顯示下，由時序控制器所輸出的時脈信號CK1~CK6有不同時序。所以，輸出信號Output1~Output4具有不同時序，亦即，每條掃描線所接收的掃描信號都不相同，所以，面板處於正常解析度顯示。 Please refer to Figure 2 and Figure 3A. Under the normal resolution display, the clock signals CK1~CK6 output by the timing controller have different timings. Therefore, the output signals Output1~Output4 have different timings, that is, the scanning signals received by each scanning line are different, so the panel is in normal resolution display.

請參考第2圖與第3B圖。於低(1/2)解析度顯示下，由時序控制器所輸出的時脈信號CK1與CK2為同相位，時脈信號CK3與CK4為同相位，時脈信號CK5與CK6為同相位。所以，輸出信號Output1與Output2為同相位，而輸出信號Output3與Output4具有同時位，亦即，2條相鄰掃描線所接收的掃描信號為相同，所以，面板處於低(1/2)解析度顯示。 Please refer to Figures 2 and 3B. Under the low (1/2) resolution display, the clock signals CK1 and CK2 output by the timing controller are in phase, the clock signals CK3 and CK4 are in phase, and the clock signals CK5 and CK6 are in phase. Therefore, the output signals Output1 and Output2 are in phase, and the output signals Output3 and Output4 have the same bit, that is, the scanning signals received by the two adjacent scanning lines are the same, so the panel is at a low (1/2) resolution. display.

詳細地說，於第3B圖的時間間隔t1中，起始信號STV為高準位且時脈信號CK1~CK6全為低準位(VSS2)時，第一級移位暫存器SR1的輸出信號Output1為低準位(VSS1)而其傳送信號Carry則為低準位(VSS2)；第二級移位暫存器SR2的輸出信號Output2為低準位(VSS1)而其傳送信號Carry則為低準位(VSS2)。相似地，第三級移位暫存器SR3的輸出信號Output3為低準位(VSS1)而其傳送信號Carry則為低準位(VSS2)；第四級移位暫存器SR4的輸出信號Output4為低準位(VSS1)而其傳送信號Carry則為低準位(VSS2)。 In detail, in the time interval t1 of FIG. 3B, when the start signal STV is at the high level and the clock signals CK1 CK CK6 are all low level (VSS2), the output of the first stage shift register SR1 Signal Output1 is low level Bit (VSS1) and its transmit signal Carry is low level (VSS2); the output signal Output2 of the second stage shift register SR2 is low level (VSS1) and its transmit signal Carry is low level (VSS2). ). Similarly, the output signal Output3 of the third-stage shift register SR3 is at a low level (VSS1) and its transmit signal Carry is at a low level (VSS2); the output signal of the fourth-stage shift register SR4 is Output4. It is low level (VSS1) and its transmit signal Carry is low level (VSS2).

於第3B圖的時間間隔t2中，起始信號STV為低準位(VSS2)且時脈信號CK1~CK2為高準位(VGH)而時脈信號CK3~CK6仍為低準位(VSS2)時，第一級移位暫存器SR1的輸出信號Output1為高準位(VGH)而其傳送信號Carry為高準位(VGH)；第二級移位暫存器SR2的輸出信號Output2為高準位(VGH)而其傳送信號Carry則為高準位(VGH)。第三級移位暫存器SR3的輸出信號Output3為低準位(VSS1)而其傳送信號Carry則為低準位(VSS2)；第四級移位暫存器SR4的輸出信號Output4為低準位(VSS1)而其傳送信號Carry則為低準位(VSS2)。 In the time interval t2 of FIG. 3B, the start signal STV is at a low level (VSS2) and the clock signals CK1 to CK2 are at a high level (VGH) and the clock signals CK3 to CK6 are still at a low level (VSS2). The output signal Output1 of the first stage shift register SR1 is at a high level (VGH) and its transmit signal Carry is a high level (VGH); the output signal Output2 of the second stage shift register SR2 is high. The level (VGH) and its transmission signal Carry is the high level (VGH). The output signal Output3 of the third-stage shift register SR3 is at a low level (VSS1) and its transmit signal Carry is at a low level (VSS2); the output signal Output4 of the fourth-stage shift register SR4 is low-level. Bit (VSS1) and its transmit signal Carry is low level (VSS2).

於第3B圖的時間間隔t3中，起始信號STV為低準位(VSS2)且時脈信號CK3~CK4為高準位(VGH)而時脈信號CK1~CK2與CK5~CK6為低準位(VSS2)時，第一級移位暫存器SR1的輸出信號Output1為低準位(VSS2)而其傳送信號Carry為低準位(VSS2)；第二級移位暫存器SR2的輸出信號Output2為低準位(VSS2)而其傳送信號Carry則為低準位(VSS2)。第三級移位暫存器SR3的輸出信號Output3為高準位(VGH)而其傳送信號Carry則為高準位 (VGH)；第四級移位暫存器SR4的輸出信號Output4為高準位(VGH)而其傳送信號Carry則為高準位(VGH)。其餘的時序可由以上說明類推，於此不重述。 In the time interval t3 of FIG. 3B, the start signal STV is at a low level (VSS2) and the clock signals CK3 to CK4 are at a high level (VGH) and the clock signals CK1 to CK2 and CK5 to CK6 are at a low level. (VSS2), the output signal Output1 of the first stage shift register SR1 is low level (VSS2) and its transmission signal Carry is low level (VSS2); the output signal of the second stage shift register SR2 Output2 is low level (VSS2) and its transmit signal Carry is low level (VSS2). The output signal Output3 of the third stage shift register SR3 is at a high level (VGH) and its transmission signal Carry is at a high level. (VGH); the output signal Output4 of the fourth stage shift register SR4 is a high level (VGH) and its transmission signal Carry is a high level (VGH). The rest of the timing can be analogized by the above description, and will not be repeated here.

由上述說明可知，於本發明第一實施例中，面板可支援雙解析度顯示：正常顯示與低(1/2)解析度顯示。 As can be seen from the above description, in the first embodiment of the present invention, the panel can support dual resolution display: normal display and low (1/2) resolution display.

第二實施例 Second embodiment

於本發明第二實施例中，顯示面板10之電路架構基本上相同或相似於第一實施例，故其細節於此不重述。不過，於本發明第二實施例中，顯示面板10可支援雙解析度顯示，正常解析度顯示與1/3解析度顯示。請參考第4圖，其顯示根據本發明第二實施例之多個移位暫存器之連接關係，第5A圖顯示根據本發明第二實施例處於正常解析度顯示模式之時序圖，第5B圖顯示根據本發明第二實施例處於1/3解析度顯示模式之時序圖。雖然第4圖中只顯示出5個移位暫存器SR1~SR5，但知本發明並不受限於此。時脈信號CK1~CK6、起始信號STV乃是由時序控制器16所輸出並經由外部準位轉換電路15升壓後輸出給移位暫存器SR1~SR5。 In the second embodiment of the present invention, the circuit architecture of the display panel 10 is substantially the same or similar to that of the first embodiment, and thus the details thereof are not repeated herein. However, in the second embodiment of the present invention, the display panel 10 can support dual resolution display, normal resolution display and 1/3 resolution display. Please refer to FIG. 4, which shows the connection relationship of a plurality of shift registers according to the second embodiment of the present invention, and FIG. 5A shows the timing chart of the normal resolution display mode according to the second embodiment of the present invention, FIG. 5B. The figure shows a timing diagram in a 1/3 resolution display mode in accordance with a second embodiment of the present invention. Although only five shift registers SR1 to SR5 are shown in Fig. 4, it is understood that the present invention is not limited thereto. The clock signals CK1 to CK6 and the start signal STV are output from the timing controller 16 and boosted by the external level conversion circuit 15 and output to the shift registers SR1 to SR5.

第一級移位暫存器SR1~第三級移位暫存器SR3可以接收相同的起始信號或是接收不同的起始信號。在此以第一級移位暫存器SR1~第三級移位暫存器SR3接收相同的起始信號為例做說明。至於第一級移位暫存器SR1~第三級移位暫存器SR3接收不同的起始信號的細節可依此類推，於此不重述。 The first stage shift register SR1~the third stage shift register SR3 can receive the same start signal or receive different start signals. Here, the first stage shift register SR1 to the third stage shift register SR3 receive the same start signal as an example for description. The details of receiving the different start signals from the first stage shift register SR1 to the third stage shift register SR3 can be deduced by analogy, and will not be repeated here.

第一級移位暫存器SR1接收由時序控制器所輸出的起始信號STV、時脈信號CK1與CK4。第一級移位暫存器SR1的傳送信號Carry做為第四級移位暫存器SR4的起始信號。第一級移位暫存器SR1的輸出信號Output1輸出給相對應的掃描線。第四級移位暫存器SR4的輸出信號Output4作為重置信號，回授給第一級移位暫存器SR1的重置端RT，以將第一級移位暫存器SR1的輸出信號Output1重置(拉至低準位)。 The first stage shift register SR1 receives the start signal STV and the clock signals CK1 and CK4 outputted by the timing controller. The transmission signal Carry of the first stage shift register SR1 serves as the start signal of the fourth stage shift register SR4. The output signal Output1 of the first stage shift register SR1 is output to the corresponding scan line. The output signal Output4 of the fourth stage shift register SR4 is used as a reset signal and is fed back to the reset terminal RT of the first stage shift register SR1 to shift the output signal of the first stage shift register SR1. Output1 is reset (pushed to low level).

相似地，第二級移位暫存器SR2接收由時序控制器所輸出的起始信號STV、時脈信號CK2與CK5。第二級移位暫存器SR2的傳送信號Carry做為第五級移位暫存器SR5的起始信號。第二級移位暫存器SR2的輸出信號Output2輸出給相對應的掃描線。第五級移位暫存器SR5的輸出信號Output5作為重置信號，回授給第二級移位暫存器SR2的重置端RT，以將第二級移位暫存器SR2的輸出信號Output2重置(拉至低準位)。 Similarly, the second stage shift register SR2 receives the start signal STV and the clock signals CK2 and CK5 outputted by the timing controller. The transmission signal Carry of the second stage shift register SR2 serves as the start signal of the fifth stage shift register SR5. The output signal Output2 of the second stage shift register SR2 is output to the corresponding scan line. The output signal Output5 of the fifth-stage shift register SR5 is returned as a reset signal to the reset terminal RT of the second-stage shift register SR2 to shift the output signal of the second-stage shift register SR2. Output2 reset (pushed to low level).

相似地，第三級移位暫存器SR3接收由時序控制器所輸出的起始信號STV、時脈信號CK3與CK6。第三級移位暫存器SR3的傳送信號Carry做為第六級移位暫存器(未示出)的起始信號。第三級移位暫存器SR3的輸出信號Output3輸出給相對應的掃描線。第六級移位暫存器的輸出信號Output6作為重置信號，回授給第三級移位暫存器SR3的重置端RT，以將第三級移位暫存器SR3的輸出信號Output3重置(拉至低準位)。 Similarly, the third stage shift register SR3 receives the start signal STV and the clock signals CK3 and CK6 outputted by the timing controller. The transmission signal Carry of the third stage shift register SR3 serves as a start signal for the sixth stage shift register (not shown). The output signal Output3 of the third stage shift register SR3 is output to the corresponding scan line. The output signal Output6 of the sixth-stage shift register is returned as a reset signal to the reset terminal RT of the third-stage shift register SR3 to shift the output signal of the third-stage shift register SR3 to Output3. Reset (pull to low level).

第四級移位暫存器SR4的起始信號乃是第一級移位暫存器SR1的傳送信號Carry，而第四級移位暫存器SR4接收由時序控制器所輸出的時脈信號CK1與CK4。第五級移位暫存器SR5的起始信號乃是第二級移位暫存器SR2的傳送信號Carry，而第五級移位暫存器SR5接收由時序控制器所輸出的時脈信號CK2與CK5。也就是說，第i級移位暫存器的傳送信號Carry做為第(i+3)級移位暫存器的起始信號，i為正整數。其他級移位暫存器的電路連接關係可依此類推，於此不重述。 The start signal of the fourth stage shift register SR4 is the first stage shift The buffer SR1 transmits a signal Carry, and the fourth stage shift register SR4 receives the clock signals CK1 and CK4 outputted by the timing controller. The start signal of the fifth stage shift register SR5 is the transfer signal Carry of the second stage shift register SR2, and the fifth stage shift register SR5 receives the clock signal output by the timing controller. CK2 and CK5. That is to say, the transmission signal Carry of the i-th stage shift register is used as the start signal of the (i+3)th stage shift register, and i is a positive integer. The circuit connection relationship of other stages of the shift register can be deduced by analogy, and will not be repeated here.

請參考第4圖與第5A圖。於正常解析度顯示下，由時序控制器所輸出的時脈信號CK1~CK6有不同時序。所以，輸出信號Output1~Output6具有不同時序，亦即，每條掃描線所接收的掃描信號都不相同，所以，面板處於正常解析度顯示。 Please refer to Figure 4 and Figure 5A. Under the normal resolution display, the clock signals CK1~CK6 output by the timing controller have different timings. Therefore, the output signals Output1~Output6 have different timings, that is, the scanning signals received by each scanning line are different, so the panel is in normal resolution display.

請參考第4圖與第5B圖。於低(1/3)解析度顯示下，由時序控制器所輸出的時脈信號CK1~CK3為同相位，時脈信號CK4~CK6為同相位。所以，輸出信號Output1~Output3為同相位，而輸出信號Output4~Output6具同時位，亦即，3條相鄰掃描線所接收的掃描信號為相同，所以，面板處於低(1/3)解析度顯示。第5B圖之詳細解說可由上述第一實施例之說明可推出，故於此不重述。 Please refer to Figures 4 and 5B. In the low (1/3) resolution display, the clock signals CK1 to CK3 output by the timing controller are in phase, and the clock signals CK4 to CK6 are in phase. Therefore, the output signals Output1~Output3 are in the same phase, and the output signals Output4~Output6 have the same bit, that is, the scanning signals received by the three adjacent scanning lines are the same, so the panel is at a low (1/3) resolution. display. The detailed explanation of FIG. 5B can be derived from the description of the first embodiment described above, and thus will not be repeated here.

由上述說明可知，於本發明第二實施例中，面板可支援雙解析度顯示：正常顯示與低(1/3)解析度顯示。 As can be seen from the above description, in the second embodiment of the present invention, the panel can support dual resolution display: normal display and low (1/3) resolution display.

第三實施例 Third embodiment

於本發明第三實施例中，顯示面板10之電路架構基本上相同或相似於第一實施例，故其細節於此不重述。不過，於本發明第三實施例中，顯示面板10可支援雙解析度顯示，正常解析度顯示與半(1/2)解析度顯示。請參考第6圖，其顯示根據本發明第三實施例之多個移位暫存器之連接關係，第7A圖顯示根據本發明第三實施例處於正常解析度顯示模式之時序圖，第7B圖顯示根據本發明第三實施例處於1/2解析度顯示模式之時序圖。雖然第6圖中只顯示出5個移位暫存器SR1~SR5，但知本發明並不受限於此。時脈信號CK1~CK8、起始信號STV乃是由時序控制器16所輸出並經由外部準位轉換電路15升壓後輸給移位暫存器SR1~SR5。 In the third embodiment of the present invention, the circuit architecture of the display panel 10 is substantially the same or similar to that of the first embodiment, and thus the details thereof are not repeated herein. However, in the third embodiment of the present invention, the display panel 10 can support dual resolution display, normal resolution display and half (1/2) resolution display. Please refer to FIG. 6 , which shows the connection relationship of a plurality of shift registers according to the third embodiment of the present invention, and FIG. 7A shows a timing chart of the normal resolution display mode according to the third embodiment of the present invention, FIG. 7B. The figure shows a timing chart in the 1/2 resolution display mode according to the third embodiment of the present invention. Although only five shift registers SR1 to SR5 are shown in Fig. 6, it is to be understood that the present invention is not limited thereto. The clock signals CK1 to CK8 and the start signal STV are output from the timing controller 16 and boosted by the external level conversion circuit 15 and then supplied to the shift registers SR1 to SR5.

第一級移位暫存器SR1與第二級移位暫存器SR2可以接收相同的起始信號或是接收不同的起始信號。在此以第一級移位暫存器SR1與第二級移位暫存器SR2接收相同的起始信號為例做說明。至於第一級移位暫存器SR1與第二級移位暫存器SR2接收不同的起始信號的細節可依此類推，於此不重述。 The first stage shift register SR1 and the second stage shift register SR2 can receive the same start signal or receive different start signals. Here, the first stage shift register SR1 and the second stage shift register SR2 receive the same start signal as an example for description. The details of receiving the different start signals for the first stage shift register SR1 and the second stage shift register SR2 can be deduced by analogy and will not be repeated here.

第一級移位暫存器SR1接收由時序控制器所輸出的起始信號STV、時脈信號CK1與CK3。第一級移位暫存器SR1的傳送信號Carry做為第三級移位暫存器SR3的起始信號。第一級移位暫存器SR1的輸出信號Output1輸出給相對應的掃描線。第三級移位暫存器SR3的輸出信號Output3作為重置信號，回授給第一級移位暫存器SR1的重置端RT，以將第一級移位暫存器SR1的輸出信號 Output1重置(拉至低準位)。 The first stage shift register SR1 receives the start signal STV and the clock signals CK1 and CK3 outputted by the timing controller. The transmission signal Carry of the first stage shift register SR1 serves as the start signal of the third stage shift register SR3. The output signal Output1 of the first stage shift register SR1 is output to the corresponding scan line. The output signal Output3 of the third stage shift register SR3 is returned as a reset signal to the reset terminal RT of the first stage shift register SR1 to shift the output signal of the first stage shift register SR1. Output1 is reset (pushed to low level).

相似地，第二級移位暫存器SR2接收由時序控制器所輸出的起始信號STV、時脈信號CK2與CK4。第二級移位暫存器SR2的傳送信號Carry做為第四級移位暫存器SR4的起始信號。第二級移位暫存器SR2的輸出信號Output2輸出給相對應的掃描線。第四級移位暫存器SR4的輸出信號Output4作為重置信號，回授給第二級移位暫存器SR2的重置端RT，以將第二級移位暫存器SR2的輸出信號Output2重置(拉至低準位)。 Similarly, the second stage shift register SR2 receives the start signal STV and the clock signals CK2 and CK4 outputted by the timing controller. The transmission signal Carry of the second stage shift register SR2 serves as the start signal of the fourth stage shift register SR4. The output signal Output2 of the second stage shift register SR2 is output to the corresponding scan line. The output signal Output4 of the fourth stage shift register SR4 is sent as a reset signal to the reset terminal RT of the second stage shift register SR2 to shift the output signal of the second stage shift register SR2. Output2 reset (pushed to low level).

第三級移位暫存器SR3的起始信號乃是第一級移位暫存器SR1的傳送信號Carry，而第三級移位暫存器SR3接收由時序控制器所輸出的時脈信號CK3與CK5。第四級移位暫存器SR4的起始信號乃是第二級移位暫存器SR2的傳送信號Carry，而第四級移位暫存器SR4接收由時序控制器所輸出的時脈信號CK4與CK6。也就是說，第i級移位暫存器的傳送信號Carry做為第(i+2)級移位暫存器的起始信號，第(i+2)級移位暫存器的輸出信號Output(i)做為第i級移位暫存器的重置信號，i為正整數。其他級移位暫存器的電路連接關係可依此類推，於此不重述。 The start signal of the third stage shift register SR3 is the transfer signal Carry of the first stage shift register SR1, and the third stage shift register SR3 receives the clock signal output by the timing controller. CK3 and CK5. The start signal of the fourth stage shift register SR4 is the transfer signal Carry of the second stage shift register SR2, and the fourth stage shift register SR4 receives the clock signal output by the timing controller. CK4 and CK6. That is to say, the transmission signal Carry of the i-th stage shift register is used as the start signal of the (i+2)th stage shift register, and the output signal of the (i+2)th stage shift register Output(i) is used as the reset signal of the i-th shift register, and i is a positive integer. The circuit connection relationship of other stages of the shift register can be deduced by analogy, and will not be repeated here.

基本上，第三實施例之該些移位暫存器間的電路連接關係相同或相似於第一實施例，故其細節於此不重述。由第7B圖可看出，由於時序控制器輸出8個時脈信號CK1~CK8給移位暫存器，所以，於第7B圖中，當處於低(1/2)解析度顯示時，CK1~CK2為同相位，CK3~CK4為同相位，CK5~CK6為同相位，CK7~CK8為同相位，且輸出信號Output1~Output2為同相位，輸出信號Output3~Output4為同相位，輸出信號Output5~Output6為同相位，輸出信號Output7~Output8為同相位。 Basically, the circuit connection relationship between the shift registers of the third embodiment is the same or similar to that of the first embodiment, and thus the details thereof are not repeated herein. It can be seen from Fig. 7B that since the timing controller outputs eight clock signals CK1~CK8 to the shift register, in Fig. 7B, when at low (1/2) resolution display, CK1 ~CK2 is in phase, CK3~CK4 are the same Phase, CK5~CK6 are in phase, CK7~CK8 are in phase, and output signals Output1~Output2 are in phase, output signals Output3~Output4 are in phase, output signals Output5~Output6 are in phase, and output signals Output7~Output8 are In phase.

由上述說明可知，於本發明第三實施例中，面板可支援雙解析度顯示：正常顯示與低(1/2)解析度顯示。 As can be seen from the above description, in the third embodiment of the present invention, the panel can support dual resolution display: normal display and low (1/2) resolution display.

第四實施例 Fourth embodiment

於本發明第四實施例中，顯示面板10之電路架構基本上相同或相似於第一實施例，故其細節於此不重述。不過，於本發明第四實施例中，顯示面板10可支援雙解析度顯示，正常解析度顯示與低(1/4)解析度顯示。請參考第8圖，其顯示根據本發明第四實施例之多個移位暫存器之連接關係，第9A圖顯示根據本發明第四實施例處於正常解析度顯示模式之時序圖，第9B圖顯示根據本發明第四實施例處於1/4解析度顯示模式之時序圖。雖然第8圖中只顯示出5個移位暫存器SR1~SR5，但知本發明並不受限於此。時脈信號CK1~CK8、起始信號STV乃是由時序控制器16所輸出並經由外部準位轉換電路15升壓後輸給移位暫存器SR1~SR5。 In the fourth embodiment of the present invention, the circuit architecture of the display panel 10 is substantially the same or similar to that of the first embodiment, and thus the details thereof are not repeated herein. However, in the fourth embodiment of the present invention, the display panel 10 can support dual resolution display, normal resolution display and low (1/4) resolution display. Please refer to FIG. 8 , which shows the connection relationship of a plurality of shift registers according to the fourth embodiment of the present invention, and FIG. 9A shows a timing chart of the normal resolution display mode according to the fourth embodiment of the present invention, FIG. 9B. The figure shows a timing chart in the 1/4 resolution display mode according to the fourth embodiment of the present invention. Although only five shift registers SR1 to SR5 are shown in Fig. 8, the present invention is not limited thereto. The clock signals CK1 to CK8 and the start signal STV are output from the timing controller 16 and boosted by the external level conversion circuit 15 and then supplied to the shift registers SR1 to SR5.

第一級移位暫存器SR1~第四級移位暫存器SR4可以接收相同的起始信號或是接收不同的起始信號。在此以第一級移位暫存器SR1~第四級移位暫存器SR4接收相同的起始信號為例做說明。至於第一級移位暫存器SR1~第四級移位暫存器SR4接收不同的起始信號的細節可依此類推，於此不重述。 The first stage shift register SR1~fourth stage shift register SR4 can receive the same start signal or receive different start signals. Here, the first stage shift register SR1 to the fourth stage shift register SR4 receive the same start signal as an example for explanation. As for the details of the first stage shift register SR1 to the fourth stage shift register SR4 receiving different start signals, Analogy, not repeated here.

第一級移位暫存器SR1接收由時序控制器所輸出的起始信號STV、時脈信號CK1與CK5。第一級移位暫存器SR1的傳送信號Carry做為第五級移位暫存器SR5的起始信號。第一級移位暫存器SR1的輸出信號Output1輸出給相對應的掃描線。第五級移位暫存器SR5的輸出信號Output5回授給第一級移位暫存器SR1的重置訊號RT，以將第一級移位暫存器SR1的輸出信號Output1重設(拉至低準位)。 The first stage shift register SR1 receives the start signal STV and the clock signals CK1 and CK5 outputted by the timing controller. The transmission signal Carry of the first stage shift register SR1 serves as the start signal of the fifth stage shift register SR5. The output signal Output1 of the first stage shift register SR1 is output to the corresponding scan line. The output signal Output5 of the fifth-stage shift register SR5 is fed back to the reset signal RT of the first-stage shift register SR1 to reset the output signal Output1 of the first-stage shift register SR1. To the low level).

相似地，第二級移位暫存器SR2接收由時序控制器所輸出的起始信號STV、時脈信號CK2與CK6。第二級移位暫存器SR2的傳送信號Carry做為第六級移位暫存器(未示出)的起始信號。第二級移位暫存器SR2的輸出信號Output2輸出給相對應的掃描線。第六級移位暫存器(未示出)的輸出信號Output6回授給第二級移位暫存器SR2的重置訊號RT，以將第二級移位暫存器SR2的輸出信號Output2重設(拉至低準位)。 Similarly, the second stage shift register SR2 receives the start signal STV and the clock signals CK2 and CK6 outputted by the timing controller. The transmission signal Carry of the second stage shift register SR2 serves as a start signal for the sixth stage shift register (not shown). The output signal Output2 of the second stage shift register SR2 is output to the corresponding scan line. The output signal Output6 of the sixth stage shift register (not shown) is fed back to the reset signal RT of the second stage shift register SR2 to shift the output signal Output2 of the second stage shift register SR2. Reset (pull to low level).

相似地，第三級移位暫存器SR3接收由時序控制器所輸出的起始信號STV、時脈信號CK3與CK7。第三級移位暫存器SR3的傳送信號Carry做為第七級移位暫存器(未示出)的起始信號。第三級移位暫存器SR3的輸出信號Output3輸出給相對應的掃描線。第七級移位暫存器的輸出信號Output7回授給第三級移位暫存器SR3的重置訊號RT，以將第三級移位暫存器SR3的輸出信號Output3重設(拉至低準位)。 Similarly, the third stage shift register SR3 receives the start signal STV and the clock signals CK3 and CK7 outputted by the timing controller. The transmission signal Carry of the third stage shift register SR3 serves as a start signal for the seventh stage shift register (not shown). The output signal Output3 of the third stage shift register SR3 is output to the corresponding scan line. The output signal Output7 of the seventh-stage shift register is fed back to the reset signal RT of the third-stage shift register SR3 to reset the output signal Output3 of the third-stage shift register SR3 (pull to Low level).

相似地，第四級移位暫存器SR4接收由時序控制器所輸出的起始信號STV、時脈信號CK4與CK8。第四級移位暫存器SR4的傳送信號Carry做為第八級移位暫存器(未示出)的起始信號。第四級移位暫存器SR4的輸出信號Output4輸出給相對應的掃描線。第八級移位暫存器的輸出信號Output8作為重置信號，回授給第四級移位暫存器SR4的重置端RT，以將第四級移位暫存器SR4的輸出信號Output4重置(拉至低準位)。 Similarly, the fourth stage shift register SR4 receives the start signal STV and the clock signals CK4 and CK8 outputted by the timing controller. The transmission signal Carry of the fourth stage shift register SR4 serves as a start signal of the eighth stage shift register (not shown). The output signal Output4 of the fourth stage shift register SR4 is output to the corresponding scan line. The output signal Output8 of the eighth-stage shift register is returned as a reset signal to the reset terminal RT of the fourth-stage shift register SR4 to shift the output signal of the fourth-stage shift register SR4 to Output4. Reset (pull to low level).

第五級移位暫存器SR5的起始信號乃是第一級移位暫存器SR1的傳送信號Carry，而第五級移位暫存器SR5接收由時序控制器所輸出的時脈信號CK1與CK5。也就是說，於本發明第四實施例中，第i級移位暫存器的傳送信號Carry做為第(i+4)級移位暫存器的起始信號，i為正整數。其他級移位暫存器的電路連接關係可依此類推，於此不重述。 The start signal of the fifth stage shift register SR5 is the transfer signal Carry of the first stage shift register SR1, and the fifth stage shift register SR5 receives the clock signal output by the timing controller. CK1 and CK5. That is, in the fourth embodiment of the present invention, the transmission signal Carry of the i-th stage shift register is used as the start signal of the (i+4)th stage shift register, and i is a positive integer. The circuit connection relationship of other stages of the shift register can be deduced by analogy, and will not be repeated here.

請參考第8圖與第9A圖。於正常解析度顯示下，由時序控制器所輸出的時脈信號CK1~CK8有不同時序。所以，輸出信號Output1~Output8具有不同時序。雖然輸出信號Output5~Output8並未顯示出，但可由上述說明類推出。亦即，每條掃描線所接收的掃描信號都不相同，所以，面板處於正常解析度顯示。 Please refer to Figure 8 and Figure 9A. Under the normal resolution display, the clock signals CK1~CK8 output by the timing controller have different timings. Therefore, the output signals Output1~Output8 have different timings. Although the output signals Output5~Output8 are not shown, they can be derived from the above description. That is, the scan signals received by each scan line are different, so the panel is in normal resolution display.

請參考第8圖與第9B圖。於低(1/4)解析度顯示下，由時序控制器所輸出的時脈信號CK1~CK4為同相位，時脈信號CK5~CK8為同相位。所以，輸出信號Output1~Output4為同相位，而輸出信號 Output5~Output8具同時位，亦即，4條相鄰掃描線所接收的掃描信號為相同，所以，面板處於低(1/4)解析度顯示。第9B圖之詳細解說可由上述實施例之說明推出，故於此不重述。 Please refer to Figure 8 and Figure 9B. In the low (1/4) resolution display, the clock signals CK1 to CK4 output by the timing controller are in phase, and the clock signals CK5 to CK8 are in phase. Therefore, the output signals Output1~Output4 are in phase, and the output signal Output5~Output8 has simultaneous bits, that is, the scanning signals received by the four adjacent scanning lines are the same, so the panel is in a low (1/4) resolution display. The detailed description of Fig. 9B can be derived from the description of the above embodiment, and therefore will not be repeated here.

由上述說明可知，於本發明第四實施例中，面板可支援雙解析度顯示：正常顯示與低(1/4)解析度顯示。 As can be seen from the above description, in the fourth embodiment of the present invention, the panel can support dual resolution display: normal display and low (1/4) resolution display.

於本發明其他可能實施例中，如果要面板支援雙解析度顯示：正常顯示與低(1/N)解析度顯示的話，N為大於1的正整數，則前N級移位暫存器接收由時序控制器所送來的起始信號(可同相位或不同相位)，時序控制器至少送出2N個時脈信號。以前2N級移位暫存器而言，第i級(i小於/等於N)移位暫存器接收時脈信號CKi與CK(i+N)，第i級移位暫存器的傳送信號Carry當成第(i+N)級移位暫存器的起始信號，第(i+N)級移位暫存器的輸出信號Output當成第i級移位暫存器的重設信號。於正常顯示下，2N個時脈信號為不同相位；於低(1/N)解析度顯示下，2N個時脈信號中，前N個時脈信號具有相同相位，後N個時脈信號具有相同相位，如此，對前2N級移位暫存器而言，前N級移位暫存器的輸出信號Output具有相同相位，後N級移位暫存器的輸出信號Output具有相同相位。 In other possible embodiments of the present invention, if the panel is to support dual resolution display: if the normal display and the low (1/N) resolution are displayed, and N is a positive integer greater than 1, the first N shift register is received. The start signal (which can be in phase or different phase) sent by the timing controller, and the timing controller sends at least 2N clock signals. In the previous 2N stage shift register, the i-th stage (i is less than/equal to N) shift register receives the clock signals CKi and CK(i+N), and the transmission signal of the i-th stage shift register Carry is the start signal of the (i+N)th stage shift register, and the output signal Output of the (i+N)th stage shift register is regarded as the reset signal of the i-th stage shift register. In the normal display, 2N clock signals are different phases; in the low (1/N) resolution display, among the 2N clock signals, the first N clock signals have the same phase, and the last N clock signals have The same phase, as such, for the first 2N stage shift register, the output signal Output of the first N stage shift register has the same phase, and the output signal Output of the latter N stage shift register has the same phase.

綜上所述，雖然本發明已以實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧顯示面板 10‧‧‧ display panel

11‧‧‧薄膜電晶體陣列基板 11‧‧‧Film transistor array substrate

12‧‧‧畫素區域 12‧‧‧ pixel area

13‧‧‧掃描線 13‧‧‧ scan line

14‧‧‧GOP驅動電路 14‧‧‧GOP drive circuit

16‧‧‧時序控制器 16‧‧‧Sequence Controller

15‧‧‧外部準位轉換電路 15‧‧‧External level conversion circuit

SR1~SR5‧‧‧移位暫存器 SR1~SR5‧‧‧Shift register

第1圖繪示利用非晶矽閘極技術之顯示面板的示意圖。 FIG. 1 is a schematic view showing a display panel using an amorphous germanium gate technique.

第2圖顯示根據本發明第一實施例之多個移位暫存器之連接關係。 Fig. 2 shows the connection relationship of a plurality of shift registers in accordance with the first embodiment of the present invention.

第3A圖顯示根據本發明第一實施例處於正常解析度顯示模式之時序圖。 Fig. 3A is a timing chart showing the normal resolution display mode according to the first embodiment of the present invention.

第3B圖顯示根據本發明第一實施例處於1/2解析度顯示模式之時序圖。 Fig. 3B is a timing chart showing the display mode in the 1/2 resolution according to the first embodiment of the present invention.

第4圖顯示根據本發明第二實施例之多個移位暫存器之連接關係。 Fig. 4 shows the connection relationship of a plurality of shift registers in accordance with the second embodiment of the present invention.

第5A圖顯示根據本發明第二實施例處於正常解析度顯示模式之時序圖。 Fig. 5A is a timing chart showing the normal resolution display mode according to the second embodiment of the present invention.

第5B圖顯示根據本發明第二實施例處於1/3解析度顯示模式之時序圖。 Fig. 5B is a timing chart showing the display mode in the 1/3 resolution according to the second embodiment of the present invention.

第6圖顯示根據本發明第三實施例之多個移位暫存器之連接關係。 Fig. 6 shows the connection relationship of a plurality of shift registers in accordance with the third embodiment of the present invention.

第7A圖顯示根據本發明第三實施例處於正常解析度顯示模式之時序圖。 Fig. 7A is a timing chart showing the normal resolution display mode according to the third embodiment of the present invention.

第7B圖顯示根據本發明第三實施例處於1/2解析度顯示模式之時序圖。 Fig. 7B is a timing chart showing the display mode in the 1/2 resolution according to the third embodiment of the present invention.

第8圖顯示根據本發明第四實施例之多個移位暫存器之連接關係。 Figure 8 is a diagram showing the connection relationship of a plurality of shift registers in accordance with a fourth embodiment of the present invention.

第9A圖顯示根據本發明第四實施例處於正常解析度顯示模式之時序圖。 Fig. 9A is a timing chart showing the normal resolution display mode according to the fourth embodiment of the present invention.

第9B圖顯示根據本發明第四實施例處於1/4解析度顯示模式之時序圖。 Fig. 9B is a timing chart showing the display mode in the 1/4 resolution according to the fourth embodiment of the present invention.

SR1~SR4‧‧‧移位暫存器 SR1~SR4‧‧‧Shift register

Claims

一種支援雙解析度顯示之顯示裝置，包括：一顯示面板，具有一薄膜電晶體陣列基板；複數條掃描線，形成於該薄膜電晶體陣列基板上；一時序控制器，輸出一起始信號與複數時脈信號；以及一驅動電路，形成於該薄膜電晶體陣列基板上，該驅動電路包括複數個移位暫存器，該些移位暫存器接收該起始信號與該些時脈信號，該些移位暫存器輸出個別第一輸出信號以驅動該些掃描線，該些移位暫存器之一第(i)級移位暫存器輸出一第二輸出信號以起始該些移位暫存器之一第(i+j)級移位暫存器，i與j為正整數且j大於等於2；其中，於低解析度顯示下，該時序控制器輸出相同相位之j個時脈信號以驅動該些移位暫存器之該第(i)級至一第(i+j-1)級移位暫存器，以使得該第(i)級至該第(i+j-1)級移位暫存器所輸出之該些第一輸出信號具有相同相位來驅動相對應掃描線。 A display device supporting dual resolution display, comprising: a display panel having a thin film transistor array substrate; a plurality of scan lines formed on the thin film transistor array substrate; and a timing controller outputting a start signal and a plurality of a clock signal; and a driving circuit formed on the thin film transistor array substrate, the driving circuit includes a plurality of shift registers, the shift registers receiving the start signal and the clock signals, The shift registers output respective first output signals to drive the scan lines, and one of the shift registers (i) stage shift register outputs a second output signal to start the One (i+j)-stage shift register of one of the shift registers, i and j are positive integers and j is greater than or equal to 2; wherein, in the low-resolution display, the timing controller outputs the same phase j Clock signals for driving the (i)th to (i+j-1)th stage shift registers of the shift registers to cause the (i)th to the (i) The first output signals output by the +j-1) stage shift register have the same phase to drive the corresponding scan lines.

如申請專利範圍第1項所述之顯示裝置，其中，該些移位暫存器之該第(i+j)級移位暫存器所輸出之該第一輸出信號更重置該些移位暫存器之該第(i)級移位暫存器。 The display device of claim 1, wherein the first output signal output by the (i+j)th stage shift register of the shift register further resets the shift The (i)th stage shift register of the bit register.

如申請專利範圍第1項所述之顯示裝置，其中，於正常顯示下，該時序控制器輸出不同相位之該些時脈信號，以使得該些移位暫存器之個別第一輸出信號為不同相位。 The display device of claim 1, wherein, in the normal display, the timing controller outputs the clock signals of different phases, so that the individual first output signals of the shift registers are Different phases.

如申請專利範圍第1項所述之顯示裝置，更包括：一外部準位轉換電路。該外部準位轉換電路之一端耦接至該時序控制器，調變該時序控制器所輸出之該起始信號及該些時脈信號；該外部準位轉換電路之另一端耦接至該驅動電路之該些移位暫存器，輸出經調變之該起始信號與該些時脈信號。 The display device according to claim 1, further comprising: An external level conversion circuit. One end of the external level conversion circuit is coupled to the timing controller to modulate the start signal and the clock signals output by the timing controller; the other end of the external level conversion circuit is coupled to the driving The shift registers of the circuit output the modulated start signal and the clock signals.

如申請專利範圍第1項所述之顯示裝置，其中，於1/2解析度顯示下，該些時脈信號至少包括一第一至一第四時脈信號，該些移位暫存器之前兩級移位暫存器接收該起始信號，該些移位暫存器之該第(i)級移位暫存器接收該第一與該第三時脈信號，該些移位暫存器之一第(i+1)級移位暫存器接收該第二與該第四時脈信號，j=2，該第一與該第二時脈信號為同相位，該第三與該第四時脈信號為同相位。 The display device of claim 1, wherein, in the 1/2 resolution display, the clock signals include at least a first to a fourth clock signal, before the shift registers The two-stage shift register receives the start signal, and the (i)th stage shift register of the shift register receives the first and third clock signals, and the shifts are temporarily stored. The (i+1)th stage shift register receives the second and fourth clock signals, j=2, the first and the second clock signals are in phase, and the third and the The fourth clock signal is in phase.

如申請專利範圍第1項所述之顯示裝置，其中，於1/3解析度顯示下，該些時脈信號至少包括一第一至一第六時脈信號，該些移位暫存器之前三級移位暫存器接收該起始信號，該些移位暫存器之該第(i)級移位暫存器接收該第一與該第四時脈信號，該些移位暫存器之一第(i+1)級移位暫存器接收該第二與該第五時脈信號，該些移位暫存器之一第(i+2)級移位暫存器接收該第三與該第六時脈信號，j=3，該第一、該第二與該第三時脈信號為同相位，該第四、該第五與該第六時脈信號為同相位。 The display device of claim 1, wherein, in the 1/3 resolution display, the clock signals include at least a first to a sixth clock signal, before the shift registers The three-stage shift register receives the start signal, and the (i)th stage shift register of the shift register receives the first and fourth clock signals, and the shifts are temporarily stored. The (i+1)th stage shift register receives the second and the fifth clock signals, and the (i+2)th stage shift register of the one of the shift registers receives the The third and the sixth clock signals, j=3, the first, the second and the third clock signals are in phase, and the fourth, fifth and sixth clock signals are in phase.

如申請專利範圍第1項所述之顯示裝置，其中，於1/4解析度顯示下，該些時脈信號至少包括一第一至一第八時脈信號，該些移位暫存器之前四級移位暫存器接收該起始信號，該些移位暫存器之該第(i)級移位暫存器接收該第一與該第五時脈信號，該些移位暫存器之一第(i+1)級移位暫存器接收該第二與該第六時脈信號，該些移位暫存器之一第(i+2)級移位暫存器接收該第三與該第七時脈信號，該些移位暫存器之一第(i+3)級移位暫存器接收該第四與該第八時脈信號，j=4，該第一、該第二、該第三與該第四時脈信號為同相位，該第五、該第六、該第七與該第八時脈信號為同相位。 The display device of claim 1, wherein, in the 1/4 resolution display, the clock signals comprise at least a first to an eighth clock signal, before the shift registers The four-stage shift register receives the start signal, and the (i)th stage shift register of the shift register receives the first and the fifth clock signals, and the shifts are temporarily stored. The (i+1)th stage shift register receives the second and the sixth clock signals, and the (i+2)th stage shift register of the one of the shift registers receives the Third and the seventh clock signal, one of the shift registers, the (i+3)th stage shift register receives the fourth and the eighth clock signals, j=4, the first The second, the third, and the fourth clock signals are in phase, and the fifth, sixth, seventh, and eighth clock signals are in phase.

一種驅動方法，應用於支援雙解析度顯示之一顯示裝置，該驅動方法包括：於正常顯示下，以不同相位之複數時脈信號驅動該顯示裝置之一驅動電路之複數移位暫存器，以使得該些移位暫存器之個別第一輸出信號為不同相位來驅動該顯示裝置之複數掃描線；以及於低解析度顯示下，以相同相位之j個時脈信號驅動該些移位暫存器之該第(i)級至一第(i+j-1)級移位暫存器，以使得該該第(i)級至該第(i+j-1)級移位暫存器所輸出之該些第一輸出信號具有相同相位來驅動相對應掃描線，該些移位暫存器之一第(i)級移位暫存器輸出一第二輸出信號以起始該些移位暫存器之一第(i+j)級移位暫存器，i與j為正整數且j大於等於2，該些移位暫存器之該第(i+j)級移位暫存器所輸出之該第一輸出信號更重置該些移位暫存器之該第(i)級移位暫存器。 A driving method is applied to a display device supporting a dual-resolution display, the driving method comprising: driving a plurality of shift registers of a driving circuit of the display device with a complex clock signal of different phases under normal display, Driving the plurality of scan lines of the display device with different first output signals of the shift registers in different phases; and driving the shifts with j clock signals of the same phase under low resolution display The (i)th to the (i+j-1)th stage of the register shift register, so that the (i)th to the (i+j-1)th shift is temporarily suspended. The first output signals output by the memory have the same phase to drive the corresponding scan lines, and one of the shift registers (i) stage shift register outputs a second output signal to start the One of the shift registers, the (i+j)th stage shift register, i and j are a positive integer and j is greater than or equal to 2, and the first output signal output by the (i+j)th stage shift register of the shift register further resets the shift register (i) Stage shift register.

如申請專利範圍第8項所述之驅動方法，其中，於1/2解析度顯示下，該些時脈信號至少包括一第一至一第四時脈信號，該些移位暫存器之前兩級移位暫存器被該起始信號所起始，該些移位暫存器之該第(i)級移位暫存器接收該第一與該第三時脈信號，該些移位暫存器之一第(i+1)級移位暫存器接收該第二與該第四時脈信號，j=2，該第一與該第二時脈信號為同相位，該第三與該第四時脈信號為同相位。 The driving method of claim 8, wherein, in the 1/2 resolution display, the clock signals include at least a first to a fourth clock signal, before the shift registers The two-stage shift register is started by the start signal, and the (i)th stage shift register of the shift register receives the first and third clock signals, and the shift One (i+1)th stage shift register of the bit register receives the second and fourth clock signals, j=2, and the first and second clock signals are in phase, the first The third phase is in phase with the fourth clock signal.

如申請專利範圍第8項所述之驅動方法，其中，於1/3解析度顯示下，該些時脈信號至少包括一第一至一第六時脈信號，該些移位暫存器之前三級移位暫存器被該起始信號所起始，該些移位暫存器之該第(i)級移位暫存器接收該第一與該第四時脈信號，該些移位暫存器之一第(i+1)級移位暫存器接收該第二與該第五時脈信號，該些移位暫存器之一第(i+2)級移位暫存器接收該第三與該第六時脈信號，j=3，該第一、該第二與該第三時脈信號為同相位，該第四、該第五與該第六時脈信號為同相位。 The driving method of claim 8, wherein, in the 1/3 resolution display, the clock signals include at least a first to a sixth clock signal, before the shift registers a three-stage shift register is started by the start signal, and the (i)th stage shift register of the shift registers receives the first and fourth clock signals, and the shifts The (i+1)th stage shift register of the bit register receives the second and the fifth clock signals, and the (i+2)th stage shift register of one of the shift registers Receiving the third and the sixth clock signals, j=3, the first, the second and the third clock signals are in phase, and the fourth, the fifth and the sixth clock signals are In phase.

如申請專利範圍第8項所述之驅動方法，其中，於1/4解析度顯示下，該些時脈信號至少包括一第一至一第八時脈信號，該些移位暫存器之前四級移位暫存器被該起始信號所起始，該些移位暫存器之該第(i)級移位暫存器接收該第一與該第五時脈信號，該些移位暫存器之一第(i+1)級移位暫存器接收該第二與該第六時脈信號，該些移位暫存器之一第(i+2)級移位暫存器接收該第三與該第七時脈信號，該些移位暫存器之一第(i+3)級移位暫存器接收該第四與該第八時脈信號，j=4，該第一、該第二、該第三與該第四時脈信號為同相位，該第五、該第六、該第七與該第八時脈信號為同相位。 The driving method according to item 8 of the patent application, wherein, under the display of 1/4 resolution, The clock signals include at least a first to an eighth clock signal, and the shift register registers are started by the start signal, and the shift registers are The first (i)th stage shift register receives the first and the fifth clock signals, and the one (i+1)th stage shift register of the shift register receives the second and the a sixth clock signal, wherein one (i+2)th stage shift register of the shift register receives the third and the seventh clock signal, one of the shift registers ( The i+3) stage shift register receives the fourth and the eighth clock signals, j=4, and the first, second, third, and fourth clock signals are in phase, the first 5. The sixth, the seventh and the eighth clock signal are in phase.