TWI429031B - 高壓積體電路、電子裝置、與電路的製程與封裝 - Google Patents

高壓積體電路、電子裝置、與電路的製程與封裝 Download PDF

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Publication number
TWI429031B
TWI429031B TW096103340A TW96103340A TWI429031B TW I429031 B TWI429031 B TW I429031B TW 096103340 A TW096103340 A TW 096103340A TW 96103340 A TW96103340 A TW 96103340A TW I429031 B TWI429031 B TW I429031B
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Taiwan
Prior art keywords
substrate
electronic components
wafer
semiconductor
insulating
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TW096103340A
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English (en)
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TW200816404A (en
Inventor
Laurence P Sadwick
Ruey-Jen Hwu
Mohammad M Mojarradi
Jehn Huar Chern
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Innovate Llc
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Publication of TW200816404A publication Critical patent/TW200816404A/zh
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Publication of TWI429031B publication Critical patent/TWI429031B/zh

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Description

高壓積體電路、電子裝置、與電路的製程與封裝
本發明大致上係關於高壓積體電路(IC)、電子裝置、與高壓電路的製程與封裝。更明確地說，本發明係關於用於製作與製造能夠在數十伏特至數萬伏特的範圍中進行電壓運作之高壓積體電子元件的製程。
高壓積體電路(IC)、電子裝置、與電路具有眾多應用。高壓IC、高壓電子裝置、與電路可用來取代大型的離散電子組件，例如個別的高壓電晶體、電阻器、以及變壓器。此外，可能還會希望將該些大體上為大型的離散高壓組件直接整合在矽之上、整合在一封裝之中、或是整合在印刷電路板(PCB)之上，以便達到更大微型化、更高可靠度、以及更低電力消耗的目的。此等高壓IC、高壓電子裝置、與電路還可藉由去除大量電子組件所必要的至少一些「拾放(pick and place)」作業來縮小目前採用大型電子組件的高壓電子元件的尺寸並且降低其成本。再者，還有機會使用常用於製造積體電路的大量生產設施與製程。
不過，當形成在半導體基板之上時以及當安置在PCB之上時，高壓電子元件卻需要特別注意實際的佈局。這係因為高電壓可能會對鄰近的組件或是電路線路造成電弧，並且從而會導致該等電路故障及/或損壞。崩潰電壓(Vb d )係一電子組件耐受高電壓之能力的常用度量值。具有高崩潰電壓(Vb d )的電子裝置比較能耐受裝置失效。因此，希望在高壓IC、高壓電子裝置與電路之中會具有極高的崩潰電壓(Vb d )。
早期用於整合高壓組件的方式係將重點放在PCB層級。舉例來說，ElHatem等人獲頒的美國專利案第5,699,231號便揭示隔離一具有狹縫或其它削切形狀之PCB上的離散電氣組件，結合該PCB的表面模封，以便防止該電路板之表面上於高壓節點與低壓節點之間發生電荷遷移。該等狹縫或其它削切形狀可讓該模封材料在該電路板與該等電子裝置附近流動並且流過該電路板與該等電子裝置。不過，ElHatem等人所揭示的方式卻僅能在PCB層級達到較大的密度。
已經有人採取其它的方式來製造高壓IC。舉例來說，Mojaradi等人獲頒的美國專利案第5,382,826號便揭示藉由堆疊任意數量的低壓電晶體來整合一高壓電晶體。如Mojaradi等人所獲頒的專利案中所揭示者，可以使用螺旋狀與星狀的電場板來改變等位電場線的空間配置，用以防止電壓集中。Mojaradi等人還進一步揭示，藉由以串聯組態的方式來堆疊數個裝置，便可提高該電路的電壓範圍。不過，此等串聯堆疊組態通常需要用到高壓電阻器，用於經由一分壓網路以及其它構件來正確地施加閘極電壓偏壓。即使在已整合的形式中，高壓電阻器的體積仍然非常龐大。因此，如果一製程同樣可輕易地提供高壓電阻器用以施加高壓電晶體偏壓以及用於其它應用中的話，將會特別有利。
Hu等人獲頒的美國專利案第4,908,328號則揭示一種用於形成一氧化物隔離半導體晶圓的製程，其可包含形成一相關的高壓電晶體。Hu等人所提出的製程包含：利用氧化物將一第一晶圓黏接至一第二晶圓；形成一貫穿氧化物的溝槽；以及利用一經過磊晶再成長的半導體來進行回填，以便擺設該等高壓裝置。不過，Hu等人似乎並未揭示如何在一基板上形成個別的電路、如何分離該基板上的該等個別電路、如何對一模組進行切晶處理(dicing)使其成為該等分離的個別電路、如何隔離該模組、如何在該模組上進行連接、以及如何進行回填用以進一步隔離該等個別的電路並且用以達到高崩潰電壓(Vb d )的目的。
用於封裝高壓電晶體的另一種方式則揭示在Mojaradi等人獲頒的美國專利案第5,577,617號之中。更明確地說，該’617號專利揭示的係使用一導線架來安置多個個別電晶體且同時隔離基板，用以在單一封裝中達成複數個可電堆疊的高壓電晶體的目的。該’617號專利還揭示，利用一隔離環氧樹脂來包封被安置在該等晶粒安置片上的該等晶粒則可達成進一步隔離的目的。該包封會提供進一步絕緣效果，因為該包封劑的介電常數大於空氣的介電常數。
ElHatem等人獲頒的美國專利案第5,739,582號則揭示一種將多個高壓裝置封裝在一多晶片模組之中的方法。更明確地說，該’582號專利揭示於一封裝的凹腔中安置任何數量的高壓晶片，將該等高壓裝置電連接在一起並且將該等高壓裝置電連接至一導線架。該’582號專利還進一步揭示使用三種塗劑來提供進一步隔離。首先，會塗敷一非導體的環氧樹脂，用於將該等裝置安置在該凹腔層。接著，則會將一聚亞醯胺或DupontT M PyraluxT M 薄層塗敷至每一個該等裝置的向下側處。最後，則會將一由Q1－6646 HipecT M Gel晶粒塗佈材料所組成的晶粒塗劑塗敷至每一個晶片的向上側處，用以抑制電弧。不過，該’582號專利卻警示必須使用所有三種塗佈材料(聚亞醯胺68、晶粒塗佈材料70、以及非導體的環氧樹脂72)方能達到並且承受該等極高的運作電壓。即使該等塗佈材料中僅缺少其中一者，或是僅有其中一者有缺陷，該封裝所能夠承受的電壓會大幅地下滑，而且該等部件的可靠度將會嚴重地降低。(參見該專利的第6至11頁，第二段，第4行)
據此，本技術中仍然需要一種用於整合低壓電子裝置的製程與封裝，以便形成高壓積體電路、高壓電子裝置與電路。
本文揭示一種用於整合電子元件的製程的一實施例。該項製程可包含提供一具有複數個電子元件的半導體。該項製程可進一步包含提供一絕緣體，以及將該半導體黏接至該絕緣體或是利用該絕緣體來塗佈該半導體。該項製程可進一步包含對該等電子元件進行開槽處理(trenching)，以便在該半導體上以物理的方式來彼此分離該等電子元件。該項製程可進一步包含對該等經過開槽的電子元件進行切晶處理，用以形成至少一絕緣模組。該項製程可進一步包含將該至少一絕緣模組附接至一晶片載板，並且將該至少一絕緣模組電連接至該晶片載板，用以達成一積體電路。
本文還揭示一種用於整合電子元件的製程的另一實施例。該項製程可包含提供一另外含有複數個電子元件的半導體基板。該項製程可進一步包含將一聚亞醯胺層或是其它的絕緣層塗敷至該半導體基板。該項製程可進一步包含對該等電子元件進行開槽處理，用以形成複數個經過開槽的電子元件，以及對該等經過開槽的電子元件進行切晶處理，用以形成至少一絕緣模組。該項製程可進一步包含將該至少一絕緣模組附接至一晶片載板，並且將該至少一絕緣模組電連接至該晶片載板，用以達成一積體電路。
本文還揭示一種用於封裝積體電路的方法的一實施例。該製程可包含提供一經過處理的半導體晶圓，其上製作著複數個電子元件。該方法可進一步包含視情況來研磨該經過處理的半導體晶圓，以便縮減厚度。該方法可進一步包含對該經過處理的半導體晶圓進行切晶處理，以便以物理的方式將該等電子元件分離成複數個晶粒。該方法可包含將該等晶粒黏接至一電子元件封裝。該方法可包含相互電連接該等晶粒並且將該等晶粒電連接至該電子元件封裝。該方法可包含回填該等晶粒之間與附近的間隙以及密封該電子元件封裝，以便提供一經過封裝的積體電路。
本文揭示一種根據本發明之用於覆晶封裝積體電路的方法的一實施例。該方法可包含提供一經過處理的半導體晶圓，其會在一電子元件側上製作著複數個電子元件並且在一基板側上具有本體半導體。該方法可進一步包含視情況來研磨該基板側，以便縮減厚度。該方法可進一步包含將一堆疊晶圓黏接至該基板側，並且對該電子元件側進行底層凸塊(under－bump)金屬化處理。該方法可進一步包含對該經過處理的半導體晶圓進行切晶處理，以便以物理的方式將該等電子元件分離成複數個晶粒，以及將該等晶粒中至少其中一者分離成一電子元件模組。該方法可進一步包含將該電子元件模組覆晶黏接至一覆晶載板。該方法可進一步包含利用一絕緣體來塗佈該電子元件模組，並且視情況來對該電子元件模組與該覆晶載板之間的間隙進行底層填充。
現在將參考本發明實施例的圖式，其中，本文會針對相同的結構提供相同的參考代表符號。當然，該等圖式僅係本發明之示範性實施例的示意圖以及概略代表圖，而且，它們既未限制本發明，也並未必然依照比例來繪製或顯示。
圖1A至1E所示的係根據本發明使用絕緣體來封裝複數個積體電路的製程的一實施例。下文所揭示的製程可利用複數個個別電晶體來達成極高的崩潰電壓，舉例來說，數千伏特。根據圖1A至1E中所示之製程所構成的積體電路特別適用於具有高崩潰電壓(Vb d )的高壓電子元件。
現在參考圖1A，一半導體100可具備複數個電子元件，如圖中102處所示者。該半導體100可能係由矽、鍺、砷化鎵、氮化鎵、碳化矽、鑽石、其它III/V族的半導體化合物、或是任何其它合宜的半導體材料所構成。再者，半導體100可構成晶圓或基板。該等電子元件102可以是希望隔離電路系統中之個別組件或模組的任何合宜的電子電路，舉例來說(但是並不具任何限制意義)，形成在半導體100之表面中的一電路以及某些電晶體或是眾多電晶體、或是眾多電路、或是高壓電晶體。該等電子元件102可以是相同的電子電路、個別獨特的電子電路、或是兩者的任何組合。該等電子元件102可針對任何合宜的功能或用途，利用任何合宜的半導體製程來形成。圖1A還顯示出一絕緣體104。絕緣體104可以是任何合宜的絕緣材料，舉例來說(但是並不具任何限制意義)，陶瓷、玻璃、或是矽。
圖1B所示的係利用一黏著劑106來將半導體100黏接至該絕緣體104。該黏著劑106可以是適合用於將複數個電子組件黏接在一起的任何非導電的黏著劑。舉例來說(但是並不具任何限制意義)，可購自位於美國明尼蘇達州聖保羅市3M公司的各種合宜的半導體黏著劑材料，其包含黏接薄膜與膠帶、光固化與環氧樹脂黏著劑。其它合宜的黏接技術則可包含熟習本技術的人士所熟知的陽極黏接法以及矽/SiO2 黏接法。
圖1C所示的係用於以物理方式來彼此分離該半導體上之該等高壓電子元件或是對該等高壓電子元件進行「開槽」處理的示意圖。開槽可利用任何合宜的方法來達成，舉例來說(但是並不具任何限制意義)，濕式蝕刻、乾式蝕刻、蒸汽蝕刻、氣體蝕刻、電漿蝕刻、以及深反應離子蝕刻(DRIE)，用以根據本發明製程之實施例在該等組件之間產生複數條空氣間隙或溝槽108(圖1C中顯示出四條溝槽)。可用來進行開槽的特殊濕式蝕刻溶液係乙二胺－焦兒茶醇－水(ethylenediamine－pyrocatechol－water)溶液(EDP)。EDP溶液會沿著矽的晶軸來蝕刻矽。
為縮短實施開槽所需要的時間，可利用熟習本技術的人士所熟知的任何合宜的晶圓薄化製程來薄化該半導體100。根據本發明的實施例，薄化可在開槽之前或之後來實施。應該注意的係，開槽、鋸切、及/或切晶可各自單獨使用或是結合使用，以便根據本文所揭示之製程的實施例來達成與實現更高壓的裝置。
必要的話，可利用一合宜的絕緣材料來進一步回填或塗佈由開槽所形成的該等空氣間隙或溝槽108。回填可包含利用下面的方法來沉積高介電崩潰材料，舉例來說(但是並不具任何限制意義)：網印法、噴墨法、微加工法、化學氣相沉積法(CVD)、以及物理氣相沉積法(PVD)。
本發明希望最小化任何兩個相鄰電子元件102島狀部之間的間隔(溝槽寬度)，以便最小化整體的積體電路尺寸。因此，30 μ m或更窄的溝槽寬度係本發明所希望的溝槽寬度。空氣的介電強度範圍係從約33KVAC/cm至57KVAC/cm。所以，當島狀部之間沒有導體介質時，30至50 μ m的空氣間隙(溝槽108)便不可能耐受1200V以及更高的電壓偏壓。所以，根據本發明實施例，較佳的係，利用一高介電的崩潰成型化合物來回填空氣間隙或溝槽108。有各種回填材料適用於本發明的製程，舉例來說(但是並不具任何限制意義)，聚對二甲苯(Parylene)(也就是，N型、C型、與D型聚對二甲苯，有時候亦稱為「Paralyne」)；以及氰基丙烯酸酯(Super GlueT M 的化學名稱)。聚對二甲苯係一種特有的聚合物保形塗劑，其實際上可適應於任何形狀，該等形狀包含裂縫、點、尖銳的邊緣、以及平坦外露的內表面。舉例來說，N型聚對二甲苯的介電強度為7000V/mil。因此，N型聚對二甲苯特別適合作為寬度範圍在10至50 μ m之中的溝槽的回填材料。可利用已知的製程將N型聚對二甲苯真空沉積在電子元件的表面上以及半導體晶圓的表面上。
回填溝槽108亦可利用對該等電子元件102與溝槽108進行保形塗佈來達成。保形塗佈是一個將一介電材料噴灑在一裝置組件之上，尤其是用以保護該裝置組件，使其不會遭到濕氣、菌類、灰塵、腐蝕、磨損、以及其它環境應力的破壞之製程。舉例來說(但是並不具任何限制意義)，適合用來填入該等溝槽108之中的常見保形塗劑包含：矽樹脂、丙烯酸樹脂、胺基甲酸乙酯、環氧樹脂、以及聚對二甲苯。該些塗劑通常能夠提高介電崩潰電壓。藉由對該等溝槽108進行開槽與回填而以物理方式來分離該等電子元件102，那麼該等電子元件102的其中一者的運作會不經意地影響其它鄰近電子元件102之運作的機會便會比較小。再者，相較於單獨進行開槽，開槽再加上回填所提高的崩潰電壓(Vb d )通常會比較大。
圖1D所示的係對該已黏接的半導體100與絕緣體104進行晶粒分離或者「切晶」以便形成一絕緣模組110的示意圖。舉例來說(但是並不具任何限制意義)，該絕緣模組110可以是一電路，其具有任何合宜數量之低壓電晶體或高壓電晶體或是任何合宜數量之電子電路以實施任何選定功能。如熟習本技術的人士所知者，晶粒分離製程係將一半導體晶圓切割(通常如間隙111所示)成複數個晶粒(晶片)，每一者均包含一完整的半導體裝置或電路。切晶可在完成裝置(離散裝置與積體裝置)製作之後來施行。於大直徑半導體的情況中，利用一具有超薄鑽石刀片的高精密切晶機沿著較佳的結晶面來部份切割該晶圓便可進行晶圓切晶。雖然圖1D中僅顯示出單一個絕緣模組110，不過，熟習本技術的人士將很容易明白，可從原始已黏接的半導體100與絕緣體104中分離出多個絕緣模組110。可利用適合用來對電子組件進行切晶的任何方法來實施切晶。
圖1E所示的係根據本發明之晶粒附接以及銲線以便形成一積體電路114的示意圖。晶粒附接是一個將該絕緣模組110附接至一晶片載板112的製程。舉例來說，可利用上面針對黏接該半導體100與絕緣體104所討論的任何黏著劑來達成晶粒附接。可利用任何合宜的晶片載板技術或架構來形成該晶片載板112。圖1E中所示的晶片載板112可包含一晶片載板基板116以及一或多條導線118(圖1E中顯示出兩條)。
銲線是一個可相互連接該絕緣模組110中的電子電路102，並且將該絕緣模組110中的電子電路102連接至外部的晶片載板112的製程。如圖1E中所示，可利用複數條電線122(圖1E中顯示出四條)來將該絕緣模組110連接至晶片載板112上的導線118，或是用來交互連接形成於該半導體100之中的複數個電子元件102。舉例來說，可利用熟習半導體製作技術的人士所熟知的任何合宜方法來實施該銲線作業。再者，圖中雖然以銲線處理作為將該絕緣模組110(晶粒)電連接至該晶片載板112的方法，不過，熟習本技術的人士將很容易瞭解，根據本發明，亦可使用其它合宜的方法來將該晶粒電連接至該晶片載板112，舉例來說，覆晶裝配。
一旦附接該晶粒且該絕緣模組110被電連接(舉例來說，使用銲線技術或覆晶技術)至該晶片載板112之後，在該絕緣模組110與該晶片載板112之間便可能會有複數個空氣間隙120。此時，可於本製程中利用保形塗佈(如上面所討論)來密封該積體電路114。為清楚表示起見，圖1A至1E中並未顯示出保形塗佈、鈍化、包封、或是用來密封該積體電路114的其它方式，不過，在使用之前，通常必須用到上面的作業來完成封裝該積體電路114。當回填溝槽108已經蓋住該絕緣模組110之表面上的電氣墊(圖中並未顯示)時，那麼在進行銲線之前便必須藉由移除該保形塗劑來製備該等墊。無論如何，該經過銲線處理的積體電路114通常會需要保形塗劑。
該些晶片載板112(或封裝)可以是任何合宜的商用封裝，舉例來說(但是並不具任何限制意義)，其包含具有各種導線組態的塑膠封裝或陶瓷封裝。不過，晶片載板112的導線間的間隔(導線間距)通常必須大於低壓封裝的導線間的間隔。舉例來說，約1000V的高壓運作通常會用到範圍在約200 μ m至約400 μ m之中的導線間距。或者，倘若利用一具有標準墊間隔的習知低壓封裝來達成約1000V高壓運作的話，則可使用該封裝中位於該低壓接腳相反側中的高壓接腳。當然，為解釋本發明新穎的方法，本文僅提供解釋性範例，而且該等範例並不具任何限制意義。
電子元件102可能會依照任何合宜的製程而具備任何所希的形式或功能。高壓電子電路特別適用於根據本發明用來整合電子元件之製程的本實施例。不過，本文所述之製程並不僅限於高壓電子元件。該電子元件102中用來形成該絕緣模組110所包含的必要電晶體與電路的數量可能會依據用來製造該絕緣模組110的低壓電晶體與電路及高壓電晶體與電路的所希的運作電壓以及其運作電壓而定。當希望一能夠運作在高電壓處的絕緣模組110係由低壓電晶體與電路所組成時，便可能必須用到以串聯、並聯、或是任何其它組態來運作之較高數量的低壓電晶體與電路，方能達到該高壓運作的目的。
圖2A至2D所示的係根據本發明使用聚亞醯胺絕緣材料來整合複數個電子元件(尤其是高壓電子元件)的製程的另一實施例。聚亞醯胺原本係由DuPontT M 所開發出來的一種塑膠(一種合成的聚合樹脂)，其非常耐用、易於加工、而且能夠處置非常高的溫度。聚亞醯胺的絕緣性亦非常地高，而且不會污染其周圍環境，也就是，在正常的運作條件下並不會除氣。VespelT M 與KaptonT M 均係可購自DuPontT M 的示範性聚亞醯胺產品。
現在參考圖2A，圖中所示的係一其中會形成複數個電子元件(大體上如102處所示)的半導體基板200，在其下方則具有一厚的聚亞醯胺層203。該半導體基板200與該聚亞醯胺層203會共同形成一絕緣晶圓(大體上如205處所示)。該半導體基板200可能係由矽或任何其它半導體材料所構成，例如上面針對圖1A至1E所列舉的材料。該絕緣的聚亞醯胺層203可以用熟習半導體製作技術的人士所熟知的任何合宜方式被塗敷至該半導體基板200，舉例來說(但是並不具任何限制意義)，微機電系統技術(MEMS)、微製作技術、微加工技術、網印技術、噴墨技術、熱沉積技術、化學氣相沉積技術、物理氣相沉積技術、以及任何其它合宜的技術。
圖2B所示的係一具有複數個電子元件102的示範性絕緣晶圓205的剖面圖，該等電子元件102已經過開槽處理或者藉由溝槽108以物理的方式被分離。開槽可利用上面針對圖1C所述者來實施。亦可對該等溝槽108套用如上面所述的保形塗佈或回填處理，以便進一步隔離且提高該等電子元件102的崩潰電壓(Vb d )。
圖2C所示的係用於對該絕緣晶圓205進行切晶處理以獲得複數個絕緣模組210(圖2C中僅顯示出一個)的剖面圖。同樣地，可利用任何合宜的切晶方法來實施該切晶作業，舉例來說，上面參考圖1D所述的方法。切晶可在完成裝置(離散裝置與積體裝置)製作之後來施行。於大直徑半導體的情況中，利用一具有超薄鑽石刀片的高精密切晶機沿著較佳的結晶面來部份切割該晶圓便可實施晶圓切晶。雖然圖2C中僅顯示出單一個絕緣模組210，不過，熟習本技術的人士便很容易明白，可從原始的絕緣晶圓205中分離出多個絕緣模組210。另外，根據另一實施例亦可使用多層絕緣層。可利用熟習本技術的人士所熟知之適合用來切晶、蝕刻、或是分離電子組件的任何方法來對絕緣模組210實施切晶與分離。
圖2D所示的係將該絕緣模組210晶粒附接以及銲線至一晶片載板112以便形成一積體電路214的示意圖。同樣地，該晶片載板112可能係任何合宜的晶片載板，舉例來說，如上面參考圖1E所述者。同樣地，可利用任何合宜的構件來實施銲線，如電線122所示者，用以彼此交互連接該等電子元件102以及將該等電子元件102連接至該晶片載板112上的導線118。最後，則可對該積體電路214進行保形塗佈、回填、包封、或是其它的密封作業(圖2A至2D中並未顯示)，以便在使用之前填充該等空氣間隙120並且對該封裝進行拋光處理。為提高產品的可靠度，重要的係必須利用特定種類的絕緣體來鈍化該等焊線。聚對二甲苯以及氰基丙烯酸酯(Super GlueT M 的化學名稱)均係特別適合作為鈍化材料的範例。在經過鈍化之後，便可實施最終的塑膠或陶瓷封裝步驟。
回填與鈍化可利用適合用來提高崩潰電壓，同時縮減島狀部間隔(溝槽寬度)的其它材料來達成，例如介電強度非常高(數百kV/cm至~1MV/cm甚至更高)的光阻材料。舉例來說(但是並不具任何限制意義)，各種可圖案化聚合物包含可購自眾多來源(其包含位於美國麻薩諸塞州紐頓市的Micro－Chem)的SU－8(一種以環氧樹脂為主的負向光阻)以及聚甲基丙烯酸甲酯(PMMA)，以及同樣可購自眾多來源的聚二甲基矽氧烷(PDMS)。SU－8、PMMA、以及PDMS全部具有極高的介電強度。舉例來說，PDMS的介電強度據報導為210KV/cm。PDMS同樣非常適合用來將塑膠材料黏接至一矽晶圓。位於日本的Sumitomo Chemical則係額外成型化合物的另一來源，其可能適合根據本發明用來進行回填。
下面表1所示的係針對兩種溝槽寬度以及針對兩種回填材料(也就是，空氣間隙(沒有任何介電回填)以及氰基丙烯酸酯(Super GlueT M ))和崩潰電壓(Vb d )有關的實驗資料。
本文所揭示的製程特別適用於整合複數個低壓電子裝置來形成高壓IC、高壓電子裝置、與電路。圖3所示的係適合藉由上面所述之製程來進行整合的一示範性高壓電路的電路圖，明確地說，圖中所示的係一具有複數個堆疊的低壓電晶體(如虛線方塊302中所示)的高壓電流源300。
根據本發明的另一項特點係在一電晶體的漂移區上方形成複數個高阻值的的多晶矽(poly)電阻器。舉例來說，當配合本發明新穎的製程來使用一習知的互補金屬氧化物半導體(CMOS)製作過程時，可將一高阻值的的多晶矽電阻器放置在一電晶體的漂移區上方。此多晶矽電阻器係充當一分散電場板，因此會提高該電晶體的崩潰電壓。此多晶矽電阻器還可充當一用於所要的積體電路的高壓堆疊的電阻器元件，而且該電阻器並不需要用到額外的面積。
現在將參考圖4A至4F來詳細討論根據本發明用於整合複數個電子元件的製程的另一實施例。圖4A所示的係已經過處理而將複數個電子元件102引入基板404的表面402之中的已完成的半導體晶圓的剖面圖，大體上係由箭頭400A所示。舉例來說(但是並不具任何限制意義)，該半導體晶圓400A可以是一經過CMOS處理的晶圓，或是根據任何習知的半導體製程處理之後的任何其它半導體晶圓。
圖4B所示的係一經過薄化的晶圓的剖面圖，大體上係由箭頭400B所示。藉由研磨、蝕刻、或是熟習本技術的人士所熟知之用於薄化一半導體晶圓的任何其它合宜的方式來從已完成的半導體晶圓400A中移除多餘的基板材料便可獲得薄化晶圓400B。舉例來說，將一研磨膠帶塗敷至該等電子元件102所在的表面402處並且利用研磨劑來將基板404的反向側406研磨至一合宜的厚度便可達成薄化的目的。
圖4C所示的係一受到支撐的晶圓的剖面圖，大體上係由箭頭400C所示。藉由將一支撐基板408或是一電子元件封裝(圖中並未顯示)附接至薄化晶圓400B的反向側406便可獲得受到支撐的晶圓400C。可以使用黏著劑或任何其它合宜的構件來將支撐基板408附接至薄化晶圓400B的反向側406。支撐基板408可以是一絕緣基板或介電基板，用以進一步隔離電子元件102。
圖4D所示的係一經過切晶的晶圓的剖面圖，大體上係由箭頭400D所示。藉由鋸切、蝕刻、或是用於以物理方式來將複數個電子元件102彼此分離的任何其它合宜的方式來對形成在該受到支撐的晶圓400C之上的複數個電子元件102進行切晶處理，便可獲得經過切晶的晶圓400D，不過，如本文所揭示且熟習本技術的人士亦熟知的係，該等電子元件102仍然會在支撐基板408上受到支撐。
圖4E所示的係一經過交互連接的晶圓的剖面圖，大體上係由箭頭400E所示。電子元件102之間的交互連接線以及連接至一用於封裝的晶片載板(圖4E中並未顯示，不過請參見圖4F以及下文的相關討論)的交互連接線的形式可以是如圖4E中所示的焊線410。不過，用於達成電子元件102與封裝(圖4E中並未顯示)間之電交互連接的任何合宜的構件均涵蓋在本發明的範疇內。
圖4F所示的係一經過安置的晶圓的剖面圖，大體上係由箭頭400F所示。藉由將經過交互連接的晶圓400E安置在一晶片載板412或是其它電子元件封裝(圖中並未顯示)之上便可獲得經過安置的晶圓400F。應該注意的係，圖4E中所示之交互連接作業亦可在圖4F中所示之安置作業後面來實施。任何合宜的黏著劑或黏著膠帶均可用來將經過交互連接的晶圓400E安置在晶片載板412之上。最後，便可利用一保形塗劑來回填、鈍化、及/或密封該經過安置的晶圓，並且將其封裝成一積體電路，如上所述。
現在將參考圖5A至5F來詳細討論根據本發明用於整合複數個電子元件的製程的又一實施例。圖5A所示的係已經過處理而將複數個電子元件102引入一基板504的頂表面502之中的一已完成的半導體晶圓的剖面圖，大體上係由箭頭500A所示。舉例來說(但是並不具任何限制意義)，該半導體晶圓500A可以是一經過CMOS處理的晶圓(如圖4A中所示的400A)，或是根據任何習知的半導體製程處理之後的任何其它半導體晶圓。
圖5B所示的係一受到支撐的晶圓的剖面圖，大體上係由箭頭500B所示。藉由將一支撐基板508附接至半導體晶圓500A的頂表面502便可獲得受到支撐的晶圓500B。可以使用黏著劑或任何其它合宜的構件來將支撐基板508附接至半導體晶圓500A的頂表面502。支撐基板508可以是一絕緣基板或介電基板，用以進一步隔離電子元件102。
圖5C所示的係一經過薄化的晶圓的剖面圖，大體上係由箭頭500C所示。藉由研磨、蝕刻、或是熟習本技術的人士所熟知之用於薄化一半導體晶圓的任何其它合宜的方式來從受到支撐的晶圓500B中移除多餘的基板504材料便可獲得經過薄化的晶圓500C。舉例來說，將一研磨膠帶塗敷至該受到支撐的晶圓500B的反向側506並且利用研磨劑來將基板504研磨至一合宜的厚度便可達成薄化的目的。應該注意的係，根據另一實施例，圖5C中所示的晶圓薄化作業亦可在圖5B中所示之將該支撐基板508(如圖5B中所示)附接至半導體晶圓500A的正面處之前便先完成。
圖5D所示的係一經過切晶的晶圓的剖面圖，大體上係由箭頭500D所示。藉由倒置(翻轉)經過薄化的晶圓500C並且藉由鋸切、蝕刻、或是用於以物理方式來將複數個電子元件102彼此分離的任何其它合宜的方式來對形成在該經過薄化的晶圓500C之上的複數個電子元件102進行切晶處理，從而引入複數條間隙416，便可獲得經過切晶的晶圓500D。應該明白的係，如本文所揭示且熟習本技術的人士亦熟知，該等經過切晶處理的電子元件102仍然可在支撐基板508上受到支撐。
圖5E所示的係一經過交互連接的晶圓的剖面圖，大體上係由箭頭500E所示。電子元件102之間的交互連接線以及連接至一用於封裝的晶片載板(圖5E中並未顯示，不過請參見圖5F以及下文的相關討論)的交互連接線的形式可能係如圖5E中所示的焊線410。不過，用於達成電子元件102與封裝(圖5E中並未顯示)間之電交互連接的任何合宜的構件均涵蓋在本發明的範疇內。根據另一實施例，可根據上面所述的方法與材料來對間隙416進行回填、鈍化、或是保形塗佈(圖5E中並未顯示)，以便進一步隔離電子元件102並且穩定焊線410。
圖5F所示的係一經過安置的晶圓的剖面圖，大體上係由箭頭500F所示。藉由將經過交互連接的晶圓500E安置在一晶片載板412之上便可獲得經過安置的晶圓500F。應該注意的係，圖5E中所示之交互連接作業亦可在圖5F中所示之安置作業後面來實施。任何合宜的黏著劑或黏著膠帶均可用來將經過交互連接的晶圓500E安置在晶片載板412之上。最後，便可利用一保形塗劑來回填、鈍化、或是密封該經過安置的晶圓，並且將其封裝成一積體電路，如上所述。
現在將參考圖6A至6E來詳細討論根據本發明用於整合複數個電子元件的製程的又一實施例。圖6A所示的係已經過處理而將複數個電子元件102引入一基板604的頂表面602之中的一已完成的半導體晶圓的剖面圖，大體上係由箭頭600A所示。舉例來說(但是並不具任何限制意義)，該半導體晶圓600A可以是一經過CMOS處理的晶圓，或是根據任何習知的半導體製程處理之後的任何其它半導體晶圓。
圖6B所示的係一經過圖案化之受到支撐的晶圓的剖面圖，大體上係由箭頭600B所示。藉由附接一經過圖案化之支撐基板608便可獲得經過圖案化之受到支撐的晶圓600B，該支撐基板608在半導體晶圓600A的頂表面602相鄰處具有複數條經過圖案化的交互連接線614。可以使用黏著劑或任何其它合宜的構件來將經過圖案化的支撐基板608附接至半導體晶圓600A的頂表面602。支撐基板608可以是一絕緣基板或介電基板，用以進一步隔離電子元件102。不過，亦可利用複數條交互連接線來圖案化經過圖案化的支撐基板608，用以選擇性地彼此交互連接複數個電子元件102。
圖6C所示的係一經過薄化的晶圓的剖面圖，大體上係由箭頭600C所示。藉由研磨、蝕刻、或是熟習本技術的人士所熟知之用於薄化一半導體晶圓的任何其它合宜的方式來從經過圖案化之受到支撐的晶圓600B中移除多餘的基板604材料便可獲得經過薄化的晶圓600C。舉例來說，將一研磨膠帶塗敷至該經過圖案化之受到支撐的晶圓600B的反向側606處並且利用研磨劑來將基板604研磨至一合宜的厚度便可達成薄化的目的。應該注意的係，根據另一製程實施例，圖6C中所示的晶圓薄化作業亦可在圖6B中所示之將該經過圖案化之支撐基板608(如圖6B中所示)附接至半導體晶圓600A的正面處之前便先完成。
圖6D所示的係一經過切晶的晶圓的剖面圖，大體上係由箭頭600D所示。藉由鋸切、蝕刻、或是用於以物理方式來將複數個電子元件102彼此分離的任何其它合宜的方式來對形成在該經過薄化的晶圓600C之上的複數個電子元件102進行切晶處理，便可獲得經過切晶的晶圓600D。應該明白的係，如本文所揭示且熟習本技術的人士亦熟知的係，該等經過切晶的電子元件102仍然會在支撐基板608上受到支撐。一旦形成該經過切晶的晶圓600D之後，便可利用一保形塗劑來對其進行回填、鈍化、或是密封，以便填入由圖6D中所示之切晶製程所形成的間隙416之中。應該注意的係，圖6D中並未顯示出該項回填作業。
圖6E所示的係一經過安置的晶圓的剖面圖，大體上係由箭頭600E所示。藉由將經過切晶的晶圓600D安置在一晶片載板412之上便可獲得經過安置的晶圓600E。應該注意的係，亦可實施額外的交互連接作業(圖6E中並未顯示)，用以將經過切晶的晶圓600D電連接至該晶片載板412。任何合宜的黏著劑或黏著膠帶均可用來將經過切晶的晶圓600D安置在晶片載板412之上。最後，便可利用一保形塗劑來回填、鈍化、或是密封該經過安置的晶圓，並且將其封裝成一積體電路，即如上所述者。
現在將參考圖7A至7E來詳細討論根據本發明用於整合複數個電子元件的製程的再一實施例。圖7A所示的係已經過處理而將複數個電子元件102引入一基板704的頂表面702之中的一已完成的半導體晶圓的剖面圖，大體上係由箭頭700A所示。半導體晶圓700A可進一步包含形成在頂表面702之上的複數條多晶矽電阻器交互連接線714，用以選擇性地彼此交互連接複數個電子元件102。舉例來說(但是並不具任何限制意義)，該半導體晶圓700A可以是一經過CMOS處理的晶圓，或是根據任何習知的半導體製程處理之後的任何其它半導體晶圓。
圖7B所示的係一受到支撐的晶圓的剖面圖，大體上係由箭頭700B所示。藉由將一支撐基板708附接至半導體晶圓700A的頂表面702便可獲得受到支撐的晶圓700B。在又一實施例中，可如同圖6B至6E中所示之經過圖案化的交互連接線614般地利用複數條交互連接線來進一步圖案化支撐基板708，用以進一步交互連接複數個電子元件102。經過圖案化的交互連接線614可由任何合宜的導體材料所構成，舉例來說(但是並不具任何限制意義)，鋁、金、以及鉑。再者，經過圖案化的交互連接線614亦可依照熟習本技術的人士所熟知的任何合宜的沉積製程來形成。可在將支撐基板708附接至該半導體晶圓700A之前先對齊位於支撐基板708之上的經過圖案化的交互連接線614。
可以使用黏著劑或任何其它合宜的構件來將支撐基板708附接至半導體晶圓700A的頂表面702。支撐基板708可以是一絕緣基板或介電基板，用以進一步隔離電子元件102。不過，如上面所述，根據另一實施例，亦可利用複數條交互連接線614來選擇性地圖案化支撐基板708，用以選擇性地彼此交互連接複數個電子元件102。
圖7C所示的係一經過薄化的晶圓的剖面圖，大體上係由箭頭700C所示。藉由研磨、蝕刻、或是熟習本技術的人士所熟知之用於薄化一半導體晶圓的任何其它合宜的方式來從受到支撐的晶圓700B中移除多餘的基板704材料便可獲得薄化晶圓700C。舉例來說，將一研磨膠帶塗敷至該受到支撐的晶圓700B的反向側706並且利用研磨劑來將基板704研磨至一合宜的厚度便可達成薄化的目的。應該注意的係，根據另一實施例，圖7C中所示的晶圓薄化作業亦可在圖7B中所示之將該支撐基板708(如圖7B中所示)附接至半導體晶圓700A的正面處之前便先完成。
圖7D所示的係一經過切晶的晶圓的剖面圖，大體上係由箭頭700D所示。藉由鋸切、蝕刻、或是用於以物理方式來將複數個電子元件102彼此分離以便引入間隙416的任何其它合宜的方式來對形成在該經過薄化的晶圓700C之上的複數個電子元件102進行切晶處理，便可獲得經過切晶的晶圓700D。應該明白的係，如本文所揭示且熟習本技術的人士亦熟知的係，該等經過切晶的電子元件102仍然會在支撐基板708上受到支撐。一旦形成該經過切晶的晶圓700D之後，便可利用一保形塗劑來對其進行回填、鈍化、或是密封，以便填入由圖7D中所示之切晶製程所形成的間隙416之中。應該注意的係，圖7D中並未顯示出該項回填作業。
圖7E所示的係一經過安置的晶圓的剖面圖，大體上係由箭頭700E所示。藉由將經過切晶的晶圓700D安置在一晶片載板412之上便可獲得經過安置的晶圓700E。應該注意的係，亦可實施額外的交互連接作業(圖7E中並未顯示)，用以將經過切晶的晶圓700D電連接至該晶片載板412。任何合宜的黏著劑或黏著膠帶均可用來將經過切晶的晶圓700D安置在晶片載板412之上。最後，便可利用一保形塗劑來進一步回填、鈍化、或是密封該經過安置的晶圓，並且將其封裝成一積體電路，即如上所述者。
圖8所示的係根據本發明用於封裝複數個IC的方法800的一示範性實施例的流程圖。方法800可包含提供802一經過處理的半導體晶圓，其上製作著複數個電子元件。如上所述，根據本發明實施例，該半導體晶圓可以是由任何合宜的半導體材料所構成，舉例來說(但是並不具任何限制意義)，矽、鍺、砷化鎵、氮化鎵、碳化矽、鑽石、其它III/V族的半導體化合物、或是任何其它合宜的半導體材料。電子元件可經由任何合宜的電子元件製程來形成，舉例來說，包含CMOS製程。
方法800可進一步包含視情況來研磨804該經過處理的半導體晶圓，以便縮減厚度。研磨804該經過處理的半導體晶圓可包含塗敷研磨膠帶至該經過處理的晶圓的一電子元件側處，並且研磨該經過處理的晶圓的一反向側，舉例來說，請參見圖9B以及下文相關討論的研磨膠帶956。
方法800可進一步包含對該經過處理的半導體晶圓進行切晶處理806，以便以物理的方式將該等電子元件分離成複數個晶粒。切晶806可利用任何熟知的切晶方法來實施。舉例來說(但是並不具任何限制意義)，對該經過處理的半導體晶圓進行切晶處理806可包含塗敷切晶膠帶至該經過處理的半導體晶圓的一基板側上並且對該等電子元件之間的區域進行鑽石尖頭鋸切作業。
方法800可進一步包含將該等晶粒黏接808至一電子元件封裝。將該等晶粒黏接808至一電子元件封裝可包含使用下面任何一或多者：非導電的環氧樹脂、黏著劑、黏著膠帶、熱黏接、共熔黏接、矽/SiO2 黏接、陽極黏接、或是用於將電子元件晶粒附接至一電子元件封裝的任何其它合宜的黏著劑或方法。該電子元件封裝可以是任何合宜的材料與組態。舉例來說(但是並不具任何限制意義)，該電子元件封裝可以是由陶瓷材料所構成，並且會被配置成熟習本技術的人士所熟知的框帽組件。
方法800可進一步包含相互電連接810該等晶粒並且將該等晶粒電連接至該電子元件封裝。舉例來說，請參見圖9E中所示以及下文與本文其它地方所討論的銲線作業。方法800可進一步包含回填812該等晶粒之間與附近的間隙，以及密封814該電子元件封裝，以便提供一經過封裝的積體電路。藉由塗敷聚對二甲苯或是氰基丙烯酸酯或是任何其它合宜的回填材料便可完成回填812。密封814可包括完全地回填該電子元件封裝。或者，一旦已經達到回填來塗佈該等被電連接的晶粒之後，便可排空該電子元件封裝內的剩餘空間或腔室，以便提高崩潰電壓；或者可利用氮來填充該電子元件封裝內的剩餘空間或腔室，以便改善散熱特徵。
圖9A至9G所示的係對應於(圖8中所示之)方法800的一特殊實施例的一系列製程。更明確地說，圖9A所示的係一經過處理的半導體晶圓952的剖面圖。半導體晶圓952在一半導體基板954的其中一側上可能會形成一電子元件層902。
圖9B所示的係一已經視情況經過薄化之經過處理的半導體晶圓960的剖面圖。藉由塗敷一研磨膠帶956至基板954的電子元件902側並且依照用於薄化半導體晶圓的任何熟知方法來薄化反向側或基板側954，便可達到選配性薄化的目的。圖9C所示的係一已經過切晶處理之經過處理的半導體晶圓的剖面圖。更明確地說，圖9C所示的係一經過切晶的晶圓966，其含有六個晶粒962，該等晶粒962係藉由在該等晶粒962之間創造間隙964而形成的。根據各實施例，塗敷切晶膠帶968至該半導體基板954然後進行鑽石尖頭鋸切作業或是套用熟習本技術的人士所熟知的任何其它合宜的切晶方法，便可實施切晶作業。
圖9D所示的係在擺放於一半導體封裝上之前，對該等晶粒中之一者所實施的拾放作業的剖面圖。更明確地說，圖9D所示的拾放工具頭正透過晶粒膠帶968向上推移(參見遭到釋放的晶粒962附近的箭頭)，以便釋放一晶粒962用以擺放在一半導體封裝上。
圖9E所示的係安置該等晶粒962以及彼此電連接該等晶粒962與將該等晶粒962電連接至該半導體封裝。更明確地說，圖9E顯示出有兩個晶粒962已經被黏接978至一電子元件封裝(圖9E中並未完全顯示，不過可參見圖9G中的980)的底表面972。該底表面972可形成一層絕緣材料973。絕緣材料973可以是由聚亞醯胺或是任何其它合宜的絕緣材料(例如本文中所揭示的前述材料)所構成。電子元件封裝980可以是任何合宜的封裝材料並且可具有適合用來接納晶粒962的組態與技術。黏接978可利用非導電的環氧樹脂、黏著劑、黏著膠帶、熱黏接、共熔黏接、矽/SiO2 黏接、陽極黏接、或是本文中所揭示之用於將電子元件晶粒附接至一電子元件封裝的任何其它合宜的黏著劑或方法來達成。圖9E還顯示出使用焊線974來相互電連接該等晶粒962並且將該等晶粒962電連接至該電子元件封裝的導線架(圖中部份顯示在976處)。
圖9F所示的係回填982圖9E之該等經過電連接的晶粒962。更明確地說，圖9F所示的係使用一被塗敷至該等經過電連接的晶粒962之裸露表面的回填材料982。此回填材料還會進一步彼此隔離該等晶粒962，以便達到更高的崩潰電壓。
圖9G所示的係密封988該電子元件封裝980的剖面圖，用以提供一經過封裝的IC，大體上係由箭頭990所示。更明確地說，圖9G所示的係一具有一帽部986的框帽組件(FLA)，該帽部986具有複數個密封體988，該等密封體可藉由熱、電流、或是其它方法來活化。帽部986可由任何合宜的材料所構成，舉例來說(但是並不具任何限制意義)，「Alloy 42」或是「KovarT M 」。KovarT M 係Westinghouse的一種產品商標，其為鐵、鎳、與鈷的合金，該合金和玻璃具有相同的熱膨脹係數，所以，通常會用於玻璃至金屬密封或陶瓷至金屬的密封。
圖9G還顯示出電子元件封裝980內安置著且包封著982該等晶粒962的腔室984可能未被完全填充。根據本發明其中一實施例，密封該電子元件封裝980可包含在密封988該帽部986之前先於該腔室984之中引入氮氣。充滿氮氣的電子元件封裝980會具有良好的導熱特徵。根據另一實施例，可在密封988該帽部986之前先排空該腔室984。該腔室984之中的真空會提供更高的崩潰電壓特徵。
圖10所示的係根據本發明用於覆晶封裝複數個積體電路的方法1000的一實施例的流程圖。方法1000可包含提供1002一經過處理的半導體晶圓，其會在一電子元件側上製作著複數個電子元件並且在一基板側上具有本體半導體。方法1000可進一步包含視情況來研磨1004該基板側，以便縮減厚度。方法1000可進一步包含將一堆疊的晶圓黏接1006至該基板側。方法1000可進一步包含對該電子元件側進行底層凸塊金屬化處理1008。方法1000可進一步包含對該經過處理的半導體晶圓進行切晶處理1010，以便以物理的方式將該等電子元件分離成複數個晶粒。方法1000可進一步包含將該等晶粒中的至少一者分離1012成一電子元件模組。方法1000可進一步包含將該電子元件模組覆晶黏接1014至一覆晶載板。方法1000可進一步包含利用一絕緣體來塗佈1016該電子元件模組。方法1000可進一步包含視情況來對該電子元件模組與該覆晶載板之間的間隙進行底層填充1018。
根據其中一實施例，將該堆疊的晶圓黏接至該基板側可包含在該堆疊晶圓與該基板側之間塗敷一可熱密封的聚亞醯胺膠帶。不過，用於黏接該堆疊的晶圓的任何合宜的方法均可配合本發明的原理來運用。根據再一實施例，該堆疊的晶圓可以是由CorningT M 產品代號為7740的硼矽酸鹽玻璃所構成。不過，應該明白的係，配合在該經過處理之半導體晶圓的覆晶黏接中提供一非導電絕緣基板作為一堆疊的晶圓的目的，亦可運用其它形式與材料的堆疊的晶圓。
根據另一實施例，該覆晶載板可以是一印刷電路板。根據其它實施例，該覆晶載板可以是使用熟習本技術的人士所熟知之覆晶技術的任何合宜的IC封裝。再者，利用一絕緣體來塗佈該電子元件模組可包含利用聚對二甲苯、氰基丙烯酸酯、或是本文所揭示之任何其它合宜的絕緣塗劑來塗佈該電子元件模組。
雖然在本文中所解釋的本發明實施例已經清楚地顯示出本發明的前述優點，不過，亦可對本發明的組態、設計、以及結構進行各種改變而仍可達到該些優點。所以，本文中和本發明的結構與功能相關的具體細節僅具示範效果，並不具任何限制意義。
100．．．半導體
102．．．電子元件
104．．．絕緣體
106．．．黏著劑
108．．．溝槽
110．．．絕緣模組
111．．．間隙
112．．．晶片載板
114．．．積體電路
116．．．晶片載板基板
118．．．導線
120．．．空氣間隙
122．．．電線
200．．．半導體基板
203．．．聚亞醯胺層
205．．．絕緣晶圓
210．．．絕緣模組
214．．．積體電路
300．．．高壓電流源
302．．．低壓電晶體
400A．．．半導體晶圓
400B．．．經過薄化的晶圓
400C．．．受到支撐的晶圓
400D．．．經過切晶的晶圓
400E．．．經過交互連接的晶圓
400F．．．經過安置的晶圓
402．．．基板404的表面
404．．．基板
406．．．基板404的反向側
408．．．支撐基板
410．．．焊線
412．．．晶片載板
416．．．間隙
500A．．．半導體晶圓
500B．．．受到支撐的晶圓
500C．．．經過薄化的晶圓
500D．．．經過切晶的晶圓
500E．．．經過交互連接的晶圓
500F．．．經過安置的晶圓
502．．．基板504的頂表面
504．．．基板
506．．．受到支撐的晶圓500B的反向側
508．．．支撐基板
600A．．．半導體晶圓
600B．．．經過圖案化之受到支撐的晶圓
600C．．．經過薄化的晶圓
600D．．．經過切晶的晶圓
600E．．．經過安置的晶圓
602．．．基板604的頂表面
604．．．基板
606．．．經過圖案化之受到支撐的晶圓600B的反向側
608．．．支撐基板
614．．．交互連接線
700A．．．半導體晶圓
700B．．．受到支撐的晶圓
700C．．．經過薄化的晶圓
700D．．．經過切晶的晶圓
700E．．．經過安置的晶圓
702．．．基板704的頂表面
704．．．基板
706．．．受到支撐的晶圓700B的反向側
708．．．支撐基板
714．．．多晶矽電阻器交互連接線
902．．．電子元件
952．．．半導體晶圓
954．．．半導體基板
956．．．研磨膠帶
960．．．經過薄化的半導體晶圓
962．．．晶粒
964．．．間隙
966．．．經過切晶的晶圓
968．．．晶粒膠帶
972．．．電子元件封裝980的底表面
973．．．絕緣材
974．．．焊線
976．．．導線架
978．．．黏接
980．．．電子元件封裝
982．．．回填材料
984．．．腔室
986．．．帽部
988．．．密封體
990．．．經過封裝的積體電路
下面圖式係描繪用於實現本發明的示範性實施例。該等圖式中之本發明的不同圖面或實施例中相同的元件符號代表相同的部件。
圖1A至1E所示的係根據本發明使用一絕緣體來整合複數個電子元件的製程的一實施例。
圖2A至2D所示的係根據本發明使用一厚的聚亞醯胺層來整合複數個電子元件的製程的一實施例。
圖3所示的係適合利用根據本發明之製程來進行整合的一示範性高壓電路的電路圖，明確地說，該高壓電路係一具有複數個堆疊的高壓電晶體的高壓電流源。
圖4A至4F所示的係根據本發明用於整合複數個電子元件的製程的另一實施例。
圖5A至5F所示的係根據本發明用於整合複數個電子元件的製程的又一實施例。
圖6A至6E所示的係根據本發明用於整合複數個電子元件的製程的再一實施例。
圖7A至7E所示的係根據本發明用於整合複數個電子元件的製程的另一實施例。
圖8所示的係根據本發明用於封裝複數個積體電路的方法的一示範性實施例的流程圖。
圖9A至9G所示的係對應於圖8之方法的一特殊實施例的一系列製程。
圖10所示的係根據本發明用於覆晶封裝複數個積體電路的方法的一實施例的流程圖。
100．．．半導體
102．．．電子元件
104．．．絕緣體
106．．．黏著劑
108．．．溝槽
110．．．絕緣模組
111．．．間隙
112．．．晶片載板
114．．．積體電路
116．．．晶片載板基板
118．．．導線
120．．．空氣間隙
122．．．電線

Claims (24)

  1. 一種用於整合電子元件的製程，其係包括：提供一含有複數個電子元件的半導體；提供至少一絕緣體；將該半導體黏接至該至少一絕緣體；對該等電子元件進行開槽處理，以便該等電子元件在實體上彼此分離；對該等經過開槽的電子元件進行切晶處理以形成至少一絕緣模組，其中該至少一絕緣模組包括至少一未切晶的溝槽；將該至少一絕緣模組附接至一晶片載板；以及讓該至少一絕緣模組上的該等電子元件彼此電連接為跨於該至少一未切晶的溝槽，並且將該等電子元件電連接至該晶片載板以達成一積體電路。
  2. 如申請專利範圍第1項之製程，其進一步包括回填該等經過開槽的電子元件。
  3. 如申請專利範圍第2項之製程，其中，回填係包括使用下面至少其中一者來沉積高介電崩潰材料：網印法、噴墨法、微加工法、微機電系統(MEMS)技術、化學氣相沉積法(CVD)、以及物理氣相沉積法(PVD)。
  4. 如申請專利範圍第2項之製程，其中，回填係包括塗敷聚對二甲苯或氰基丙烯酸酯。
  5. 如申請專利範圍第1項之製程，其進一步包括保形塗佈該積體電路。
  6. 如申請專利範圍第1項之製程，其中，保形塗佈係包括塗敷聚對二甲苯。
  7. 如申請專利範圍第1項之製程，其中，提供一半導體係包括提供下面至少其中一者：矽基板、鍺基板、砷化鎵基板、氮化鎵基板、III/V族化合物基板、以及碳化矽基板。
  8. 如申請專利範圍第1項之製程，其中，提供該絕緣體係包括提供下面至少其中一者：鑽石基板、陶瓷基板、玻璃基板、矽基板、石英基板、藍寶石基板、塑膠基板、樹脂基板、以及聚亞醯胺層。
  9. 如申請專利範圍第1項之製程，其中，將該半導體基板黏接至該絕緣體係包括使用一黏著劑或黏著膠帶。
  10. 如申請專利範圍第1項之製程，其中，將該半導體基板黏接至該絕緣體係包括位於一矽基板上的二氧化矽。
  11. 如申請專利範圍第1項之製程，其中，開槽係包括下面至少其中一者：濕式蝕刻、乾式蝕刻、以及深反應離子蝕刻(DRIE)。
  12. 如申請專利範圍第1項之製程，其中，切晶係包括利用一鑽石尖頭鋸來進行鋸切。
  13. 如申請專利範圍第1項之製程，其中，將該至少一絕緣模組附接至該晶片載板係包括利用下面至少其中一者來將該至少一絕緣模組附接至一晶片載板基板：黏著劑、熱黏接、共熔黏接、矽/SiO2 黏接、以及陽極黏接。
  14. 如申請專利範圍第1項之製程，其中，將該至少一絕緣模組附接至該晶片載板係包括將該至少一絕緣模組附 接至一覆晶組件。
  15. 如申請專利範圍第1項之製程，其中，讓該至少一絕緣模組上的該等電子元件彼此電連接並且將該等電子元件電連接至該晶片載板係包括進行銲線。
  16. 一種用於整合電子元件的製程，其係包括：提供一另外含有複數個電子元件的半導體基板；將一絕緣層塗敷至該半導體基板；對該等電子元件進行開槽處理，用以形成複數個經過開槽的電子元件；對該等經過開槽的電子元件進行切晶處理，用以形成至少一絕緣模組，其中該至少一絕緣模組包括至少一未切晶的溝槽；將該至少一絕緣模組附接至一晶片載板；以及讓該至少一絕緣模組的該等電子元件彼此電連接並且將該等電子元件電連接至該晶片載板，用以達成一積體電路。
  17. 如申請專利範圍第16項之製程，其中，將一絕緣層塗敷至該半導體基板係包括將下面至少其中一者塗敷至該半導體基板：聚亞醯胺、陶瓷、玻璃、矽、以及石英。
  18. 如申請專利範圍第16項之製程，其中，提供一半導體基板係包括提供一由下面至少其中一者所構成的基板：矽、鍺、砷化鎵、碳化矽、氮化鎵、鑽石、或是III/V族化合物。
  19. 如申請專利範圍第16項之製程，其中，對該等電子 元件進行開槽處理係包括下面至少其中一者：濕式蝕刻、乾式蝕刻、或是深反應離子蝕刻(DRIE)。
  20. 如申請專利範圍第16項之製程，其中，對該等經過開槽的電子元件進行切晶處理係包括利用一鑽石尖頭鋸片來進行鋸切。
  21. 如申請專利範圍第16項之製程，其中，將該至少一絕緣模組附接至一晶片載板係包括使用下面至少其中一者：黏著劑或覆晶組件。
  22. 如申請專利範圍第16項之製程，其中，電連接該至少一絕緣模組係包括進行銲線。
  23. 如申請專利範圍第16項之製程，其進一步包括利用聚對二甲苯或氰基丙烯酸酯來回填溝槽。
  24. 如申請專利範圍第16項之製程，其進一步包括保形塗佈該積體電路。
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