TWI427973B - Flexray transmitter - Google Patents
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Description
本揭示內容是有關於一種FlexRay電路，且特別是有關於一種FlexRay發射電路。The present disclosure is directed to a FlexRay circuit, and more particularly to a FlexRay transmit circuit.
近年來，車用網路通訊協定FlexRay蓬勃發展，相關系統技術已愈趨成熟。此標準協定主要是針對先進自動化控制應用而訂的通訊系統，可提供高傳輸速率、備援傳輸通道。目前，FlexRay已逐漸取代串列控制網路(Control Area Network,CAN)，大有成為線傳控制系統(X-by-wire)車輛應用主要技術之趨勢。In recent years, FlexRay, a vehicle network communication protocol, has flourished and related system technologies have become more mature. This standard protocol is primarily a communication system for advanced automation control applications that provides high transmission rates and redundant transmission channels. At present, FlexRay has gradually replaced the Control Area Network (CAN), which has become the main technology of X-by-wire vehicle applications.
具體而言，由於車用電控應用需要具備確定性、容錯性及支援分布式控制系統的高速匯流排系統，因此非常適合採用FlexRay技術。FlexRay可使汽車發展成百分之百的電控系統，進而減低後備機械系統的支援需求。然而，目前FlexRay產品體積較大且售價頗高。在封裝化的FlexRay產品中，首推飛利浦(Philips)公司所生產之FlexRay晶片組型號TJA1080；但是，此晶片組係採用雙載子接面電晶體(Bipolar Junction Transistor,BJT)及複雜且不公開之電路設計，來符合FlexRay對於通訊協定的規範。In particular, because automotive electronic control applications require deterministic, fault-tolerant, and high-speed bus systems that support distributed control systems, FlexRay technology is well suited. FlexRay enables the car to develop into a 100% electronic control system, thereby reducing the support requirements of the backup mechanical system. However, FlexRay products are currently large and expensive. Among the packaged FlexRay products, the FlexRay chipset model TJA1080 produced by Philips is the first; however, this chipset uses Bipolar Junction Transistor (BJT) and is complex and undisclosed. The circuit is designed to comply with FlexRay's specifications for communication protocols.
因此，目前市面上尚無公開技術，探討如何設計一電路架構，以符合FlexRay之通訊協定規格。Therefore, there is currently no open technology on the market to explore how to design a circuit architecture to comply with FlexRay's protocol specifications.
因此，本揭示內容之一技術態樣是在提供一種FlexRay發射器，且其係以CMOS邏輯閘實現之，較市面上之產品製造成本低廉且低功耗。Therefore, one aspect of the present disclosure is to provide a FlexRay transmitter, which is implemented by a CMOS logic gate, which is cheaper to manufacture and lower in power consumption than commercially available products.
依據本揭示內容一實施方式，提出一種FlexRay發射器，包含一第一發射器及一第二發射器。第一發射器包含一第一CMOS電流鏡及一第一傳輸閘。第一發射器之第一傳輸閘係用以根據一第一狀態編碼，決定是否使第一發射器之第一CMOS電流鏡產生一電流，以提供一正壓差給一匯流排之第一端，且同時提供一負壓差給匯流排之第二端。第二發射器亦包含一第二CMOS電流鏡及一第二傳輸閘。第二發射器之第二傳輸閘係用以根據一第二狀態編碼，決定是否使第二發射器之第二CMOS電流鏡產生一電流，以提供一負壓差給匯流排之第一端，且同時提供一正壓差給匯流排之第二端。According to an embodiment of the present disclosure, a FlexRay transmitter is provided, including a first transmitter and a second transmitter. The first transmitter includes a first CMOS current mirror and a first transmission gate. The first transmission gate of the first transmitter is configured to determine whether to cause a current of the first CMOS current mirror of the first emitter to generate a positive voltage difference according to a first state encoding to provide a positive voltage difference to the first end of the busbar And simultaneously providing a negative pressure difference to the second end of the bus bar. The second transmitter also includes a second CMOS current mirror and a second transmission gate. The second transmission gate of the second transmitter is configured to determine whether to generate a current by the second CMOS current mirror of the second emitter according to a second state encoding to provide a negative voltage difference to the first end of the bus bar. At the same time, a positive pressure difference is provided to the second end of the bus bar.
藉此，本揭示內容之FlexRay發射器，可以符合車用網路通訊協定之規格，且實現低成本及低功耗之產品。Thereby, the FlexRay transmitter of the present disclosure can meet the specifications of the vehicle network communication protocol and realize low cost and low power consumption products.
請參考第1圖，第1圖係本揭示內容一實施方式之 FlexRay發射器的結構示意圖。第1圖中，FlexRay發射器100主要包含一第一發射器110及一第二發射器130。第一發射器110包含一第一CMOS電流鏡111及一第一傳輸閘112。第一發射器110之第一傳輸閘112係用以根據一第一狀態編碼，決定是否使第一發射器110之第一CMOS電流鏡111產生一電流，以提供一正壓差給一匯流排120之第一端121，且同時提供一負壓差給匯流排120之第二端122。第二發射器130亦包含一第二CMOS電流鏡131及一第二傳輸閘132。第二發射器130之第二傳輸閘132係用以根據一第二狀態編碼，決定是否使第二發射器130之第二CMOS電流鏡131產生一電流，以提供一負壓差給匯流排120之第一端121，且同時提供一正壓差給匯流排120之第二端122。Please refer to FIG. 1 , which is an embodiment of the present disclosure. Schematic diagram of the FlexRay transmitter. In FIG. 1 , the FlexRay transmitter 100 mainly includes a first transmitter 110 and a second transmitter 130. The first transmitter 110 includes a first CMOS current mirror 111 and a first transmission gate 112. The first transmission gate 112 of the first transmitter 110 is configured to determine whether to generate a current by the first CMOS current mirror 111 of the first transmitter 110 according to a first state code to provide a positive voltage difference to a bus. The first end 121 of the 120 is simultaneously provided with a negative pressure differential to the second end 122 of the bus bar 120. The second transmitter 130 also includes a second CMOS current mirror 131 and a second transmission gate 132. The second transmission gate 132 of the second transmitter 130 is configured to determine whether to generate a current by the second CMOS current mirror 131 of the second transmitter 130 according to a second state code to provide a negative voltage difference to the bus bar 120. The first end 121 and a positive pressure difference are simultaneously provided to the second end 122 of the bus bar 120.
具體而言，在FlexRay的通訊協定中，要求輸入資料訊號為兩組電位邏輯相反的訊號，亦即資料傳輸狀態下第一狀態編碼與第二狀態編碼的電位邏輯須相反，以確保訊號的正確性。當第一狀態編碼與第二狀態編碼分別為一高邏輯電位與一低邏輯電位時，表示此FlexRay發射器100可以依據輸入訊號，產生兩組同樣電位邏輯相反的訊號。而當第一狀態編碼與第二狀態編碼同為高電位或同為低電位時，表示此輸入訊號並不可靠或FlexRay發射器100處於閒置狀態，FlexRay發射器100不應依據此一對輸入訊號，產生有意義的輸出電位訊號。這是因為在車用電子中，電路所承受的電磁干擾、漏電干擾、接地位準飄移等負面因素，遠較一般靜置於固定環境之電路為高。Specifically, in the FlexRay communication protocol, the input data signal is required to be two groups of potential logic opposite signals, that is, the first state code and the second state coded potential logic in the data transmission state must be opposite to ensure the correct signal. Sex. When the first state code and the second state code are respectively a high logic potential and a low logic potential, it indicates that the FlexRay transmitter 100 can generate two sets of signals with the same potential logic opposite according to the input signal. When the first state code and the second state code are both high or low, it indicates that the input signal is not reliable or the FlexRay transmitter 100 is in an idle state, and the FlexRay transmitter 100 should not rely on the pair of input signals. , produces a meaningful output potential signal. This is because in the vehicle electronics, the negative factors such as electromagnetic interference, leakage interference, and grounding level drift of the circuit are much higher than those of the circuit that is normally placed in a fixed environment.
因此，細究本實施方式之FlexRay發射器100，可以清楚知悉如下操作規則：當第一傳輸閘112與第二傳輸閘132收到邏輯相反的第一狀態編碼與第二狀態編碼時，若第一狀態編碼代表驅動第一CMOS電流鏡111映射一電流到匯流排120，則第二狀態編碼代表不驅動第二CMOS電流鏡131映射一電流到匯流排120。此時，第一發射器110便提供一正壓差給匯流排120之第一端121，且同時提供一負壓差給匯流排120之第二端122。換句話說，匯流排120的輸出電位訊號為電位邏輯相反的第一端121高電位邏輯與第二端122低電位邏輯，記作(1,0)。Therefore, the FlexRay transmitter 100 of the present embodiment can be clearly aware of the following operational rules: when the first transmission gate 112 and the second transmission gate 132 receive the first state code and the second state code that are opposite in logic, if the first The state code represents driving the first CMOS current mirror 111 to map a current to the bus bar 120, and the second state code represents not driving the second CMOS current mirror 131 to map a current to the bus bar 120. At this time, the first transmitter 110 provides a positive pressure difference to the first end 121 of the bus bar 120 and simultaneously provides a negative voltage difference to the second end 122 of the bus bar 120. In other words, the output potential signal of the bus bar 120 is the first potential of the potential logic opposite to the high potential logic and the low potential logic of the second terminal 122, which is denoted as (1, 0).
而當第一傳輸閘112與第二傳輸閘132所收到之輸入訊號為第一狀態編碼代表不驅動第一CMOS電流鏡111映射一電流到匯流排120，而第二狀態編碼代表驅動第二CMOS電流鏡131映射一電流到匯流排120時；第二發射器130便提供一正壓差給匯流排120之第二端122，且同時提供一負壓差給匯流排120之第一端121，記作(0,1)。When the first transmission gate 112 and the second transmission gate 132 receive the input signal, the first state code represents not driving the first CMOS current mirror 111 to map a current to the bus bar 120, and the second state code represents the driving second. The CMOS current mirror 131 maps a current to the bus bar 120; the second transmitter 130 provides a positive voltage difference to the second terminal 122 of the bus bar 120, and simultaneously provides a negative voltage difference to the first end 121 of the bus bar 120. , recorded as (0,1).
至於其他不工作狀態或受干擾狀態，皆會使第一發射器110之第一電流鏡111與第二發射器130之第二電流鏡131同時映射電流或不映射電流到匯流排120，則匯流排120之第一端121與第二端122自然不會產生一組邏輯電位相反的輸出電位訊號。As for the other non-operating state or the disturbed state, the first current mirror 111 of the first emitter 110 and the second current mirror 131 of the second emitter 130 simultaneously map current or do not map current to the bus bar 120, and then confluence The first end 121 and the second end 122 of the row 120 naturally do not generate a set of output potential signals having opposite logic potentials.
綜上所述，本實施方式之FlexRay發射器100即可符合車用網路通訊協定FlexRay之規格要求。In summary, the FlexRay transmitter 100 of the present embodiment can meet the specifications of the automotive network protocol FlexRay.
請繼續參考第2圖，第2圖是第1圖之匯流排120的 電路圖。第2圖中，匯流排120更包括一第一電阻123、一偏壓電源124及一第二電阻125。此處係提供一可行之匯流排120的設計方式，以使前述第一CMOS電流鏡111及第二CMOS電流鏡131所映射之電流可以轉換為正壓差或負壓差於匯流排120之第一端121與第二端122上；而非用以限制本實施方式之FlexRay發射器100在匯流排120設計上的其他可行態樣。Please continue to refer to FIG. 2, which is the bus bar 120 of FIG. Circuit diagram. In FIG. 2, the bus bar 120 further includes a first resistor 123, a bias power source 124, and a second resistor 125. Here, a feasible bus bar 120 is provided in such a manner that the current mapped by the first CMOS current mirror 111 and the second CMOS current mirror 131 can be converted into a positive pressure difference or a negative voltage difference in the bus bar 120. One end 121 and second end 122; rather than limiting other possible aspects of the FlexRay emitter 100 of the present embodiment in the design of the busbar 120.
具體而言，當第一發射器110驅動第一CMOS電流鏡111產生映射電流時，一映射電流由節點a流經第一電阻123到達偏壓電源124，使第一端121之電位高於偏壓電源124一壓差，此即所謂正壓差。與此同時，第一CMOS電流鏡111亦產生一映射電流，從偏壓電源124經第二電阻125流向節點c，而使第二端122之電位低於偏壓電源124一壓差，此即所謂負壓差。有趣的是，透過電路上的匹配設計，上述兩組映射電流可實為同一股電流。相同地，透過電路上的匹配設計，正壓差之絕對值可以等於負壓差之絕對值。Specifically, when the first emitter 110 drives the first CMOS current mirror 111 to generate a mapping current, a mapping current flows from the node a through the first resistor 123 to the bias power source 124, so that the potential of the first terminal 121 is higher than the bias voltage. The pressure source 124 has a pressure difference, which is called a positive pressure difference. At the same time, the first CMOS current mirror 111 also generates a mapping current from the bias power source 124 to the node c via the second resistor 125, so that the potential of the second terminal 122 is lower than the voltage difference of the bias power source 124. The so-called negative pressure difference. Interestingly, the two sets of mapped currents can be the same current through the matching design on the circuit. Similarly, the absolute value of the positive pressure difference can be equal to the absolute value of the negative pressure difference through the matching design on the circuit.
值得注意的是，此時第二發射器130不可同時驅動第二CMOS電流鏡131，使節點b與節點d有電流通過；否則第一端121與第二端122便無法產生穩定的正壓差與負壓差，以及所謂第一狀態編碼與第二狀態編碼需互為電位邏輯相反的訊號。It should be noted that, at this time, the second emitter 130 cannot simultaneously drive the second CMOS current mirror 131 to pass the current between the node b and the node d; otherwise, the first end 121 and the second end 122 cannot generate a stable positive pressure difference. The negative voltage difference, and the so-called first state code and the second state code, are mutually opposite to each other.
另一方面，第二發射器130的作動方式，與前述第一發射器110相同；其差異僅在於當第二發射器130作動時，映射電流由節點d流入第二端122，且由節點b流出第一 端121，而使正負壓差易位。On the other hand, the second transmitter 130 operates in the same manner as the first transmitter 110 described above; the difference is only that when the second transmitter 130 is actuated, the mapping current flows from the node d to the second terminal 122, and is caused by the node b. Outflow first End 121, and the positive and negative pressure differences are translocated.
請繼續參考第3圖，第3圖是第1圖之傳輸閘的電路圖。具體而言，為了利用CMOS電路實現FlexRay發射器100，使其具有平衡的電路特性，除了電流鏡可採CMOS電流鏡以外，第一傳輸閘112及第二傳輸閘132亦可採用CMOS傳輸閘140之電路結構。換句話說，CMOS傳輸閘140可由一個N型場效電晶體141與一個P型場效電晶體142所組成。P型場效電晶體142的源極與N型場效電晶體141之汲極共點，P型場效電晶體142的汲極與N型場效電晶體141之源極共點。Please continue to refer to Figure 3, which is a circuit diagram of the transmission gate of Figure 1. Specifically, in order to implement the FlexRay transmitter 100 by using a CMOS circuit to have balanced circuit characteristics, the first transmission gate 112 and the second transmission gate 132 may also adopt a CMOS transmission gate 140 in addition to the current mirror CMOS current mirror. The circuit structure. In other words, the CMOS transfer gate 140 can be composed of an N-type field effect transistor 141 and a P-type field effect transistor 142. The source of the P-type field effect transistor 142 is co-located with the drain of the N-type field effect transistor 141, and the drain of the P-type field effect transistor 142 is co-located with the source of the N-type field effect transistor 141.
接下來，請參考第4圖，第4圖是第1圖之CMOS電流鏡的電路圖。第一發射器110之第一CMOS電流鏡111及第二發射器130之第二CMOS電流鏡131，皆可採用第4圖所繪示之結構設計。具體而言，CMOS電流鏡150是由一個PMOS電流源151及一個NMOS電流槽152所組成，且受控於前述CMOS傳輸閘140。由於第一發射器110與第二發射器130皆為CMOS電路設計方式，本實施方式之FlexRay發射器100較諸飛利浦所用之BJT電路省電且低製作成本。Next, please refer to FIG. 4, which is a circuit diagram of the CMOS current mirror of FIG. 1. The first CMOS current mirror 111 of the first emitter 110 and the second CMOS current mirror 131 of the second emitter 130 can adopt the structural design shown in FIG. Specifically, the CMOS current mirror 150 is composed of a PMOS current source 151 and an NMOS current sink 152, and is controlled by the aforementioned CMOS transmission gate 140. Since both the first transmitter 110 and the second transmitter 130 are in a CMOS circuit design manner, the FlexRay transmitter 100 of the present embodiment saves power and has a lower manufacturing cost than the BJT circuit used by Philips.
最後，請參考第5圖，第5圖是第1圖之詳細電路圖。第五圖中，第一發射器110之PMOS電流源包括一第一P型場效電晶體M1及一第二P型場效電晶體M5，第一P型場效電晶體M1之源極電性連接一電壓源Vdd，其閘極與其汲極共點，且其汲極電性連接傳輸閘112。傳輸閘112則由N型場效電晶體M2與P型場效電晶體M3所組成。 第二P型場效電晶體M5之源極電性連接電壓源Vdd，其閘極與第一P型場效電晶體M1之閘極共點，且其汲極電性連接第一端121。Finally, please refer to Figure 5, which is a detailed circuit diagram of Figure 1. In the fifth figure, the PMOS current source of the first transmitter 110 includes a first P-type field effect transistor M1 and a second P-type field effect transistor M5, and the source of the first P-type field effect transistor M1 A voltage source Vdd is connected to the gate, and its gate is co-located with its drain, and its drain is electrically connected to the transmission gate 112. The transfer gate 112 is composed of an N-type field effect transistor M2 and a P-type field effect transistor M3. The source of the second P-type field effect transistor M5 is electrically connected to the voltage source Vdd, and the gate thereof is co-located with the gate of the first P-type field effect transistor M1, and the gate is electrically connected to the first end 121.
第一發射器110之NMOS電流槽包括一第一N型場效電晶體M4及一第二N型場效電晶體M6。第一N型場效電晶體M4之源極接地，其汲極與其閘極共點，且其汲極電性連接傳輸閘112。第二N型場效電晶體M6之閘極與第一N型場效電晶體M4之閘極共點，其源極接地，其汲極電性連接第二端122。The NMOS current slot of the first emitter 110 includes a first N-type field effect transistor M4 and a second N-type field effect transistor M6. The source of the first N-type field effect transistor M4 is grounded, its drain is co-located with its gate, and its drain is electrically connected to the transfer gate 112. The gate of the second N-type field effect transistor M6 is co-located with the gate of the first N-type field effect transistor M4, the source thereof is grounded, and the drain is electrically connected to the second end 122.
同理，第二發射器130之PMOS電流源包括一第一P型場效電晶體m1及一第二P型場效電晶體m5(注意其位置)，第一P型場效電晶體m1之源極電性連接電壓源Vdd，其閘極與其汲極共點，且其汲極電性連接傳輸閘132。第二P型場效電晶體m5之源極電性連接電壓源Vdd，其閘極與第一P型場效電晶體m1之閘極共點，且其汲極電性連接第二端122，而非第一端121。Similarly, the PMOS current source of the second emitter 130 includes a first P-type field effect transistor m1 and a second P-type field effect transistor m5 (note its position), and the first P-type field effect transistor m1 The source is electrically connected to the voltage source Vdd, and its gate is co-located with its drain, and its drain is electrically connected to the transfer gate 132. The source of the second P-type field effect transistor m5 is electrically connected to the voltage source Vdd, the gate thereof is co-located with the gate of the first P-type field effect transistor m1, and the gate is electrically connected to the second end 122, Instead of the first end 121.
第二發射器130之NMOS電流槽包括一第一N型場效電晶體m4及一第二N型場效電晶體m6(注意其位置)。第一N型場效電晶體m4之源極接地，其汲極與其閘極共點，且其汲極電性連接傳輸閘132。第二N型場效電晶體m6之閘極與第一N型場效電晶體m4之閘極共點，其源極接地，其汲極電性連接第一端121，而非第二端122。The NMOS current slot of the second emitter 130 includes a first N-type field effect transistor m4 and a second N-type field effect transistor m6 (note its position). The source of the first N-type field effect transistor m4 is grounded, its drain is co-located with its gate, and its drain is electrically connected to the transfer gate 132. The gate of the second N-type field effect transistor m6 is co-located with the gate of the first N-type field effect transistor m4, the source thereof is grounded, and the drain is electrically connected to the first end 121 instead of the second end 122. .
請參考第6圖，第6圖是本揭示內容另一實施方式之FlexRay接收器200的結構示意圖。第6圖中，FlexRay接收器200包括一遲滯比較器210、一窗口比較器220及一 充放電幫浦230。遲滯比較器210係用以比較一第一輸入電壓201與一第二輸入電壓202，並根據比較結果產生一輸出訊號。窗口比較器220係並聯遲滯比較器210，用以當第一輸入電壓210與第二輸入電壓220位於一預設電壓區間221時，輸出一閒置狀態訊號222。充放電幫浦230串聯窗口比較器220，係用以消除閒置狀態訊號222之脈波雜訊。Please refer to FIG. 6. FIG. 6 is a schematic structural diagram of a FlexRay receiver 200 according to another embodiment of the present disclosure. In FIG. 6, the FlexRay receiver 200 includes a hysteresis comparator 210, a window comparator 220, and a Charge and discharge pump 230. The hysteresis comparator 210 is configured to compare a first input voltage 201 and a second input voltage 202, and generate an output signal according to the comparison result. The window comparator 220 is a parallel hysteresis comparator 210 for outputting an idle state signal 222 when the first input voltage 210 and the second input voltage 220 are in a predetermined voltage interval 221 . The charge and discharge pump 230 series window comparator 220 is used to eliminate the pulse wave noise of the idle state signal 222.
具體而言，前述FlexRay發射器100之第一端121與第二端122的電壓值會被傳輸到FlexRay接收器200，以作為第一輸入電壓201與第二輸入電壓202。當第一輸入電壓201與第二輸入電壓202之電位邏輯相反，也就是其產生是根據有意義的第一狀態編碼與第二狀態編碼時，遲滯比較器210會根據第一輸入電壓201與第二輸入電壓202之比較結果產生輸出訊號。更正確的說，遲滯比較器210是在確保第一輸入電壓201與第二輸入電壓202兩者之間存在一定的差值；也就是說，當第一輸入電壓201與第二輸入電壓202邏輯轉態時(一個由高電位變低電位，另一個由低電位變高電位)，遲滯比較器210可以確認兩輸入比較訊號電壓其中之一，必須再大於或小於另一輸入電壓一個所設計的電壓值，這樣作的主要目的是消除雜訊的影響，以取得正確的輸出訊號。Specifically, the voltage values of the first end 121 and the second end 122 of the aforementioned FlexRay transmitter 100 are transmitted to the FlexRay receiver 200 as the first input voltage 201 and the second input voltage 202. When the first input voltage 201 is logically opposite to the potential of the second input voltage 202, that is, when the generation is based on the meaningful first state encoding and the second state encoding, the hysteresis comparator 210 according to the first input voltage 201 and the second The comparison of the input voltages 202 produces an output signal. More correctly, the hysteresis comparator 210 is to ensure a certain difference between the first input voltage 201 and the second input voltage 202; that is, when the first input voltage 201 and the second input voltage 202 are logic In the transition state (one from low to low and the other from low to high), the hysteresis comparator 210 can confirm that one of the two input comparison signal voltages must be greater than or less than another input voltage. The main purpose of the voltage value is to eliminate the effects of noise to obtain the correct output signal.
舉例而言，如果第一狀態編碼與第二狀態編碼為一高一低(1,0)，則遲滯比較器210之輸出可假設為邏輯高電位(1)；反之，第一狀態編碼與第二狀態編碼為一低一高(0,1)，則遲滯比較器210之輸出為邏輯低電位(0)；重點是，當第 一狀態編碼與第二狀態編碼同為高電位(1,1)或低電位(0,0)，第一端121與第二端122之電位不可預知，而遲滯比較器210便因第一輸入電壓201與第二輸入電壓202並未能存在一定的差值(預期高電位與低電位之差值)，而不理會此一雜訊擾動或閒置狀態。所以，遲滯比較器210之輸出訊號可以正確反應第一狀態編碼與第二狀態編碼所代表的訊號意義。For example, if the first state code and the second state code are one high and one low (1, 0), the output of the hysteresis comparator 210 can be assumed to be a logic high potential (1); otherwise, the first state code and the first state The two-state code is a low-high (0,1), then the output of the hysteresis comparator 210 is a logic low (0); the focus is on The state code and the second state code are both high (1, 1) or low (0, 0), the potentials of the first end 121 and the second end 122 are unpredictable, and the hysteresis comparator 210 is due to the first input. The voltage 201 and the second input voltage 202 do not have a certain difference (the difference between the expected high potential and the low potential), regardless of the noise disturbance or idle state. Therefore, the output signal of the hysteresis comparator 210 can correctly reflect the meaning of the signal represented by the first state code and the second state code.
窗口比較器220的功能是當輸入電壓，亦即第一輸入電壓201與第二輸入電壓202之差值，落在某一設計的電壓區間時，能夠偵測並指示出來。承上所述，此一區間即代表第一狀態編碼與第二狀態編碼並未呈現邏輯電位相反的狀態，是閒置狀態(Idle)；窗口比較器220因而產生閒置狀態訊號222。由此觀之，遲滯比較器210所產生的輸出訊號即可作為車用網路通訊協定FlexRay所要求之資料訊號R-data；而窗口比較器220所產生之閒置狀態訊號222即符合車用網路通訊協定FlexRay所要求之閒置指標R-idle。The function of the window comparator 220 is that when the input voltage, that is, the difference between the first input voltage 201 and the second input voltage 202, falls within a certain design voltage interval, it can be detected and indicated. As described above, the interval represents that the first state code and the second state code do not exhibit a state opposite to the logic potential, and is an idle state (Idle); the window comparator 220 thus generates the idle state signal 222. Therefore, the output signal generated by the hysteresis comparator 210 can be used as the data signal R-data required by the vehicle network protocol FlexRay; and the idle state signal 222 generated by the window comparator 220 conforms to the vehicle network. The idle indicator R-idle required by the road protocol FlexRay.
然而，由於輸入訊號的轉態，必定會經過所設計的電壓區間，亦即預設電壓區間221，進而造成窗口比較器220的輸出值，亦即閒置狀態訊號222，出現短脈波雜訊。所以，本實施方式將充放電幫浦230的兩輸入接在一起，配合所設計的負載電容值，以濾除短脈波雜訊。However, due to the transition state of the input signal, the designed voltage interval, that is, the preset voltage interval 221, must be passed, thereby causing the output value of the window comparator 220, that is, the idle state signal 222, and short pulse noise. Therefore, in this embodiment, the two inputs of the charge and discharge pump 230 are connected together, and the designed load capacitance value is matched to filter out short pulse noise.
最後，請參考第7圖，第7圖是第6圖之詳細電路圖。第7圖中，本實施方式之FlexRay接收器200更包括一取樣電路240；取樣電路240係串聯於遲滯比較器210，以取 樣輸出訊號，產生數位形式的資料訊號。更進一步的說，取樣電路240可以包括一延遲電路241及一D型正反器242；當FlexRay接收器200處於非低功耗模式，亦即FlexRay發射器100傳過來的資料不是代表閒置狀態時，取樣電路240可以讓資料訊號符合最初始的輸入訊號，亦即第一狀態編碼與第二狀態編碼。因此，延遲電路241可以使資料訊號在時間上匹配閒置狀態訊號222；而D型正反器242可以使資料訊號符合最初始的輸入訊號。Finally, please refer to Figure 7, which is a detailed circuit diagram of Figure 6. In FIG. 7, the FlexRay receiver 200 of the present embodiment further includes a sampling circuit 240; the sampling circuit 240 is connected in series to the hysteresis comparator 210 to take The sample output signal generates a digital signal in the form of a digit. Further, the sampling circuit 240 may include a delay circuit 241 and a D-type flip-flop 242; when the FlexRay receiver 200 is in a non-low power mode, that is, the data transmitted by the FlexRay transmitter 100 is not representative of an idle state. The sampling circuit 240 allows the data signal to conform to the initial input signal, that is, the first state code and the second state code. Therefore, the delay circuit 241 can make the data signal match the idle state signal 222 in time; and the D-type flip-flop 242 can make the data signal conform to the initial input signal.
另一方面，充放電幫浦230可再串聯一反向器250，則當FlexRay接收器200處於非低功耗模式時，反向器250可以讓差動訊號(第一輸入電壓201與第二輸入電壓202之差值)的大小符合FlexRay協定的要求。具體而言，FlexRay協定要求邏輯1表示訊號很小，匯流排120狀態應為Idle或Idle_LP。邏輯0表示訊號足夠大，指示匯流排狀態應為Data。但閒置狀態訊號222之邏輯關係正好相反，故可經反向器250調整之，使閒置狀態訊號在相位邏輯上匹配資料訊號。On the other hand, the charge and discharge pump 230 can be connected in series with an inverter 250, and when the FlexRay receiver 200 is in the non-low power mode, the inverter 250 can make the differential signal (the first input voltage 201 and the second The magnitude of the difference in input voltage 202 is in accordance with the requirements of the FlexRay protocol. Specifically, the FlexRay protocol requires a logic 1 to indicate that the signal is small and the bus 120 state should be Idle or Idle_LP. A logic 0 indicates that the signal is large enough to indicate that the bus status should be Data. However, the logical relationship of the idle state signal 222 is reversed, so that it can be adjusted by the inverter 250 to make the idle state signal logically match the data signal.
接下來，本揭示內容以雙向差動電壓傳輸架構進行點對點傳輸，來測試上述實施方式所揭露之FlexRay發射器100與FlexRay接收器200，以驗證其效能如下。Next, the present disclosure performs point-to-point transmission with a bidirectional differential voltage transmission architecture to test the FlexRay transmitter 100 and the FlexRay receiver 200 disclosed in the above embodiments to verify its performance as follows.
請參照第8圖，第8圖是傳輸訊號之波形圖。第8圖中，實線是前述FlexRay發射器100與FlexRay接收器200間訊號之波形眼圖；而虛線是FlexRay通訊協定最低需求之波形眼圖。Please refer to Figure 8. Figure 8 is a waveform diagram of the transmission signal. In Fig. 8, the solid line is the waveform eye diagram of the signal between the aforementioned FlexRay transmitter 100 and the FlexRay receiver 200; and the dashed line is the waveform eye diagram of the minimum requirement of the FlexRay protocol.
具體而言，從一個資料序列的波形眼圖可觀察一個訊 號的各種品質。一個接收器的訊號有許多特性，像是振幅雜訊、***符號干擾或者抖動，這都會影響從信號中萃取正確資訊的機率。一個訊號的波形眼圖可用以判讀這些訊號特性的資訊。在雙向差動電壓傳輸架構中，假設FlexRay發射器100要傳送訊號給FlexRay接收器200，則第8圖中實線是代表在FlexRay發射器100上第一端121和第二端122的電壓差，而虛線則是FlexRay所要求最小規格的波形眼圖。實線部分所形成的波形眼圖很明顯的包含虛線部分，因此符合FlexRay規格的要求。相同的現象也可以在FlexRay接收器200的第一輸入電壓201與第二輸入電壓202間電壓差之波形眼圖中觀察到。由第8圖可知悉，本實施方式之訊號符合FlexRay通訊協定所要求之訊號需求。Specifically, a signal can be observed from the waveform eye diagram of a data sequence. The various qualities of the number. A receiver's signal has many characteristics, such as amplitude noise, interpolated interference, or jitter, which can affect the probability of extracting the correct information from the signal. A waveform eye diagram of a signal can be used to interpret information about the characteristics of these signals. In the bidirectional differential voltage transmission architecture, assuming that the FlexRay transmitter 100 is to transmit a signal to the FlexRay receiver 200, the solid line in FIG. 8 represents the voltage difference between the first end 121 and the second end 122 on the FlexRay transmitter 100. The dotted line is the waveform eye diagram of the minimum size required by FlexRay. The undulating eye diagram formed by the solid line portion clearly includes the dotted line portion and therefore meets the requirements of the FlexRay specification. The same phenomenon can also be observed in the waveform eye diagram of the voltage difference between the first input voltage 201 and the second input voltage 202 of the FlexRay receiver 200. As can be seen from Fig. 8, the signal of this embodiment conforms to the signal requirements required by the FlexRay protocol.
請一併參照第9A圖與第9B圖；第9A圖是FlexRay接收器200接收資料正確性指標之波形圖，第9B圖是FlexRay接收器200接收資料之波形圖。由第9A圖與第9B圖亦可知悉，本實施方式之接收器200在輸出轉移函數時，亦符合FlexRay通訊協定所要求之訊號需求。具體比較數據如下表所示：
請一併參照第10圖與第11圖。第10圖是本揭示內容於測試中，根據FlexRay通訊協定，定義一發射器之訊號時序的波形圖。第11圖是模擬前述FlexRay發射器100延遲時間規格的波形圖。由第10圖與第11圖可知悉，前述FlexRay發射器100所產生之訊號波形亦符合FlexRay通訊協定之規定。相關數據之比較亦一併列於上表。Please refer to Figure 10 and Figure 11 together. Figure 10 is a waveform diagram of the present invention in which the signal timing of a transmitter is defined in accordance with the FlexRay communication protocol. Figure 11 is a waveform diagram simulating the aforementioned FlexRay transmitter 100 delay time specification. It can be seen from FIGS. 10 and 11 that the signal waveform generated by the aforementioned FlexRay transmitter 100 is also in compliance with the FlexRay protocol. A comparison of relevant data is also included in the above table.
請一併參照第12圖與第13圖。第12圖是本揭示內容於測試中，根據FlexRay通訊協定，定義一接收器之訊號時序的波形圖。第13圖是模擬前述FlexRay接收器200延遲時間規格的波形圖。由第12圖與第13圖可知悉，前述 FlexRay接收器200所產生之訊號波形亦符合FlexRay通訊協定之規定。相關數據之比較亦一併列於上表。Please refer to Figure 12 and Figure 13 together. Figure 12 is a waveform diagram of the present invention in which the signal timing of a receiver is defined in accordance with the FlexRay communication protocol. Figure 13 is a waveform diagram simulating the delay time specification of the aforementioned FlexRay receiver 200. It can be seen from Figures 12 and 13 that the foregoing The signal waveform generated by the FlexRay receiver 200 also conforms to the FlexRay protocol. A comparison of relevant data is also included in the above table.
請參照第14圖，第14圖是模擬工作狀態下，上述實施方式之FlexRay發射器100與FlexRay接收器200的波形圖。從第14圖中可看出，當FlexRay發射器100處於正常收發狀態時，假設傳送資料(TxD)每100ns變化一次，則當匯流排傳輸指標(BusGuardian_Enable,BGE)為邏輯1且發射資料正確性指標(TxEN)為邏輯0時，接收資料正確性指標(RxEN)為邏輯0，若匯流排上的電壓差(TP1)為正，接收資料(RxD)為邏輯1，若匯流排上的電壓差(TP1)為負，接收資料(RxD)為邏輯0；當匯流排傳輸指標(BGE)為邏輯0或輸出資料正確性指標(TxEN)為邏輯1時，匯流排上的電壓差(TP1)為0，接收資料正確性指標(RxEN)和接收資料(RxD)同時為邏輯1。因此FlexRay發射器100與FlexRay接收器200動作正確，符合FlexRay通訊協定之要求。Referring to FIG. 14, FIG. 14 is a waveform diagram of the FlexRay transmitter 100 and the FlexRay receiver 200 of the above embodiment in a simulated operation state. As can be seen from Fig. 14, when the FlexRay transmitter 100 is in the normal transmission and reception state, assuming that the transmission data (TxD) changes every 100 ns, when the bus transmission index (BusGuardian_Enable, BGE) is logic 1 and the data is correctly corrected. When the indicator (TxEN) is logic 0, the received data correctness indicator (RxEN) is logic 0. If the voltage difference (TP1) on the bus is positive, the received data (RxD) is logic 1, if the voltage difference on the bus is (TP1) is negative, the received data (RxD) is logic 0; when the bus transmission indicator (BGE) is logic 0 or the output data correctness indicator (TxEN) is logic 1, the voltage difference (TP1) on the bus is 0, Receive Data Correctness Indicator (RxEN) and Receive Data (RxD) are both logic 1. Therefore, the FlexRay transmitter 100 and the FlexRay receiver 200 operate correctly and comply with the FlexRay protocol.
雖然本發明已以諸實施方式揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and it is obvious to those skilled in the art that various modifications and refinements can be made without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.
100‧‧‧FlexRay發射器100‧‧‧FlexRay Transmitter
110‧‧‧第一發射器110‧‧‧First launcher
111‧‧‧第一CMOS電流鏡111‧‧‧First CMOS current mirror
112‧‧‧第一傳輸閘112‧‧‧First transmission gate
131‧‧‧第二CMOS電流鏡131‧‧‧Second CMOS current mirror
132‧‧‧第二傳輸閘132‧‧‧Second transmission gate
150‧‧‧CMOS電流鏡150‧‧‧CMOS current mirror
120‧‧‧匯流排120‧‧‧ busbar
121‧‧‧第一端121‧‧‧ first end
122‧‧‧第二端122‧‧‧ second end
123‧‧‧第一電阻123‧‧‧First resistance
124‧‧‧偏壓電源124‧‧‧ bias power supply
125‧‧‧第二電阻125‧‧‧second resistance
130‧‧‧第二發射器130‧‧‧Second launcher
140‧‧‧CMOS傳輸閘140‧‧‧CMOS transmission gate
141‧‧‧N型場效電晶體141‧‧‧N type field effect transistor
142‧‧‧P型場效電晶體142‧‧‧P type field effect transistor
151‧‧‧PMOS電流源151‧‧‧PMOS current source
152‧‧‧NMOS電流槽152‧‧‧NMOS current tank
200‧‧‧FlexRay接收器200‧‧‧FlexRay Receiver
201‧‧‧第一輸入電壓201‧‧‧First input voltage
202‧‧‧第二輸入電壓202‧‧‧second input voltage
210‧‧‧遲滯比較器210‧‧‧hysteresis comparator
220‧‧‧窗口比較器220‧‧‧Window Comparator
221‧‧‧預設電壓區間221‧‧‧Preset voltage range
222‧‧‧閒置狀態訊號222‧‧‧ Idle state signal
230‧‧‧充放電幫浦230‧‧‧Charge and discharge pump
240‧‧‧取樣電路240‧‧‧Sampling circuit
241‧‧‧延遲電路241‧‧‧Delay circuit
242‧‧‧正反器242‧‧‧Factor
250‧‧‧反向器250‧‧‧ reverser
M1~M6、m1~m6‧‧‧電晶體M1~M6, m1~m6‧‧‧O crystal
為讓本揭示內容之上述和其他目的、特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1圖是本揭示內容一實施方式之FlexRay發射器的結構示意圖。The above and other objects, features, advantages and embodiments of the present disclosure will become more apparent and understood. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of the structure of a FlexRay transmitter according to an embodiment of the present disclosure.
第2圖是第1圖之匯流排120的電路圖。Fig. 2 is a circuit diagram of the bus bar 120 of Fig. 1.
第3圖是第1圖之傳輸閘112/132的電路圖。Figure 3 is a circuit diagram of the transfer gate 112/132 of Figure 1.
第4圖是第1圖之CMOS電流鏡111/131的電路圖。Fig. 4 is a circuit diagram of the CMOS current mirror 111/131 of Fig. 1.
第5圖是第1圖之詳細電路圖。Fig. 5 is a detailed circuit diagram of Fig. 1.
第6圖是本揭示內容另一實施方式之FlexRay接收器的結構示意圖。Figure 6 is a block diagram showing the structure of a FlexRay receiver according to another embodiment of the present disclosure.
第7圖是第6圖之詳細電路圖。Figure 7 is a detailed circuit diagram of Figure 6.
第8圖是傳輸訊號之波形圖。Figure 8 is a waveform diagram of the transmission signal.
第9A圖是FlexRay接收器200接收資料正確性指標之波形圖。Figure 9A is a waveform diagram of the FlexRay Receiver 200 receiving data correctness indicators.
第9B圖是FlexRay接收器200接收資料之波形圖。Figure 9B is a waveform diagram of the data received by the FlexRay receiver 200.
第10圖是本揭示內容於測試中，根據FlexRay通訊協定，定義一發射器之訊號時序的波形圖。Figure 10 is a waveform diagram of the present invention in which the signal timing of a transmitter is defined in accordance with the FlexRay communication protocol.
第11圖是模擬FlexRay發射器100延遲時間規格的波形圖。Figure 11 is a waveform diagram of the simulation of the FlexRay transmitter 100 delay time specification.
第12圖是本揭示內容於測試中，根據FlexRay通訊協定，定義一接收器之訊號時序的波形圖。Figure 12 is a waveform diagram of the present invention in which the signal timing of a receiver is defined in accordance with the FlexRay communication protocol.
第13圖是模擬FlexRay接收器200延遲時間規格的波形圖。Figure 13 is a waveform diagram of the simulation of the FlexRay receiver 200 delay time specification.
第14圖是模擬工作狀態下，FlexRay發射器100與FlexRay接收器200的波形圖。Figure 14 is a waveform diagram of the FlexRay transmitter 100 and the FlexRay receiver 200 in a simulated operating state.
110‧‧‧第一發射器110‧‧‧First launcher
120‧‧‧匯流排120‧‧‧ busbar
130‧‧‧第二發射器130‧‧‧Second launcher
M1~M6、m1~m6‧‧‧電晶體M1~M6, m1~m6‧‧‧O crystal
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99111469A TWI427973B (en) | 2010-04-13 | 2010-04-13 | Flexray transmitter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99111469A TWI427973B (en) | 2010-04-13 | 2010-04-13 | Flexray transmitter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201136245A TW201136245A (en) | 2011-10-16 |
| TWI427973B true TWI427973B (en) | 2014-02-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW99111469A TWI427973B (en) | 2010-04-13 | 2010-04-13 | Flexray transmitter |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI427973B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9088514B2 (en) * | 2012-07-23 | 2015-07-21 | Broadcom Corporation | Flexray communications using ethernet |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050104633A1 (en) * | 2002-01-23 | 2005-05-19 | Bernd Elend | Transmitter output stage for a two-wire bus |
| US20060109601A1 (en) * | 2002-11-05 | 2006-05-25 | Stephan Bolz | Protective circuit for protection against over voltage for a can- bus transceiver |
-
2010
- 2010-04-13 TW TW99111469A patent/TWI427973B/en not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050104633A1 (en) * | 2002-01-23 | 2005-05-19 | Bernd Elend | Transmitter output stage for a two-wire bus |
| US20060109601A1 (en) * | 2002-11-05 | 2006-05-25 | Stephan Bolz | Protective circuit for protection against over voltage for a can- bus transceiver |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201136245A (en) | 2011-10-16 |
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