TWI423744B - Printed circuit board and coexisting layout method thereof - Google Patents

Printed circuit board and coexisting layout method thereof Download PDF

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Publication number
TWI423744B
TWI423744B TW97130265A TW97130265A TWI423744B TW I423744 B TWI423744 B TW I423744B TW 97130265 A TW97130265 A TW 97130265A TW 97130265 A TW97130265 A TW 97130265A TW I423744 B TWI423744 B TW I423744B
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pair
conductive portion
coupled
component
circuit board
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TW97130265A
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TW201008407A (en
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Yung Chieh Chen
Cheng Shien Li
Shou Kuo Hsu
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Hon Hai Prec Ind Co Ltd
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Description

電路板及其共存佈線方法Circuit board and coexisting wiring method thereof

本發明涉及一種電路板及其佈線方法，特別關於一種電路板及其共存佈線方法。The present invention relates to a circuit board and a wiring method thereof, and more particularly to a circuit board and a coexisting wiring method thereof.

隨著科技的進步，對於相同的產品，會因應不同使用者的需求而改變內部的一些功能，因而一種產品會有許多不同的產品規格。對於產品的電路板而言，通常會使用一種佈線方式，再藉由選擇焊接不同的線路而產生不同的功能及規格，故高速訊號，例如高速差分訊號的共存佈線的應用就更加廣泛。With the advancement of technology, for the same product, some internal functions will be changed according to the needs of different users, so a product will have many different product specifications. For the circuit board of the product, a wiring method is usually used, and different functions and specifications are generated by selectively soldering different lines, so that the application of high-speed signals, such as high-speed differential signals, is more widely used.

請參照圖1所示，為習知的一種電路板1的共存佈線的線路圖，電路板1具有藉由單一佈線方式形成的一第一傳輸線對11A、11B、一第二傳輸線對12A、12B及一第三傳輸線對13A、13B，且第二傳輸線對12A、12B設置第一傳輸線對11A、11B及第三傳輸線對13A、13B之間。Referring to FIG. 1 , which is a circuit diagram of a conventional coexistence wiring of a circuit board 1 , the circuit board 1 has a first transmission line pair 11A, 11B and a second transmission line pair 12A, 12B formed by a single wiring manner. And a third transmission line pair 13A, 13B, and the second transmission line pair 12A, 12B is disposed between the first transmission line pair 11A, 11B and the third transmission line pair 13A, 13B.

請同時參照圖2與圖3所示，兩個規格不同的電路板1A、1B分別具有一控制晶片14，而控制晶片14產生高速訊號對S1、S2，例：高速差分訊號對並與第一傳輸線對11A、11B耦接。電路板1A、1B並分別與一第一電子裝置15(如圖2所示)及一第二電子裝置16(如圖3所示)耦接，第一電子裝置15耦接電路板1A的第一傳輸線對11A、11B及第二傳輸線對12A、12B之間(如圖2所示)；而第二電子裝置16耦接電路板1B的第三傳輸線對13A、13B，而 電路板1B需再藉由耦接二個分隔元件，通常為阻值0Ω的電阻器R1、R2在第二傳輸線對12A、12B及第三傳輸線對13A、13B之間，即可將訊號傳輸至第二電子裝置16。然而，上述方式，就第一電子裝置15而言，第二傳輸線對12A、12B因無傳輸作用而造成電路殘段；就第二電子裝置16而言，需增加二個區隔組件，進而提升成本。Referring to FIG. 2 and FIG. 3 simultaneously, two different boards 1A and 1B have a control chip 14 respectively, and the control chip 14 generates high-speed signal pairs S1 and S2, for example, a high-speed differential signal pair and the first The transmission line pair 11A, 11B is coupled. The circuit boards 1A, 1B are coupled to a first electronic device 15 (shown in FIG. 2) and a second electronic device 16 (shown in FIG. 3). The first electronic device 15 is coupled to the first circuit board 1A. A transmission line pair 11A, 11B and a second transmission line pair 12A, 12B (as shown in FIG. 2); and the second electronic device 16 is coupled to the third transmission line pair 13A, 13B of the circuit board 1B, and The circuit board 1B needs to transmit signals to and between the second transmission line pair 12A, 12B and the third transmission line pair 13A, 13B by coupling two separation elements, usually resistors R1 and R2 having a resistance of 0 Ω. The second electronic device 16. However, in the above manner, in the first electronic device 15, the second transmission line pair 12A, 12B causes a circuit residual due to no transmission; in the second electronic device 16, two additional components are added, thereby cost.

爰因於此，如何提供一種利用相同佈線即可依據不同需求產生不同訊號線連結，且免除區隔元件並降低成本的電路板及其共存佈線方法，已成為重要課題之一。Because of this, it has become one of the important topics to provide a circuit board and a coexisting wiring method that can generate different signal line connections according to different requirements by using the same wiring, and eliminate the division components and reduce the cost.

鑒於以上課題，本發明之目的為提供一種利用相同佈線即可依據不同需求產生不同訊號線連結，且免除區隔元件並降低成本的電路板及其共存佈線方法。In view of the above problems, an object of the present invention is to provide a circuit board capable of generating different signal line connections according to different requirements by using the same wiring, and eliminating the division components and reducing the cost, and a coexistence wiring method thereof.

為達上述目的，依據本發明之一種電路板，耦接有一電子裝置，其包含一第一元件、一第二元件、一第一佈線層以及一第二佈線層。本發明中，第一佈線層設有一耦接一控制晶片的第一導電部對，第二佈線層設有一第二導電部對、一第三導電部對及一第四導電部對，第三導電部對設置於第二導電部對及第四導電部對之間，第三導電部對相對應且耦接第一佈線層的第一導電部對。當第二導電部對耦接電子裝置時，第一元件及第二元件使第二導電部對及第三導電部對耦接，當第四導電部對耦接電子裝置時，第一元件及第二元件使第三導電部對及第四導電部對耦 接。To achieve the above object, a circuit board according to the present invention is coupled to an electronic device including a first component, a second component, a first wiring layer, and a second wiring layer. In the present invention, the first wiring layer is provided with a first conductive portion pair coupled to a control wafer, and the second wiring layer is provided with a second conductive portion pair, a third conductive portion pair and a fourth conductive portion pair, and a third The pair of conductive portions are disposed between the pair of second conductive portions and the pair of fourth conductive portions, and the third conductive portion pairs and couples the first conductive portions of the first wiring layer. When the second conductive portion pair is coupled to the electronic device, the first component and the second component couple the second conductive portion pair and the third conductive portion pair, and when the fourth conductive portion pair is coupled to the electronic device, the first component and The second component couples the third conductive portion pair and the fourth conductive portion Pick up.

為達上述目的，依據本發明之一種電路板之共存佈線方法包含下列步驟：於一第一佈線層上設置一第一導電部對，並使第一導電部對耦接一控制晶片；於一第二佈線層上設置一第二導電部對、一第三導電部對及一第四導電部對，其中第三導電部對設置第二導電部對及第四導電部對之間；耦接第三導電部對及第一導電部對；以及當第二導電部對耦接一電子裝置時，使第二導電部對及第三導電部對耦接；當第四導電部對耦接一電子裝置時，使第三導電部對及第四導電部對耦接。In order to achieve the above object, a method for coexisting a circuit board according to the present invention comprises the steps of: providing a first conductive portion pair on a first wiring layer and coupling the first conductive portion pair to a control wafer; a second conductive portion pair, a third conductive portion pair and a fourth conductive portion pair are disposed on the second wiring layer, wherein the third conductive portion pair is disposed between the second conductive portion pair and the fourth conductive portion pair; The third conductive portion pair and the first conductive portion pair; and when the second conductive portion pair is coupled to an electronic device, the second conductive portion pair and the third conductive portion are coupled; when the fourth conductive portion is coupled to the first In the electronic device, the third conductive portion pair and the fourth conductive portion pair are coupled.

承上所述，本發明之電路板及其共存佈線方法，藉由電路板單一佈線，而使第一元件及第二元件可耦接於第二導電部對及第三導電部對之間，或耦接於第三導電部對及第四導電部對之間以改變訊號連接。與習知技術相較，本發明僅藉由單一佈線與第一元件及第二元件配合，使第一元件及第二元件耦接不同佈線，就可產生不同的訊號線連接，此種方式，不僅可使電路板依據不同需求具有不同的規格，更不需再增加區隔元件，進而降低成本。As described above, the circuit board of the present invention and the method for coexisting the same, the first component and the second component can be coupled between the pair of the second conductive portion and the third conductive portion by a single wiring of the circuit board. Or coupled between the third conductive portion pair and the fourth conductive portion pair to change the signal connection. Compared with the prior art, the present invention can only generate different signal line connections by coupling a first component and a second component to different wires by a single wire and the first component and the second component. Not only can the board have different specifications according to different requirements, but also need to increase the partition components, thereby reducing the cost.

以下將參照相關圖式，說明依據本發明較佳實施方式之一種電路板及其共存佈線方法。Hereinafter, a circuit board and a coexisting wiring method thereof according to a preferred embodiment of the present invention will be described with reference to the related drawings.

請參照圖4所示，本實施方式的電路板2包含一第一元件21、一第二元件22、一第一佈線層23、一第二佈線 層24、一設於第一佈線層23與第二佈線層24之間的絕緣層(圖未示)、一連接部對29A、29B及一控制晶片3。電路板2於實施上可為一主機板。Referring to FIG. 4, the circuit board 2 of the present embodiment includes a first component 21, a second component 22, a first wiring layer 23, and a second wiring. The layer 24, an insulating layer (not shown) disposed between the first wiring layer 23 and the second wiring layer 24, a pair of connecting portions 29A, 29B, and a control wafer 3. The circuit board 2 can be implemented as a motherboard.

於本實施方式中，第一佈線層23具有一第一導電部對25A、25B，而第一導電部對25A、25B於實施上為一對焊盤或一對焊墊。In the present embodiment, the first wiring layer 23 has a pair of first conductive portions 25A, 25B, and the first conductive portion pairs 25A, 25B are implemented as a pair of pads or a pair of pads.

第二佈線層24具有一第二導電部對26A、26B、一第三導電部對27A、27B及一第四導電部對28A、28B，而第三導電部對27A、27B設置在第二導電部對26A、26B及第四導電部對28A、28B之間，且第三導電部對27A、27B與第一導電部對25A、25B相互對應且通過連接部對29A、29B耦接。連接部對29A、29B於實施上可為一對過孔，或一對埋孔。The second wiring layer 24 has a second conductive portion pair 26A, 26B, a third conductive portion pair 27A, 27B and a fourth conductive portion pair 28A, 28B, and the third conductive portion pair 27A, 27B is disposed at the second conductive portion. The pair of portions 26A, 26B and the fourth pair of conductive portions 28A, 28B, and the third pair of conductive portions 27A, 27B and the first pair of conductive portions 25A, 25B correspond to each other and are coupled by the pair of connection portions 29A, 29B. The pair of connection portions 29A, 29B may be a pair of via holes or a pair of buried holes.

本實施方式的第一元件21與第二元件22相互對應設置，且可為電容器或電阻器，在此以第一元件21與第二元件22皆為一交流耦合電容器為例。The first element 21 and the second element 22 of the present embodiment are disposed corresponding to each other, and may be a capacitor or a resistor. Here, the first element 21 and the second element 22 are both an AC coupling capacitor as an example.

控制晶片3耦接第一導電部對25A、25B並產生一高速訊號對S3、S4，而高速訊號對S3、S4於實施上可為一高速差分訊號對，且控制晶片3藉由第一導電部25A、25B對傳輸高速訊號S3、S4對至第三導電部對27A、27B。The control chip 3 is coupled to the first conductive portion pair 25A, 25B and generates a high speed signal pair S3, S4, and the high speed signal pair S3, S4 can be implemented as a high speed differential signal pair, and the control chip 3 is controlled by the first conductive The sections 25A, 25B are paired to transmit the high speed signals S3, S4 to the third pair of conductive portions 27A, 27B.

一電子裝置4可耦接到第二導電部對26A、26B(如圖4所示)或第四導電部對28A、28B(如圖5所示)。An electronic device 4 can be coupled to the second pair of conductive portions 26A, 26B (shown in Figure 4) or the fourth pair of conductive portions 28A, 28B (shown in Figure 5).

請再參照圖4所示，當電子裝置4耦接到第二導電部對26A、26B時，第一元件21耦接第二導電部對26A及 第三導電部對27A，第二元件22耦接第二導電部對26B及第三導電部對27B，而控制晶片3將高速訊號對S3、S4通過第一導電部對25A、25B、第三導電部對27A、27B、第一元件21、第二元件22及第二導電部對26A、26B傳輸至電子裝置4。Referring to FIG. 4 again, when the electronic device 4 is coupled to the second conductive portion pair 26A, 26B, the first component 21 is coupled to the second conductive portion pair 26A and The third conductive portion pair 27A, the second component 22 is coupled to the second conductive portion pair 26B and the third conductive portion pair 27B, and the control wafer 3 passes the high-speed signal pair S3, S4 through the first conductive portion pair 25A, 25B, and the third The pair of conductive portions 27A, 27B, the first member 21, the second member 22, and the second pair of conductive portions 26A, 26B are transmitted to the electronic device 4.

請參照圖5所示，當電子裝置4耦接到第四導電部對28A、28B時，第一組件21耦接第三導電部對27A及第四導電部對28A，第二元件22耦接第三導電部對27B及第四導電部對28B，而控制晶片3將高速訊號對S3、S4通過第一導電部對25A、25B、第三導電部對27A、27B、第一元件21、第二元件22及第四導電部對28A、28B傳輸至電子裝置4。As shown in FIG. 5, when the electronic device 4 is coupled to the fourth conductive portion pair 28A, 28B, the first component 21 is coupled to the third conductive portion pair 27A and the fourth conductive portion pair 28A, and the second component 22 is coupled. The third conductive portion pair 27B and the fourth conductive portion pair 28B, and the control wafer 3 passes the high speed signal pair S3, S4 through the first conductive portion pair 25A, 25B, the third conductive portion pair 27A, 27B, the first element 21, The two elements 22 and the fourth conductive portion pairs 28A, 28B are transmitted to the electronic device 4.

於本實施方式中，電路板2藉由相同的佈線，而依據不同需求僅改變第一元件21及第二元件22耦接的位置，就可使電路板2產生不同的規格。In the present embodiment, the circuit board 2 can be made to have different specifications by changing the position where the first component 21 and the second component 22 are coupled according to different requirements by the same wiring.

另外，請參照圖6所示，本發明電路板2的共存佈線方法的較佳實施方式包括步驟S01至S05。In addition, referring to FIG. 6, a preferred embodiment of the coexistence wiring method of the circuit board 2 of the present invention includes steps S01 to S05.

步驟S01，於第一佈線層23上設置第一導電部對25A、25B，並使第一導電部對25A、25B耦接控制晶片3。In step S01, the first conductive portion pairs 25A, 25B are disposed on the first wiring layer 23, and the first conductive portion pairs 25A, 25B are coupled to the control wafer 3.

步驟S02，於第二佈線層24上設置第二導電部對26A、26B、第三導電部對27A、27B及第四導電部28A、28B，使第三導電部對27A、27B設置第二導電部對26A、26B及第四導電部對28A、28B之間，且第三導電部對27A、27B相對應第一導電部對25A、25B。 步驟S03，耦接第三導電部對27A、27B與第一導電部對25A、25B。Step S02, the second conductive portion pair 26A, 26B, the third conductive portion pair 27A, 27B and the fourth conductive portion 28A, 28B are disposed on the second wiring layer 24, so that the third conductive portion pair 27A, 27B is provided with the second conductive portion. The pair of portions 26A, 26B and the fourth pair of conductive portions 28A, 28B, and the third pair of conductive portions 27A, 27B correspond to the first pair of conductive portions 25A, 25B. In step S03, the third conductive portion pair 27A, 27B and the first conductive portion pair 25A, 25B are coupled.

電路板可依據不同需求而執行步驟S04或S05，以產生不同規格。The circuit board can perform step S04 or S05 according to different needs to generate different specifications.

步驟S04，當電子裝置4耦接到第二導電部對26A、26B時，將第一元件21耦接第二導電部對26A及第三導電部對27A，第二元件22耦接第二導電部對26B及第三導電部對27B。In step S04, when the electronic device 4 is coupled to the second conductive portion pair 26A, 26B, the first component 21 is coupled to the second conductive portion pair 26A and the third conductive portion pair 27A, and the second component 22 is coupled to the second conductive portion. The pair 26B and the third conductive portion pair 27B.

步驟S05，當電子裝置4耦接到第四導電部對28A、28B時，第一組件21耦接第三導電部對27A及第四導電部對28A，第二元件22耦接第三導電部對27B及第四導電部對28B。In step S05, when the electronic device 4 is coupled to the fourth conductive portion pair 28A, 28B, the first component 21 is coupled to the third conductive portion pair 27A and the fourth conductive portion pair 28A, and the second component 22 is coupled to the third conductive portion. Pair 27B and fourth conductive portion pair 28B.

本發明的電路板及其共存佈線方法，僅藉由單一佈線與第一元件21及第二元件22配合，使第一元件21及第二元件22耦接不同的佈線導電部對，就可產生不同的訊號線連接，此種方式，不僅可使電路板依據不同需求具有不同的規格，更不需再增加區隔組件，進而降低成本。In the circuit board of the present invention and the coexisting wiring method, the first element 21 and the second element 22 are coupled to different wiring conductive parts by only a single wiring, and the first element 21 and the second element 22 are coupled to each other. Different signal lines are connected. In this way, not only can the circuit board have different specifications according to different requirements, but also the partition components are not needed, thereby reducing the cost.

本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，舉凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。The invention complies with the requirements of the invention patent, and proposes a patent application according to law. The above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

電路板‧‧‧ 1、1A、1B、2Circuit board ‧‧ 1, 1A, 1B, 2

第一傳輸線對‧‧‧11A、11BThe first transmission line is ‧‧1111A, 11B

第二傳輸線對‧‧‧12A、12BSecond transmission line pair ‧‧12A, 12B

第三傳輸線對‧‧‧13A、13BThird transmission line pair ‧‧13A, 13B

控制晶片‧‧‧14、3Control chip ‧‧14,3

第一電子裝置‧‧‧15First electronic device ‧‧15

第二電子裝置‧‧‧16Second electronic device ‧‧16

第一元件‧‧‧21First component ‧‧21

第二元件‧‧‧22Second component ‧‧22

第一佈線層‧‧‧23First wiring layer ‧‧23

第二佈線層‧‧‧24Second wiring layer ‧‧24

第一導電部對‧‧‧25A、25BThe first conductive part is ‧‧‧25A, 25B

第二導電部對‧‧‧26A、26BThe second conductive part is ‧‧‧26A, 26B

第三導電部對‧‧‧27A、27BThe third conductive part is ‧‧27A, 27B

第四導電部對‧‧‧28A、28BThe fourth conductive part is ‧‧28A, 28B

連接部對‧‧‧29A、29BConnections to ‧‧‧29A, 29B

電子裝置‧‧‧4Electronic device ‧‧4

電阻器‧‧‧R1、R2Resistor ‧‧‧R1, R2

高速訊號對‧‧‧ S1、S2、S3、S4High-speed signal pair ‧‧ S1, S2, S3, S4

圖1為顯示習知的電路板的共存佈線的線路圖。1 is a circuit diagram showing a coexistence wiring of a conventional circuit board.

圖2為顯示習知的電路板耦接第一電子裝置的連接圖。2 is a connection diagram showing a conventional circuit board coupled to a first electronic device.

圖3為顯示習知的電路板耦接第二電子裝置的連接圖。3 is a connection diagram showing a conventional circuit board coupled to a second electronic device.

圖4為顯示本發明較佳實施方式的一種電路板的***圖。4 is an exploded view showing a circuit board of a preferred embodiment of the present invention.

圖5為顯示本發明較佳實施方式的另一種電路板的***圖。Figure 5 is an exploded view showing another circuit board in accordance with a preferred embodiment of the present invention.

圖6為顯示本發明較佳實施方式的電路板的共存佈線的流程圖。Fig. 6 is a flow chart showing the coexistence wiring of the circuit board of the preferred embodiment of the present invention.

電路板‧‧‧2Circuit board ‧‧2

控制晶片‧‧‧3Control chip ‧‧3

電子裝置‧‧‧4Electronic device ‧‧4

第一元件‧‧‧21First component ‧‧21

第二元件‧‧‧22Second component ‧‧22

第一佈線層‧‧‧23First wiring layer ‧‧23

第二佈線層‧‧‧24Second wiring layer ‧‧24

第一導電部對‧‧‧25A、25BThe first conductive part is ‧‧‧25A, 25B

第二導電部對‧‧‧26A、26BThe second conductive part is ‧‧‧26A, 26B

第三導電部對‧‧‧27A、27BThe third conductive part is ‧‧27A, 27B

第四導電部對‧‧‧28A、28BThe fourth conductive part is ‧‧28A, 28B

連接部對‧‧‧29A、29BConnections to ‧‧‧29A, 29B

高速訊號對‧‧‧S3、S4High-speed signal pair ‧‧S3, S4

Claims (16)

一種電路板，耦接有一電子裝置，該電路板包含：一第一組件；一第二元件；一第一佈線層，該第一佈線層設有耦接一控制晶片的一第一導電部對；以及一第二佈線層，該第二佈線層設有一第二導電部對、一第三導電部對及一第四導電部對，該第三導電部對設置於該第二導電部對及該第四導電部對之間，該第三導電部對相對應耦接該第一佈線層的該第一導電部對；當該第二導電部對耦接該電子裝置時，該第一元件及該第二元件使該第二導電部對及該第三導電部對耦接，當該第四導電部對耦接該電子裝置時，該第一元件及該第二元件使該第三導電部對及該第四導電部對耦接。A circuit board coupled to an electronic device, the circuit board comprising: a first component; a second component; a first wiring layer, the first wiring layer is provided with a first conductive portion coupled to a control wafer And a second wiring layer, the second wiring layer is provided with a second conductive portion pair, a third conductive portion pair and a fourth conductive portion pair, the third conductive portion pair is disposed on the second conductive portion Between the pair of fourth conductive portions, the third conductive portion pair is opposite to the first conductive portion of the first wiring layer; when the second conductive portion pair is coupled to the electronic device, the first component And the second component couples the second conductive portion pair and the third conductive portion pair. When the fourth conductive portion pair is coupled to the electronic device, the first component and the second component make the third conductive The pair is coupled to the fourth conductive portion. 如申請專利範圍第1項所述之電路板，其中該第三導電部對是通過一連接部對與該第一導電部對耦接。The circuit board of claim 1, wherein the third pair of conductive portions are coupled to the pair of first conductive portions through a pair of connecting portions. 如申請專利範圍第2項所述之電路板，其中該連接部對為一對過孔或埋孔。The circuit board of claim 2, wherein the pair of connecting portions is a pair of via holes or buried holes. 如申請專利範圍第1項所述之電路板，其中該第一元件及該第二元件為一電阻器。The circuit board of claim 1, wherein the first component and the second component are a resistor. 如申請專利範圍第1項所述之電路板，其中該第一元件及該第二元件為一電容器。The circuit board of claim 1, wherein the first component and the second component are a capacitor. 如申請專利範圍第5項所述之電路板，其中該電容器為一交流耦合電容器。The circuit board of claim 5, wherein the capacitor is an AC coupling capacitor. 如申請專利範圍第1項所述之電路板，其中該控制晶片 用於產生一高速訊號對。The circuit board of claim 1, wherein the control chip Used to generate a high speed signal pair. 如申請專利範圍第7所述之電路板，其中該高速訊號對為一高速差分訊號對。The circuit board of claim 7, wherein the high speed signal pair is a high speed differential signal pair. 一種電路板的共存佈線方法，包含下列步驟：於一第一佈線層上設置一第一導電部對，並使該第一導電部對耦接一控制晶片；於一第二佈線層上設置一第二導電部對、一第三導電部對及一第四導電部對，其中該第三導電部對設置於該第二導電部對及該第四導電部對之間；耦接該第三導電部對與該第一導電部對；以及當該第二導電部對耦接一電子裝置時，使該第二導電部對及該第三導電部對耦接；當該第四導電部對耦接一電子裝置時，使該第三導電部對及該第四導電部對耦接。A method for coexisting wiring of a circuit board includes the steps of: disposing a first conductive portion on a first wiring layer, and coupling the first conductive portion to a control wafer; and disposing a second wiring layer a second conductive portion pair, a third conductive portion pair and a fourth conductive portion pair, wherein the third conductive portion pair is disposed between the second conductive portion pair and the fourth conductive portion pair; coupled to the third The pair of conductive portions is opposite to the first conductive portion; and when the pair of second conductive portions is coupled to an electronic device, the second conductive portion pair is coupled to the third conductive portion; when the fourth conductive portion is paired When coupled to an electronic device, the third conductive portion pair and the fourth conductive portion pair are coupled. 如申請專利範圍第9項所述之共存佈線方法，其中該第三導電部是通過一連接部對與該第一導電部對耦接。The coexisting wiring method according to claim 9, wherein the third conductive portion is coupled to the first conductive portion through a pair of connecting portions. 如申請專利範圍第10項所述之共存佈線方法，其中該連接部對為一對過孔或埋孔。The coexisting wiring method according to claim 10, wherein the pair of connecting portions is a pair of via holes or buried holes. 如申請專利範圍第9項所述之共存佈線方法，其中該第一元件及該第二元件為一電阻器。The coexistence wiring method of claim 9, wherein the first component and the second component are a resistor. 如申請專利範圍第9項所述之共存佈線方法，其中該第一元件及該第二元件為一電容器。The coexistence wiring method of claim 9, wherein the first component and the second component are a capacitor. 如申請專利範圍第13項所述之共存佈線方法，其中該電容器為一交流耦合電容器。The coexistence wiring method according to claim 13, wherein the capacitor is an AC coupling capacitor. 如申請專利範圍第9項所述之共存佈線方法，其中該 控制晶片用於產生一高速訊號對。The coexistence wiring method according to claim 9 of the patent application, wherein the The control chip is used to generate a high speed signal pair. 如申請專利範圍第15項所述之共存佈線方法，其中該高速訊號對為一高速差分訊號對。The coexistence wiring method of claim 15, wherein the high speed signal pair is a high speed differential signal pair.
TW97130265A 2008-08-08 2008-08-08 Printed circuit board and coexisting layout method thereof TWI423744B (en)

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TWI491331B (en) * 2010-08-05 2015-07-01 鴻海精密工業股份有限公司 Printed circuit board
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Publication number Priority date Publication date Assignee Title
TWI231160B (en) * 2002-11-04 2005-04-11 Intel Corp A mechanism to cross high-speed differential pairs
TW200706075A (en) * 2005-07-29 2007-02-01 Hon Hai Prec Ind Co Ltd Method for matching impedance between difference vias and transmission lines

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI231160B (en) * 2002-11-04 2005-04-11 Intel Corp A mechanism to cross high-speed differential pairs
TW200706075A (en) * 2005-07-29 2007-02-01 Hon Hai Prec Ind Co Ltd Method for matching impedance between difference vias and transmission lines

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