TWI403233B - Method for performing a layout on a motherboard and a motherboard designed by the method - Google Patents
Method for performing a layout on a motherboard and a motherboard designed by the method Download PDFInfo
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- TWI403233B TWI403233B TW98116291A TW98116291A TWI403233B TW I403233 B TWI403233 B TW I403233B TW 98116291 A TW98116291 A TW 98116291A TW 98116291 A TW98116291 A TW 98116291A TW I403233 B TWI403233 B TW I403233B
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Description
本發明涉及一種主機板設計方法，尤其涉及一種主機板佈局佈線方法及利用該方法佈局佈線的主機板。The present invention relates to a motherboard design method, and more particularly to a motherboard layout and routing method and a motherboard for routing using the method.
目前的主機板佈局佈線設計方法中，如果需要在同一個印刷電路板上同時實現兩種不同規格的主機板，則需要運用共同佈局佈線(Co-lay)技術直接將兩種不同規格的零件相連(參閱圖1所示)，以實現兩種不同規格的主機板。但是，這種直接連接的方法會產生多餘的電路殘留線。In the current motherboard layout design method, if two different specifications of the motherboard are required to be simultaneously implemented on the same printed circuit board, it is necessary to directly connect two different specifications by using a common layout (Co-lay) technology. (See Figure 1) to implement two different sizes of motherboards. However, this method of direct connection produces extra circuit residual lines.
參閱圖1所示，當只使用連接器1，而不接連接器2時，連接器1和連接器2之間的連線將變成多餘的。而且，多餘的電路殘留線對連接器1上的訊號完整性會造成嚴重的反射效應。Referring to FIG. 1, when only the connector 1 is used, and the connector 2 is not connected, the connection between the connector 1 and the connector 2 becomes redundant. Moreover, the excess circuit residual line can have a severe reflection effect on the signal integrity on the connector 1.
鑒於以上內容，有必要提供一種主機板佈局佈線方法，其可利用導通孔與被動元件的焊盤連接，在主機板上佈局佈線兩種不同規格的零件，該方法包括如下步驟：在主機板上層放置兩個被動元件，下層放置兩個被動元件；用導通孔一連接主機板上層第一個被動元件的一端焊盤和該主機板下層對應的第一個被動元件的同一端焊盤；用導通孔二連接主機板上層第二個被動元件的與所述上層第一個被動元件同一端的焊盤和該主機板下層對應的第二個被動元件的同一端焊盤；將主機板上層的兩個被動元件的另外一端的焊盤連接至第一個零件，主機板下層的兩個被動元件的另外一端的焊盤連接至第二個零件。In view of the above, it is necessary to provide a motherboard layout method that can connect the pads to the pads of the passive components and lay out two different sizes of components on the motherboard. The method includes the following steps: Two passive components are placed, two passive components are placed in the lower layer; one end pad of the first passive component on the upper layer of the motherboard is connected with the same end pad of the first passive component corresponding to the lower layer of the motherboard; The hole 2 is connected to the same end pad of the second passive component of the upper passive layer of the upper layer and the second passive component corresponding to the lower layer of the lower layer of the motherboard; The pad on the other end of the passive component is connected to the first component, and the pad on the other end of the two passive components in the lower layer of the motherboard is connected to the second component.
鑒於以上內容，還有必要提供一種利用上述方法佈局佈線的主機板，所述主機板的上層放置有兩個被動元件，下層放置有兩個被動元件；主機板上層第一個被動元件的一端焊盤和該主機板下層對應的第一個被動元件的同一端焊盤透過導通孔一連接；主機板上層第二個被動元件的與所述上層第一個被動元件同一端的焊盤和該主機板下層對應的第二個被動元件的同一端焊盤透過導通孔二連接；主機板上層的兩個被動元件的另外一端的焊盤連接至第一個零件，主機板下層的兩個被動元件的另外一端的焊盤連接至第二個零件。In view of the above, it is also necessary to provide a motherboard that is laid out by the above method, the upper layer of the motherboard is placed with two passive components, the lower layer is placed with two passive components, and the one end of the first passive component of the motherboard is soldered. The same end pad of the first passive component corresponding to the lower layer of the motherboard is connected through the via hole; the pad of the second passive component of the motherboard and the same end of the first passive component of the upper layer and the motherboard The same end pad of the second passive component corresponding to the lower layer is connected through the via hole 2; the pad of the other end of the two passive components of the motherboard layer is connected to the first component, and the other two passive components of the lower layer of the motherboard The pad at one end is connected to the second part.
所述被動元件包括電容和電阻。The passive component includes a capacitor and a resistor.
所述第一個零件和第二個零件為不同規格的零件。The first part and the second part are parts of different specifications.
當使用兩個不同規格的零件中的一個時，只接主機板上層或下層的兩個被動元件，差分訊號相應地從主機板上層或下層通過，進入該零件。When one of two different gauge parts is used, only two passive components on the upper or lower layer of the main board are connected, and the differential signal is correspondingly passed from the upper or lower layer of the main board to enter the part.
相較於習知技術，所述的主機板佈局佈線方法，可以利用導通孔與被動元件的焊盤連接，在主機板上佈局佈線兩種不同規格的零件，避免了不同規格零件的訊號相互之間產生干擾。Compared with the prior art, the motherboard layout method can connect the pads to the pads of the passive components, and lay and route two different specifications on the motherboard, thereby avoiding signals of different specifications. Interference occurs.
參閱圖1所示，係現有技術中主機板共同佈局佈線的方法。在圖1中，零件1和零件2為兩種不同規格的零件，本實施方式中以連接器為例進行說明，以下描述稱為連接器1和連接器2。在其他實施方式中，零件1和零件2也可以選用相同規格的零件。當只使用連接器1，而不接連接器2時，連接器1和連接器2之間的連線3將變成多餘的(標記為stub)。Referring to FIG. 1 , it is a method for common layout of a motherboard in the prior art. In FIG. 1, the part 1 and the part 2 are two different sizes of components. In the present embodiment, a connector is taken as an example, and the following description is referred to as a connector 1 and a connector 2. In other embodiments, parts 1 and 2 may also be selected from the same size. When only the connector 1 is used, and the connector 2 is not connected, the connection 3 between the connector 1 and the connector 2 will become redundant (labeled as a stub).
參閱圖2所示，係本發明主機板佈局佈線方法的平面圖，其中，差分訊號控制晶片用於輸出差分訊號，在本實施方式中，該差分訊號控制晶片位於主機板的南橋晶片組或北橋晶片組中。圖3A和圖3B是本發明主機板佈局佈線方法的立體圖，參閱圖3A和圖3B所示，該方法在主機板佈局佈線時，在主機板上層放置兩個被動元件，參閱圖3A所示的電容41和電容51，在主機板下層放置兩個被動元件，參閱圖3B所示的電容42和電容52。然後，用導通孔一連接主機板上層第一個被動元件的一端焊盤和該主機板下層對應的第一個被動元件的同一端焊盤，例如，圖3A所示的利用導通孔4連接電容41的焊盤h1和電容42的焊盤h2；用導通孔二連接主機板上層第二個被動元件的與所述上層第一個被動元件同一端的焊盤和該主機板下層對應的第二個被動元件的同一端焊盤，例如，圖3B所示的利用導通孔5連接電容51的焊盤h3和電容52的焊盤h4。最後，將主機板上層的兩個被動元件的另外一端的焊盤連接至兩個不同規格的零件中的一個，如將上層的電容41的焊盤h5和電容51的焊盤h7連接至連接器1；將主機板下層的兩個被動元件的另外一端的焊盤連接至兩個不同規格的零件中的另外一個，如將下層的電容42的焊盤h6和電容52的焊盤h8連接至連接器2。所述被動元件可以是電容或電阻，本實施方式中採用電容(根據需要也可以選擇電阻)。Referring to FIG. 2, it is a plan view of a layout method of a motherboard of the present invention, wherein the differential signal control chip is used for outputting a differential signal. In the embodiment, the differential signal control chip is located on a south bridge chipset or a north bridge chip of the motherboard. In the group. 3A and FIG. 3B are perspective views of the layout method of the motherboard of the present invention. Referring to FIG. 3A and FIG. 3B, the method places two passive components on the motherboard during the layout of the motherboard, as shown in FIG. 3A. Capacitor 41 and capacitor 51 place two passive components on the lower layer of the motherboard, see capacitor 42 and capacitor 52 shown in Figure 3B. Then, the one end pad of the first passive component on the motherboard layer and the same end pad of the first passive component corresponding to the lower layer of the motherboard are connected by the via hole, for example, the capacitor connected by the via hole 4 is shown in FIG. 3A. a pad h1 of 41 and a pad h2 of the capacitor 42; a via 2 for connecting a pad of the second passive component of the motherboard with the same end of the first passive component of the upper layer and a second corresponding to the lower layer of the motherboard The same end pad of the passive component, for example, the pad h3 of the capacitor 51 and the pad h4 of the capacitor 52 are connected by the via 5 as shown in FIG. 3B. Finally, the pad of the other end of the two passive components of the motherboard is connected to one of two different specifications, such as the pad h5 of the upper capacitor 41 and the pad h7 of the capacitor 51 to the connector. 1; connect the pad of the other end of the two passive components of the lower layer of the motherboard to the other of the two different specifications, such as connecting the pad h6 of the lower capacitor 42 and the pad h8 of the capacitor 52 to the connection Device 2. The passive component may be a capacitor or a resistor, and a capacitor is used in the embodiment (a resistor may be selected as needed).
在本實施方式中，主機板上層的兩個被動元件另外一端的焊盤連接至連接器1，主機板下層的兩個被動元件對應的一端的焊盤連接至連接器2。在其他實施方式中，主機板上層的兩個被動元件的另外一端的焊盤也可以連接至連接器2，而主機板下層的兩個被動元件的對應的一端的焊盤則連接至連接器1。In the present embodiment, the pads of the other end of the two passive components of the motherboard are connected to the connector 1, and the pads of the corresponding ones of the two passive components of the lower layer of the motherboard are connected to the connector 2. In other embodiments, the pads of the other end of the two passive components of the motherboard layer may also be connected to the connector 2, and the pads of the corresponding one ends of the two passive components of the lower layer of the motherboard are connected to the connector 1 .
在圖3A和圖3B中，以電容為例進行說明。其中，電容41和電容51位於主機板上層(如圖3A的線路一所示)，電容42和電容52位於主機板下層(如圖3B的線路二所示)，導通孔4分別連接電容41一端的焊盤h1和電容42一端的焊盤h2，導通孔5分別連接電容51一端的焊盤h3和電容52一端的焊盤h4。電容41和電容51另外一端的焊盤h5和h7連接至連接器1，電容42和電容52另外一端的焊盤h6和h8連接至連接器2。In FIGS. 3A and 3B, a capacitor will be described as an example. The capacitor 41 and the capacitor 51 are located on the upper board layer (as shown in line 1 of FIG. 3A), the capacitor 42 and the capacitor 52 are located on the lower layer of the motherboard (as shown in line 2 of FIG. 3B), and the via hole 4 is respectively connected to the end of the capacitor 41. The pad h1 and the pad h2 at one end of the capacitor 42 connect the pad h3 at one end of the capacitor 51 and the pad h4 at one end of the capacitor 52, respectively. The pads 41 and h7 at the other end of the capacitor 41 and the capacitor 51 are connected to the connector 1, and the pads h6 and h8 at the other end of the capacitor 42 and the capacitor 52 are connected to the connector 2.
使用連接器1時，只接主機板上層的兩個被動元件(電容41和電容51)，差分訊號從主機板上層通過(如虛線所示)，進入連接器1，參閱圖3A中的線路一所示。When connector 1 is used, only two passive components (capacitor 41 and capacitor 51) on the upper layer of the motherboard are connected, and the differential signal passes through the upper layer of the motherboard (as indicated by a broken line), and enters connector 1, see line 1 in FIG. 3A. Shown.
使用連接器2時，只接主機板下層的兩個被動元件(電容42和電容52)，差分訊號從主機板下層通過(如虛線所示)，進入連接器2，參閱圖3B中的線路二所示。When connector 2 is used, only two passive components (capacitor 42 and capacitor 52) on the lower layer of the motherboard are connected, and the differential signal passes through the lower layer of the motherboard (as indicated by a broken line), and enters connector 2, see line 2 in FIG. 3B. Shown.
無論是線路一的訊號流向，還是線路二的訊號流向，都可以維持高速差分訊號的完整性。Whether the signal flow of line one or the signal flow of line two can maintain the integrity of high-speed differential signals.
對比圖4A和圖5A，圖4A為採用現有技術類比相鄰插槽的結果示意圖，可見會產生800mil(mil，密耳為長度單位，即0.0254毫米，也等於一英寸的千分之一)的線路殘餘，而圖5A為利用線路一進行的類比相鄰插槽的結果示意圖，完全消除了多餘的電路殘餘線。4A and FIG. 5A, FIG. 4A is a schematic diagram showing the results of using an analogous adjacent slot in the prior art. It can be seen that 800 mil (mil, mil is the length unit, ie, 0.0254 mm, which is also equal to one thousandth of an inch). The line remains, and Figure 5A is a schematic diagram of the results of analogous adjacent slots using line one, completely eliminating redundant circuit residual lines.
同樣，圖4B為採用現有技術類比間隔插槽的結果示意圖，會產生1600mil的線路殘餘，而圖5B為利用線路二進行的類比間隔插槽的結果示意圖，則完全消除了多餘的電路殘餘線。Similarly, FIG. 4B is a schematic diagram showing the results of a prior art analog-spaced slot, which results in a 1600 mil line residual, and FIG. 5B is a schematic diagram of the result of an analog-spaced slot using line two, completely eliminating redundant circuit residual lines.
透過上述比對圖4和圖5的類比結果可知，現有技術中的主機板佈局佈線方法的高速差分訊號具有較差的訊號完整性，而利用導通孔與被動元件的焊盤連接，在主機板上佈局佈線兩種不同規格的零件，可以完全消除多餘的電路殘餘線，保證差分訊號的完整性。Through the comparison of the analogy results of FIG. 4 and FIG. 5, the high-speed differential signal of the motherboard layout method in the prior art has poor signal integrity, and the via is connected to the pad of the passive component on the motherboard. Layout and routing of two different sizes of parts can completely eliminate redundant circuit residual lines and ensure the integrity of differential signals.
最後應說明的是，以上實施方式僅用以說明本發明的技術方案而非限制，儘管參照較佳實施方式對本發明進行了詳細說明，本領域的普通技術人員應當理解，可以對本發明的技術方案進行修改或等同替換，而不脫離本發明技術方案的精神和範圍。It should be noted that the above embodiments are merely illustrative of the technical solutions of the present invention, and the present invention is not limited thereto. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that Modifications or equivalents are made without departing from the spirit and scope of the invention.
1．．．零件1. . . Components
2．．．零件2. . . Components
4．．．導通孔4. . . Via
5．．．導通孔5. . . Via
41．．．電容41. . . capacitance
42．．．電容42. . . capacitance
51．．．電容51. . . capacitance
52．．．電容52. . . capacitance
h1與h5．．．電容41的焊盤H1 and h5. . . Pad of capacitor 41
h2與h6．．．電容42的焊盤H2 and h6. . . Pad of capacitor 42
h3與h7．．．電容51的焊盤H3 and h7. . . Pad of capacitor 51
h4與h8．．．電容52的焊盤H4 and h8. . . Pad of capacitor 52
圖1係現有技術中主機板共同佈局佈線的方法。FIG. 1 is a schematic diagram of a common layout of a motherboard in the prior art.
圖2係本發明主機板佈局佈線方法的平面圖。2 is a plan view showing a method of layout and wiring of a motherboard of the present invention.
圖3A和圖3B係本發明主機板佈局佈線方法的立體圖。其中，圖3A係圖2中線路一的主機板佈局佈線立體圖，圖3B係圖2中線路二的主機板佈局佈線立體圖。3A and 3B are perspective views of a layout method of a motherboard of the present invention. 3A is a perspective view of the layout of the motherboard of the line 1 in FIG. 2, and FIG. 3B is a perspective view of the layout of the motherboard of the line 2 in FIG.
圖4係採用現有技術進行主機板佈局佈線的差分訊號傳輸類比結果示意圖。其中，圖4A為相鄰插槽的類比結果示意圖，圖4B為間隔插槽的類比結果示意圖。FIG. 4 is a schematic diagram showing the analogy results of differential signal transmission using the prior art for motherboard layout and routing. 4A is a schematic diagram of analogy results of adjacent slots, and FIG. 4B is a schematic diagram of analogy results of slotted slots.
圖5係採用本發明所述主機板佈局佈線方法差分訊號傳輸的類比結果示意圖。其中，圖5A為線路一的類比結果示意圖，圖5B為線路二的類比結果示意圖。FIG. 5 is a schematic diagram showing the analogy result of differential signal transmission by using the layout and routing method of the motherboard of the present invention. 5A is a schematic diagram of the analogy result of the line one, and FIG. 5B is a schematic diagram of the analogy result of the line 2.
1．．．零件1. . . Components
2．．．零件2. . . Components
4．．．導通孔4. . . Via
5．．．導通孔5. . . Via
41．．．電容41. . . capacitance
42．．．電容42. . . capacitance
51．．．電容51. . . capacitance
52．．．電容52. . . capacitance
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| TWI683613B (en) * | 2017-02-10 | 2020-01-21 | 華碩電腦股份有限公司 | Circuit layout structure |
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| TWI484882B (en) * | 2011-12-30 | 2015-05-11 | Uer Technology Corp | Welding structure and welding method for connecting lithium battery to electric circuit board |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TW200524484A (en) * | 2003-12-24 | 2005-07-16 | Sanyo Electric Co | Hybrid integrated circuit device and manufacturing method thereof |
| CN2746714Y (en) * | 2004-10-27 | 2005-12-14 | 威盛电子股份有限公司 | Signal transmission structure of line substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200524484A (en) * | 2003-12-24 | 2005-07-16 | Sanyo Electric Co | Hybrid integrated circuit device and manufacturing method thereof |
| CN2746714Y (en) * | 2004-10-27 | 2005-12-14 | 威盛电子股份有限公司 | Signal transmission structure of line substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI683613B (en) * | 2017-02-10 | 2020-01-21 | 華碩電腦股份有限公司 | Circuit layout structure |
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