TWI421988B - 凸塊接墊結構 - Google Patents

凸塊接墊結構 Download PDF

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TWI421988B
TWI421988B TW100144118A TW100144118A TWI421988B TW I421988 B TWI421988 B TW I421988B TW 100144118 A TW100144118 A TW 100144118A TW 100144118 A TW100144118 A TW 100144118A TW I421988 B TWI421988 B TW I421988B
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conductive
layer
bump
pad
pad structure
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TW201308542A (zh
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Ming Tzong Yang
yu hua Huang
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Mediatek Inc
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Description

凸塊接墊結構
本發明係有關於一種半導體封裝技術，特別是有關於一種用於電子裝置的互連(interconnection)的凸塊接墊(bump pad)結構。
在微電子工業中，積體電路(integrated circuit,IC)的製造通常包括IC的製作與封裝。IC晶片(dies/chips)需經過封裝並透過凸塊/接合接墊(bump/bond pads)而電性連接至外部電路，例如封裝基板、印刷電路板(printed circuit board,PCB)或其他晶片。為了將晶片連接至外部電路，通常會使用接線及/或導電凸塊。舉例來說，將導電凸塊形成於一晶片的對應的凸塊/接合接墊上，接著將晶片翻轉，藉以將導電凸塊連接至形成於一外部電路上所對應的接觸接點(contact)上。
近來，由於製造成本持續增加以及加上環境因素，越來越多使用無鉛焊料來作為導電凸塊。然而，上述的無鉛焊料會因為無鉛焊料的遷移而造成白凸塊(white bump)的現象。「白凸塊」一詞表示在一封裝中，因為連接晶片時垂直應力的轉移或是因為連接晶片之後進行其他熱製程步驟而造成晶片破裂的問題。由於堅硬的無鉛凸塊，使白凸塊的問題在無鉛覆晶接合(Controlled Collapse Chip Connection,C4)技術中特別的嚴重。
第1圖為用於晶片的習知凸塊接墊結構100的剖面示意圖。凸塊接墊結構100包括一絕緣層101，例如低介電材料(low-k material)層，其具有多層互連結構，包括彼此分隔開的金屬層102、104、106及108。再者，金屬介層插塞(via plug)(例如，金屬介層插塞103、107)設置於金屬層102、104、106及108之間，且與其電性連接。多層互連結構通常連接至晶片中的電子裝置(未繪示)。一凸塊接墊112直接形成於多層互連結構的最上層金屬層108上，且其局部為一鈍化保護層110所覆蓋。一凸塊下方金屬(under bump metallurgic,UBM)層114形成於凸塊接墊112上，且露出於鈍化保護層110，用以放置無鉛焊料凸塊(未繪示)。
在上述的凸塊接墊結構100中，凸塊接墊112通常使用較大的介層窗(via)112a來連接多層互連結構，因而產生較大的垂直應力。為了防止絕緣層101因施加的應力而受到損害，通常會使用至少二層較厚的金屬層106及108。若僅使用一層較厚的金屬層，較大的垂直應力會引發如上所述的「白凸塊」的問題，因而降低裝置的可靠度。然而，使用二層較厚的金屬層則會增加製造成本。因此，有必要尋求一種新的凸塊接墊結構，其能夠改善上述的問題。
有鑒於此，本發明之目的在於提供改良式的凸塊接墊結構，以改善上述白凸塊的問題。
本發明一實施例提供一種凸塊接墊結構，包括：一絕緣層；一導電接墊，設置於絕緣層上；一環型導電層，埋設於絕緣層內且大體上沿著導電接墊的邊緣下方；以及至少一第一導電介層插塞，埋設於絕緣層內且位於導電接墊與環型導電層之間，使導電接墊電性連接至環型導電層。
本發明另一實施例提供一種凸塊接墊結構，包括：一絕緣層；一導電接墊，設置於絕緣層上；至少一導電區段，埋設於絕緣層內且大體上沿著導電接墊的邊緣下方；以及至少一第一導電介層插塞，埋設於絕緣層內且位於導電接墊與導電區段之間，使導電接墊電性連接至導電區段。
本發明所提出之凸塊接墊結構，藉由環型導電層/導電區段設置於絕緣層內且大體上沿著導電接墊的邊緣下方，以及第一導電介層插塞的設置，可以減輕或排除白凸塊的問題。
以下說明包含了本發明實施例之製作與目的。然而，可輕易了解以下說明在於闡明本發明實施例之製做與使用，並非用於限定本發明的範圍。在圖式及內文中，相同或相似的部件係使用相同或相似的標號。再者，為了圖式的簡化與便利性，圖式中部件的外形及厚度得以放大。另外，未繪示或未揭露於圖式及內文中的部件係熟習技藝中慣用的部件。
請參照第2A及2B圖，第2A圖為根據本發明一實施例之具有環型導電層之凸塊接墊結構的剖面示意圖，第2B圖為第2A圖中環型導電層的平面示意圖。凸塊接墊結構200可使用於一晶片或封裝基底等等。請參照第2A圖，凸塊接墊結構200包括一絕緣層201。在一實施例中，絕緣層201係形成於一半導體基底(未繪示)上。半導體基底可包括矽基底或其他半導體材料基底。半導體基底可包含各種元件，例如可包括電晶體、電阻及其他熟習的半導體元件。絕緣層201可作為內層介電層(interlayer dielectric，ILD)或是金屬層間介電層(inter-metal dielectric，IMD)，且絕緣層201可包括氧化物、氮化物、氮氧化物或其組合，或低介電材料(low-k material)，例如氟矽玻璃(fluorinated silicate glass，FSG)、摻雜碳的氧化物(carbon doped oxide)、甲基矽酸鹽類(methyl silsequioxane，MSQ)、含氫矽酸鹽類(hydrogen silsequioxane，HSQ)、或氟四乙基矽酸鹽(fluorine tetra-ethyl-orthosilicate，FTEOS)等。絕緣層201可藉由化學氣相沉積(chemical vapor deposition，CVD)、低壓化學氣相沉積(low pressure CVD，LPCVD)、電漿增強化學氣相沉積(plasma enhanced CVD，PECVD)、高密度電漿化學氣相沉積(high density plasma CVD，HDPCVD)、或其他習知沉積技術形成之。
一多層互連結構埋設於絕緣層201內，且電性連接至形成於半導體基底內或半導體基底上的的元件(未繪示)。多層互連結構可藉由習知的鑲嵌製程而形成，且其包括複數個導電層202，位於絕緣層201內不同的層位，使內部的導電層202能夠彼此分隔開來。再者，多互連結構也包括複數個導電介層插塞203，設置於絕緣層201內位於不同層位的導電層202之間，且電性連接至這些導電層202。
作為凸塊/接合接墊的一導電接墊212係設置於絕緣層201上。導電接墊212可包括鋁、銅、其合金或其他適當的習知金屬材料。
一鈍化保護層210係形成於絕緣層201上，且覆蓋導電接墊212。鈍化保護層210可包括有機材料(例如，綠漆(solder mask))或無機材料(例如，氧化矽或氮化矽)，且可透過沉積製程而形成。鈍化保護層210內形成一開口，以露出導電接墊212的上表面而作為後續凸塊製程的接觸窗口。
一凸塊下方金屬(UBM)層214形成於自鈍化保護層210露出的導電接墊212上，用以放置一無鉛焊料凸塊(未繪示)。通常凸塊下方金屬層214為一多層結構，且可包括一黏著層(例如，鈦鎢(TiW))，接著為一擴散阻障層(例如，鎳、鎳釩或鉻銅(Ni、NiV or CrCu))以及一焊料潤濕層(例如，銅)。
在本實施例中，特別的是一環型導電層206(其厚度大於多層互連結構中每一導電層202的厚度)埋設於絕緣層201內，且其位於高於多層互連結構的層位，以降低自導電接墊212施加至多層互連結構的巨大垂直應力。
環型導電層206可包括銅，且可藉由習知鑲嵌製程而形成。再者，環型導電層206大體上設置於導電接墊212的下方並沿著導電接墊212的邊緣，且透過導電介層插塞205(其埋設於環型導電層206與多層互連結構之間的絕緣層201內)而電性連接至多層互連結構，使來自導電接墊212的垂直應力可由環型導電層206以及位於導電接墊212與多層互連結構之間的絕緣層201來共同分擔。也就是說，位於導電接墊212與多層互連結構之間的絕緣層201部分可作為應力緩衝層，用以降低施加於多層互連結構的應力。
在一實施例中，如第2B圖所示，環型導電層206的俯視形狀為八邊形。在另一實施例中，環型導電層206的俯視形狀可為圓形、矩形、六邊形或其他形狀。
至少一導電介層插塞208埋設於導電接墊212與環型導電層206之間的絕緣層201內，使導電接墊212電性連接至環型導電層206。在本實施例中，複數個導電介層插塞208埋設於絕緣層201內，且對應排列於八邊形的環型導電層206的邊緣。再者，每一導電介層插塞208在俯視圖中的形狀可為矩形、方形或其他形狀。
由於所施加的應力是從導電接墊212經過每一導電介層插塞208與環型導電層206至多層互連結構，且導電介層插塞208的面積小於第1圖中所示的介層窗112a的面積，因此可施加一相對較小的應力至多層互連結構。再者由於自導電接墊212施加的應力集中於導電接墊212的中心附近，環型導電層206放置於導電接墊212的邊緣下方，也會使得施加到多層互連結構的應力較小。因此，因多層互連結構上的應力轉移而造成絕緣層201損壞的問題得以減輕或排除。另外，相較於習知技術中使用二層厚的金屬層來防止白凸塊問題來說，根據上述實施例之具有環型導電層的凸塊接墊結構可進一步降低製造成本而增加產品的競爭力。
請參照第3A及3B圖，第3A圖為根據本發明一實施例之具有環型導電層之凸塊接墊結構的剖面示意圖，第3B圖為第3A圖中環型導電層的平面示意圖，其中相同於第2A及2B圖的部件使用相同的標號並省略其說明。在本實施例中，除了一浮置(floating)導電層207埋設於導電接墊212正下方的絕緣層201內且被環型導電層206所圍繞之外，第3A及3B圖中的凸塊接墊結構200的結構相同於第2A及2B圖所示的實施例。
「浮置」一詞表示導電層207與導電接墊212以及形成於半導體基底內及其上的任何元件(如以上所述)電性隔離。在本實施例中，浮置導電層207與環型導電層206位於相同的層位。在一實施例中，浮置導電層207與環型導電層206可同時藉由習知鑲嵌製程而形成，因此浮置導電層207與環型導電層206可包括相同的材料。另外，浮置導電層207也可在形成環型導電層206之前或之後才形成，其可包括與環型導電層206的材料相同或不同的材料。
上述額外的浮置導電層207可進一步加強凸塊接墊結構200中對導電接墊212的支撐性。再者，由於導電層207為浮置的，因此浮置導電層207不會引起寄生電容(parasitic capacitance)。另外，本實施例的凸塊接墊結構200同樣可獲得第2A圖中的凸塊接墊結構200所能獲得的優點。
請參照第4A及4B圖，第4A圖為根據本發明一實施例之具有導電區段之凸塊接墊結構的剖面示意圖，第4B圖為第4A圖中導電區段的平面示意圖，其中相同於第2A及2B圖的部件使用相同的標號並省略其說明。在本實施例中，凸塊接墊結構200相似於第2A圖中所示的凸塊接墊結構，而不同之處在於以至少一導電區段206a(其大體上位於導電接墊212邊緣的下方)取代第2A圖中的環型導電層206，且使至少一導電介層插塞208埋設於導電接墊212與導電區段206a之間的絕緣層201內，用以作為導電接墊212與導電區段206a之間的電性連接。
在本實施例中，由於導電區段206a所佔據的面積小於第2A圖中環型導電層206所佔據的面積，因此所省下的面積可供接線佈線之用，藉以增加接線佈線的設計彈性。同樣地，本實施例的凸塊接墊結構200同樣可獲得第2A圖中的凸塊接墊結構200所能獲得的優點。
在另一實施例中，如第4B圖所示，凸塊接墊結構200可包括複數個導電區段206a及與其對應的複數個導電介層插塞208。舉例來說，上述導電區段206a排列成環且大體上位於導電接墊212的邊緣下方。同樣地，本實施例的凸塊接墊結構200同樣可獲得第2A圖中的凸塊接墊結構200所能獲得的優點。需注意的是雖然本實施例中不連續環的俯視形狀為八邊形，然而在一些實施例中，其亦可為矩形、六邊形或者其他形狀。
在另一實施例中，如第4B圖所示，凸塊接墊結構200更包括一浮置導電層207埋設於導電接墊212正下方的絕緣層201內，且被上述導電區段206a所圍繞。因此，本實施例的凸塊接墊結構200同樣可獲得第3A圖中凸塊接墊結構200所能獲得的優點。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．凸塊接墊結構
101．．．絕緣層
102、104、106、108．．．金屬層
103、107．．．金屬介層插塞
110．．．鈍化保護層
112．．．凸塊接墊
112a．．．介層窗
114．．．凸塊下方金屬層
200．．．凸塊接墊結構
201．．．絕緣層
202．．．金屬層
203、205、208．．．金屬介層插塞
206．．．環型導電層
206a．．．導電區段
207．．．浮置導電層
210．．．鈍化保護層
212．．．凸塊接墊
214．．．凸塊下方金屬層
第1圖為用於晶片的習知凸塊接墊結構之剖面示意圖；
第2A圖為根據本發明一實施例之具有環型導電層之凸塊接墊結構之剖面示意圖；
第2B圖為第2A圖中環型導電層之平面示意圖；
第3A圖為根據本發明另一實施例之具有環型導電層之凸塊接墊結構之剖面示意圖；
第3B圖為第3A圖中環型導電層之平面示意圖；
第4A圖為根據本發明一實施例之具有導電區段之凸塊接墊結構之剖面示意圖；及
第4B圖為第4A圖中導電區段之平面示意圖。
200．．．凸塊接墊結構
201．．．絕緣層
202．．．金屬層
203、205、208．．．金屬介層插塞
206．．．環型導電層
210．．．鈍化保護層
212．．．凸塊接墊
214．．．凸塊下方金屬層

Claims (19)

  1. 一種凸塊接墊結構，包括：一絕緣層；一導電接墊，設置於該絕緣層上；一環型導電層，埋設於該絕緣層內且大體上沿著該導電接墊的邊緣下方；以及至少一第一導電介層插塞，埋設於該絕緣層內且位於該導電接墊與該環型導電層之間，使該導電接墊電性連接至該環型導電層。
  2. 如申請專利範圍第1項所述之凸塊接墊結構，更包括一浮置導電層，埋設於該導電接墊正下方的該絕緣層內且被該環型導電層所圍繞。
  3. 如申請專利範圍第1項所述之凸塊接墊結構，更包括一多層互連結構，埋設於該環型導電層下方的該絕緣層內且電性連接至該環型導電層，該多層互連結構包括：彼此分隔開的複數個導電層；以及複數個第二導電介層插塞，設置於該等導電層之間且電性連接至該等導電層。
  4. 如申請專利範圍第1項所述之凸塊接墊結構，更包括一凸塊下方金屬層，設置於該導電接墊上。
  5. 如申請專利範圍第1項所述之凸塊接墊結構，其中該導電接墊包括鋁。
  6. 如申請專利範圍第1項所述之凸塊接墊結構，其中該環型導電層包括銅。
  7. 如申請專利範圍第1項所述之凸塊接墊結構，其中該環型導電層的俯視形狀為圓形、矩形、六邊形、或八邊形。
  8. 如申請專利範圍第1項所述之凸塊接墊結構，其中該第一導電介層插塞與該導電接墊包括相同的材料。
  9. 如申請專利範圍第1項所述之凸塊接墊結構，其中該第一導電介層插塞的俯視形狀為矩形或方形。
  10. 一種凸塊接墊結構，包括：一絕緣層；一導電接墊，設置於該絕緣層上；至少一導電區段，埋設於該絕緣層內且大體上沿著該導電接墊的邊緣下方；以及至少一第一導電介層插塞，埋設於該絕緣層內且位於該導電接墊與該導電區段之間，使該導電接墊電性連接至該導電區段。
  11. 如申請專利範圍第10項所述之凸塊接墊結構，其中該凸塊接墊結構包括複數個導電區段以及與其對應的複數個第一導電介層插塞，且其中該等導電區段排列成一個環，且大體上沿著該導電接墊的邊緣下方。
  12. 如申請專利範圍第11項所述之凸塊接墊結構，更包括一浮置導電層，埋設於該導電接墊正下方的該絕緣層內且被該等導電區段所圍繞。
  13. 如申請專利範圍第11項所述之凸塊接墊結構，其中該環的俯視形狀為圓形、矩形、六邊形、或八邊形。
  14. 如申請專利範圍第10項所述之凸塊接墊結構，更包括一多層互連結構，埋設於該導電區段下方的該絕緣層內且電性連接至該導電區段，該多層互連結構包括：彼此分隔開的複數個導電層；以及複數個第二導電介層插塞，設置於該等導電層之間且電性連接至該等導電層。
  15. 如申請專利範圍第10項所述之凸塊接墊結構，更包括一凸塊下方金屬層，設置於該導電接墊上。
  16. 如申請專利範圍第10項所述之凸塊接墊結構，其中該導電接墊包括鋁。
  17. 如申請專利範圍第10項所述之凸塊接墊結構，其中該導電區段包括銅。
  18. 如申請專利範圍第10項所述之凸塊接墊結構，其中該第一導電介層插塞與該導電接墊包括相同的材料。
  19. 如申請專利範圍第10項所述之凸塊接墊結構，其中該第一導電介層插塞的俯視形狀為矩形或方形。
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