TWI421508B - Power supply voltage reduction detection circuit - Google Patents
Power supply voltage reduction detection circuit Download PDFInfo
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- TWI421508B TWI421508B TW097130437A TW97130437A TWI421508B TW I421508 B TWI421508 B TW I421508B TW 097130437 A TW097130437 A TW 097130437A TW 97130437 A TW97130437 A TW 97130437A TW I421508 B TWI421508 B TW I421508B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0084—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring voltage only
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
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Description
本發明係關於一種用以檢測電源電壓之降低的電源電壓降低檢測電路。The present invention relates to a power supply voltage drop detecting circuit for detecting a decrease in a power supply voltage.
一般而言，半導體裝置係裝載有用以檢測電源電壓之降低的電源電壓降低檢測電路。當該電源電壓降低檢測電路檢測出電源電壓未達最低動作電壓時，半導體裝置係藉由截斷(shutdown)進行錯誤動作的電路或電源電壓降低檢測電路以外的所有電路，而使錯誤動作消失。In general, a semiconductor device is provided with a power supply voltage drop detecting circuit for detecting a decrease in a power supply voltage. When the power supply voltage drop detecting circuit detects that the power supply voltage has not reached the minimum operating voltage, the semiconductor device causes the erroneous operation to disappear by shutting down all circuits other than the circuit that performs the erroneous operation or the power supply voltage lowering detecting circuit.
在此說明半導體裝置的最低動作電壓。The lowest operating voltage of the semiconductor device will be described here.
第5圖係顯示半導體裝置之要素電路之例的電路圖。第5圖的電路係藉由NMOS電晶體31至34所構成的NMOS疊接式(cascode type)的電流鏡電路。該電路的最低動作電壓係NMOS電晶體31之臨限值電壓的絕對值及過驅動電壓的合計、與NMOS電晶體32之臨限值電壓的絕對值及過驅動電壓的合計的和電壓。Fig. 5 is a circuit diagram showing an example of an element circuit of a semiconductor device. The circuit of Fig. 5 is an NMOS cascode type current mirror circuit composed of NMOS transistors 31 to 34. The lowest operating voltage of the circuit is the sum of the absolute value of the threshold voltage and the overdrive voltage of the NMOS transistor 31, and the sum of the absolute value of the threshold voltage of the NMOS transistor 32 and the overdrive voltage.
第6圖係顯示半導體裝置之其他要素電路之例的電路圖。第6圖的電路係藉由PMOS電晶體41至44所構成的PMOS疊接式的電流鏡電路。該電路的最低動作電壓係PMOS電晶體41之臨限值電壓的絕對值及過驅動電壓的合計、與PMOS電晶體42之臨限值電壓的絕對值及過驅動電壓的合計的和電壓。Fig. 6 is a circuit diagram showing an example of other element circuits of the semiconductor device. The circuit of Fig. 6 is a PMOS stacked current mirror circuit composed of PMOS transistors 41 to 44. The lowest operating voltage of the circuit is the sum of the absolute value of the threshold voltage and the overdrive voltage of the PMOS transistor 41, and the sum of the absolute value of the threshold voltage of the PMOS transistor 42 and the overdrive voltage.
第7圖係顯示半導體裝置之其他要素電路之例的電路圖。第7圖的電路係藉由PMOS電晶體51、PMOS電晶體55至56、NMOS電晶體52、NMOS電晶體54及電阻53所構成的定電流電路。使該電路進行動作的訊號係輸入至PMOS電晶體55的閘極，當PMOS電晶體55導通(ON)時，該電路即進行動作。該電路的最低動作電壓係NMOS電晶體52之臨限值電壓的絕對值及過驅動電壓的合計、與NMOS電晶體54之臨限值電壓的絕對值及過驅動電壓的合計的和電壓、以及PMOS電晶體55之臨限值電壓的絕對值及過驅動電壓的合計、與PMOS電晶體56之臨限值電壓的絕對值及過驅動電壓的合計的和電壓中較高者的電壓。Fig. 7 is a circuit diagram showing an example of other element circuits of the semiconductor device. The circuit of Fig. 7 is a constant current circuit composed of a PMOS transistor 51, PMOS transistors 55 to 56, an NMOS transistor 52, an NMOS transistor 54, and a resistor 53. The signal for operating the circuit is input to the gate of the PMOS transistor 55, and the circuit operates when the PMOS transistor 55 is turned "ON". The minimum operating voltage of the circuit is the sum of the absolute value of the threshold voltage and the overdrive voltage of the NMOS transistor 52, the sum of the absolute value of the threshold voltage of the NMOS transistor 54 and the overdrive voltage, and The sum of the absolute value of the threshold voltage and the overdrive voltage of the PMOS transistor 55, and the voltage of the sum of the sum of the absolute value of the threshold voltage of the PMOS transistor 56 and the overdrive voltage.
半導體裝置一般而言係大部分使用上述要素電路，因此半導體裝置的最低動作電壓係半導體裝置內和電壓為最高的2個NMOS電晶體中之一個NMOS電晶體之臨限值電壓的絕對值及過驅動電壓的合計、與另一NMOS電晶體之臨限值電壓的絕對值及過驅動電壓的合計的和電壓、以及半導體裝置內和電壓為最高的2個PMOS電晶體中之一個PMOS電晶體之臨限值電壓的絕對值及過驅動電壓的合計、與另一PMOS電晶體之臨限值電壓的絕對值及過驅動電壓的合計的和電壓中較高者的電壓。In general, a semiconductor device generally uses the above-described element circuit. Therefore, the minimum operating voltage of the semiconductor device is the absolute value of the threshold voltage of one of the two NMOS transistors in the semiconductor device and the highest voltage. The sum of the driving voltage, the sum of the absolute value of the threshold voltage of the other NMOS transistor and the overdrive voltage, and the PMOS transistor of the two PMOS transistors having the highest voltage and the highest voltage in the semiconductor device. The sum of the absolute value of the threshold voltage and the overdrive voltage, and the voltage of the sum of the sum of the absolute value of the threshold voltage of the other PMOS transistor and the overdrive voltage.
就習知之電源電壓降低檢測電路加以說明。第8圖係顯示習知之電源電壓降低檢測電路之示意圖。A description will be given of a conventional power supply voltage drop detecting circuit. Figure 8 is a schematic diagram showing a conventional power supply voltage drop detecting circuit.
習知之電源電壓降低檢測電路係具備有：用以輸出基準電壓的基準電壓電路72；以電阻75與電阻76將電源71的電源電壓分壓而將分壓電壓予以輸出的分壓電路73；將基準電壓與分壓電壓作比較而檢測電源電壓之降低的差動放大電路74；以及將差動放大電路74的輸出端子上拉(pull up)的上拉電阻77(例如參照專利文獻1)。The conventional power supply voltage reduction detecting circuit includes: a reference voltage circuit 72 for outputting a reference voltage; a voltage dividing circuit 73 for dividing a power supply voltage of the power source 71 by a resistor 75 and a resistor 76 to output a divided voltage; A differential amplifier circuit 74 that detects a decrease in the power supply voltage by comparing the reference voltage with the divided voltage, and a pull-up resistor 77 that pulls up the output terminal of the differential amplifier circuit 74 (see, for example, Patent Document 1) .
(專利文獻1)日本特開2005-278056號公報(第4圖)(Patent Document 1) Japanese Laid-Open Patent Publication No. 2005-278056 (Fig. 4)
但是，在藉由專利文獻1所揭示的電路中，係必須設置基準電壓電路、分壓電路及差動放大電路，而使電路規模變大。因而，由此使消耗電流變多。However, in the circuit disclosed in Patent Document 1, it is necessary to provide a reference voltage circuit, a voltage dividing circuit, and a differential amplifying circuit to increase the circuit scale. Thus, the current consumption is thereby increased.
本發明係鑑於上述課題而研創者，提供一種電路規模較小的電源電壓降低檢測電路。The present invention has been made in view of the above problems, and provides a power supply voltage drop detecting circuit having a small circuit scale.
本發明為了解決上述課題，提供一種電源電壓降低檢測電路，係用以檢測電源電壓之降低的電源電壓降低檢測電路，其特徵為具備有：第一電晶體，為第一導電型，根據前述電源電壓，輸出根據由前述電源電壓減算臨限值電壓的絕對值及過驅動電壓而得之電壓的源極電壓；第二電晶體，為前述第一導電型，根據前述第一電晶體的源極電壓進行導通/關斷；第三電晶體，為第二導電型，根據接地電壓，輸出根據在前述接地電壓加算臨限值電壓的絕對值及過驅動電壓而得之電壓的源極電壓；第四電晶體，為前述第二導電型，根據前述第三電晶體的源極電壓進行導通/關斷；第一定電流電路，對前述第一電晶體供給電流；第二定電流電路，對前述第二電晶體及前述第三電晶體供給電流；以及第三定電流電路，對前述第四電晶體供給電流。In order to solve the above problems, the present invention provides a power supply voltage reduction detecting circuit for detecting a power supply voltage drop detecting circuit, which is characterized in that: a first transistor is provided, and is a first conductive type, according to the power supply. a voltage outputting a source voltage of a voltage obtained by subtracting an absolute value of the threshold voltage and an overdrive voltage from the power supply voltage; the second transistor being the first conductivity type, according to the source of the first transistor The voltage is turned on/off; the third transistor is a second conductivity type, and according to the ground voltage, the source voltage of the voltage obtained by adding the absolute value of the threshold voltage and the overdrive voltage to the ground voltage is output; a fourth transistor, which is in the second conductivity type, is turned on/off according to a source voltage of the third transistor; a first constant current circuit supplies current to the first transistor; and a second constant current circuit The second transistor and the third transistor supply current; and a third constant current circuit that supplies current to the fourth transistor.
本發明之電源電壓降低檢測電路係不需要設置基準電壓電路、分壓電路及差動放大電路，電路規模變得較小。因而，由此使消耗電流變少。The power supply voltage reduction detecting circuit of the present invention does not require a reference voltage circuit, a voltage dividing circuit, and a differential amplifying circuit, and the circuit scale becomes small. Thus, the current consumption is thereby reduced.
以下參照圖示，說明本發明之電源電壓降低檢測電路之實施形態。Hereinafter, an embodiment of the power supply voltage drop detecting circuit of the present invention will be described with reference to the drawings.
第1圖係顯示本發明之電源電壓降低檢測電路的電路圖。Fig. 1 is a circuit diagram showing a power supply voltage drop detecting circuit of the present invention.
本發明之電源電壓降低檢測電路係具備有：電源端子1、接地端子2及輸出端子3。此外，電源電壓降低檢測電路係具備有定電流電路4至6。此外，電源電壓降低檢測電路係具備有：NMOS電晶體12、NMOS電晶體17、PMOS電晶體15及PMOS電晶體19。The power supply voltage drop detecting circuit of the present invention includes a power supply terminal 1, a ground terminal 2, and an output terminal 3. Further, the power supply voltage drop detecting circuit is provided with constant current circuits 4 to 6. Further, the power supply voltage drop detecting circuit includes an NMOS transistor 12, an NMOS transistor 17, a PMOS transistor 15, and a PMOS transistor 19.
定電流電路4被設在NMOS電晶體12的源極與接地端子2之間。定電流電路5被設在電源端子1與PMOS電晶體15的源極之間。定電流電路6被設在輸出端子3與接地端子2之間。NMOS電晶體12的閘極及汲極係連接於電源端子1，背閘極(back-gate)係連接於接地端子2。NMOS電晶體17的閘極係連接於NMOS電晶體12的源極，源極及背閘極係連接於接地端子2，汲極係連接於PMOS電晶體15的汲極。PMOS電晶體15的閘極係連接於接地端子2，背閘極係連接於電源端子1。PMOS電晶體19的閘極係連接於PMOS電晶體15的源極，源極及背閘極係連接於電源端子1，汲極係連接於輸出端子3。The constant current circuit 4 is provided between the source of the NMOS transistor 12 and the ground terminal 2. The constant current circuit 5 is provided between the power supply terminal 1 and the source of the PMOS transistor 15. The constant current circuit 6 is provided between the output terminal 3 and the ground terminal 2. The gate and the drain of the NMOS transistor 12 are connected to the power supply terminal 1, and the back-gate is connected to the ground terminal 2. The gate of the NMOS transistor 17 is connected to the source of the NMOS transistor 12, the source and the back gate are connected to the ground terminal 2, and the drain is connected to the drain of the PMOS transistor 15. The gate of the PMOS transistor 15 is connected to the ground terminal 2, and the back gate is connected to the power supply terminal 1. The gate of the PMOS transistor 19 is connected to the source of the PMOS transistor 15, the source and the back gate are connected to the power supply terminal 1, and the drain is connected to the output terminal 3.
關於NMOS電晶體12及NMOS電晶體17，NMOS電晶體12之臨限值電壓的絕對值及過驅動電壓的合計、與NMOS電晶體17之臨限值電壓的絕對值及過驅動電壓的合計的和電壓係高於半導體裝置內之預定2個NMOS電晶體中之一個NMOS電晶體之臨限值電壓的絕對值及過驅動電壓的合計與另一NMOS電晶體之臨限值電壓的絕對值及過驅動電壓的合計的和電壓。關於PMOS電晶體15及PMOS電晶體19亦為相同。Regarding the NMOS transistor 12 and the NMOS transistor 17, the sum of the absolute value of the threshold voltage and the overdrive voltage of the NMOS transistor 12, and the sum of the absolute value of the threshold voltage of the NMOS transistor 17 and the overdrive voltage. And the voltage system is higher than the absolute value of the threshold voltage and the overdrive voltage of one of the predetermined two NMOS transistors in the semiconductor device and the absolute value of the threshold voltage of the other NMOS transistor and The sum and voltage of the overdrive voltage. The PMOS transistor 15 and the PMOS transistor 19 are also the same.
此外，定電流電路4係對NMOS電晶體12供給電流。定電流電路5係對NMOS電晶體17及PMOS電晶體15供給電流。定電流電路6係對PMOS電晶體19供給電流。NMOS電晶體12係根據電源電壓，輸出根據由電源電壓減算臨限值電壓的絕對值及過驅動電壓而得之電壓的源極電壓。根據該源極電壓，NMOS電晶體17進行導通(ON)/關斷(OFF)。PMOS電晶體15係根據接地電壓，輸出根據在接地電壓加算臨限值電壓的絕對值及過驅動電壓而得之電壓的源極電壓。根據該源極電壓，PMOS電晶體19進行導通/關斷。Further, the constant current circuit 4 supplies a current to the NMOS transistor 12. The constant current circuit 5 supplies current to the NMOS transistor 17 and the PMOS transistor 15. The constant current circuit 6 supplies a current to the PMOS transistor 19. The NMOS transistor 12 outputs a source voltage of a voltage obtained by subtracting the absolute value of the threshold voltage and the overdrive voltage from the power supply voltage in accordance with the power supply voltage. The NMOS transistor 17 is turned ON/OFF according to the source voltage. The PMOS transistor 15 outputs a source voltage of a voltage obtained by adding an absolute value of the threshold voltage and an overdrive voltage to the ground voltage in accordance with the ground voltage. The PMOS transistor 19 is turned on/off according to the source voltage.
接著說明本發明之電源電壓降低檢測電路的動作。Next, the operation of the power supply voltage decrease detecting circuit of the present invention will be described.
在此，將NMOS電晶體之臨限值電壓的絕對值設為Vtn，將PMOS電晶體之臨限值電壓的絕對值設為Vtp。Here, the absolute value of the threshold voltage of the NMOS transistor is Vtn, and the absolute value of the threshold voltage of the PMOS transistor is Vtp.
若電源電壓變低，NMOS電晶體12的閘極電壓即變低，NMOS電晶體12呈關斷，NMOS電晶體17的閘極電壓亦變低，NMOS電晶體17亦呈關斷。因此，PMOS電晶體19的閘極電壓變高，PMOS電晶體19係呈關斷。若電源電壓未達2Vtp，NMOS電晶體12及NMOS電晶體17尚呈導通，但是藉由PMOS電晶體15，PMOS電晶體19的閘極電壓未完全成為低位準，PMOS電晶體19係呈關斷。因此，若電源電壓未達2Vtp，亦即，若電源電壓成為未達半導體裝置之最低動作電壓，電源電壓降低檢測電路係將低位準訊號作為檢測訊號而由輸出端子3輸出至外部。If the power supply voltage becomes lower, the gate voltage of the NMOS transistor 12 becomes lower, the NMOS transistor 12 is turned off, the gate voltage of the NMOS transistor 17 is also lowered, and the NMOS transistor 17 is also turned off. Therefore, the gate voltage of the PMOS transistor 19 becomes high, and the PMOS transistor 19 is turned off. If the power supply voltage is less than 2Vtp, the NMOS transistor 12 and the NMOS transistor 17 are still turned on, but with the PMOS transistor 15, the gate voltage of the PMOS transistor 19 is not completely low, and the PMOS transistor 19 is turned off. . Therefore, if the power supply voltage is less than 2Vtp, that is, if the power supply voltage becomes the lowest operating voltage of the semiconductor device, the power supply voltage drop detecting circuit outputs the low level signal as the detection signal to the outside through the output terminal 3.
當電源電壓變低，電源電壓未達2Vtn時，NMOS電晶體12尚呈導通，但是藉由定電流電路4，NMOS電晶體17的閘極電壓未完全成為高位準，NMOS電晶體17係呈關斷，PMOS電晶體19的閘極電壓成為高位準，PMOS電晶體19亦呈關斷。因此，若電源電壓未達2Vtn，亦即，電源電壓未達半導體裝置的最低動作電壓，電源電壓降低檢測電路係將低位準訊號作為檢測訊號而由輸出端子3輸出至外部。When the power supply voltage becomes low and the power supply voltage is less than 2Vtn, the NMOS transistor 12 is still turned on, but by the constant current circuit 4, the gate voltage of the NMOS transistor 17 is not completely high, and the NMOS transistor 17 is turned off. Broken, the gate voltage of the PMOS transistor 19 becomes a high level, and the PMOS transistor 19 is also turned off. Therefore, if the power supply voltage is less than 2Vtn, that is, the power supply voltage does not reach the minimum operating voltage of the semiconductor device, the power supply voltage reduction detecting circuit outputs the low level signal as the detection signal to the outside through the output terminal 3.
電源電壓比2Vtp及2Vtn之雙方更低，之後，若電源電壓變高，NMOS電晶體12的閘極電壓會變高，NMOS電晶體12進行導通，NMOS電晶體17的閘極電壓亦變高，NMOS電晶體17亦呈導通。因此，PMOS電晶體19的閘極電壓變低，PMOS電晶體19亦呈導通。當電源電壓為2Vtn以上時，NMOS電晶體12及NMOS電晶體17係呈導通，但是藉由PMOS電晶體15，PMOS電晶體19的閘極電壓未完全成為低位準，PMOS電晶體19尚呈關斷。當電源電壓為2Vtp以上時，NMOS電晶體12及NMOS電晶體17係已呈導通，PMOS電晶體19的閘極電壓成為低位準，PMOS電晶體19亦呈導通。因此，當電源電壓為2Vtp以上時，亦即，電源電壓為半導體裝置之最低動作電壓以上時，電源電壓降低檢測電路係將高位準訊號作為檢測訊號而由輸出端子3輸出至外部。The power supply voltage is lower than both of 2Vtp and 2Vtn. Thereafter, if the power supply voltage becomes high, the gate voltage of the NMOS transistor 12 becomes high, the NMOS transistor 12 is turned on, and the gate voltage of the NMOS transistor 17 also becomes high. The NMOS transistor 17 is also turned on. Therefore, the gate voltage of the PMOS transistor 19 becomes low, and the PMOS transistor 19 is also turned on. When the power supply voltage is 2Vtn or more, the NMOS transistor 12 and the NMOS transistor 17 are turned on, but by the PMOS transistor 15, the gate voltage of the PMOS transistor 19 is not completely low, and the PMOS transistor 19 is still off. Broken. When the power supply voltage is 2 Vtp or more, the NMOS transistor 12 and the NMOS transistor 17 are turned on, the gate voltage of the PMOS transistor 19 is at a low level, and the PMOS transistor 19 is also turned on. Therefore, when the power supply voltage is 2 Vtp or more, that is, when the power supply voltage is equal to or higher than the lowest operating voltage of the semiconductor device, the power supply voltage drop detecting circuit outputs the high level signal as the detection signal to the outside through the output terminal 3.
電源電壓比2Vtp及2Vtn之雙方更低，之後，電源電壓變高，當電源電壓為2Vtn以上時，NMOS電晶體12及NMOS電晶體17係導通，PMOS電晶體19的閘極電壓成為低位準，PMOS電晶體19亦導通。因此，當電源電壓為2Vtn以上時，亦即，電源電壓為半導體裝置之最低動作電壓以上時，電源電壓降低檢測電路係將高位準訊號作為檢測訊號而由輸出端子3輸出至外部。The power supply voltage is lower than both of 2Vtp and 2Vtn. Thereafter, the power supply voltage becomes high. When the power supply voltage is 2Vtn or more, the NMOS transistor 12 and the NMOS transistor 17 are turned on, and the gate voltage of the PMOS transistor 19 becomes a low level. The PMOS transistor 19 is also turned on. Therefore, when the power supply voltage is 2 Vtn or more, that is, when the power supply voltage is equal to or higher than the lowest operating voltage of the semiconductor device, the power supply voltage drop detecting circuit outputs the high level signal as the detection signal to the outside through the output terminal 3.
接著說明本發明之電源電壓降低檢測電路的定電流電路。第2圖係顯示本發明之電源電壓降低檢測電路之定電流電路之一具體例的電路圖。Next, a constant current circuit of the power supply voltage drop detecting circuit of the present invention will be described. Fig. 2 is a circuit diagram showing a specific example of a constant current circuit of the power supply voltage decrease detecting circuit of the present invention.
定電流電路4係藉由例如空乏型(depletion type)NMOS電晶體11予以實現。空乏型NMOS電晶體11的閘極、源極及背閘極係連接於接地端子2，汲極係連接於NMOS電晶體11的源極。空乏型NMOS電晶體11的汲極係由NMOS電晶體12的源極抽出電流。The constant current circuit 4 is realized by, for example, a depletion type NMOS transistor 11. The gate, the source, and the back gate of the depletion NMOS transistor 11 are connected to the ground terminal 2, and the drain is connected to the source of the NMOS transistor 11. The drain of the depletion NMOS transistor 11 draws current from the source of the NMOS transistor 12.
定電流電路5係藉由例如空乏型NMOS電晶體11及PMOS電晶體13至14予以實現。PMOS電晶體13的閘極及汲極係連接於NMOS電晶體12的汲極，源極及背閘極係連接於電源端子1。PMOS電晶體14的閘極係連接於PMOS電晶體13的閘極，源極及背閘極係連接於電源端子1，汲極係連接於PMOS電晶體15的源極。PMOS電晶體14的汲極係將根據定電流電路4之電流的電流流至PMOS電晶體15的源極。The constant current circuit 5 is realized by, for example, a depletion type NMOS transistor 11 and PMOS transistors 13 to 14. The gate and the drain of the PMOS transistor 13 are connected to the drain of the NMOS transistor 12, and the source and the back gate are connected to the power supply terminal 1. The gate of the PMOS transistor 14 is connected to the gate of the PMOS transistor 13, the source and the back gate are connected to the power supply terminal 1, and the drain is connected to the source of the PMOS transistor 15. The drain of the PMOS transistor 14 flows a current according to the current of the constant current circuit 4 to the source of the PMOS transistor 15.
定電流電路6係藉由例如空乏型NMOS電晶體11、PMOS電晶體13至14、NMOS電晶體16及NMOS電晶體18予以實現。NMOS電晶體16的閘極及汲極係連接於PMOS電晶體15的汲極，源極係連接於NMOS電晶體17的汲極，背閘極係連接於接地端子2。NMOS電晶體18的閘極係連接於NMOS電晶體16的閘極，源極及背閘極係連接於接地端子2，汲極係連接於PMOS電晶體19的汲極。NMOS電晶體18的汲極係由PMOS電晶體19的汲極抽出根據定電流電路4之電流的電流。The constant current circuit 6 is realized by, for example, a depletion type NMOS transistor 11, PMOS transistors 13 to 14, an NMOS transistor 16, and an NMOS transistor 18. The gate and the drain of the NMOS transistor 16 are connected to the drain of the PMOS transistor 15, the source is connected to the drain of the NMOS transistor 17, and the back gate is connected to the ground terminal 2. The gate of the NMOS transistor 18 is connected to the gate of the NMOS transistor 16, the source and the back gate are connected to the ground terminal 2, and the drain is connected to the drain of the PMOS transistor 19. The drain of the NMOS transistor 18 extracts the current of the current according to the constant current circuit 4 from the drain of the PMOS transistor 19.
如以上說明所示，本發明之電源電壓降低檢測電路並不需要設置基準電壓電路、分壓電路及差動放大電路，電路規模變得較小。因此，消耗電流亦變得較少。As described above, the power supply voltage drop detecting circuit of the present invention does not need to provide a reference voltage circuit, a voltage dividing circuit, and a differential amplifying circuit, and the circuit scale becomes small. Therefore, the current consumption also becomes less.
此外，為了補償基準電壓的偏差，必須進行分壓電路的電阻調製(trimming)，但是調製變得不需要。因此，由於減少製造步驟，因此製造成本變低。Further, in order to compensate for variations in the reference voltage, it is necessary to perform resistance trimming of the voltage dividing circuit, but modulation becomes unnecessary. Therefore, since the manufacturing steps are reduced, the manufacturing cost becomes low.
此外，即使PMOS電晶體與NMOS電晶體的動作關係為任一者，當電源電壓成為未達半導體裝置的最低動作電壓時，電源電壓降低檢測電路係將低位準訊號作為檢測訊號而由輸出端子3輸出至外部，因此半導體裝置並不會進行錯誤動作。In addition, even if the operational relationship between the PMOS transistor and the NMOS transistor is any, when the power supply voltage becomes the lowest operating voltage of the semiconductor device, the power supply voltage reduction detecting circuit uses the low level signal as the detection signal and is output terminal 3 The output is external, so the semiconductor device does not perform an erroneous operation.
其中，亦可將第1圖及第2圖中的NMOS電晶體變更為PMOS電晶體，將PMOS電晶體變更為NMOS電晶體。However, the NMOS transistor in FIGS. 1 and 2 may be changed to a PMOS transistor, and the PMOS transistor may be changed to an NMOS transistor.
接著參照圖示，說明本發明之其他實施例之電源電壓降低檢測電路。Next, a power supply voltage drop detecting circuit according to another embodiment of the present invention will be described with reference to the drawings.
第3圖係顯示本發明之其他實施例之電源電壓降低檢測電路的電路圖。在與第1圖的電源電壓降低檢測電路的差異中，定電流電路4係被變更為定電流電路7，定電流電路5係被變更為定電流電路8，定電流電路6係被變更為定電流電路9。Fig. 3 is a circuit diagram showing a power supply voltage drop detecting circuit of another embodiment of the present invention. In the difference from the power supply voltage decrease detecting circuit of Fig. 1, the constant current circuit 4 is changed to the constant current circuit 7, the constant current circuit 5 is changed to the constant current circuit 8, and the constant current circuit 6 is changed to Current circuit 9.
第4圖係顯示本發明之其他實施例之電源電壓降低檢測電路之定電流電路之一具體例的電路圖。在與第2圖之電源電壓降低檢測電路的差異中，NMOS電晶體12係被變更為PMOS電晶體22，NMOS電晶體17係被變更為PMOS電晶體27，PMOS電晶體15係被變更為NMOS電晶體25，PMOS電晶體19係被變更為NMOS電晶體29。在此，空乏型NMOS電晶體11係被變更為空乏型NMOS電晶體21，PMOS電晶體13係被變更為NMOS電晶體23，PMOS電晶體14係被變更為NMOS電晶體24，NMOS電晶體16係被變更為PMOS電晶體26，NMOS電晶體18係被變更為PMOS電晶體28。Fig. 4 is a circuit diagram showing a specific example of a constant current circuit of a power supply voltage drop detecting circuit of another embodiment of the present invention. In the difference from the power supply voltage drop detecting circuit of Fig. 2, the NMOS transistor 12 is changed to the PMOS transistor 22, the NMOS transistor 17 is changed to the PMOS transistor 27, and the PMOS transistor 15 is changed to the NMOS. The transistor 25 and the PMOS transistor 19 are changed to the NMOS transistor 29. Here, the depletion NMOS transistor 11 is changed to the depletion NMOS transistor 21, the PMOS transistor 13 is changed to the NMOS transistor 23, and the PMOS transistor 14 is changed to the NMOS transistor 24, and the NMOS transistor 16 The PMOS transistor 26 is changed to the PMOS transistor 28. The NMOS transistor 18 is changed to the PMOS transistor 28.
可知即使如第3圖及第4圖所示構成電源電壓降低檢測電路，亦可獲得與第1圖及第2圖所示之電源電壓降低檢測電路相同的效果。It is understood that even if the power supply voltage decrease detecting circuit is configured as shown in FIGS. 3 and 4, the same effects as those of the power supply voltage lowering detecting circuit shown in FIGS. 1 and 2 can be obtained.
1．．．電源端子1. . . Power terminal
2．．．接地端子2. . . Ground terminal
3．．．輸出端子3. . . Output terminal
4至6．．．定電流電路4 to 6. . . Constant current circuit
12、16至18、23至25、29、31至34、52、54．．．NMOS電晶體12, 16 to 18, 23 to 25, 29, 31 to 34, 52, 54. . . NMOS transistor
11、21．．．空乏型NMOS電晶體11, 21. . . Depleted NMOS transistor
13至15、19、22、26至28、41至44、51、55至56．．．PMOS電晶體13 to 15, 19, 22, 26 to 28, 41 to 44, 51, 55 to 56. . . PMOS transistor
53、75、76．．．電阻53, 75, 76. . . resistance
71．．．電源71. . . power supply
72．．．基準電壓電路72. . . Reference voltage circuit
73．．．分壓電路73. . . Voltage dividing circuit
74．．．差動放大電路74. . . Differential amplifier circuit
77．．．上拉電阻77. . . Pull-up resistor
第1圖係顯示本發明之電源電壓降低檢測電路的電路圖。Fig. 1 is a circuit diagram showing a power supply voltage drop detecting circuit of the present invention.
第2圖係顯示本發明之電源電壓降低檢測電路之定電流電路之一具體例的電路圖。Fig. 2 is a circuit diagram showing a specific example of a constant current circuit of the power supply voltage decrease detecting circuit of the present invention.
第3圖係顯示本發明之其他實施例之電源電壓降低檢測電路的電路圖。Fig. 3 is a circuit diagram showing a power supply voltage drop detecting circuit of another embodiment of the present invention.
第4圖係顯示本發明之其他實施例之電源電壓降低檢測電路之定電流電路之一具體例的電路圖。Fig. 4 is a circuit diagram showing a specific example of a constant current circuit of a power supply voltage drop detecting circuit of another embodiment of the present invention.
第5圖係顯示半導體裝置之要素電路之例的電路圖。Fig. 5 is a circuit diagram showing an example of an element circuit of a semiconductor device.
第6圖係顯示半導體裝置之要素電路之其他例的電路圖。Fig. 6 is a circuit diagram showing another example of the element circuit of the semiconductor device.
第7圖係顯示半導體裝置之要素電路之其他例的電路圖。Fig. 7 is a circuit diagram showing another example of the element circuit of the semiconductor device.
第8圖係顯示習知之電源電壓降低檢測電路的電路圖。Fig. 8 is a circuit diagram showing a conventional power supply voltage drop detecting circuit.
1．．．電源端子1. . . Power terminal
2．．．接地端子2. . . Ground terminal
3．．．輸出端子3. . . Output terminal
4至6．．．定電流電路4 to 6. . . Constant current circuit
12、17．．．NMOS電晶體12, 17. . . NMOS transistor
15、19．．．PMOS電晶體15, 19. . . PMOS transistor
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| JP2008201662A JP5203086B2 (en) | 2007-08-10 | 2008-08-05 | Power supply voltage drop detection circuit |
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| CN106249034B (en) * | 2016-08-15 | 2018-10-02 | 北京航空航天大学 | A kind of on piece voltage drop alarm for cooperateing with dynamic voltage frequency adjustment system |
| JP7325352B2 (en) * | 2020-02-07 | 2023-08-14 | エイブリック株式会社 | Reference voltage circuit |
| CN113406509B (en) * | 2021-06-11 | 2022-05-10 | 浙江今日阳光新能源车业有限公司 | Electric vehicle electric quantity display method, electric vehicle instrument and computer storage medium |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW591800B (en) * | 2001-09-13 | 2004-06-11 | Toshiba Corp | Constant voltage generation circuit and semiconductor memory device |
| JP2005278056A (en) * | 2004-03-26 | 2005-10-06 | Matsushita Electric Ind Co Ltd | Circuit for detecting power supply voltage drop |
| TW200615732A (en) * | 2004-07-05 | 2006-05-16 | Seiko Instr Inc | Voltage regulator |
| US20060261860A1 (en) * | 2005-05-17 | 2006-11-23 | Fuji Electric Device Technology Co., Ltd. | DC to DC converter and voltage detecting circuit and current detecting circuit thereof |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5888450U (en) * | 1981-12-10 | 1983-06-15 | リコーエレメックス株式会社 | Initial reset circuit |
| JPH0619686B2 (en) * | 1983-08-29 | 1994-03-16 | 日本電信電話株式会社 | Power supply circuit |
| JPS6111839A (en) * | 1984-06-26 | 1986-01-20 | Ricoh Co Ltd | Power-on initializing circuit |
| JP2972245B2 (en) * | 1989-11-29 | 1999-11-08 | 株式会社日立製作所 | Reference voltage output circuit with voltage detection function |
| JPH03218064A (en) * | 1990-01-23 | 1991-09-25 | Sharp Corp | Semiconductor integrated circuit device |
| JP3077072B2 (en) * | 1992-07-14 | 2000-08-14 | 三機工業株式会社 | Pipeline transportation method for waste |
| KR970075931A (en) * | 1996-05-16 | 1997-12-10 | 김광호 | Programmable low voltage detection circuit |
| US5838191A (en) * | 1997-02-21 | 1998-11-17 | National Semiconductor Corporation | Bias circuit for switched capacitor applications |
| JP3806011B2 (en) * | 2001-10-05 | 2006-08-09 | セイコーインスツル株式会社 | Voltage detection circuit |
| JP2005191821A (en) * | 2003-12-25 | 2005-07-14 | Seiko Epson Corp | Comparator circuit and power supply circuit |
| JP2006112906A (en) * | 2004-10-14 | 2006-04-27 | Sanyo Electric Co Ltd | Voltage detection circuit |
| US7161861B2 (en) * | 2004-11-15 | 2007-01-09 | Infineon Technologies Ag | Sense amplifier bitline boost circuit |
| JP4562638B2 (en) * | 2005-10-27 | 2010-10-13 | 三洋電機株式会社 | Low voltage detection circuit |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW591800B (en) * | 2001-09-13 | 2004-06-11 | Toshiba Corp | Constant voltage generation circuit and semiconductor memory device |
| JP2005278056A (en) * | 2004-03-26 | 2005-10-06 | Matsushita Electric Ind Co Ltd | Circuit for detecting power supply voltage drop |
| TW200615732A (en) * | 2004-07-05 | 2006-05-16 | Seiko Instr Inc | Voltage regulator |
| US20060261860A1 (en) * | 2005-05-17 | 2006-11-23 | Fuji Electric Device Technology Co., Ltd. | DC to DC converter and voltage detecting circuit and current detecting circuit thereof |
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| KR101444465B1 (en) | 2014-09-24 |
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