TWI419636B - Multiple circuit board and semiconductor device - Google Patents
Multiple circuit board and semiconductor device Download PDFInfo
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- TWI419636B TWI419636B TW97101866A TW97101866A TWI419636B TW I419636 B TWI419636 B TW I419636B TW 97101866 A TW97101866 A TW 97101866A TW 97101866 A TW97101866 A TW 97101866A TW I419636 B TWI419636 B TW I419636B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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Description
本發明是有關不包含具有藉由引洞(via)連接而導通連接之穿孔(through hole)的核(core)基板之半導體用多層電路基板，且有關藉由將導體電路層與絕緣層交互地單面積層之增建(build up)方法所製作的多層電路基板及半導體裝置。The present invention relates to a multilayer circuit substrate for a semiconductor which does not include a core substrate having a through hole through which a via connection is connected, and by interchanging the conductor circuit layer and the insulating layer A multilayer circuit substrate and a semiconductor device fabricated by a build-up method of a single-area layer.
近年在半導體領域，自高密度安裝技術之進步以來就有由以往之面安裝邁向區域性安裝之傾向，而持續開發並增加BGA(Ball Grid Array；球閘陣列封裝)或CSP(Chip Scale Package；晶片尺寸封裝)等新的封裝。又資訊傳達之高速化也正進行中。因此，中介層(interposer)用硬質(Rigid)基板係變得比以前更受到注目，而對高耐熱、低熱膨脹、低誘電基板(low dielectric substrate)之要求也變高。In recent years, in the field of semiconductors, since the advancement of high-density mounting technology, there has been a tendency to move from the past installation to the regional installation, and continue to develop and increase BGA (Ball Grid Array; ball gate array package) or CSP (Chip Scale Package) ; new package such as wafer size package). The speed of information transmission is also in progress. Therefore, the interposer has been attracting more attention than the conventional Rigid substrate system, and the demand for high heat resistance, low thermal expansion, and low dielectric substrate has also become high.
再者，隨著電子機器的高機能化等之要求，而邁向電子零件的高密度聚集化，更邁向高密度安裝化等，在此所使用之對應高密度安裝的半導體用多層電路基板等係比以前更邁向小型化及高密度化。此半導體用多層電路基板等之對應高密度化手段係多採用增建多層電路基板。In addition, with the demand for higher performance of electronic devices, the high-density aggregation of electronic components is progressing toward higher-density mounting, and the multilayer circuit substrate for semiconductors used for high-density mounting is used here. The system is becoming more compact and denser than before. In the corresponding high-density means such as a multilayer circuit board for a semiconductor, a multilayer circuit board is often used.
又，取代以往一直使用之增建多層電路基板(第1圖)而邁向半導體用多層電路基板之更薄型化、高速信號化，提議有不包含具有藉由引洞接連而導通接連之穿孔的核基板之由在單面上將導體電路層與絕緣層交互地增建而成之 多層電路基板(第2圖)，其中，在多層電路基板之一邊的面上形成內墊(inner pad)，在另一邊之面上形成外墊(out pad)(例如，參照專利文獻1：日本特開2000-323613號公報)。In addition, it is proposed to reduce the thickness and high-speed signalization of the multilayer circuit board for semiconductors in addition to the conventional multilayer circuit board (Fig. 1) which has been used in the past, and it is proposed that the perforation having the continuity of the via holes is not included. The core substrate is formed by interactively adding a conductor circuit layer and an insulating layer on one side. In the multilayer circuit board (Fig. 2), an inner pad is formed on one side of the multilayer circuit board, and an outer pad is formed on the other side (for example, refer to Patent Document 1: Japan) JP-A-2000-323613).
然而，由於是在單面上積層，故在以往使用之絕緣層是會隨著絕緣層之薄型化而降低彈性模數，又由於絕緣層之線膨脹係數為與導體電路之線膨脹係數不同，所以在多層電路基板之製造步驟中，多層電路基板有大幅反翹之問題。However, since the layer is laminated on one side, the insulating layer used in the past has a lower modulus of elasticity as the insulating layer is thinned, and since the coefficient of linear expansion of the insulating layer is different from the coefficient of linear expansion of the conductor circuit. Therefore, in the manufacturing steps of the multilayer circuit substrate, the multilayer circuit substrate has a problem of a large anti-warpage.
為了抑制多層電路基板之反翹，而檢討將2片金屬板相對向組合製成一體化的複合金屬板，在此複合金屬板之兩面上交互地積層導體電路層與絕緣層，最後剝開黏在一起的金屬板，藉由蝕刻金屬板而可得到多層電路基板(例如，參照專利文獻2:WO2003-039219號公報)。然而，若僅如此則仍不能達到充分的改善。In order to suppress the anti-warping of the multi-layer circuit substrate, it is reviewed that the two metal plates are combined to form an integrated composite metal plate, and the conductor circuit layer and the insulating layer are alternately laminated on both sides of the composite metal plate, and finally the adhesive layer is peeled off. A multilayer circuit board can be obtained by etching a metal plate together with a metal plate (see, for example, Patent Document 2: WO2003-039219). However, if this is the case, sufficient improvement cannot be achieved.
本發明是在由單面積層而成之多層電路基板中，製造反翹少之多層電路基板，且在進行安裝半導體元件之步驟中、在進行安裝半導體元件後的信賴性試驗步驟中，提供反翹少之多層電路基板及半導體裝置。In the multilayer circuit board formed of a single-area layer, the present invention is to manufacture a multilayer circuit substrate having a small amount of anti-warpage, and in the step of mounting the semiconductor element, in the reliability test step after mounting the semiconductor element, providing a reverse A multilayer circuit board and a semiconductor device that are less curved.
為了達成上述目的，記載於下述[1]至[8]的本發明係：[1]一種多層電路基板，其係由複數組之導體電路層與絕緣層所形成，為不包含具有藉由引洞連接而導通連接之穿孔的核基板之單面積層之多層電路基板，其特徵為： 前述絕緣層的玻璃移轉溫度為170℃以上，在玻璃移轉溫度以下之線膨脹係數為35ppm以下，彈性模數為5GPa以上。In order to achieve the above object, the invention is described in the following [1] to [8]: [1] A multilayer circuit substrate formed by a plurality of conductor circuit layers and an insulating layer, which are not included A multi-layer circuit substrate of a single-area layer of a core substrate in which a via hole is connected to be connected to a via, and is characterized by: The insulating layer has a glass transition temperature of 170 ° C or higher, a linear expansion coefficient of 35 ppm or less at a glass transition temperature or less, and an elastic modulus of 5 GPa or more.
[2]如[1]所述之多層電路基板，其中，前述絕緣層中至少有一層為含有纖維基材者。[2] The multilayer circuit substrate according to [1], wherein at least one of the insulating layers is a fiber-containing substrate.
[3]如[2]所述之多層電路基板，其中，前述含有纖維基材之絕緣層係至少具有第1樹脂層、第2樹脂層、及纖維基材，且在第1樹脂層與第2樹脂層之間介設有纖維基材。[3] The multilayer circuit board according to the above [2], wherein the insulating layer containing the fiber base material has at least a first resin layer, a second resin layer, and a fiber base material, and the first resin layer and the first resin layer 2 A fibrous substrate is interposed between the resin layers.
[4]如[3]所述之多層電路基板，其中，前述第1樹脂層之厚度B1與第2樹脂層之厚度B2之比值(B2/B1)為滿足0<B2/B1≦1者。[4] The multilayer circuit board according to the above [3], wherein a ratio (B2/B1) of the thickness B1 of the first resin layer to the thickness B2 of the second resin layer is 0<B2/B1≦1.
[5]如[2]所述之多層電路基板，其中，前述絕緣層之纖維基材厚度為10至35μm。[5] The multilayer circuit substrate according to [2], wherein the insulating layer has a fiber base material having a thickness of 10 to 35 μm.
[6]如[2]所述之多層電路基板，其中，前述纖維基材為玻璃纖維布(Glass Cloth)。[6] The multilayer circuit substrate according to [2], wherein the fiber base material is a glass cloth (Glass Cloth).
[7]如[1]所述之多層電路基板，其中，前述絕緣層為由含有氰酸酯樹脂之樹脂組成物所構成者。[7] The multilayer circuit substrate according to [1], wherein the insulating layer is composed of a resin composition containing a cyanate resin.
[8]一種半導體裝置，其特徵是使用上述[1]所述之多層電路基板。[8] A semiconductor device using the multilayer circuit substrate according to [1] above.
本發明係半導體用多層電路基板，多層電路基板係例如可用在如BGA之半導體元件搭載基板上。The present invention is a multilayer circuit substrate for a semiconductor, and the multilayer circuit substrate can be used, for example, on a semiconductor element mounting substrate such as a BGA.
第1圖係表示以往之代表性的增建多層電路基板的 圖。第2圖係表示在本發明相關的由複數組的導體電路層與絕緣層所形成，且不包含具有藉由引洞(via)連接而導通連接之穿孔的核基板之單面積層的多層電路基板的概略結構圖，其中，在多層電路基板之一邊的面上形成內墊，在另一邊之面上形成外墊。Fig. 1 is a view showing a conventional representative of a multilayer circuit board Figure. Figure 2 is a diagram showing a multilayer circuit of a single-layer layer of a core substrate formed of a complex array of conductor circuit layers and insulating layers and having no vias connected by vias for via connections. A schematic structural view of a substrate in which an inner pad is formed on one side of a multilayer circuit substrate, and an outer pad is formed on the other side.
在本發明之多層電路基板中所使用的絕緣層之玻璃移轉溫度是以170℃以上為宜。更佳為175℃以上。若小於上述範圍，在製造步驟加熱後回到室溫時之反翹會變大。控制多層電路基板之反翹的因素，可列舉玻璃移轉溫度以下的線膨脹係數。若線膨脹係數為35ppm以上，則與通常在電路中所使用的銅之線膨脹係數(17至18ppm/℃)相比係變大2倍以上，而為反翹變大之原因。又，本發明之多層電路基板之彈性模數是以在5GPa以上為佳。本發明之多層電路基板與以往之多層電路基板相比，由於沒有核層，故為了保持形狀而以彈性模數為5GPa以上者為宜。The glass transition temperature of the insulating layer used in the multilayer circuit substrate of the present invention is preferably 170 ° C or higher. More preferably, it is 175 ° C or more. If it is less than the above range, the anti-warpage becomes large when it is returned to room temperature after heating in the manufacturing step. The factor for controlling the backlash of the multilayer circuit substrate is a linear expansion coefficient below the glass transition temperature. When the linear expansion coefficient is 35 ppm or more, it is twice as large as the linear expansion coefficient (17 to 18 ppm/° C.) of copper used in the circuit, which is a cause of a large anti-warpage. Further, the multilayer circuit substrate of the present invention preferably has an elastic modulus of 5 GPa or more. Since the multilayer circuit board of the present invention has no core layer as compared with the conventional multilayer circuit board, it is preferable to have a modulus of elasticity of 5 GPa or more in order to maintain the shape.
本發明使用之絕緣層，以含有玻璃纖維基材或有機纖維基材作為纖維基材者為宜，例如，可列舉如作為玻璃纖維基材的玻璃織布、玻璃不織布等玻璃纖維布(Glass Cloth)或作為有機纖維基材的有機織布、有機不織布等。在多層電路基板中含有纖維基材的絕緣層係至少要有一層為宜。因此，使用如此纖維基材的絕緣層，因為構成纖維基材的纖維束不易發生彎曲，所以彈性模數等機械特性為優異。The insulating layer used in the present invention is preferably a glass fiber substrate or an organic fiber substrate as a fiber substrate. For example, glass cloth such as glass woven fabric or glass nonwoven fabric as a glass fiber substrate (Glass Cloth) Or an organic woven fabric, an organic nonwoven fabric, or the like as an organic fiber base material. At least one layer of the insulating layer containing the fibrous base material in the multilayer circuit substrate is preferred. Therefore, the use of the insulating layer of the fibrous base material is excellent in mechanical properties such as elastic modulus because the fiber bundle constituting the fibrous base material is less likely to be bent.
含有前述纖維基材的絕緣層，較佳為至少具有第1樹脂層、第2樹脂層、及纖維基材，且在第1樹脂層與第2 樹脂層之間介設有纖維基材者。The insulating layer containing the fiber base material preferably has at least a first resin layer, a second resin layer, and a fiber base material, and is in the first resin layer and the second resin layer. A fiber substrate is interposed between the resin layers.
又，若依本發明之較佳的態樣，可列舉如上述絕緣層的第1樹脂層厚度B1與第2樹脂層厚度B2之比值(B2/B1)滿足0<B2/B1≦1者。亦即，纖維基材係相對於絕緣層的厚度方向為不均勻分布。因內層的電路圖型而使需要之樹脂量有所不同時，樹脂可能有擠出之情形，或有掩埋電路之樹脂不足之情形。本發明之絕緣層即使是在此情形，藉由適度調整第1樹脂層與第2樹脂層之厚度，而變化纖維基材之厚度方向之位置，可充分掩埋電路，又可防止不必要之樹脂擠出。Further, according to a preferred aspect of the present invention, the ratio (B2/B1) of the thickness P1 of the first resin layer to the thickness B2 of the second resin layer of the insulating layer satisfies 0<B2/B1≦1. That is, the fibrous substrate is unevenly distributed with respect to the thickness direction of the insulating layer. When the amount of resin required differs depending on the circuit pattern of the inner layer, the resin may be extruded or the resin of the buried circuit may be insufficient. In this case, the insulating layer of the present invention can appropriately cover the thickness direction of the fiber base material by appropriately adjusting the thicknesses of the first resin layer and the second resin layer, thereby sufficiently burying the circuit and preventing unnecessary resin. Extrusion.
此比值(B2/B1)以在0.5以下為宜，尤其以在0.2至0.4更佳，此比值(B2/B1)在上述範圍內時，特別可降低纖維基材之起伏，依此而使絕緣層的平坦性可更加提升。The ratio (B2/B1) is preferably 0.5 or less, particularly preferably 0.2 to 0.4, and when the ratio (B2/B1) is within the above range, the undulation of the fibrous substrate is particularly lowered, thereby insulating The flatness of the layer can be further improved.
本發明使用之絕緣層，為了降低絕緣層之線膨脹係數，以使用氰酸酯樹脂為宜。氰酸酯樹脂可使用例如由鹵化氰化物與酚類反應而成者、或將此以加熱等方法而預聚合化者等。具體而言，可列舉如酚醛清漆型(novolac)氰酸酯樹脂、雙酚A型氰酸酯樹脂、雙酚E型氰酸酯樹脂、四甲基雙酚F型氰酸酯樹脂等雙酚型氰酸酯樹脂等。In order to reduce the linear expansion coefficient of the insulating layer, the insulating layer used in the present invention preferably uses a cyanate resin. As the cyanate resin, for example, a compound obtained by reacting a halogenated cyanide with a phenol or a method of prepolymerizing it by heating or the like can be used. Specific examples thereof include bisphenols such as novolac type cyanate resin, bisphenol A type cyanate resin, bisphenol E type cyanate resin, and tetramethyl bisphenol F type cyanate resin. Type cyanate resin or the like.
此等氰酸酯樹脂之中，若使用酚醛清漆型氰酸酯樹脂，則在藉由增加交聯密度而可更加提高耐熱性的同時，例如即使在使用薄型物作為乃附有銅箔之預浸體(prepreg)之骨架材的玻璃纖維布時，也可賦予附有銅箔之預浸體之硬化物優異之剛性(彈性模數)，尤其可提高在加熱時之剛 性(彈性模數)。Among these cyanate resins, when a novolak-type cyanate resin is used, heat resistance can be further improved by increasing the crosslinking density, and for example, even if a thin material is used as a pre-attached copper foil In the case of a glass fiber cloth of a prepreg skeleton, the rigidity (elastic modulus) of the cured product of the prepreg with the copper foil can be imparted, and in particular, the heating can be performed. Sex (elastic modulus).
因此，將此附有銅箔之預浸體應用在已安裝半導體零件之封裝基板上時，可提高其連接信賴性。Therefore, when the prepreg with the copper foil is applied to the package substrate on which the semiconductor component is mounted, the connection reliability can be improved.
又，藉由使用酚醛清漆型氰酸酯樹脂，可提高硬化物之難燃性。判定其原因是酚醛清漆型氰酸酯樹脂在結構上苯環所佔比率偏高，因而容易碳化之故。Further, by using a novolac type cyanate resin, the flame retardancy of the cured product can be improved. The reason for this was judged to be that the novolac type cyanate resin has a high ratio of the benzene ring in the structure, and thus it is easily carbonized.
上述酚醛清漆型氰酸酯樹脂，例如以使用下述一般式(1)所示者為宜。The novolac type cyanate resin is preferably used, for example, by using the following general formula (1).
上述一般式(1)所示之酚醛清漆型氰酸酯樹脂之重複單元n，例如可使用1至10者，而以2至7者為特別適宜使用。The repeating unit n of the novolac type cyanate resin represented by the above general formula (1) can be, for example, 1 to 10, and 2 to 7 is particularly preferably used.
藉此，使酚醛清漆型氰酸酯樹脂之處理性、或硬化物之交聯密度良好者，可作為此等特性的平衡優異者。Thereby, the resin of the novolac type cyanate resin or the crosslink density of the cured product can be excellent as a balance of these characteristics.
上述n數太小時，變得易結晶化，對於泛用溶劑之溶解性變小且處理性變差。另一方面，上述n數太大時，硬化物之交聯密度過剩而變高，產生耐水性下降或硬化物變脆等現象。When the number of n is too small, it becomes easy to crystallize, and the solubility in a general-purpose solvent is small and the handleability is deteriorated. On the other hand, when the number of n is too large, the crosslinking density of the cured product becomes excessive and becomes high, and the water resistance is lowered or the cured product becomes brittle.
就上述氰酸酯樹脂之分子量而言，例如重量平均分子量(Mw)可使用500至4,500者，特別可適用600至3,000者。With respect to the molecular weight of the above cyanate resin, for example, a weight average molecular weight (Mw) may be used in the range of 500 to 4,500, and particularly preferably in the range of 600 to 3,000.
藉此，使製作附有載體(carrier)之預浸體時的處理性、或製作多層電路基板時的成形性、層間剝離強度等良好者，可作為此等特性之平衡優異者。Thereby, the handleability at the time of producing a prepreg with a carrier, the moldability at the time of producing a multilayer circuit board, the interlayer peeling strength, and the like can be excellent as a balance of these characteristics.
上述Mw太小時，製作附有載體之預浸體時會產生黏著(tack)性，會使處理性降低。另一方面，上述Mw太大時，則反應變快，在製作多層電路基板時有成形不良或層間剝離強度下降之情形。When the above Mw is too small, when a prepreg with a carrier is produced, tackiness is generated, and handleability is lowered. On the other hand, when the Mw is too large, the reaction becomes fast, and when the multilayer circuit board is produced, there is a case where the molding failure or the interlayer peel strength is lowered.
上述氰酸酯樹脂較佳為可使用Mw在上述範圍內者之中的一種，亦可併用Mw為不同之2種以上者。The cyanate resin is preferably one of Mw in the above range, and two or more kinds of Mw may be used in combination.
又，上述氰酸酯樹脂之Mw係例如可用GPC(膠滲透層析法)來測定。Further, the Mw of the cyanate resin can be measured, for example, by GPC (gel permeation chromatography).
本發明所使用之絕緣層中，構成第1樹脂層之樹脂組成物與構成第2樹脂層之樹脂組成物可為同一者，亦可為相異者。使用不同樹脂組成物作為第1樹脂層與第2樹脂層時，例如，可變更使用之樹脂種類或使用量，亦可變更無機充填材等添加劑之種類或使用量。當可使用組成不同之樹脂組成物作為第1樹脂層與第2樹脂層時，變得可因應所要求之性能來設計樹脂層，有可使樹脂選擇之幅度變寬之優點。例如，面對內層電路之樹脂層可考慮到掩埋性而做成柔軟的組成，相反側之面可考慮到表面粗糙化而做成能均勻地粗糙化的組成等，在絕緣層的兩面可賦予不同之機能。In the insulating layer used in the present invention, the resin composition constituting the first resin layer and the resin composition constituting the second resin layer may be the same or different. When a different resin composition is used as the first resin layer and the second resin layer, for example, the type and amount of the resin to be used may be changed, and the type or amount of the additive such as the inorganic filler may be changed. When a resin composition having a different composition can be used as the first resin layer and the second resin layer, the resin layer can be designed in accordance with the required performance, and there is an advantage that the width of the resin can be widened. For example, the resin layer facing the inner layer circuit can be made into a soft composition in consideration of burying property, and the surface on the opposite side can be made to be uniformly roughened in consideration of surface roughening, and the like can be formed on both sides of the insulating layer. Give different functions.
在本發明所使用之絕緣層中，第1樹脂層之厚度雖說無特別限定者，但以比第2樹脂層之厚度厚者為宜，由第 1樹脂層所掩埋之電路層只要為可掩埋者即可。例如，當經掩埋之電路層之厚度為T，第1樹脂層之厚度為t時，(T/t)是以0.3≦(T/t)≦1.5為宜，更佳為0.5≦(T/t)≦1，一般而言，為了充分掩埋電路，以將面對內層電路之樹脂層的厚度變厚為宜。In the insulating layer used in the present invention, the thickness of the first resin layer is not particularly limited, but it is preferably thicker than the thickness of the second resin layer. The circuit layer to be buried by the resin layer may be any one that can be buried. For example, when the thickness of the buried circuit layer is T and the thickness of the first resin layer is t, (T/t) is preferably 0.3 ≦(T/t) ≦ 1.5, more preferably 0.5 ≦ (T/). t) ≦ 1, in general, in order to sufficiently bury the circuit, it is preferable to thicken the thickness of the resin layer facing the inner layer circuit.
本發明使用之纖維基材，在上述纖維基材之中，也以玻璃纖維布為宜，玻璃纖維布之厚度舉例如可使用10至180μm者。又，基重(每1m2 之玻璃纖維布重量)可使用例如12至209g/m2 者。尤其以使用玻璃纖維布之厚度為10至35μm，基重為12至25g/m2 之薄的玻璃纖維布為佳。The fibrous base material used in the present invention is preferably a glass fiber cloth among the above fibrous base materials, and the thickness of the glass fiber cloth can be, for example, 10 to 180 μm. Further, the basis weight (weight of the glass fiber cloth per 1 m 2 ) may be, for example, 12 to 209 g/m 2 . In particular, it is preferred to use a glass fiber cloth having a thickness of 10 to 35 μm and a basis weight of 12 to 25 g/m 2 .
在本發明中，尤其以線膨脹係數(CTE: Coefficient of Thermal Expansion)在6ppm以下之玻璃纖維布為更佳，又以3.5ppm以下之玻璃纖維布為特佳。藉由使用具有如上述之線膨脹係數的玻璃纖維布，則可有效地抑制由本發明使用之絕緣層所構成的多層電路基板以及使用該多層電路基板之半導體封裝的反翹。In the present invention, in particular, a glass fiber cloth having a coefficient of thermal expansion (CTE: Coefficient of Thermal Expansion) of 6 ppm or less is more preferable, and a glass fiber cloth of 3.5 ppm or less is particularly preferable. By using the glass fiber cloth having the linear expansion coefficient as described above, it is possible to effectively suppress the multilayer circuit substrate composed of the insulating layer used in the present invention and the reverse warpage of the semiconductor package using the multilayer circuit substrate.
再者，本發明使用之玻璃纖維布是以楊氐率在62至100GPa為宜，較佳為65至92GPa，更佳為89至92GPa。當玻璃纖維布之楊氐率在上述之範圍時，由於例如可有效地抑制半導體安裝時因回流(reflow)熱而造成之電路基板的變形，故可提高電子零件之連接信賴性。Further, the glass fiber cloth used in the present invention is preferably at a rate of 62 to 100 GPa, preferably 65 to 92 GPa, more preferably 89 to 92 GPa. When the rate of the glass fiber cloth is in the above range, for example, deformation of the circuit board due to reflow heat during semiconductor mounting can be effectively suppressed, so that the connection reliability of the electronic component can be improved.
又，本發明使用之玻璃纖維布，以在1MHz的介電常數為3.8至7.0為宜，較佳為4.7至7.0，更佳為5.4至6.8。玻璃纖維布之介電常數在上述範圍時，可降低絕緣層之介 電常數，可適用在使用高速信號之半導體封裝中。Further, the glass fiber cloth used in the present invention preferably has a dielectric constant of 3.8 to 7.0 at 1 MHz, preferably 4.7 to 7.0, more preferably 5.4 to 6.8. When the dielectric constant of the glass fiber cloth is in the above range, the insulation layer can be reduced. The electrical constant can be applied to a semiconductor package using a high speed signal.
具有如上述之線膨脹係數、楊氐率及介電常數之玻璃纖維布，例如可適用E玻璃、S玻璃、NE玻璃、T玻璃等。As the glass fiber cloth having the above-described linear expansion coefficient, populus ratio, and dielectric constant, for example, E glass, S glass, NE glass, T glass, or the like can be applied.
本發明使用之玻璃纖維布之厚度，以10至35μm為宜，較佳為10至20μm。又，使用之玻璃纖維布片數並不限定為1片，也可重疊複數片薄玻璃纖維布來使用。同時，重疊複數片玻璃纖維布來使用時，其合計厚度只要滿足上述範圍就可以。The thickness of the glass fiber cloth used in the present invention is preferably 10 to 35 μm, preferably 10 to 20 μm. Further, the number of the glass fiber sheets to be used is not limited to one, and a plurality of thin glass fiber cloths may be stacked and used. Meanwhile, when a plurality of sheets of glass fiber cloth are used in combination, the total thickness thereof may be within the above range.
將本發明所使用之樹脂組成物含浸在纖維基材中的方法，並無特別限制，可列舉有：將樹脂組成物溶解到溶劑中調製成樹脂組成物清漆，在前述樹脂組成物清漆中浸漬纖維基材之方法；將該樹脂組成物清漆以各種塗布機塗布到纖維基材之塗布方法；藉由噴霧而之吹附之方法；將附有支持基材之樹脂層予以積層之方法等。此等之中，以將纖維基材浸漬在樹脂組成物清漆中的方法為佳，藉此，可提高樹脂組成物對於纖維基材之含浸性。又，將纖維基材浸漬在樹脂組成物清漆中時，可使用通常之含浸塗布設備。The method of impregnating the resin composition used in the present invention with the fiber base material is not particularly limited, and examples thereof include dissolving the resin composition in a solvent to prepare a resin composition varnish, and dipping the resin composition varnish. A method of coating a fiber base material; a coating method of applying the resin composition varnish to a fiber base material by various coaters; a method of blowing by spraying; a method of laminating a resin layer with a support base material, and the like. Among these, a method of immersing the fibrous base material in the resin composition varnish is preferred, whereby the impregnation property of the resin composition with respect to the fibrous base material can be improved. Further, when the fiber base material is immersed in the resin composition varnish, a usual impregnation coating apparatus can be used.
尤其是當纖維基材之厚度在0.045mm以下時，以從纖維基材之兩面積層薄膜狀之樹脂層的方法為宜。藉此，可自由自在地調節樹脂組成物對纖維基材之含浸量，可提高絕緣層的成形性。又，藉由分別改變從兩面積層之樹脂層之厚度，而可在纖維基材之表面內面自由變更樹脂層之厚度。又，當積層薄膜狀之樹脂層時，以使用真空的積層裝 置等較佳。In particular, when the thickness of the fibrous base material is 0.045 mm or less, a method of forming a film-like resin layer from two regions of the fibrous base material is preferred. Thereby, the impregnation amount of the resin composition to the fiber base material can be freely adjusted, and the formability of the insulating layer can be improved. Further, by changing the thickness of the resin layer from the two-area layer, the thickness of the resin layer can be freely changed on the inner surface of the surface of the fiber base material. Further, when a film-like resin layer is laminated, a laminate using a vacuum is used. It is better to set it.
具體而言，製造含有纖維基材之絕緣層的方法，可列舉如以下之方法。Specifically, a method of producing an insulating layer containing a fibrous base material is as follows.
第12圖表示製造樹脂層2之步驟的一個例子之步驟圖。在此，針對預先製造載體材料5a、5b，將此載體材料5a、5b積層在纖維基材11上之後，剝離載體薄膜之方法，具體說明之。Fig. 12 is a view showing a step of an example of a step of producing the resin layer 2. Here, a method of peeling off the carrier film after laminating the carrier materials 5a and 5b on the fiber base material 11 in advance of the carrier materials 5a and 5b will be specifically described.
預先製造由將第一樹脂組成物塗布在載體薄膜上而成之載體材料5a，與由將第二樹脂組成物塗布在別的載體薄膜上而成之載體材料5b。此時，藉由先變更第一樹脂組成物之厚度與第二樹脂組成物之厚度，則可將在纖維基材之表面內面上所形成之樹脂厚度予以自由變更。其次，使用真空積層裝置6，在減壓下，從纖維基材之兩面重疊載體材料5a及5b後以積層輥61接合。如此，藉由在減壓下接合，即使在纖維基材11之內部或在載體材料5a、5b之樹脂層與纖維基材11接合之部位存在有非充填部份，也可將此作為減壓空洞或實質的真空空洞。因此，可減少在最終所得之樹脂層2中所產生之空洞。此係由於減壓空洞或真空空洞可用後述之加熱處理而消除。作為在如此之減壓下使纖維基材11與載體材料5a、5b接合之其他裝置，例如可使用真空箱裝置等。The carrier material 5a obtained by coating the first resin composition on the carrier film and the carrier material 5b obtained by coating the second resin composition on another carrier film are prepared in advance. At this time, by changing the thickness of the first resin composition and the thickness of the second resin composition, the thickness of the resin formed on the inner surface of the surface of the fiber substrate can be freely changed. Next, using the vacuum laminating apparatus 6, the carrier materials 5a and 5b are superposed on both surfaces of the fiber base material under reduced pressure, and joined by a laminating roll 61. Thus, by bonding under reduced pressure, even if there is a non-filled portion in the inside of the fibrous base material 11 or in the portion where the resin layer of the carrier materials 5a, 5b is bonded to the fibrous base material 11, the pressure can be reduced. A hollow or substantial vacuum cavity. Therefore, voids generated in the finally obtained resin layer 2 can be reduced. This is because the decompression cavity or the vacuum cavity can be eliminated by the heat treatment described later. As another means for joining the fiber base material 11 to the carrier materials 5a, 5b under such reduced pressure, for example, a vacuum box device or the like can be used.
其次，在纖維基材11與載體材料5a、5b接合後，用熱風乾燥裝置62，以在載體材料上塗布之樹脂的熔融溫度以上之溫度進行加熱處理。藉此，在前述減壓下於接合步 驟中所產生之減壓空洞等幾乎可完全被消除。加熱處理之其他方法，例如可使用紅外線加熱裝置、加熱輥裝置、平板狀之熱盤加壓裝置等來實施。Next, after the fiber base material 11 is joined to the carrier materials 5a and 5b, heat treatment is performed by the hot air drying device 62 at a temperature equal to or higher than the melting temperature of the resin coated on the carrier material. Thereby, in the bonding step under the aforementioned decompression The decompression holes and the like generated in the step can be almost completely eliminated. Other methods of heat treatment can be carried out, for example, by using an infrared heating device, a heating roller device, a flat plate hot plate pressurizing device, or the like.
將載體材料5a、5b積層在纖維基材11上之後，剝離載體薄膜。藉由此方法，可在纖維基材11上擔持樹脂材料，而獲得內藏有纖維基材11之絕緣層。After the carrier materials 5a, 5b are laminated on the fibrous substrate 11, the carrier film is peeled off. By this method, the resin material can be carried on the fiber base material 11, and the insulating layer in which the fiber base material 11 is housed can be obtained.
又，將纖維基材浸漬在樹脂組成物清漆時，樹脂組成物清漆中所使用之溶劑，雖然期望其對樹脂組成物中之樹脂成分顯示有良好溶解性，但在沒有造成壞影響之範圍內亦可使用弱溶劑。顯示有良好溶解性之溶劑，可列舉如：丙酮、甲基乙基酮、甲基異丁基酮、環已酮、四氫呋喃、二甲基甲醯胺、二甲基乙醯胺、二甲基亞碸、乙二醇、溶纖劑(cellosolve)系、卡必醇(carbitol)系等。Further, when the fiber base material is immersed in the resin composition varnish, the solvent used in the resin composition varnish is desirably exhibiting good solubility to the resin component in the resin composition, but it does not cause a bad influence. Weak solvents can also be used. Examples of the solvent having good solubility include, for example, acetone, methyl ethyl ketone, methyl isobutyl ketone, cyclohexanone, tetrahydrofuran, dimethylformamide, dimethylacetamide, dimethyl Aachen, ethylene glycol, cellosolve, carbitol, and the like.
前述樹脂組成物清漆之固形成分，並無特別限定，但以40至80重量%為宜，尢其以50至65重量%為佳。藉此，可更加提高樹脂組成物清漆對於纖維基材的含浸性。藉由在前述纖維基材中含浸前述樹脂組成物，並在預定之溫度，例如在80至200℃等使其乾燥，而可得到絕緣層。The solid content of the resin composition varnish is not particularly limited, but is preferably 40 to 80% by weight, particularly preferably 50 to 65% by weight. Thereby, the impregnation property of the resin composition varnish to a fiber base material can be improved more. The insulating layer can be obtained by impregnating the above-mentioned resin composition with the above-mentioned resin composition and drying it at a predetermined temperature, for example, at 80 to 200 °C.
其次，針對本發明之多層電路基板之製造方法的一個例子使用實施例之第3圖至11圖說明，但不一定侷限於此。Next, an example of a method of manufacturing a multilayer circuit substrate of the present invention will be described using Figs. 3 to 11 of the embodiment, but is not necessarily limited thereto.
首先，將預浸體5(住友電木(股)製EI-6785GS，厚度 0.2mm)使用2張250x250mm正方形之可剝離(Peelable)型之附有載體銅箔之銅箔(古河電氣工業(股)製：9μm銅箔，品名F-DP附有銅載體之極薄電解銅箔、載體銅箔70μm)以使附有載體銅箔之銅箔中的載體銅箔4相接於預浸體5之方式挾住，加壓(3MPa)加熱(180℃)放置1小時而獲得支持基材(第3圖)。First, the prepreg 5 (Sumitomo Bakelite EI-6785GS, thickness) 0.2mm) Two pieces of 250x250mm square peelable (Peelable) type copper foil with carrier copper foil (made by Furukawa Electric Co., Ltd.: 9μm copper foil, F-DP with extremely thin electrolytic copper with copper carrier) The foil and the carrier copper foil (70 μm) were placed so that the carrier copper foil 4 in the copper foil with the carrier copper foil was brought into contact with the prepreg 5, and heated (180 ° C) for 1 hour under pressure (3 MPa). Support substrate (Figure 3).
支持基材之表面經軟性蝕刻處理後，使乾膜抗蝕劑(東京應化工業(股)製：AR-320，膜厚20μm)對支持基材的兩面進行輥積層，使用預定之圖案形成用遮罩來曝光、顯像，形成在導體電路之形成中所需要的抗電鍍層。其次，使支持基材作為電解電鍍用之導線，藉由電解電鍍金而形成0.1μm之電鍍金層7，在其上藉由電解電鍍鎳而形成3μm之電鍍鎳層8，再於其上藉由電解電鍍銅而形成14μm之電鍍銅層9，而得到導體電路層60。其次，將乾膜抗蝕劑剝離(第4圖)。After the surface of the support substrate was subjected to a soft etching treatment, a dry film resist (manufactured by Tokyo Ohka Kogyo Co., Ltd.: AR-320, film thickness: 20 μm) was subjected to roll lamination on both sides of the support substrate, and a predetermined pattern was formed. The mask is used for exposure and development to form an anti-plating layer required for the formation of the conductor circuit. Next, the supporting substrate is used as a wire for electrolytic plating, and a gold plating layer of 0.1 μm is formed by electrolytic plating of gold, and a nickel plating layer 8 of 3 μm is formed thereon by electrolytic plating of nickel, and then borrowed thereon. A 14 μm plated copper layer 9 was formed by electrolytic plating of copper to obtain a conductor circuit layer 60. Next, the dry film resist is peeled off (Fig. 4).
其次，在導體電路層60之表面上藉由粗糙化液(Atotech Japan(股)製：Bond film)浸漬處理90秒鐘。其次，將藉由本發明之內有玻璃纖維布之絕緣層a(住友電木(股)製：APL-3651玻璃纖維布種玻璃不織布(日本Vilene(股)製；EPC4015玻璃纖維布厚度12μm)絕緣層厚度40μm、以PET薄膜作為支持薄膜)裁斷成240x240mm之正方形，對導體電路層60之兩面進行真空加壓(名機製作所(股)製MVLP-500/600-ILA)，在第1次為溫度80℃、壓力0.5MPa，第2次為溫度100℃、壓力1.0MPa之 條件下形成，在150℃加熱30分鐘之後，剝離PET薄膜，作成絕緣層10(第5圖)。Next, the surface of the conductor circuit layer 60 was immersed by a roughening liquid (manufactured by Atotech Japan Co., Ltd.: Bond film) for 90 seconds. Next, the insulating layer a of the glass fiber cloth of the present invention (made by Sumitomo Bakelite): APL-3651 glass fiber cloth type glass non-woven fabric (made by Japan Vilene Co., Ltd.; EPC4015 glass fiber cloth thickness 12 μm) is insulated. The thickness of the layer was 40 μm, and the PET film was used as the support film. The film was cut into a square of 240×240 mm, and both sides of the conductor circuit layer 60 were vacuum-pressed (MVLP-500/600-ILA manufactured by Nihon Seiki Co., Ltd.). The temperature is 80 ° C, the pressure is 0.5 MPa, and the second time is the temperature of 100 ° C and the pressure of 1.0 MPa. Under the conditions, after heating at 150 ° C for 30 minutes, the PET film was peeled off to form an insulating layer 10 (Fig. 5).
接著，使用CO2雷射加工機(日立Via機械(股)製：LG-2G212)以加工條件為第1步驟：脈衝寬度6μ sec、投射數1發，第2步驟：脈衝寬度2μ sec、投射數1發來形成引導孔(via hole)，為了洗淨、活化絕緣層10之表面，在主成分為單乙基丁基醇之溶液(羅門哈斯(Rohm and Haas)電子材料(股)製，MLB調節劑)中以液溫80℃浸漬5分鐘，接著，在氧化性粗糙化液的過錳酸鉀作為主成分的溶液(羅門哈斯電子材料(股)製，MLB促進劑)中以液溫80℃浸漬10分鐘，接著為了洗淨錳殘渣，以硫酸溶液(羅門哈斯電子材料(股)製，MLB中和劑)在液溫40℃浸漬5分鐘，再進行水洗及溫水洗淨(第6圖)。Next, using a CO2 laser processing machine (Hitachi Via Machinery Co., Ltd.: LG-2G212), the processing conditions are the first step: a pulse width of 6 μsec, a projection number of one shot, and a second step: a pulse width of 2 μsec and a projection number. 1 is formed to form a via hole, and in order to wash and activate the surface of the insulating layer 10, a solution of a monoethyl butyl alcohol (Rohm and Haas electronic material) is used as a main component. The MLB conditioner was immersed at a liquid temperature of 80 ° C for 5 minutes, and then a solution of a potassium permanganate having a oxidizing roughening solution as a main component (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB accelerator) After immersing at 80 ° C for 10 minutes, the manganese residue was washed with a sulfuric acid solution (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB neutralizer) at a liquid temperature of 40 ° C for 5 minutes, and then washed with water and warm water. (Figure 6).
接著，使用無電解電鍍銅液(Atotech(股)製Print Gantt MSK-DK系列)在兩面形成厚度1.0μm之無電解電鍍銅層，以積層機將感光性乾膜(東京應化工業(股)製AR-320)在無電解電鍍層上於兩面形成，並曝光、顯像，而形成耐電鍍抗蝕劑(plating resist)，對耐電鍍抗蝕劑之非形成部藉由電解電鍍銅而於兩面形成厚度14μm之電解電鍍銅層。Next, an electroless copper plating layer having a thickness of 1.0 μm was formed on both sides using an electroless copper plating solution (Print Gantt MSK-DK series manufactured by Atotech Co., Ltd.), and a photosensitive dry film was laminated by a laminator (Tokyo Chemical Industry Co., Ltd.) The AR-320 is formed on both sides of the electroless plating layer, and is exposed and developed to form a plating resist, and the non-formed portion of the plating resist is electrolytically plated with copper. An electrolytically plated copper layer having a thickness of 14 μm was formed on both sides.
之後，剝離耐電鍍抗蝕劑，並將露出之無電解電鍍銅層以軟性蝕刻液(荏原電產(股)製SAC)除去，將由無電解電鍍銅層與電解電鍍銅層所構成之導體電路層12形成在兩面上，用200℃熱處理60分鐘(第7圖)。Thereafter, the plating resist is peeled off, and the exposed electroless copper plating layer is removed by a soft etching liquid (SAC manufactured by Ebara Electric Co., Ltd.), and a conductor circuit composed of an electroless copper plating layer and an electrolytic plating copper layer is formed. Layer 12 was formed on both sides and heat treated at 200 ° C for 60 minutes (Fig. 7).
重復上述步驟，將絕緣層10與導體電路層12積層單面6層(第8圖)。The above steps were repeated, and the insulating layer 10 and the conductor circuit layer 12 were laminated on one side and six layers (Fig. 8).
其次，剝開支持基材之載體銅箔4與銅箔3之間，可得到附有銅箔之多層電路基板(第9圖)。Next, a multilayer circuit board with a copper foil (Fig. 9) obtained by peeling off the carrier copper foil 4 of the support substrate and the copper foil 3 is obtained.
接著，在導體電路層12經剝開之面上張貼遮罩膠帶13(日東電工(股)製：Elep masking N-380)，以使液不會滲透之方式將附有銅箔之多層電路基板浸漬在蝕刻液(氯化亞鐵40∘ Be)中，除去銅箔3(第10圖)。此時，經蝕刻出銅箔3之電鍍金層7係具有作為抗蝕刻劑之機能，不會溶解導體電路。Next, a mask tape 13 (made by Nitto Denko Co., Ltd.: Elep masking N-380) is placed on the peeled surface of the conductor circuit layer 12 to laminate the copper foil-attached multilayer circuit substrate in such a manner that the liquid does not penetrate. The copper foil 3 was removed by immersion in an etching solution (ferric chloride 40 Å Be) (Fig. 10). At this time, the gold plating layer 7 which is etched out of the copper foil 3 has a function as an etch resist, and does not dissolve the conductor circuit.
然後剝離遮罩膠帶13，在出現電鍍金層7之部份上貼附遮罩膠帶。之後，在導體電路層12之表面上藉由粗糙化液(Atotech Japan(股)製：Bond film)浸漬處理90秒鐘，使導體電路層12之表面被粗糙化，對多層電路基板沒被遮罩之面以網版印刷機(Mino group(股)製，force2525)印刷阻焊層14(太陽油墨製造(股)製，PSR-4000 AUS703)，以使導體電路露出之方式使用預定之遮罩進行曝光、顯像、硬化，導體電路上之阻焊層(Solder Resist Layer)厚度以成為12μm之方式形成。The masking tape 13 is then peeled off, and a masking tape is attached to the portion where the gold plating layer 7 appears. After that, the surface of the conductor circuit layer 12 is roughened by the immersion treatment on the surface of the conductor circuit layer 12 by a roughening liquid (Atotech Japan: Bond film) for 90 seconds, and the multilayer circuit substrate is not covered. A masking layer 14 (made by Sun Ink Manufacturing Co., Ltd., PSR-4000 AUS703) was printed on a cover screen by a screen printing machine (manufactured by Mino Group Co., Ltd., force 2525) to use a predetermined mask in such a manner that the conductor circuit was exposed. Exposure, development, and hardening were carried out, and the thickness of the Solder Resist Layer on the conductor circuit was formed to be 12 μm.
其次，在從阻焊層14露出之導體電路12上，形成由無電解電鍍鎳層3μm與再於其上之無電解電鍍金層0.1μm所構成的電鍍層15，之後剝離遮罩膠帶，藉由銑刀(router)加工機，可得25片之單面積層多層電路基板(40mmx40mm基板)(第11圖)。Next, on the conductor circuit 12 exposed from the solder resist layer 14, a plating layer 15 composed of an electroless nickel plating layer of 3 μm and an electroless plating gold layer of 0.1 μm thereon is formed, and then the mask tape is peeled off. A 25-piece single-area multilayer circuit board (40 mm x 40 mm substrate) is obtained by a router processing machine (Fig. 11).
同時，第10圖之下面變成半導體晶片搭載部，上面變成BGA球搭載部。At the same time, the lower surface of Fig. 10 becomes a semiconductor wafer mounting portion, and the upper surface becomes a BGA ball mounting portion.
將實施例1之絕緣層a改為使用絕緣層b(住友電木(股製APL-3601，厚度40μm，以PET作為支持薄膜)，可得到單面積層多層電路基板。製作方法基本上是與實施例1相同地進行。By changing the insulating layer a of the first embodiment to the insulating layer b (Sumitomo Bakelite (available from APL-3601, thickness 40 μm, PET as a supporting film), a single-layer multilayer circuit substrate can be obtained. Example 1 was carried out in the same manner.
以下記述與實施例1相異處。The following description differs from the first embodiment.
對支持基材貼附絕緣層b之條件是用真空加壓機(名機製作所(股)製MVLP-500/600-IIA)以第1次：溫度80℃、壓力0.5MPa，第2次：溫度100℃、壓力1.0MPa之條件下，在兩面形成絕緣層b，剝開PET薄膜後，在170℃加熱45分鐘製作絕緣層10。The condition for attaching the insulating layer b to the support substrate is the first time using a vacuum press machine (MVLP-500/600-IIA manufactured by Nihon Seisakusho Co., Ltd.): temperature 80 ° C, pressure 0.5 MPa, second time: The insulating layer b was formed on both surfaces under the conditions of a temperature of 100 ° C and a pressure of 1.0 MPa, and the PET film was peeled off, and then the insulating layer 10 was formed by heating at 170 ° C for 45 minutes.
其次，使用UV-YAG雷射加工機(三菱電機(股)製：ML605LDX)，以先端輸出94μJ、射出數30發之加工條件在絕緣層10形成引導孔。Next, using a UV-YAG laser processing machine (Mitsubishi Electric Co., Ltd.: ML605LDX), a guide hole was formed in the insulating layer 10 under the processing conditions of a front end output of 94 μJ and an emission number of 30 shots.
用以將雷射開口後之絕緣層10的表面洗淨、活性化之條件：在主成分為單乙基丁基醇之溶液(羅門哈斯(Rohm and Haas)電子材料(股)製，MLB調節劑)中以液溫80℃浸漬10分鐘，接著，在氧化性粗糙化液的過錳酸鉀作為主成分的溶液(羅門哈斯電子材料(股)製，MLB促進劑)中以液溫80℃浸漬20分鐘，接著為了洗淨錳殘渣，以硫酸溶液(羅門哈斯電子材料(股)製，MLB中和劑)在液溫40℃浸漬5分鐘，再進行水洗及溫水洗淨。The condition for washing and activating the surface of the insulating layer 10 after the laser opening is: a solution in which the main component is monoethyl butyl alcohol (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB) In the conditioner, the solution was immersed at a liquid temperature of 80 ° C for 10 minutes, and then, in a solution of potassium permanganate having a oxidizing roughening solution as a main component (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB accelerator), the liquid temperature was used. After immersing at 80 ° C for 20 minutes, the manganese residue was washed with a sulfuric acid solution (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB neutralizer) at a liquid temperature of 40 ° C for 5 minutes, and then washed with water and warm water.
除了上述之外，其餘與實施例1同樣進行，而可得25片之單面積層多層電路基板(40mmx40mm基板)。Except for the above, the same procedure as in Example 1 was carried out, and 25 single-layer multilayer circuit substrates (40 mm x 40 mm substrates) were obtained.
1.樹脂組成物清漆之調整 將作為熱硬化性樹脂之酚醛清漆型氰酸酯樹脂(Lonza Japan(股)製，Prime set PT-30，重量平均分子量約2,600)15重量份、作為環氧樹脂之聯苯二亞甲基型環氧樹脂(日本化藥(股)製，NC-3000P，環氧當量275)8重量份、作為酚樹脂之聯苯二亞甲基型酚樹脂(明和化成(股)製，MEH-7851-S，羥基當量203)7重量份及作為偶合劑之環氧矽烷型偶合劑(日本UNIKA(股)製，A-187)，於常溫下溶解至相對於後述之無機充填材100重量份為0.3重量份之甲基乙基酮中，並添加作為無機充填材之球狀熔融二氧化矽SFP-10X(電氣化學工業(股)製，平均粒徑0.3μm)20重量份及球狀熔融二氧化矽SO-32R(Admatechs(股)製，平均粒徑1.5μm)50重量份，用高速攪拌機攪拌10分鐘，調製樹脂組成物清漆。1. Adjustment of resin composition varnish 15 parts by weight of a novolac type cyanate resin (manufactured by Lonza Japan Co., Ltd., Prime set PT-30, weight average molecular weight: about 2,600), which is a thermosetting resin, and a biphenyl dimethylene type as an epoxy resin. Epoxy resin (manufactured by Nippon Kayaku Co., Ltd., NC-3000P, epoxy equivalent 275) 8 parts by weight, biphenyl dimethylene phenol resin as phenol resin (Minghe Chemical Co., Ltd., MEH-7851- S, a hydroxyl group equivalent of 203), 7 parts by weight, and an epoxy decane type coupling agent (manufactured by Nippon UNIKA Co., Ltd., A-187), which is a coupling agent, is dissolved at room temperature to 0.3 parts by weight relative to 100 parts by weight of an inorganic filler to be described later. In a part by weight of methyl ethyl ketone, 20 parts by weight of spherical molten cerium oxide SFP-10X (manufactured by Electric Chemical Industry Co., Ltd., average particle diameter: 0.3 μm) and spherical molten dioxide were added as an inorganic filler. 50 parts by weight of 矽SO-32R (manufactured by Admatechs Co., Ltd., average particle diameter: 1.5 μm) was stirred for 10 minutes in a high-speed mixer to prepare a resin composition varnish.
2.載體材料之製造 載體薄膜是使用聚對苯二甲酸乙二酯(三菱化學聚酯公司製，SFB-38，厚度38μm、寬480μm)，將上述樹脂組成物清漆用逗點塗布機裝置(comma Coater)塗布，在170℃之乾燥裝置乾燥3分鐘，形成厚度20μm、寬410μm之樹脂層並使其位於載體薄膜之寬度方向的中心，而得載體材料1(最終形成第1樹脂層)。2. Manufacture of carrier materials As the carrier film, polyethylene terephthalate (manufactured by Mitsubishi Chemical Co., Ltd., SFB-38, thickness: 38 μm, width: 480 μm) was used, and the above resin composition varnish was coated with a comma coater (comma Coater). The drying apparatus at 170 ° C was dried for 3 minutes to form a resin layer having a thickness of 20 μm and a width of 410 μm and placed at the center in the width direction of the carrier film to obtain a carrier material 1 (finally forming a first resin layer).
又，以同樣之方法調整塗布之樹脂組成物清漆之量，形成厚度8μm、寬360μm之樹脂層並使其位於載體薄膜之寬度方向的中心，而得載體材料2(最終形成第2樹脂層)。Further, the amount of the applied resin composition varnish was adjusted in the same manner to form a resin layer having a thickness of 8 μm and a width of 360 μm and positioned at the center in the width direction of the carrier film to obtain a carrier material 2 (finally forming a second resin layer). .
3.絕緣層d之製造 纖維基材是使用E玻璃織布(交聯型#1015、寬360μm、厚度15μm、基重17g/m2 )，如第12圖所示藉由真空積層裝置及熱風乾燥裝置而製造預浸體。3. Fabrication of insulating layer d The fiber substrate was made of E glass woven fabric (crosslinked type #1015, width 360 μm, thickness 15 μm, basis weight 17 g/m 2 ), as shown in Fig. 12 by vacuum laminating device and hot air The prepreg is manufactured by drying the apparatus.
具體而言，在玻璃織布之兩面上，將前述載體材料1與載體材料2以位於玻璃織布之寬度方向之中心的方式分別重疊，並在750 Torr之減壓條件下使用80℃積層輥來接合。Specifically, on both sides of the glass woven fabric, the carrier material 1 and the carrier material 2 are respectively overlapped so as to be located at the center of the width direction of the glass woven fabric, and the 80 ° C laminated roller is used under a reduced pressure of 750 Torr. Come to join.
在此，在玻璃織布之寬度方向尺寸的內側領域中，將載體材料1與載體材料2之樹脂層在纖維布之兩側各別接合，同時，在玻璃織布之寬度方向尺寸的外側領域中，將載體材料1與載體材料2之樹脂層互相接合。Here, in the inner field of the width direction dimension of the glass woven fabric, the resin layer of the carrier material 1 and the carrier material 2 are bonded to each other on both sides of the fiber cloth, and at the same time, in the outer side of the width direction of the glass woven fabric. The carrier material 1 and the resin layer of the carrier material 2 are bonded to each other.
其次，將上述經接合者，藉由在設定成120℃之橫搬送型之熱風乾燥裝置內通過2分鐘，而於沒有加壓作用下進行加熱處理，得到厚度為35μm(第1樹脂層：16μm，纖維基材：15μm，第2樹脂層；4μm)之絕緣層d。Then, the bonded person was subjected to heat treatment without pressing under a hot air drying apparatus set to 120 ° C in a horizontal conveying type to obtain a thickness of 35 μm (first resin layer: 16 μm). , fibrous substrate: 15 μm, second resin layer; 4 μm) insulating layer d.
將實施例1之絕緣層a改用絕緣層d，可得25片之單面積層多層電路基板(40mmx40mm基板)。製作方法是除了使第1樹脂層配置成面對導體電路層6之外，基本上是與實施例1同樣地進行。By changing the insulating layer a of the first embodiment to the insulating layer d, 25 single-layer multilayer circuit substrates (40 mm x 40 mm substrates) were obtained. The production method was basically the same as in the first embodiment except that the first resin layer was placed to face the conductor circuit layer 6.
比較例係將實施例1之絕緣層a改用絕緣層c(味之素(股)製ABF-GX13，厚度40μm、PET薄膜作為支持薄膜)，可得單面積層多層電路基板。製作方法，基本上是與實施例1同樣地進行。In the comparative example, the insulating layer a of the first embodiment was changed to an insulating layer c (ABF-GX13 manufactured by Ajinomoto Co., Ltd., a thickness of 40 μm, and a PET film as a supporting film) to obtain a single-layer multilayer circuit substrate. The production method was basically carried out in the same manner as in Example 1.
以下記述與實施例1不同之處。The difference from the first embodiment will be described below.
對支持基材貼附絕緣層c之條件是用真空加壓機(名機製作所(股)製MVLP-500/600-IIA)以第1次：溫度105℃、壓力0.6MPa，第2次：溫度105℃、壓力0.5MPa之條件下，在兩面形成絕緣層c，剝開PET薄膜後，在180℃加熱30分鐘製作絕緣層10。The condition for attaching the insulating layer c to the support substrate is the first time using a vacuum press machine (MVLP-500/600-IIA manufactured by Nihon Seisakusho Co., Ltd.): temperature 105 ° C, pressure 0.6 MPa, second time: The insulating layer c was formed on both surfaces under the conditions of a temperature of 105 ° C and a pressure of 0.5 MPa, and the PET film was peeled off, and then the insulating layer 10 was formed by heating at 180 ° C for 30 minutes.
其次，使用UV-YAG雷射加工機(三菱電機(股)製：ML605LDX)，以先端輸出70μJ、射出數30發之加工條件在絕緣層10形成引導孔。Next, using a UV-YAG laser processing machine (Mitsubishi Electric Co., Ltd.: ML605LDX), a guide hole was formed in the insulating layer 10 under the processing conditions of a front end output of 70 μJ and an emission number of 30 shots.
用以將雷射開口後之絕緣層10表面洗淨、活性化之條件是：在主成分為單乙基丁基醇之溶液(羅門哈斯電子材料(股)製，MLB調節劑)中以液溫80℃浸漬5分鐘，接著，在氧化性粗糙化液的過錳酸鉀作為主成分的溶液(羅門哈斯電子材料(股)製，MLB促進劑)中以液溫80℃浸漬20分鐘，接著為了洗淨錳殘渣，以硫酸溶液(羅門哈斯電子材料(股)製，MLB中和劑)在液溫40℃浸漬5分鐘，再進行水洗及溫水洗淨。The condition for washing and activating the surface of the insulating layer 10 after the laser opening is: in a solution in which the main component is monoethyl butyl alcohol (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB regulator) The liquid was immersed at a temperature of 80 ° C for 5 minutes, and then immersed in a solution of potassium permanganate having an oxidizing roughening solution as a main component (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB accelerator) at a liquid temperature of 80 ° C for 20 minutes. Then, in order to wash the manganese residue, a sulfuric acid solution (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB neutralizer) was immersed at a liquid temperature of 40 ° C for 5 minutes, and then washed with water and warm water.
除了上述之外，其餘與實施例1同樣地進行，可得25片之單面積層多層電路基板(40mmx40mm基板)。Except for the above, in the same manner as in Example 1, 25 single-layer multilayer circuit boards (40 mm x 40 mm substrates) were obtained.
以下表示評估項目與評估方法。The evaluation items and evaluation methods are indicated below.
評估方法是如下所述。The evaluation method is as follows.
[玻璃移轉溫度及彈性模數] 使用常壓積層機，積層2片絕緣層，將在200℃硬化2小時後所得之物切成試驗片(寬5mmx長度30mmx厚度80μm)。[Glass transfer temperature and modulus of elasticity] Using an atmospheric laminator, two sheets of an insulating layer were laminated, and the obtained product was hardened at 200 ° C for 2 hours, and cut into test pieces (width 5 mm x length 30 mm x thickness 80 μm).
在測定中，使用動態黏彈性測定裝置(精工儀器公司製，DMS6100)，一邊以3℃/分鐘之比率昇溫，一邊給予頻率10Hz之變動而進行動態黏彈性測定，從tan δ之峰值來判定玻璃移轉溫度(Tg)，又藉由測定求得25℃、250℃之彈性模數。In the measurement, a dynamic viscoelasticity measurement was performed using a dynamic viscoelasticity measuring apparatus (DMS6100, manufactured by Seiko Instruments Inc.) at a rate of 3 ° C/min, and a dynamic viscoelasticity measurement was performed while changing the frequency by 10 Hz, and the glass was determined from the peak of tan δ. The transfer temperature (Tg) was measured and the elastic modulus at 25 ° C and 250 ° C was determined by measurement.
[線膨脹係數] 使用常壓積層機，積層2片絕緣層，在200℃硬化2小時後獲得樹脂硬化物。自所得之樹脂硬化物採取4mmx20mm之評估用試料，使用TMA裝置(TA儀器公司製)，以10℃/分鐘昇溫後測定。α1是玻璃移轉溫度以下之線膨脹係數，α2是玻璃移轉溫度以上之線膨脹係數。[Linear expansion coefficient] Two layers of the insulating layer were laminated using an atmospheric laminator, and after hardening at 200 ° C for 2 hours, a cured resin was obtained. A sample of 4 mm x 20 mm of the obtained resin was taken from the obtained resin cured product, and the temperature was measured at 10 ° C /min using a TMA apparatus (manufactured by TA Instruments Co., Ltd.). Α1 is the linear expansion coefficient below the glass transition temperature, and α2 is the linear expansion coefficient above the glass transition temperature.
[抗拉彈性模數] 使用常壓積層機，積層2片絕緣層，在200℃硬化2小時後獲得樹脂硬化物。將所得之樹脂硬化物以抗拉模式(tensile mode)在負重滿刻度20 kgf、速度5mm/min條件下進行測定。[Tensile modulus of elasticity] Two layers of the insulating layer were laminated using an atmospheric laminator, and after hardening at 200 ° C for 2 hours, a cured resin was obtained. The obtained resin cured product was measured in a tensile mode under a weight-bearing full scale of 20 kgf and a speed of 5 mm/min.
[隨溫度變化之基板反翹量] 所得之多層電路基板之反翹量係使用溫度可變雷射 三次元測定機(日立Technologies and Services公司製，型式LS220-MT100 MT50)測定在高度方向之變位，變位差之最大值當作反翹量。測定溫度是在-55℃、25℃、150℃、260℃等4點進行。在全部測定溫度中之反翹量在200μm以下者為◎、400μm以下者為○、600μm以下者為△，800μm以下者為×。[Substrate anti-warpage amount with temperature change] The resulting anti-warpage amount of the multilayer circuit substrate is a temperature-variable laser A three-dimensional measuring machine (manufactured by Hitachi Technologies and Services Co., Ltd., type LS220-MT100 MT50) measures the displacement in the height direction, and the maximum value of the displacement difference is regarded as the amount of back-up. The measurement temperature was carried out at 4 points such as -55 ° C, 25 ° C, 150 ° C, and 260 ° C. When the amount of back warpage in all the measurement temperatures is 200 μm or less, it is ◎, 400 μm or less is ○, 600 μm or less is Δ, and 800 μm or less is ×.
絕緣層之物性值及此等之評估結果係在表1表示。The physical property values of the insulating layer and the evaluation results of these are shown in Table 1.
由評估之結果可知，實施例1、2及3之溫度變化時之反翹變動小，但比較例1推測是因絕緣層之彈性模數低，又絕緣層與導體電路層之線膨脹係數差大，故溫度變化時之反翹變動也大。As a result of the evaluation, it was found that the change in the warpage of the temperatures of Examples 1, 2, and 3 was small, but Comparative Example 1 was presumed to be because the elastic modulus of the insulating layer was low, and the coefficient of linear expansion of the insulating layer and the conductor circuit layer was poor. Large, so the change in anti-warping when the temperature changes is also large.
依本發明，因絕緣層與導體電路層之線澎脹係數差為少，所以層間產生之內部應力變小，多層電路基板之反翹變小。又，使用前述多層電路基板之半導體裝置係在半導 體元件安裝步驟、信賴性試驗中，變成反翹少之半導體裝置。因此，具有在產業上之可利用性。According to the invention, since the difference in the coefficient of linear expansion between the insulating layer and the conductor circuit layer is small, the internal stress generated between the layers becomes small, and the back warpage of the multilayer circuit substrate becomes small. Moreover, the semiconductor device using the multilayer circuit substrate described above is semi-conductive In the body element mounting step and the reliability test, it becomes a semiconductor device with less anti-warpage. Therefore, it has industrial availability.
0‧‧‧核層0‧‧‧ nuclear layer
1‧‧‧增建層1‧‧‧Additional layer
1a‧‧‧絕緣層1a‧‧‧Insulation
1b‧‧‧內墊1b‧‧‧ inner pad
1c‧‧‧外墊(BGA墊)1c‧‧‧Outer mat (BGA mat)
2‧‧‧樹脂層2‧‧‧ resin layer
3‧‧‧附有載體銅箔之銅箔中的銅箔3‧‧‧ Copper foil in copper foil with carrier copper foil
4‧‧‧附有載體銅箔之銅箔中的載體銅箔4‧‧‧ Carrier copper foil in copper foil with carrier copper foil
5‧‧‧預浸體5‧‧‧Prepreg
5a、5b‧‧‧載體材料5a, 5b‧‧‧ carrier material
6‧‧‧真空積層裝置6‧‧‧Vacuum laminating device
7‧‧‧電鍍金層7‧‧‧Electroplated gold layer
8‧‧‧電鍍鎳層8‧‧‧Electroplated nickel layer
9‧‧‧電鍍銅層9‧‧‧Electroplated copper layer
10‧‧‧絕緣層10‧‧‧Insulation
11‧‧‧纖維基材11‧‧‧Fiber substrate
12‧‧‧導體電路層12‧‧‧ conductor circuit layer
13‧‧‧遮罩膠帶13‧‧‧Mask tape
14‧‧‧阻焊層14‧‧‧ solder mask
15‧‧‧電鍍層15‧‧‧Electroplating
20‧‧‧阻焊層20‧‧‧ solder mask
60‧‧‧導體電路層60‧‧‧ conductor circuit layer
61‧‧‧積層輥61‧‧‧ laminated rolls
62‧‧‧熱風乾燥裝置62‧‧‧Hot air drying device
110‧‧‧增建基板110‧‧‧Additional substrate
第1圖係表示以往之代表性的增建多層電路基板圖。Fig. 1 is a view showing a conventional representative multilayer circuit board.
第2圖係表示本發明相關的多層電路基板之概略結構圖。Fig. 2 is a view showing a schematic configuration of a multilayer circuit substrate according to the present invention.
第3圖係表示用以說明本發明之多層電路基板的支持基材之一個例子的截面圖。Fig. 3 is a cross-sectional view showing an example of a supporting substrate for explaining the multilayer circuit substrate of the present invention.
第4圖係表示用以說明本發明之多層電路基板的在支持基材上形成導體電路層之一個例子的截面圖。Fig. 4 is a cross-sectional view showing an example of forming a conductor circuit layer on a support substrate of the multilayer circuit substrate of the present invention.
第5圖係表示用以說明本發明之多層電路基板的在支持基材上形成導體電路層與絕緣層之一個例子的截面圖。Fig. 5 is a cross-sectional view showing an example of forming a conductor circuit layer and an insulating layer on a support substrate of the multilayer circuit substrate of the present invention.
第6圖係表示用以說明本發明之多層電路基板的在絕緣層上藉由雷射而形成開口部之一個例子之截面圖。Fig. 6 is a cross-sectional view showing an example of forming an opening portion by laser irradiation on an insulating layer of the multilayer circuit substrate of the present invention.
第7圖係表示用以說明本發明之多層電路基板的在絕緣層的開口部於兩面形成導體電路層之一個例子的截面圖。Fig. 7 is a cross-sectional view showing an example of forming a conductor circuit layer on both surfaces of an opening portion of an insulating layer of the multilayer circuit substrate of the present invention.
第8圖係表示用以說明本發明之多層電路基板的在單面上積層6層導體電路層與絕緣層之一個例子的截面圖。Fig. 8 is a cross-sectional view showing an example of laminating six layers of a conductor circuit layer and an insulating layer on one surface of the multilayer circuit substrate of the present invention.
第9圖係表示用以說明本發明之多層電路基板的將支持基材的載體銅箔與銅箔剝離，並形成附有銅箔之多層電路基板之一個例子的截面圖。Fig. 9 is a cross-sectional view showing an example of a multilayer circuit board with a copper foil attached to a base material substrate of the present invention, in which a carrier copper foil for supporting a substrate is peeled off from a copper foil.
第10圖係表示用以說明本發明之多層電路基板的在電路導體層上貼附遮罩膠帶之一個例子的截面圖。Fig. 10 is a cross-sectional view showing an example of attaching a mask tape to a circuit conductor layer of the multilayer circuit substrate of the present invention.
第11圖係表示用以說明本發明之多層電路基板的形成有阻焊層(Solder Resist)及鍍覆層之多層電路基板之一個例子的截面圖。Fig. 11 is a cross-sectional view showing an example of a multilayer circuit substrate on which a solder resist layer and a plating layer are formed in the multilayer circuit substrate of the present invention.
第12圖係表示製造本發明絕緣層之裝置的概略結構圖。Fig. 12 is a schematic block diagram showing an apparatus for manufacturing the insulating layer of the present invention.
1a‧‧‧絕緣層1a‧‧‧Insulation
1b‧‧‧內墊1b‧‧‧ inner pad
1c‧‧‧外墊(BGA墊)1c‧‧‧Outer mat (BGA mat)
20‧‧‧阻焊層20‧‧‧ solder mask
Claims (5)
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| JP2007097871 | 2007-04-03 | ||
| JP2007188945A JP5194601B2 (en) | 2006-07-20 | 2007-07-20 | Multilayer circuit board and semiconductor device |
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| Publication Number | Publication Date |
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| TW200843605A TW200843605A (en) | 2008-11-01 |
| TWI419636B true TWI419636B (en) | 2013-12-11 |
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| JP2012231140A (en) * | 2011-04-14 | 2012-11-22 | Sumitomo Bakelite Co Ltd | Laminate, circuit board, and semiconductor package |
| JP5955102B2 (en) * | 2012-05-29 | 2016-07-20 | 京セラ株式会社 | Wiring board and manufacturing method thereof |
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| JP2005162787A (en) * | 2003-11-28 | 2005-06-23 | Sumitomo Bakelite Co Ltd | Resin composition and substrate using the same |
| TW200710119A (en) * | 2005-08-23 | 2007-03-16 | Ngk Spark Plug Co | A filler for through hole and a multi-layered circuit substrate |
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| JP2001279006A (en) * | 2000-03-30 | 2001-10-10 | Mitsubishi Gas Chem Co Inc | Method for producing prepreg having high dielectric constant |
| JP3719093B2 (en) * | 2000-03-28 | 2005-11-24 | 松下電工株式会社 | Method for drilling non-through holes in metal foil-clad laminates |
| JP2004123870A (en) * | 2002-10-01 | 2004-04-22 | Sumitomo Bakelite Co Ltd | Prepreg manufacturing process and transfer sheet |
| JP2005038906A (en) * | 2003-07-15 | 2005-02-10 | Dainippon Printing Co Ltd | Thin wiring board without core layer |
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| JP2005162787A (en) * | 2003-11-28 | 2005-06-23 | Sumitomo Bakelite Co Ltd | Resin composition and substrate using the same |
| TW200710119A (en) * | 2005-08-23 | 2007-03-16 | Ngk Spark Plug Co | A filler for through hole and a multi-layered circuit substrate |
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