TWI416736B - Thin film transistor and method for fabricating the same - Google Patents
Thin film transistor and method for fabricating the same Download PDFInfo
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本發明是有關於一種薄膜電晶體及其製造方法，且特別是有關於一種能夠避免氧化物半導體通道層受到損傷的薄膜電晶體及其製造方法。The present invention relates to a thin film transistor and a method of fabricating the same, and more particularly to a thin film transistor capable of preventing damage to an oxide semiconductor channel layer and a method of fabricating the same.
隨著顯示科技的日益進步，人們藉著顯示器的輔助可使生活更加便利，為求顯示器輕、薄之特性，促使平面顯示器(flat panel display,FPD)成為目前的主流。常見的平面顯示器包括液晶顯示器(liquid crystal display,LCD)、電漿顯示器(plasma display)、電激發光顯示器(electroluminescent display)等。以目前最為普及的液晶顯示器為例，其主要是由薄膜電晶體陣列基板、彩色濾光基板以及夾於二者之間的液晶層所構成。特別是，在顯示器中被大量使用到的薄膜電晶體，其結構設計或是材料的選擇更是會直接影響到產品的性能。With the advancement of display technology, people can make life more convenient by the aid of the display. In order to make the display light and thin, the flat panel display (FPD) has become the mainstream. Common flat panel displays include liquid crystal displays (LCDs), plasma displays, electroluminescent displays, and the like. Taking the most popular liquid crystal display as an example, it is mainly composed of a thin film transistor array substrate, a color filter substrate, and a liquid crystal layer sandwiched therebetween. In particular, the design of a thin film transistor that is widely used in a display, its structural design or material selection directly affects the performance of the product.
在習知的薄膜電晶體陣列基板上，多採用非晶矽(amorphous silicon,a-Si)薄膜電晶體或低溫多晶矽薄膜電晶體作為各個子畫素的切換元件。近年來，已有研究指出氧化物半導體(oxide semiconductor)薄膜電晶體相較於非晶矽薄膜電晶體，具有較高的載子移動率(carrier mobility)；而氧化物半導體薄膜電晶體相較於低溫多晶矽薄膜電晶體，則具有較佳的臨界電壓(threshold voltage,Vth)均勻性。因此，氧化物半導體薄膜電晶體有潛力成為下一代平面顯示器之關鍵元件。On a conventional thin film transistor array substrate, an amorphous silicon (a-Si) thin film transistor or a low temperature polycrystalline thin film transistor is often used as a switching element of each sub-pixel. In recent years, studies have shown that oxide semiconductor thin film transistors have higher carrier mobility than amorphous germanium thin film transistors, while oxide semiconductor thin film transistors are compared with The low temperature polycrystalline germanium film transistor has a better threshold voltage (Vth) uniformity. Therefore, oxide semiconductor thin film transistors have the potential to become key components of next-generation flat panel displays.
一般會使用鋁酸作為蝕刻氧化物半導體薄膜電晶體之源極與汲極的蝕刻劑。然而，鋁酸對於氧化物半導體薄膜電晶體之氧化物半導體通道層的蝕刻選擇比不高，因而使得氧化物半導體薄膜電晶體之源極與汲極的蝕刻程序非常難以控制，進而影響到氧化物半導體薄膜電晶體的電性表現以及可靠度。Aluminic acid is generally used as an etchant for etching the source and drain of the oxide semiconductor thin film transistor. However, the etching selectivity of the alumina acid to the oxide semiconductor channel layer of the oxide semiconductor thin film transistor is not high, so that the etching process of the source and the drain of the oxide semiconductor thin film transistor is very difficult to control, thereby affecting the oxide. Electrical performance and reliability of semiconductor thin film transistors.
本發明提供一種薄膜電晶體的製造方法，能夠縮減使用光罩的製程，並避免氧化物半導體通道層受到損傷。The present invention provides a method of manufacturing a thin film transistor, which can reduce the process of using the photomask and prevent the oxide semiconductor channel layer from being damaged.
本發明提供一種薄膜電晶體，其具有突出之氧化物半導體通道層。The present invention provides a thin film transistor having a protruding oxide semiconductor channel layer.
本發明提出一種薄膜電晶體的製造方法，其包括下列步驟。於基板上形成閘極。於基板上依序形成閘絕緣層、氧化物半導體材料層以及導電層。於導電層上形成圖案化光阻層，圖案化光阻層包括二個第一部以及連接於第一部之間的第二部，各第一部之厚度大於第二部之厚度。以圖案化光阻層為罩幕，移除未被圖案化光阻層覆蓋之導電層與氧化物半導體材料層，以形成氧化物半導體通道層以及位於氧化物半導體通道層與圖案化光阻層之間的圖案化導電層。移除部分之圖案化光阻層，以減少第一部的厚度直到第二部被移除。以未被移除之第一部為罩幕，移除未被第一部覆蓋之圖案化導電層，以於氧化物半導體通道層上形成源極與汲極。The present invention provides a method of manufacturing a thin film transistor comprising the following steps. A gate is formed on the substrate. A gate insulating layer, an oxide semiconductor material layer, and a conductive layer are sequentially formed on the substrate. Forming a patterned photoresist layer on the conductive layer, the patterned photoresist layer comprises two first portions and a second portion connected between the first portions, the thickness of each of the first portions being greater than the thickness of the second portion. The patterned photoresist layer is used as a mask to remove the conductive layer and the oxide semiconductor material layer not covered by the patterned photoresist layer to form an oxide semiconductor channel layer and the oxide semiconductor channel layer and the patterned photoresist layer The patterned conductive layer is between. A portion of the patterned photoresist layer is removed to reduce the thickness of the first portion until the second portion is removed. The patterned conductive layer not covered by the first portion is removed by the first portion that is not removed, so that the source and the drain are formed on the oxide semiconductor channel layer.
在本發明之一實施例中，上述之圖案化光阻層係藉由階調式(Gray-Tone Mask，GTM)製程或半調式(Half-Tone Mask，HTM)製程所形成。In an embodiment of the invention, the patterned photoresist layer is formed by a Gray-Tone Mask (GTM) process or a Half-Tone Mask (HTM) process.
在本發明之一實施例中，上述移除未被圖案化光阻層覆蓋之導電層與氧化物半導體材料層的方法包括下列步驟。進行第一濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之導電層。進行第二濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之氧化物半導體材料層，其中第一濕式蝕刻製程所使用之蝕刻劑與第二濕式蝕刻製程所使用之蝕刻劑不同。In an embodiment of the invention, the method of removing the conductive layer and the oxide semiconductor material layer not covered by the patterned photoresist layer comprises the following steps. A first wet etching process is performed to remove the conductive layer that is not covered by the patterned photoresist layer. Performing a second wet etching process to remove the oxide semiconductor material layer not covered by the patterned photoresist layer, wherein the etchant used in the first wet etching process and the etchant used in the second wet etching process different.
在本發明之一實施例中，上述移除未被圖案化光阻層覆蓋之導電層與氧化物半導體材料層的方法包括進行濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之導電層以及氧化物半導體材料層，其中導電層與氧化物半導體材料層採用相同蝕刻劑移除。In an embodiment of the invention, the method for removing the conductive layer and the oxide semiconductor material layer not covered by the patterned photoresist layer comprises performing a wet etching process to remove the unmasked photoresist layer. A conductive layer and an oxide semiconductor material layer, wherein the conductive layer and the oxide semiconductor material layer are removed using the same etchant.
在本發明之一實施例中，上述移除部分之圖案化光阻層的方法包括灰化製程。In an embodiment of the invention, the method of removing a portion of the patterned photoresist layer includes an ashing process.
在本發明之一實施例中，上述形成源極與汲極的方法包括以未被移除之第一部為罩幕，進行濕式蝕刻以移除未被第一部覆蓋之圖案化導電層。In an embodiment of the invention, the method for forming a source and a drain includes performing a wet etching to remove a patterned conductive layer not covered by the first portion by using a first portion that is not removed as a mask. .
在本發明之一實施例中，在形成源極與汲極之後，薄膜電晶體的製造方法更包括移除第一部。In an embodiment of the invention, after forming the source and the drain, the method of fabricating the thin film transistor further includes removing the first portion.
本發明另提出一種薄膜電晶體的製造方法，其包括下列步驟。於基板上形成閘極。於基板上依序形成閘絕緣層、氧化物半導體材料層以及導電層。於導電層上形成圖案化光阻層，圖案化光阻層包括二個第一部、連接於第一部之間的第二部以及二個與各第一部連接之第三部。各第一部之厚度大於第二部之厚度，且第二部之厚度實質上等於各第三部之厚度。以圖案化光阻層為罩幕，移除未被圖案化光阻層覆蓋之導電層與氧化物半導體材料層，以形成氧化物半導體通道層以及位於氧化物半導體通道層與圖案化光阻層之間的圖案化導電層，其中因側蝕所導致的底切發生在氧化物半導體通道層之側壁處，且底切位於第三部下方。移除部分之圖案化光阻層，以減少第一部的厚度直到第二部與第三部被移除。以未被移除之第一部為罩幕，移除位於底切上方且未被第一部覆蓋之圖案化導電層，以於氧化物半導體通道層上形成源極與汲極。The present invention further provides a method of manufacturing a thin film transistor comprising the following steps. A gate is formed on the substrate. A gate insulating layer, an oxide semiconductor material layer, and a conductive layer are sequentially formed on the substrate. Forming a patterned photoresist layer on the conductive layer, the patterned photoresist layer comprises two first portions, a second portion connected between the first portions, and two third portions connected to the first portions. The thickness of each of the first portions is greater than the thickness of the second portion, and the thickness of the second portion is substantially equal to the thickness of each of the third portions. The patterned photoresist layer is used as a mask to remove the conductive layer and the oxide semiconductor material layer not covered by the patterned photoresist layer to form an oxide semiconductor channel layer and the oxide semiconductor channel layer and the patterned photoresist layer A patterned conductive layer is formed in which undercut due to undercut occurs at the sidewall of the oxide semiconductor channel layer and the undercut is located below the third portion. A portion of the patterned photoresist layer is removed to reduce the thickness of the first portion until the second and third portions are removed. The patterned conductive layer above the undercut and not covered by the first portion is removed with the first portion not removed, to form a source and a drain on the oxide semiconductor channel layer.
在本發明之一實施例中，上述之圖案化光阻層係藉由階調式製程或半調式製程所形成。In an embodiment of the invention, the patterned photoresist layer is formed by a step process or a half-tone process.
在本發明之一實施例中，上述移除未被圖案化光阻層覆蓋之導電層與氧化物半導體材料層的方法包括下列步驟。進行乾式蝕刻製程，以移除未被圖案化光阻層覆蓋之導電層。進行濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之氧化物半導體材料層。In an embodiment of the invention, the method of removing the conductive layer and the oxide semiconductor material layer not covered by the patterned photoresist layer comprises the following steps. A dry etching process is performed to remove the conductive layer that is not covered by the patterned photoresist layer. A wet etching process is performed to remove the oxide semiconductor material layer that is not covered by the patterned photoresist layer.
在本發明之一實施例中，上述之導電層包括底導電層以及頂導電層，而移除未被圖案化光阻層覆蓋之導電層與氧化物半導體材料層的方法包括下列步驟。進行第一濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之頂導電層。進行乾式蝕刻製程，以移除未被圖案化光阻層覆蓋之底導電層。進行第二濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之氧化物半導體材料層。In an embodiment of the invention, the conductive layer comprises a bottom conductive layer and a top conductive layer, and the method of removing the conductive layer and the oxide semiconductor material layer not covered by the patterned photoresist layer comprises the following steps. A first wet etching process is performed to remove the top conductive layer that is not covered by the patterned photoresist layer. A dry etching process is performed to remove the bottom conductive layer that is not covered by the patterned photoresist layer. A second wet etching process is performed to remove the oxide semiconductor material layer that is not covered by the patterned photoresist layer.
在本發明之一實施例中，上述移除部分之圖案化光阻層的方法包括灰化製程。In an embodiment of the invention, the method of removing a portion of the patterned photoresist layer includes an ashing process.
在本發明之一實施例中，上述形成源極與汲極的方法包括以未被移除之第一部為罩幕，進行乾式蝕刻以移除位於底切上方且未被第一部覆蓋之圖案化導電層。In an embodiment of the invention, the method for forming a source and a drain includes performing a dry etch with a first portion that is not removed as a mask to remove the underlying layer and not covered by the first portion. The conductive layer is patterned.
在本發明之一實施例中，在形成源極與汲極之後，薄膜電晶體的製造方法更包括移除第一部。In an embodiment of the invention, after forming the source and the drain, the method of fabricating the thin film transistor further includes removing the first portion.
本發明又提出一種薄膜電晶體的製造方法，其包括下列步驟。於基板上形成閘極。於基板上依序形成閘絕緣層、氧化物半導體材料層、底導電層以及頂導電層。於頂導電層上形成圖案化光阻層，圖案化光阻層包括二個第一部、連接於第一部之間的第二部以及二個與各第一部連接之第三部。各第一部之厚度大於第二部之厚度，且第二部之厚度實質上等於各第三部之厚度。以圖案化光阻層為罩幕，移除未被圖案化光阻層覆蓋之頂導電層與底導電層。移除部分之圖案化光阻層，以減少第一部的厚度直到第二部與第三部被移除。以未被移除之第一部為罩幕，移除未被第一部覆蓋之頂導電層以及部分氧化物半導體材料層，以於底導電層與閘絕緣層之間形成氧化物半導體通道層，其中因側蝕所導致的底切發生在氧化物半導體通道層之側壁處。以未被移除之第一部為罩幕，移除未被第一部覆蓋之底導電層以及位於底切上方之底導電層，以於氧化物半導體通道層上形成源極與汲極。The present invention further provides a method of manufacturing a thin film transistor comprising the following steps. A gate is formed on the substrate. A gate insulating layer, an oxide semiconductor material layer, a bottom conductive layer, and a top conductive layer are sequentially formed on the substrate. A patterned photoresist layer is formed on the top conductive layer. The patterned photoresist layer includes two first portions, a second portion connected between the first portions, and two third portions connected to the first portions. The thickness of each of the first portions is greater than the thickness of the second portion, and the thickness of the second portion is substantially equal to the thickness of each of the third portions. The patterned photoresist layer is used as a mask to remove the top conductive layer and the bottom conductive layer that are not covered by the patterned photoresist layer. A portion of the patterned photoresist layer is removed to reduce the thickness of the first portion until the second and third portions are removed. Removing the first conductive layer and the portion of the oxide semiconductor material not covered by the first portion to form an oxide semiconductor channel layer between the bottom conductive layer and the gate insulating layer, with the first portion not being removed as a mask The undercut caused by the side etching occurs at the sidewall of the oxide semiconductor channel layer. The first portion not removed is used as a mask to remove the bottom conductive layer not covered by the first portion and the bottom conductive layer above the undercut to form a source and a drain on the oxide semiconductor channel layer.
在本發明之一實施例中，上述之圖案化光阻層係藉由階調式製程或半調式製程所形成。In an embodiment of the invention, the patterned photoresist layer is formed by a step process or a half-tone process.
在本發明之一實施例中，上述移除未被圖案化光阻層覆蓋之頂導電層與底導電層的方法包括下列步驟。進行濕式蝕刻製程，以移除未被圖案化光阻層覆蓋之頂導電層。進行乾式蝕刻製程，以移除未被圖案化光阻層覆蓋之底導電層。In an embodiment of the invention, the method for removing the top conductive layer and the bottom conductive layer not covered by the patterned photoresist layer comprises the following steps. A wet etching process is performed to remove the top conductive layer that is not covered by the patterned photoresist layer. A dry etching process is performed to remove the bottom conductive layer that is not covered by the patterned photoresist layer.
在本發明之一實施例中，上述以未被移除之第一部為罩幕，移除未被第一部覆蓋之頂導電層以及部分氧化物半導體材料層之方法包括進行濕式蝕刻製程，以移除未被第一部覆蓋之頂導電層以及部分氧化物半導體材料層。In an embodiment of the invention, the method of removing the top conductive layer and the portion of the oxide semiconductor material layer not covered by the first portion by using the first portion that is not removed as a mask includes performing a wet etching process To remove the top conductive layer and a portion of the oxide semiconductor material layer that are not covered by the first portion.
在本發明之一實施例中，上述以未被移除之第一部為罩幕，移除未被第一部覆蓋之底導電層以及位於底切上方之底導電層之方法包括進行乾式蝕刻製程，以移除未被第一部覆蓋之底導電層以及位於底切上方之底導電層。In an embodiment of the invention, the method of removing the bottom conductive layer not covered by the first portion and the bottom conductive layer above the undercut by using the first portion not removed as a mask comprises performing dry etching The process is to remove the bottom conductive layer that is not covered by the first portion and the bottom conductive layer that is above the undercut.
在本發明之一實施例中，上述移除部分之圖案化光阻層的方法包括灰化製程。In an embodiment of the invention, the method of removing a portion of the patterned photoresist layer includes an ashing process.
在本發明之一實施例中，在形成源極與汲極之後，薄膜電晶體的製造方法更包括移除第一部。In an embodiment of the invention, after forming the source and the drain, the method of fabricating the thin film transistor further includes removing the first portion.
本發明又提出一種薄膜電晶體，其包括閘極、閘絕緣層、氧化物半導體通道層、源極以及汲極。閘絕緣層位於閘極上。氧化物半導體通道層位於閘絕緣層上。源極以及汲極位於氧化物半導體通道層上。氧化物半導體通道層之底部突出源極以及汲極其中之一之底部之水平距離約為0.1 μm至1 μm。The present invention further provides a thin film transistor comprising a gate, a gate insulating layer, an oxide semiconductor channel layer, a source, and a drain. The gate insulating layer is on the gate. The oxide semiconductor channel layer is on the gate insulating layer. The source and the drain are on the oxide semiconductor channel layer. The bottom of the oxide semiconductor channel layer protrudes from the source and the bottom of one of the drains has a horizontal distance of about 0.1 μm to 1 μm.
在本發明之一實施例中，上述之源極包括第一導電層以及第二導電層。第一導電層位於氧化物半導體通道層上。第二導電層位於第一導電層上，其中第一導電層之底部突出第二導電層之底部之水平距離約為0.1 μm至1.5 μm。In an embodiment of the invention, the source includes a first conductive layer and a second conductive layer. The first conductive layer is on the oxide semiconductor channel layer. The second conductive layer is located on the first conductive layer, wherein a bottom of the first conductive layer protrudes from a bottom of the second conductive layer by a horizontal distance of about 0.1 μm to 1.5 μm.
在本發明之一實施例中，上述之源極更包括第三導電層，其位於第二導電層上。In an embodiment of the invention, the source further comprises a third conductive layer on the second conductive layer.
在本發明之一實施例中，上述之第一導電層、第二導電層以及第三導電層之材料分別為選自由銅(Cu)、鉬(Mo)、鈦(Ti)、鋁(Al)、鎢(W)、銀(Ag)、金(Au)及其合金所組成之族群中的至少一者。In an embodiment of the invention, the materials of the first conductive layer, the second conductive layer and the third conductive layer are respectively selected from the group consisting of copper (Cu), molybdenum (Mo), titanium (Ti), and aluminum (Al). At least one of a group consisting of tungsten (W), silver (Ag), gold (Au), and alloys thereof.
基於上述，本發明之薄膜電晶體及其製造方法透過具有至少兩種不同厚度之圖案化光阻層來分別形成薄膜電晶體之氧化物半導體通道層、源極與汲極，因此可有助於減少製程步驟與成本。此外，本發明之薄膜電晶體及其製造方法可以避免氧化物半導體通道層的結構產生破壞缺陷，並能夠改善因側蝕所導致的底切現象。Based on the above, the thin film transistor of the present invention and the method of fabricating the same, by forming a patterned photoresist layer having at least two different thicknesses, respectively forming an oxide semiconductor channel layer, a source and a drain of the thin film transistor, thereby contributing to Reduce process steps and costs. Further, the thin film transistor of the present invention and the method of manufacturing the same can prevent the structure of the oxide semiconductor channel layer from being damaged, and can improve the undercut phenomenon caused by the side etching.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1D是依照本發明之第一實施例之一種薄膜電晶體的製造流程示意圖。請參照圖1A，提供基板100，並於基板100上形成閘極102。基板100例如是玻璃基板之硬質基板(rigid substrate)，或是如塑膠基板之可撓式基板(flexible substrate)等。閘極102例如是單層或多層堆疊之導電材料，如選自由銅(Cu)、鉬(Mo)、鈦(Ti)、鋁(Al)、鎢(W)、銀(Ag)、金(Au)及其合金所組成之族群中的至少一者，且閘極102的形成方法可透過微影及蝕刻製程來圖案化導電材料而製作。此外，閘極102的製作還可以與掃描線(未繪示)或共通線(未繪示)的製作整合。1A to 1D are schematic views showing a manufacturing process of a thin film transistor according to a first embodiment of the present invention. Referring to FIG. 1A, a substrate 100 is provided, and a gate 102 is formed on the substrate 100. The substrate 100 is, for example, a rigid substrate of a glass substrate, or a flexible substrate such as a plastic substrate. The gate 102 is, for example, a single layer or a plurality of layers of a conductive material, such as selected from the group consisting of copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au). And at least one of the groups of alloys and alloys thereof, and the method of forming the gate 102 can be formed by patterning a conductive material through a lithography and etching process. In addition, the fabrication of the gate 102 can also be integrated with the fabrication of scan lines (not shown) or common lines (not shown).
接著，於基板100上依序形成閘絕緣層104、氧化物半導體材料層106以及導電層108。閘絕緣層104覆蓋閘極102。閘絕緣層104可為單層結構或多層堆疊的複合結構，且其材質例如是氮化矽、氧化矽或氮氧化矽等介電材料。氧化物半導體材料層106覆蓋閘絕緣層104。氧化物半導體材料層106的材質例如是銦鎵鋅氧化物(Indium-Gallium-Zinc Oxide,IGZO)、銦鋅氧化物(Indium-Zinc Oxide,IZO)、鎵鋅氧化物(Gallium-Zinc Oxide,GZO)、氧化鋁鋅(Aluminum-Zinc Oxide,AZO)、鋅錫氧化物(Zinc-Tin Oxide,ZTO)或銦錫氧化物(Indium-Tin Oxide,ITO)等。導電層108覆蓋氧化物半導體材料層106。導電層108可為單層結構或多層堆疊的複合結構，且其材質例如是銅(Cu)、鉬(Mo)或其合金等金屬材料。導電層108之材質可與閘極102之材質相同或不同。Next, the gate insulating layer 104, the oxide semiconductor material layer 106, and the conductive layer 108 are sequentially formed on the substrate 100. The gate insulating layer 104 covers the gate 102. The gate insulating layer 104 may be a single layer structure or a multilayer stacked composite structure, and the material thereof is, for example, a dielectric material such as tantalum nitride, hafnium oxide or tantalum oxynitride. The oxide semiconductor material layer 106 covers the gate insulating layer 104. The material of the oxide semiconductor material layer 106 is, for example, Indium-Gallium-Zinc Oxide (IGZO), Indium-Zinc Oxide (IZO), and Gallium-Zinc Oxide (GZO). ), aluminum oxide (Aluminum-Zinc Oxide, AZO), zinc tin oxide (Zinc-Tin Oxide, ZTO) or indium tin oxide (Indium-Tin Oxide, ITO). Conductive layer 108 covers oxide semiconductor material layer 106. The conductive layer 108 may be a single layer structure or a multilayer stacked composite structure, and the material thereof is, for example, a metal material such as copper (Cu), molybdenum (Mo), or an alloy thereof. The material of the conductive layer 108 may be the same as or different from the material of the gate 102.
之後，於導電層108上形成圖案化光阻層110。圖案化光阻層110包括二個第一部110a以及第二部110b，其中第二部110b連接於二第一部110a之間，且各第一部110a之厚度大於第二部110b之厚度。圖案化光阻層110之第二部110b例如是位於後續預定形成通道區之上方。在一實施例中，圖案化光阻層110係藉由階調式製程或半調式製程所形成。舉例而言，本實施例可先於導電層108上全面形成一層光阻材料(未繪示)，接著使用階調式或半調式光罩來圖案化光阻材料，以形成上述之圖案化光阻層110。雖然本實施例是以階調式製程或半調式製程為例來說明，但本發明不限於此。Thereafter, a patterned photoresist layer 110 is formed on the conductive layer 108. The patterned photoresist layer 110 includes two first portions 110a and a second portion 110b, wherein the second portion 110b is connected between the two first portions 110a, and the thickness of each of the first portions 110a is greater than the thickness of the second portion 110b. The second portion 110b of the patterned photoresist layer 110 is, for example, located above a subsequent predetermined formation channel region. In one embodiment, the patterned photoresist layer 110 is formed by a step process or a half-tone process. For example, in this embodiment, a photoresist material (not shown) may be formed on the conductive layer 108, and then the photoresist material is patterned by using a tone or halftone mask to form the patterned photoresist. Layer 110. Although the present embodiment is described by taking a step process or a half-tone process as an example, the present invention is not limited thereto.
請參照圖1B，以圖案化光阻層110為罩幕，移除未被圖案化光阻層110覆蓋之導電層108與氧化物半導體材料層106，以形成氧化物半導體通道層106'以及位於氧化物半導體通道層106'與圖案化光阻層110之間的圖案化導電層108'。具體而言，在一實施例中，移除未被圖案化光阻層110覆蓋之導電層108與氧化物半導體材料層106的方法可透過先進行第一濕式蝕刻製程，以移除未被圖案化光阻層110覆蓋之導電層108；接著，再進行第二濕式蝕刻製程，以移除未被圖案化光阻層110覆蓋之氧化物半導體材料層106。第一濕式蝕刻製程所使用之蝕刻劑與第二濕式蝕刻製程所使用之蝕刻劑不同，且分別具有不同的蝕刻選擇比。具體而言，第一濕式蝕刻製程例如是利用H2 O2 的銅酸作為蝕刻劑來移除導電層108，而第二濕式蝕刻製程例如是藉由草酸作為蝕刻劑來移除氧化物半導體材料層106。由於第一濕式蝕刻製程所使用之蝕刻劑對於導電層108與氧化物半導體材料層106具有很高的蝕刻選擇比(導電層108/氧化物半導體材料層106)，因而不易蝕刻氧化物半導體材料層106。第二濕式蝕刻製程所使用之蝕刻劑對於氧化物半導體材料層106與導電層108具有很高的蝕刻選擇比(氧化物半導體材料層106/導電層108)，因而不易蝕刻導電層108，而使製程能夠獲得良好的控制。Referring to FIG. 1B, the patterned photoresist layer 110 is used as a mask to remove the conductive layer 108 and the oxide semiconductor material layer 106 that are not covered by the patterned photoresist layer 110 to form an oxide semiconductor channel layer 106' and A patterned conductive layer 108' between the oxide semiconductor channel layer 106' and the patterned photoresist layer 110. Specifically, in an embodiment, the method of removing the conductive layer 108 and the oxide semiconductor material layer 106 not covered by the patterned photoresist layer 110 may be performed by performing a first wet etching process to remove the The conductive layer 108 is patterned by the patterned photoresist layer 110; then, a second wet etching process is performed to remove the oxide semiconductor material layer 106 that is not covered by the patterned photoresist layer 110. The etchant used in the first wet etching process is different from the etchant used in the second wet etching process, and has different etching selectivity ratios, respectively. Specifically, the first wet etching process uses, for example, copper oxide of H 2 O 2 as an etchant to remove the conductive layer 108, and the second wet etching process, for example, removes oxide by using oxalic acid as an etchant. Semiconductor material layer 106. Since the etchant used in the first wet etching process has a high etching selectivity (the conductive layer 108 / the oxide semiconductor material layer 106) for the conductive layer 108 and the oxide semiconductor material layer 106, it is difficult to etch the oxide semiconductor material. Layer 106. The etchant used in the second wet etching process has a high etching selectivity (oxide semiconductor material layer 106 / conductive layer 108) for the oxide semiconductor material layer 106 and the conductive layer 108, so that the conductive layer 108 is not easily etched. The process can be well controlled.
此外，在另一實施例中，可透過濕式蝕刻製程來移除未被圖案化光阻層110覆蓋之導電層108與氧化物半導體材料層106。也就是說，導電層108與氧化物半導體材料層106是採用相同的蝕刻劑來移除，蝕刻劑對於導電層108與氧化物半導體材料層106具有相近的蝕刻率，而蝕刻劑例如是H2 O2 與濃度大於1 wt%之含氟(F)液體的混合物，或者使用鋁酸(亦即磷酸、硝酸與醋酸的混合物)。因此，只需要使用一種蝕刻劑進行濕式蝕刻製程即可同時移除導電層108與氧化物半導體材料層106。In addition, in another embodiment, the conductive layer 108 and the oxide semiconductor material layer 106 not covered by the patterned photoresist layer 110 may be removed through a wet etching process. That is, the conductive layer 108 and the oxide semiconductor material layer 106 are removed using the same etchant, and the etchant has a similar etch rate for the conductive layer 108 and the oxide semiconductor material layer 106, and the etchant is, for example, H 2 . A mixture of O 2 with a fluorine (F) liquid having a concentration greater than 1 wt%, or an alumina acid (i.e., a mixture of phosphoric acid, nitric acid and acetic acid). Therefore, it is only necessary to perform the wet etching process using an etchant to simultaneously remove the conductive layer 108 and the oxide semiconductor material layer 106.
請參照圖1C，移除部分之圖案化光阻層110，以減少第一部110a的厚度直到第二部110b被移除，而暴露出圖案化導電層108'之一部份的上表面。在一實施例中，移除部分之圖案化光阻層110的方法包括灰化製程(ashing)。詳言之，移除光阻材料之灰化製程可以採用如氧氣電漿之乾式蝕刻的方式，使圖案化光阻層110的整體厚度降低，直到厚度較小之第二部110b被完全移除為止。由於第二部110b的厚度較薄，因此在完全移除第二部110b之後，仍會有未被完全移除之第一部110a'殘留在圖案化導電層108'上。Referring to FIG. 1C, a portion of the patterned photoresist layer 110 is removed to reduce the thickness of the first portion 110a until the second portion 110b is removed, exposing the upper surface of a portion of the patterned conductive layer 108'. In an embodiment, the method of removing portions of the patterned photoresist layer 110 includes an ashing process. In detail, the ashing process for removing the photoresist material may be performed by dry etching such as oxygen plasma to reduce the overall thickness of the patterned photoresist layer 110 until the second portion 110b having a small thickness is completely removed. until. Since the thickness of the second portion 110b is thin, after the second portion 110b is completely removed, the first portion 110a' that is not completely removed remains on the patterned conductive layer 108'.
請參照圖1D，在完全移除厚度較小之第二部110b之後，以未被移除之第一部110a'為罩幕，移除未被第一部110a'覆蓋之圖案化導電層108'，以於氧化物半導體通道層106'上形成源極112與汲極114。源極112與汲極114例如是分別形成在氧化物半導體通道層106'的兩側上。在一實施例中，移除未被第一部110a'覆蓋之圖案化導電層108'而形成源極112與汲極114的方法可以採用濕式蝕刻製程，並採用對於圖案化導電層108'與氧化物半導體通道層106'具有高蝕刻選擇比(圖案化導電層108'/氧化物半導體通道層106')的蝕刻劑，如H2 O2 的銅酸。在形成源極112與汲極114之後，移除第一部110a'，以完成本實施例之薄膜電晶體的製作。移除第一部110a'的方法例如是採用乾式去光阻法或濕式去光阻法，其中可利用氧氣電漿作為反應氣體來進行灰化製程。當然，源極112與汲極114的製作還可以與資料線(未繪示)的製作整合。Referring to FIG. 1D, after the second portion 110b having a small thickness is completely removed, the patterned conductive layer 108 not covered by the first portion 110a' is removed with the unmasked first portion 110a' as a mask. The source 112 and the drain 114 are formed on the oxide semiconductor channel layer 106'. The source 112 and the drain 114 are formed, for example, on both sides of the oxide semiconductor channel layer 106', respectively. In one embodiment, the method of removing the patterned conductive layer 108 ′ that is not covered by the first portion 110 a ′ to form the source 112 and the drain electrode 114 may employ a wet etching process and adopt a patterning conductive layer 108 ′. An etchant having a high etching selectivity (patterned conductive layer 108'/oxide semiconductor channel layer 106') with the oxide semiconductor channel layer 106', such as copper oxide of H 2 O 2 . After the source 112 and the drain 114 are formed, the first portion 110a' is removed to complete the fabrication of the thin film transistor of the present embodiment. The method of removing the first portion 110a' is, for example, a dry de-resisting method or a wet de-resisting method in which an oxygen plasma is used as a reaction gas to perform an ashing process. Of course, the fabrication of the source 112 and the drain 114 can also be integrated with the production of data lines (not shown).
圖2A至圖2E是依照本發明之第二實施例之一種薄膜電晶體的製造流程示意圖。須注意的是，在圖2A至圖2E中，和圖1A至圖1D相同的構件則使用相同的標號並省略其說明。2A to 2E are schematic views showing a manufacturing process of a thin film transistor according to a second embodiment of the present invention. It is to be noted that in FIGS. 2A to 2E, the same members as those in FIGS. 1A to 1D are denoted by the same reference numerals and the description thereof will be omitted.
請參照圖2A，提供基板100，並於基板100上形成閘極102。接著，於基板100上依序形成閘絕緣層104、氧化物半導體材料層106以及導電層108。之後，於導電層108上形成圖案化光阻層210。圖案化光阻層210包括二個第一部210a、第二部210b以及第三部210c，其中第二部210b連接於第一部210a之間，第三部210c則分別與各第一部210a連接而位於第一部210a之外側。各第一部210a之厚度例如是大於第二部210b及各第三部210c之厚度，且第二部210b之厚度實質上等於各第三部210c之厚度。具體而言，圖案化光阻層210之第二部210b例如是位於後續預定形成通道區之上方，而各第三部210c例如是位於後續預定形成源極與汲極之兩相對外側的上方。在一實施例中，圖案化光阻層210係藉由階調式製程或半調式製程所形成。Referring to FIG. 2A, a substrate 100 is provided, and a gate 102 is formed on the substrate 100. Next, the gate insulating layer 104, the oxide semiconductor material layer 106, and the conductive layer 108 are sequentially formed on the substrate 100. Thereafter, a patterned photoresist layer 210 is formed on the conductive layer 108. The patterned photoresist layer 210 includes two first portions 210a, a second portion 210b, and a third portion 210c, wherein the second portion 210b is connected between the first portions 210a, and the third portion 210c is respectively associated with the first portions 210a. Connected to the outside of the first portion 210a. The thickness of each of the first portions 210a is, for example, greater than the thickness of the second portion 210b and each of the third portions 210c, and the thickness of the second portion 210b is substantially equal to the thickness of each of the third portions 210c. Specifically, the second portion 210b of the patterned photoresist layer 210 is, for example, located above the subsequently predetermined channel region, and each of the third portions 210c is located, for example, above the opposite outer side of the predetermined source and drain. In one embodiment, the patterned photoresist layer 210 is formed by a step process or a half-tone process.
請參照圖2B，以圖案化光阻層210為罩幕，移除未被圖案化光阻層210覆蓋之導電層108，以於氧化物半導體材料層106與圖案化光阻層210之間形成圖案化導電層108'。在一實施例中，移除未被圖案化光阻層210覆蓋之導電層108的方法包括進行乾式蝕刻製程，其例如使用Cl2 與BCl3 作為反應氣體來蝕刻暴露出的導電層108，且此反應氣體對於導電層108與氧化物半導體材料層106具有很高的蝕刻選擇比(導電層108/氧化物半導體材料層106)。Referring to FIG. 2B, the patterned photoresist layer 210 is used as a mask to remove the conductive layer 108 not covered by the patterned photoresist layer 210 to form between the oxide semiconductor material layer 106 and the patterned photoresist layer 210. The conductive layer 108' is patterned. In an embodiment, the method of removing the conductive layer 108 that is not covered by the patterned photoresist layer 210 includes performing a dry etching process that etches the exposed conductive layer 108 using, for example, Cl 2 and BCl 3 as a reactive gas, and This reactive gas has a high etching selectivity (conductive layer 108 / oxide semiconductor material layer 106) for the conductive layer 108 and the oxide semiconductor material layer 106.
請參照圖2C，以圖案化光阻層210為罩幕，移除未被圖案化光阻層210覆蓋之氧化物半導體材料層106，以形成氧化物半導體通道層206。在一實施例中，移除未被覆蓋之氧化物半導體材料層106的方法包括進行濕式蝕刻製程，且例如是藉由草酸作為蝕刻劑來移除暴露出的氧化物半導體材料層106。Referring to FIG. 2C, the patterned photoresist layer 210 is used as a mask to remove the oxide semiconductor material layer 106 that is not covered by the patterned photoresist layer 210 to form the oxide semiconductor channel layer 206. In one embodiment, the method of removing the uncovered oxide semiconductor material layer 106 includes performing a wet etch process and removing the exposed oxide semiconductor material layer 106, for example, by using oxalic acid as an etchant.
特別說明的是，由於利用等向性之濕式蝕刻製程來移除暴露出的氧化物半導體材料層106，且圖案化導電層108'在濕式蝕刻製程中可作為硬罩幕，因此位於圖案化導電層108'下方的氧化物半導體通道層206會因側蝕而導致其側壁處發生底切(undercut)216，且底切216例如是發生在位於相對外側之第三部210c的下方。在此實施例中，因側蝕所導致的底切216會使得圖案化導電層108'自氧化物半導體通道層206之側壁突出。In particular, since the exposed oxide semiconductor material layer 106 is removed by an isotropic wet etching process, and the patterned conductive layer 108' can serve as a hard mask in the wet etching process, it is located in the pattern. The oxide semiconductor channel layer 206 underlying the conductive layer 108' may cause an undercut 216 at its sidewall due to undercut, and the undercut 216 occurs, for example, below the third portion 210c located on the opposite side. In this embodiment, the undercut 216 due to the undercut causes the patterned conductive layer 108' to protrude from the sidewalls of the oxide semiconductor channel layer 206.
請參照圖2D，移除部分之圖案化光阻層210，以減少第一部210a的厚度直到第二部210b與第三部210c被移除。在一實施例中，移除部分之圖案化光阻層210的方法可採用灰化製程，其例如是使用氧氣電漿之乾式蝕刻的方式，使圖案化光阻層210的整體厚度降低。由於第二部210b與第三部210c的厚度較薄，因此在完全移除第二部210b與第三部210c之後，仍會有未被完全移除之第一部210a'殘留在圖案化導電層108'上。此時，剩餘之第一部210a'會使部分的圖案化導電層108'暴露出來，且被暴露出的部分圖案化導電層108'例如是位於底切216上方。Referring to FIG. 2D, a portion of the patterned photoresist layer 210 is removed to reduce the thickness of the first portion 210a until the second portion 210b and the third portion 210c are removed. In one embodiment, the method of removing portions of the patterned photoresist layer 210 may employ an ashing process that reduces the overall thickness of the patterned photoresist layer 210, for example, by dry etching using oxygen plasma. Since the thickness of the second portion 210b and the third portion 210c is thin, after the second portion 210b and the third portion 210c are completely removed, the first portion 210a' that is not completely removed remains in the patterned conductive portion. On layer 108'. At this point, the remaining first portion 210a' exposes a portion of the patterned conductive layer 108', and the exposed portion of the patterned conductive layer 108' is, for example, over the undercut 216.
請參照圖2E，以未被移除之第一部210a'為罩幕，移除位於底切216上方且未被第一部210a'覆蓋之圖案化導電層108'，以於氧化物半導體通道層206上形成源極212與汲極214。在一實施例中，形成源極212與汲極214的方法包括進行乾式蝕刻製程，其例如使用Cl2 與BCl3 作為反應氣體來移除暴露的圖案化導電層108'。在形成源極212與汲極214之後，可以進一步移除第一部210a'，以完成本實施例之薄膜電晶體的製作。移除第一部210a'的方法例如是採用乾式去光阻法或濕式去光阻法，其中可利用氧氣電漿作為反應氣體來進行灰化製程。Referring to FIG. 2E, the patterned conductive layer 108' located above the undercut 216 and not covered by the first portion 210a' is removed with the first portion 210a' not being removed as a mask to the oxide semiconductor channel. Source 212 and drain 214 are formed on layer 206. In one embodiment, the method of forming source 212 and drain 214 includes performing a dry etch process that removes exposed patterned conductive layer 108' using, for example, Cl 2 and BCl 3 as reactive gases. After the source 212 and the drain 214 are formed, the first portion 210a' may be further removed to complete the fabrication of the thin film transistor of the present embodiment. The method of removing the first portion 210a' is, for example, a dry de-resisting method or a wet de-resisting method in which an oxygen plasma is used as a reactive gas to perform an ashing process.
在此說明的是，如圖2D及圖2E所示，第一部210a'除了暴露出通道區上的部分圖案化導電層108'外，還暴露出位於底切216上方之圖案化導電層108'的突出部。因此，在移除暴露的圖案化導電層108'之後，可以去除底切216上方之圖案化導電層108'的突出部，使得所形成之源極212與汲極214不會自氧化物半導體通道層206之側壁突出。在一實施例中，氧化物半導體通道層206例如是突出源極212與汲極214，而形成兩段式的側壁輪廓。氧化物半導體通道層206之底部突出源極212與汲極214其中之一之底部之水平距離D1約為0.1 μm至1.0 μm。It is noted that, as shown in FIGS. 2D and 2E, the first portion 210a' exposes the patterned conductive layer 108 above the undercut 216 in addition to exposing a portion of the patterned conductive layer 108' on the channel region. 'The prominent part. Thus, after the exposed patterned conductive layer 108' is removed, the protrusions of the patterned conductive layer 108' over the undercut 216 can be removed such that the source 212 and drain 214 are formed from the oxide semiconductor channel. The sidewalls of layer 206 protrude. In one embodiment, the oxide semiconductor channel layer 206 is, for example, protruding from the source 212 and the drain 214 to form a two-stage sidewall profile. The bottom of the oxide semiconductor channel layer 206 protrudes from the source 212 and the bottom of one of the drains 214 by a horizontal distance D1 of about 0.1 μm to 1.0 μm.
此外，由於位於底切216上方之圖案化導電層108'突出部是利用圖案化光阻層210之剩餘的第一部210a'作為罩幕而移除，因此在形成圖案化光阻層210時，還可以根據氧化物半導體通道層206之底切216的程度來設計位於兩相對外側之第三部210c的佈局，以使得位於底切216上方之圖案化導電層108'可以被暴露出來而有利於後續之移除，如圖2D所示。In addition, since the patterned conductive layer 108' protrusion above the undercut 216 is removed by using the remaining first portion 210a' of the patterned photoresist layer 210 as a mask, when the patterned photoresist layer 210 is formed The layout of the third portions 210c on opposite outer sides can also be designed according to the extent of the undercut 216 of the oxide semiconductor channel layer 206 such that the patterned conductive layer 108' over the undercut 216 can be exposed to be advantageous. Subsequent removal, as shown in Figure 2D.
圖3A至圖3F是依照本發明之第三實施例之一種薄膜電晶體的製造流程示意圖。須注意的是，在圖3A至圖3F中，和圖2A至圖2E相同的構件則使用相同的標號並省略其說明。在第三實施例之薄膜電晶體的製造方法與第二實施例所述之方法類似，然而兩者之間的差異主要是在於：導電層的配置結構以及形成圖案化導電層之方式。3A to 3F are schematic views showing a manufacturing process of a thin film transistor according to a third embodiment of the present invention. It is to be noted that in FIGS. 3A to 3F, the same members as those in FIGS. 2A to 2E are denoted by the same reference numerals and the description thereof will be omitted. The method of manufacturing the thin film transistor of the third embodiment is similar to that of the second embodiment, but the difference between the two is mainly in the arrangement structure of the conductive layer and the manner in which the patterned conductive layer is formed.
請參照圖3A，提供基板100，並於基板100上形成閘極102。接著，於基板100上依序形成閘絕緣層104、氧化物半導體材料層106以及導電層308。在一實施例中，導電層308包括底導電層以及頂導電層，且底導電層以及頂導電層例如是具有不同的蝕刻選擇性。詳言之，導電層308的形成方法例如是於氧化物半導體材料層106上依序形成第一導電層308a、第二導電層308b以及第三導電層308c，其中第一導電層308a例如是作為底導電層，而其上之第二導電層308b與第三導電層308c例如是作為頂導電層。第一導電層308a、第二導電層308b、第三導電層308c之材料分別可選自由銅(Cu)、鉬(Mo)、鈦(Ti)、鋁(Al)、鎢(W)、銀(Ag)、金(Au)及其合金所組成之族群中的至少一者。舉例而言，第一導電層308a的材質例如是鈦，第二導電層308b的材質例如是鋁，第三導電層308c的材質例如是鉬，而形成多層堆疊的複合金屬結構。Referring to FIG. 3A, a substrate 100 is provided, and a gate 102 is formed on the substrate 100. Next, a gate insulating layer 104, an oxide semiconductor material layer 106, and a conductive layer 308 are sequentially formed on the substrate 100. In an embodiment, the conductive layer 308 includes a bottom conductive layer and a top conductive layer, and the bottom conductive layer and the top conductive layer have, for example, different etch selectivity. In detail, the forming method of the conductive layer 308 is, for example, sequentially forming the first conductive layer 308a, the second conductive layer 308b, and the third conductive layer 308c on the oxide semiconductor material layer 106, wherein the first conductive layer 308a is, for example, The bottom conductive layer, and the second conductive layer 308b and the third conductive layer 308c thereon are, for example, a top conductive layer. The materials of the first conductive layer 308a, the second conductive layer 308b, and the third conductive layer 308c may be selected from copper (Cu), molybdenum (Mo), titanium (Ti), aluminum (Al), tungsten (W), and silver ( At least one of the group consisting of Ag), gold (Au), and alloys thereof. For example, the material of the first conductive layer 308a is, for example, titanium, the material of the second conductive layer 308b is, for example, aluminum, and the material of the third conductive layer 308c is, for example, molybdenum, to form a multi-layer stacked composite metal structure.
之後，於導電層308上形成圖案化光阻層210。圖案化光阻層210包括二個第一部210a、第二部210b以及第三部210c，其中第二部210b連接於第一部210a之間，第三部210c則分別與各第一部210a連接而位於第一部210a之外側。各第一部210a之厚度例如是大於第二部210b及各第三部210c之厚度，且第二部210b之厚度實質上等於各第三部210c之厚度。Thereafter, a patterned photoresist layer 210 is formed on the conductive layer 308. The patterned photoresist layer 210 includes two first portions 210a, a second portion 210b, and a third portion 210c, wherein the second portion 210b is connected between the first portions 210a, and the third portion 210c is respectively associated with the first portions 210a. Connected to the outside of the first portion 210a. The thickness of each of the first portions 210a is, for example, greater than the thickness of the second portion 210b and each of the third portions 210c, and the thickness of the second portion 210b is substantially equal to the thickness of each of the third portions 210c.
請參照圖3B，以圖案化光阻層210為罩幕，移除未被圖案化光阻層210覆蓋之頂導電層(即第三導電層308c與第二導電層308b)，以於第一導電層308a與圖案化光阻層210之間形成圖案化第三導電層308c'與圖案化第二導電層308b'。在一實施例中，移除暴露出的第三導電層308c與第二導電層308b的方法包括進行第一濕式蝕刻製程，其例如是藉由鋁酸(亦即磷酸、硝酸與醋酸的混合物)作為蝕刻劑。Referring to FIG. 3B, the patterned photoresist layer 210 is used as a mask to remove the top conductive layer (ie, the third conductive layer 308c and the second conductive layer 308b) that is not covered by the patterned photoresist layer 210. A patterned third conductive layer 308c' and a patterned second conductive layer 308b' are formed between the conductive layer 308a and the patterned photoresist layer 210. In one embodiment, the method of removing the exposed third conductive layer 308c and the second conductive layer 308b includes performing a first wet etching process, for example, by using aluminoic acid (ie, a mixture of phosphoric acid, nitric acid, and acetic acid). ) as an etchant.
請參照圖3C，以圖案化光阻層210為罩幕，移除未被圖案化光阻層210覆蓋之底導電層(即第一導電層308a)，以於氧化物半導體材料層106與圖案化第二導電層308b'之間形成圖案化第一導電層308a'，因而形成如圖案化導電層308'之疊層。在一實施例中，移除暴露出的第一導電層308a的方法包括進行乾式蝕刻製程，其例如使用Cl2 與BCl3 作為反應氣體。Referring to FIG. 3C, the patterned photoresist layer 210 is used as a mask to remove the bottom conductive layer (ie, the first conductive layer 308a) not covered by the patterned photoresist layer 210, and the oxide semiconductor material layer 106 and the pattern. A patterned first conductive layer 308a' is formed between the second conductive layers 308b', thereby forming a stack such as the patterned conductive layer 308'. In one embodiment, the method of removing the exposed first conductive layer 308a includes performing a dry etch process using, for example, Cl 2 and BCl 3 as the reactive gas.
請參照圖3D，以圖案化光阻層210為罩幕，移除未被圖案化光阻層210覆蓋之氧化物半導體材料層106，以形成氧化物半導體通道層306。在一實施例中，移除未被覆蓋之氧化物半導體材料層106的方法包括進行第二濕式蝕刻製程，且例如是藉由草酸作為蝕刻劑。Referring to FIG. 3D, the patterned photoresist layer 210 is used as a mask to remove the oxide semiconductor material layer 106 that is not covered by the patterned photoresist layer 210 to form the oxide semiconductor channel layer 306. In one embodiment, the method of removing the uncovered oxide semiconductor material layer 106 includes performing a second wet etch process, and is performed, for example, by oxalic acid as an etchant.
類似地，由於利用等向性之濕式蝕刻製程來移除暴露出的氧化物半導體材料層106，且圖案化導電層308'在濕式蝕刻製程中可作為硬罩幕，因此由側蝕所導致的底切316會發生在氧化物半導體通道層306之側壁處，且底切316例如是位於相對外側之第三部210c的下方。如此一來，圖案化導電層308'例如會自氧化物半導體通道層306之側壁突出。Similarly, since the exposed oxide semiconductor material layer 106 is removed by an isotropic wet etching process, and the patterned conductive layer 308' can serve as a hard mask in the wet etching process, The resulting undercut 316 may occur at the sidewalls of the oxide semiconductor channel layer 306, and the undercut 316 is, for example, below the third portion 210c on the opposite outer side. As such, the patterned conductive layer 308' may protrude from the sidewall of the oxide semiconductor channel layer 306, for example.
請參照圖3E，移除部分之圖案化光阻層210，以減少第一部210a的厚度直到第二部210b與第三部210c被移除，而暴露出圖案化第三導電層308c'之部份上表面。此時，未被完全移除之第一部210a'會殘留在圖案化導電層308'上，而暴露出位於後續預定形成通道區上方之部分圖案化導電層308'以及位於底切316上方之圖案化導電層308'的突出部。在一實施例中，移除部分之圖案化光阻層210的方法可採用灰化製程，其例如是使用氧氣電漿之乾式蝕刻的方式，使圖案化光阻層210的整體厚度降低。Referring to FIG. 3E, a portion of the patterned photoresist layer 210 is removed to reduce the thickness of the first portion 210a until the second portion 210b and the third portion 210c are removed, thereby exposing the patterned third conductive layer 308c'. Part of the upper surface. At this time, the first portion 210a' that is not completely removed may remain on the patterned conductive layer 308', exposing a portion of the patterned conductive layer 308' located above the subsequent predetermined formation channel region and above the undercut 316. The protrusion of the conductive layer 308' is patterned. In one embodiment, the method of removing portions of the patterned photoresist layer 210 may employ an ashing process that reduces the overall thickness of the patterned photoresist layer 210, for example, by dry etching using oxygen plasma.
請參照圖3F，以未被移除之第一部210a'為罩幕，移除位於底切316上方且未被第一部210a'覆蓋之圖案化導電層308'，以於氧化物半導體通道層306上形成源極312與汲極314。在一實施例中，形成源極312與汲極314的方法包括進行乾式蝕刻製程，其例如使用Cl2 與BCl3 作為反應氣體來移除暴露的圖案化導電層308'。此外，在形成源極312與汲極314之後，可以進一步移除第一部210a'，以完成本實施例之薄膜電晶體的製作。Referring to FIG. 3F, the first portion 210a' that has not been removed is used as a mask to remove the patterned conductive layer 308' located above the undercut 316 and not covered by the first portion 210a' for the oxide semiconductor channel. A source 312 and a drain 314 are formed on layer 306. In one embodiment, the method of forming source 312 and drain 314 includes performing a dry etch process that removes exposed patterned conductive layer 308' using, for example, Cl 2 and BCl 3 as reactive gases. In addition, after the source 312 and the drain 314 are formed, the first portion 210a' may be further removed to complete the fabrication of the thin film transistor of the present embodiment.
在本實施例中，藉由使第三部210c下方之部分圖案化導電層308'暴露出來，因此在進行乾式蝕刻製程之後，位於底切316上方之圖案化導電層308'的突出部即可被去除，且氧化物半導體通道層306例如是突出源極312與汲極314。此外，圖案化光阻層210的佈局同樣地也可以根據氧化物半導體通道層306之底切316的程度來設計位於兩相對外側之第三部210c的範圍。In this embodiment, by exposing a portion of the patterned conductive layer 308' under the third portion 210c, the protrusion of the patterned conductive layer 308' located above the undercut 316 can be performed after the dry etching process. The oxide semiconductor channel layer 306 is removed, for example, by the source 312 and the drain 314. In addition, the layout of the patterned photoresist layer 210 can also be designed in the range of the third portion 210c on the opposite sides according to the extent of the undercut 316 of the oxide semiconductor channel layer 306.
值得一提的是，由於圖案化第一導電層308a'、圖案化第二導電層308b'以及圖案化第三導電層308c'例如是具有不同的蝕刻選擇性，因此在進行乾式蝕刻製程來移除未被第一部210a'覆蓋之圖案化導電層308'時，圖案化第一導電層308a'、圖案化第二導電層308b'以及圖案化第三導電層308c'被移除的程度也會有所差異。此外，在一實施例中，圖案化第一導電層308a'與圖案化第二導電層308b'所構成的堆疊結構例如是具有實質上連續的側壁，其可以為垂直側壁或傾斜側壁(tapered sidewall)。因此，氧化物半導體通道層306以及源極312與汲極314會在兩相對外側處形成三段式的側壁輪廓，且源極312與汲極314會在通道區處形成兩段式的側壁輪廓。It is worth mentioning that since the patterned first conductive layer 308a', the patterned second conductive layer 308b', and the patterned third conductive layer 308c' have different etching selectivity, for example, a dry etching process is performed to move In addition to the patterned conductive layer 308' not covered by the first portion 210a', the degree to which the patterned first conductive layer 308a', the patterned second conductive layer 308b', and the patterned third conductive layer 308c' are removed is also There will be differences. Moreover, in an embodiment, the stacked structure of the patterned first conductive layer 308a' and the patterned second conductive layer 308b' has, for example, a substantially continuous sidewall, which may be a vertical sidewall or a slanted sidewall (tapered sidewall) ). Therefore, the oxide semiconductor channel layer 306 and the source 312 and the drain 314 form a three-stage sidewall profile at opposite outer sides, and the source 312 and the drain 314 form a two-stage sidewall profile at the channel region. .
舉例而言，如圖3F之區域A的局部放大示意圖所示，氧化物半導體通道層306之底部突出源極312與汲極314其中之一之底部(亦即圖案化第一導電層308a'之底部)之水平距離D2約為0.1 μm至1 μm，且圖案化第一導電層308a'之底部突出圖案化第二導電層308b'之底部之水平距離D3約為0.1 μm至1.5 μm。另一方面，如圖3F之區域B的局部放大示意圖所示，在通道區中，圖案化第一導電層308a'之底部突出圖案化第二導電層308b'之底部之水平距離D4約為0.1 μm至1.5 μm。For example, as shown in a partially enlarged schematic view of region A of FIG. 3F, the bottom of the oxide semiconductor channel layer 306 protrudes from the bottom of one of the source 312 and the drain 314 (ie, the patterned first conductive layer 308a'). The horizontal distance D2 of the bottom portion is about 0.1 μm to 1 μm, and the horizontal distance D3 of the bottom of the patterned first conductive layer 308a' protruding from the bottom of the patterned second conductive layer 308b' is about 0.1 μm to 1.5 μm. On the other hand, as shown in the partially enlarged schematic view of the region B of FIG. 3F, in the channel region, the horizontal distance D4 of the bottom of the patterned first conductive layer 308a' protruding from the bottom of the patterned second conductive layer 308b' is about 0.1. Mm to 1.5 μm.
在本實施例中，在以濕式蝕刻製程形成氧化物半導體通道層306之後，進行乾式蝕刻來移除位於底切316上方且未被第一部210a'覆蓋之圖案化導電層308'。如此一來，即可消除氧化物半導體通道層306中因側蝕所導致的底切現象。In the present embodiment, after the oxide semiconductor channel layer 306 is formed by a wet etching process, dry etching is performed to remove the patterned conductive layer 308' located above the undercut 316 and not covered by the first portion 210a'. As a result, undercut due to side etching in the oxide semiconductor channel layer 306 can be eliminated.
圖4A至圖4C是依照本發明之第四實施例之一種主動元件陣列基板的製造流程示意圖。須注意的是，圖4A至圖4C所示之製造流程是接續圖3C後的步驟，且在圖4A至圖4C中，和圖3A至圖3F相同的構件則使用相同的標號並省略其說明。在第四實施例之薄膜電晶體的製造方法與第三實施例所述之方法類似，然而兩者之間的差異主要是在於：形成圖案化導電層及形成氧化物半導體通道層之方式。4A to 4C are schematic diagrams showing a manufacturing process of an active device array substrate in accordance with a fourth embodiment of the present invention. It should be noted that the manufacturing flow shown in FIG. 4A to FIG. 4C is the step subsequent to FIG. 3C, and in FIGS. 4A to 4C, the same members as those in FIGS. 3A to 3F are denoted by the same reference numerals and the description thereof is omitted. . The method of manufacturing the thin film transistor of the fourth embodiment is similar to that of the third embodiment, but the difference between the two is mainly in the manner of forming the patterned conductive layer and forming the oxide semiconductor channel layer.
請參照圖4A，在形成圖案化導電層308'之疊層後，移除部分之圖案化光阻層210，以減少第一部210a的厚度直到第二部210b與第三部210c被移除。此時，未被完全移除之第一部210a'會殘留在圖案化導電層308'上，而暴露出位於後續預定形成通道區上方之部分圖案化導電層308'以及位於底切316上方之圖案化導電層308'的突出部。在一實施例中，移除部分之圖案化光阻層210的方法可採用灰化製程，其例如是使用氧氣電漿之乾式蝕刻的方式，使圖案化光阻層210的整體厚度降低。Referring to FIG. 4A, after forming the lamination of the patterned conductive layer 308', a portion of the patterned photoresist layer 210 is removed to reduce the thickness of the first portion 210a until the second portion 210b and the third portion 210c are removed. . At this time, the first portion 210a' that is not completely removed may remain on the patterned conductive layer 308', exposing a portion of the patterned conductive layer 308' located above the subsequent predetermined formation channel region and above the undercut 316. The protrusion of the conductive layer 308' is patterned. In one embodiment, the method of removing portions of the patterned photoresist layer 210 may employ an ashing process that reduces the overall thickness of the patterned photoresist layer 210, for example, by dry etching using oxygen plasma.
請參照圖4B，以未被移除之第一部210a'為罩幕，移除未被第一部210a'覆蓋之頂導電層(亦即圖案化第三導電層308c'與圖案化第二導電層308b')以及部分氧化物半導體材料層106，而底導電層(亦即圖案化第一導電層308a')例如是不會被移除。因此，在圖案化第一導電層308a'與第一部210a'之間形成圖案化第三導電層408c、圖案化第二導電層408b，且在圖案化第一導電層308a'與閘絕緣層104之間形成氧化物半導體通道層406。在一實施例中，移除未被覆蓋之圖案化第三導電層308c'、圖案化第二導電層308b'以及部分氧化物半導體材料層106的方法包括進行濕式蝕刻製程，且例如是藉由鋁酸(亦即磷酸、硝酸與醋酸的混合物)作為蝕刻劑，且此蝕刻劑對圖案化第一導電層308a'之材質的蝕刻率低。Referring to FIG. 4B, the top portion 210a' that is not removed is used as a mask to remove the top conductive layer (ie, the patterned third conductive layer 308c' and the patterned second layer that are not covered by the first portion 210a'. The conductive layer 308b') and a portion of the oxide semiconductor material layer 106, while the bottom conductive layer (ie, the patterned first conductive layer 308a'), for example, is not removed. Therefore, a patterned third conductive layer 408c, a patterned second conductive layer 408b are formed between the patterned first conductive layer 308a' and the first portion 210a', and the first conductive layer 308a' and the gate insulating layer are patterned. An oxide semiconductor channel layer 406 is formed between 104. In an embodiment, the method of removing the uncovered patterned third conductive layer 308c', the patterned second conductive layer 308b', and the portion of the oxide semiconductor material layer 106 includes performing a wet etching process, and for example, borrowing An alumina acid (i.e., a mixture of phosphoric acid, nitric acid, and acetic acid) is used as an etchant, and the etchant has a low etching rate for the material of the patterned first conductive layer 308a'.
類似地，由於採用等向性之濕式蝕刻製程來形成圖案化第三導電層408c、圖案化第二導電層408b及氧化物半導體通道層406，且此濕式蝕刻製程不易移除圖案化第一導電層308a'，因此在氧化物半導體通道層406之側壁處會發生因側蝕所導致的底切416。換言之，圖案化第一導電層308a'例如是自圖案化第三導電層408c、圖案化第二導電層408b以及氧化物半導體通道層406之側壁突出。Similarly, the patterned third conductive layer 408c, the patterned second conductive layer 408b, and the oxide semiconductor channel layer 406 are formed by an isotropic wet etching process, and the wet etching process is difficult to remove the patterning A conductive layer 308a', and thus an undercut 416 due to undercutting may occur at the sidewalls of the oxide semiconductor channel layer 406. In other words, the patterned first conductive layer 308a' protrudes, for example, from the sidewalls of the patterned third conductive layer 408c, the patterned second conductive layer 408b, and the oxide semiconductor channel layer 406.
請參照圖4C，以未被移除之第一部210a'為罩幕，移除未被第一部210a'覆蓋之圖案化第一導電層308a'以及位於底切416上方之圖案化第一導電層308a'，以形成圖案化第一導電層408a。圖案化第一導電層408a、圖案化第二導電層408b以及圖案化第三導電層408c例如是構成圖案化導電層408之疊層，以於氧化物半導體通道層406上分別作為源極412與汲極414。在一實施例中，上述移除未被第一部210a'覆蓋之圖案化第一導電層308a'以及位於底切416上方之圖案化第一導電層308a'的方法包括進行乾式蝕刻製程，其例如使用Cl2 與BCl3 作為反應氣體來移除暴露的圖案化第一導電層308a'。此外，在形成源極412與汲極414之後，可以進一步移除第一部210a'，即完成本實施例之薄膜電晶體的製作。Referring to FIG. 4C, the first portion 210a' that has not been removed is used as a mask to remove the patterned first conductive layer 308a' not covered by the first portion 210a' and the patterned first layer above the undercut 416. Conductive layer 308a' to form patterned first conductive layer 408a. The patterned first conductive layer 408a, the patterned second conductive layer 408b, and the patterned third conductive layer 408c are, for example, a stack constituting the patterned conductive layer 408 to serve as the source 412 on the oxide semiconductor channel layer 406, respectively. Bungee 414. In one embodiment, the method of removing the patterned first conductive layer 308a' that is not covered by the first portion 210a' and the patterned first conductive layer 308a' above the undercut 416 includes performing a dry etching process. for example, Cl 2 and BCl 3 as a reactive gas to remove the first patterned conductive layer 308a is exposed. ' In addition, after the source 412 and the drain 414 are formed, the first portion 210a' may be further removed, that is, the fabrication of the thin film transistor of the present embodiment is completed.
承上述，圖案化第三導電層408c與圖案化第二導電層408b所構成的堆疊結構例如是具有實質上連續的側壁，其可以為垂直側壁或傾斜側壁。此外，氧化物半導體通道層406以及源極412與汲極414例如是會在兩相對外側處形成三段式的側壁輪廓，且源極412與汲極414例如是會在通道區處形成兩段式的側壁輪廓。類似圖3F之區域A的局部放大示意圖，本實施例之氧化物半導體通道層406之底部突出源極412與汲極414其中之一之底部(亦即圖案化第一導電層408a之底部)之水平距離約為0.1 μm至1 μm，且圖案化第一導電層408a之底部突出圖案化第二導電層408b之底部之水平距離約為0.1 μm至1.5 μm。In view of the above, the stacked structure of the patterned third conductive layer 408c and the patterned second conductive layer 408b has, for example, a substantially continuous sidewall, which may be a vertical sidewall or a sloped sidewall. In addition, the oxide semiconductor channel layer 406 and the source 412 and the drain 414 may form a three-stage sidewall profile at opposite outer sides, for example, and the source 412 and the drain 414 may form two segments at the channel region, for example. Side wall profile. A portion of the oxide semiconductor channel layer 406 of the present embodiment protrudes from the bottom of one of the source 412 and the drain 414 (that is, the bottom of the patterned first conductive layer 408a). The horizontal distance is about 0.1 μm to 1 μm, and the bottom of the patterned first conductive layer 408a protrudes from the bottom of the patterned second conductive layer 408b by a horizontal distance of about 0.1 μm to 1.5 μm.
在本實施例中，先利用濕式蝕刻製程來同時移除未被第一部210a'覆蓋之圖案化第三導電層308c'、圖案化第二導電層308b'以及部分氧化物半導體材料層106，而留下圖案化第一導電層308a'；之後才藉由乾式蝕刻製程來移除未被第一部210a'覆蓋之圖案化第一導電層308a'。如此一來，即可消除由等向性濕式蝕刻製程對氧化物半導體通道層406所造成的底切現象。In this embodiment, the wet etching process is used to simultaneously remove the patterned third conductive layer 308c', the patterned second conductive layer 308b', and a portion of the oxide semiconductor material layer 106 that are not covered by the first portion 210a'. The patterned first conductive layer 308a' is left behind; the patterned first conductive layer 308a' not covered by the first portion 210a' is removed by a dry etching process. In this way, the undercut caused by the isotropic wet etching process to the oxide semiconductor channel layer 406 can be eliminated.
特別說明的是，在第三及第四實施例中，是以形成第一導電層308a作為底導電層、形成第二導電層308b與第三導電層308c作為頂導電層之三層堆疊的複合結構為例來進行說明，但本發明並不限於此。當然，在其他實施例中，底導電層例如是由多層金屬層所組成，且頂導電層也例如是由單層或多層的金屬層所組成，所屬技術領域中具有通常知識者當可依前述實施例知其變化及應用，故於此不再贅述。Specifically, in the third and fourth embodiments, the composite of the first conductive layer 308a as the bottom conductive layer and the second conductive layer 308b and the third conductive layer 308c as the top conductive layer is formed. The structure is described as an example, but the present invention is not limited thereto. Of course, in other embodiments, the bottom conductive layer is composed of, for example, a plurality of metal layers, and the top conductive layer is also composed of, for example, a single layer or a plurality of metal layers, and those having ordinary knowledge in the art can The embodiments are susceptible to variations and applications, and thus will not be described again.
而且，須注意的是，以上所述之薄膜電晶體的製造方法主要是用來詳細說明形成氧化物半導體通道層、源極與汲極之流程，以使熟習此項技術者能夠據以實施，但並非用以限定本發明之範圍。至於薄膜電晶體的其他構件或佈局，均可依所屬技術領域中具有通常知識者所知的技術適當調整，而不限於上述實施例所述。Moreover, it should be noted that the method for fabricating the thin film transistor described above is mainly used to describe in detail the process of forming the oxide semiconductor channel layer, the source and the drain, so that those skilled in the art can implement it. However, it is not intended to limit the scope of the invention. As for other members or layouts of the thin film transistor, it can be appropriately adjusted according to a technique known to those skilled in the art, and is not limited to the above embodiment.
綜上所述，本發明之薄膜電晶體及其製造方法至少具有下列優點：In summary, the thin film transistor of the present invention and the method of manufacturing the same have at least the following advantages:
1. 上述實施例之薄膜電晶體及其製造方法藉由具有多個厚度之圖案化光阻層來形成氧化物半導體通道層以及源極與汲極，因而利用此減光罩製程可有助於減少製程步驟與成本。1. The thin film transistor of the above embodiment and the method of fabricating the same, the oxide semiconductor channel layer and the source and the drain are formed by a patterned photoresist layer having a plurality of thicknesses, so that the use of the mask process can contribute to Reduce process steps and costs.
2. 上述實施例之薄膜電晶體及其製造方法可以避免氧化物半導體通道層受損，並改善因側蝕所導致的底切現象，因而使製程能夠獲得良好的控制。2. The thin film transistor of the above embodiment and the method of manufacturing the same can prevent the oxide semiconductor channel layer from being damaged and improve the undercut caused by the side etching, thereby enabling the process to be well controlled.
3. 上述實施例之薄膜電晶體及其製造方法能夠與現有的製程整合，並且廣泛應用在形成多種不同佈局之薄膜電晶體。3. The thin film transistor of the above embodiment and its manufacturing method can be integrated with existing processes, and are widely used in forming a plurality of thin film transistors of different layouts.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100．．．基板100. . . Substrate
102．．．閘極102. . . Gate
104．．．閘絕緣層104. . . Brake insulation
106．．．氧化物半導體材料層106. . . Oxide semiconductor material layer
106'、206、306、406．．．氧化物半導體通道層106', 206, 306, 406. . . Oxide semiconductor channel layer
108、308．．．導電層108, 308. . . Conductive layer
108'、308'、408．．．圖案化導電層108', 308', 408. . . Patterned conductive layer
110、210．．．圖案化光阻層110, 210. . . Patterned photoresist layer
110a、110a'、210a、210a'．．．第一部110a, 110a', 210a, 210a'. . . First
110b、210b．．．第二部110b, 210b. . . Second part
112、212、312、412．．．源極112, 212, 312, 412. . . Source
114、214、314、414‧‧‧汲極114, 214, 314, 414‧‧‧ bungee
210c‧‧‧第三部210c‧‧‧ third
216、316、416‧‧‧底切216, 316, 416‧‧ ‧ undercut
308a‧‧‧第一導電層308a‧‧‧First conductive layer
308a'、408a‧‧‧圖案化第一導電層308a', 408a‧‧‧ patterned first conductive layer
308b‧‧‧第二導電層308b‧‧‧Second conductive layer
308b'、408b‧‧‧圖案化第二導電層308b', 408b‧‧‧ patterned second conductive layer
308c‧‧‧第三導電層308c‧‧‧ third conductive layer
308c'、408c‧‧‧圖案化第三導電層308c', 408c‧‧‧ patterned third conductive layer
A、B‧‧‧區域A, B‧‧‧ area
D1、D2、D3、D4‧‧‧水平距離D1, D2, D3, D4‧‧‧ horizontal distance
圖1A至圖1D是依照本發明之第一實施例之一種薄膜電晶體的製造流程示意圖。1A to 1D are schematic views showing a manufacturing process of a thin film transistor according to a first embodiment of the present invention.
圖2A至圖2E是依照本發明之第二實施例之一種薄膜電晶體的製造流程示意圖。2A to 2E are schematic views showing a manufacturing process of a thin film transistor according to a second embodiment of the present invention.
圖3A至圖3F是依照本發明之第三實施例之一種薄膜電晶體的製造流程示意圖。3A to 3F are schematic views showing a manufacturing process of a thin film transistor according to a third embodiment of the present invention.
圖4A至圖4C是依照本發明之第四實施例之一種主動元件陣列基板的製造流程示意圖。4A to 4C are schematic diagrams showing a manufacturing process of an active device array substrate in accordance with a fourth embodiment of the present invention.
100．．．基板100. . . Substrate
102．．．閘極102. . . Gate
104．．．閘絕緣層104. . . Brake insulation
206．．．氧化物半導體通道層206. . . Oxide semiconductor channel layer
212．．．源極212. . . Source
214．．．汲極214. . . Bungee
D1．．．水平距離D1. . . Horizontal distance
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