TWI416639B - 形成ｃ４連接於積體電路晶片和所致元件的方法 - Google Patents

形成ｃ４連接於積體電路晶片和所致元件的方法 Download PDF

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Publication number
TWI416639B
TWI416639B TW096113388A TW96113388A TWI416639B TW I416639 B TWI416639 B TW I416639B TW 096113388 A TW096113388 A TW 096113388A TW 96113388 A TW96113388 A TW 96113388A TW I416639 B TWI416639 B TW I416639B
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Taiwan
Prior art keywords
layer
wafer
metallization
capture pad
insulating layer
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TW096113388A
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English (en)
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TW200807590A (en
Inventor
Timothy H Daubenspeck
Mukta G Farooq
Jeffrey P Gambino
Christopher D Muzzy
Kevin S Petrarca
Wolfgang Sauter
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Ultratech Inc
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Publication of TW200807590A publication Critical patent/TW200807590A/zh
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Publication of TWI416639B publication Critical patent/TWI416639B/zh

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Description

形成C4連接於積體電路晶片和所致元件的方法
本發明係關於一種微電子電路晶片與晶片承載基板間的互連，而且特別關於一種區域陣列覆晶互連技術，也就是熟知的可控塌陷晶片連接(controlled collapse chip connection；C4)技術。
區域陣列覆晶互連或者C4技術，將焊料凸塊(solder bump)區域陣列放置於經製造的微電子電路晶片或積體電路晶片的頂部，而且藉由上下翻轉晶片及對準晶片與承載基板上的墊，隨後回流焊料以連接焊料凸塊，而使得晶片經由焊料凸塊連接晶片承載基板。因晶片正面朝下放置於承載板上而稱為覆晶接合。C4技術的優點在於：1)晶片的整體區域可受到焊料凸塊覆蓋，使得晶片上具有最多數量的輸入/輸出點；2)晶片上的電路之互連距離較短，因此允許較快訊號反應以及較低的電感；3)功率與熱量分佈較平均；以及4)降低同時切換雜訊。
焊料凸塊是沉積在圖案化焊料可濕層狀結構上，也就是熟知的球限冶金術(Ball Limiting Metallurgy；BLM)。球限冶金術(BLM)界定接點金 屬墊於晶片的頂表面上，而且晶片經由焊料成為可濕的，並且也限制焊料橫向流動至金屬墊。當焊料凸塊在圖案化BLM上回流以形成球後，晶片係連結至晶片載板上的焊料可濕層之匹配足印(matching footprint)。BLM通常是多層結構，包含一下黏著層、一中間反應阻障層以及一可濕性上層。下層提供對下方基板的黏著，且此層亦可作為擴散/反應阻障層，以防止矽晶圓與其線路層相互影響。此層是薄的，大約是數百至數千埃間的厚度，而且通常經由濺鍍製程或蒸鍍製程沉積在晶圓鈍化層上，鈍化層為如聚亞醯胺類的聚合物，或者氧化物，亦或氮化物。黏著層材料的範例可為鉻、鈦鎢合金(TiW)、鉭、鎢、鈦、氮化鈦(TiN)、氮化鉭(TaN)、鋯(Zr)或這些材料的組合。
BLM的中間層是一反應阻障層，其可藉由融熔焊料為可焊接的，但其反應緩慢到允許多數次回流循環(reflow cycle)而不會完全消耗掉。此層的材料可為鉻、鉻銅(CrCu)、銅、鋁、鎳或包含一或多種這些材料的金屬，而且在利用物理氣相沉積(PVD)、濺鍍或蒸鍍沉積後，通常具有數千埃至數微米範圍的厚度。
BLM的上層是可濕性焊料，其提供簡易焊料 可濕性以及與焊料快速反應。銅(Cu)是一般使用的材料範例，而且其厚度是在數百埃至數千埃間範圍。並且，在一些情形中，藉由濺鍍製程、電鍍製程或非電鍍製程沉積後，銅的厚度可高達到微米的程度。
一些熟知的技術可製造焊料凸塊於BLM結構的頂部，例如蒸鍍製程、電鍍製程、模板印刷製程(stencil printing)、膠膏網印製程(paste screening)以及融熔焊料注入製程。目前形成C4焊料凸塊的方法是透過厚(100um)乾燥光阻薄膜遮罩，將焊料電鍍至BLM結構上。在光阻剝離的步驟後，以電鍍焊料凸塊充當遮罩，使用濕蝕刻將BLM圖案化。這技術描述於名稱為「低成本晶圓凸塊(Low-cost wafer bumping)」,IBM J.Res.& Dev.,Vol.49,No.4/5,July/September 2005的論文中，而且其亦描述注入模鑄式焊料(Injection Molded Solder)技術，本說明書較佳方法將焊料沉積於BLM結構或晶圓內之晶片上的捕捉墊。「低成本晶圓凸塊(Low cost wafer bumping)」的論文於此併入作為參考。
目前C4焊料凸塊的問題之一在於，由環境觀點來看焊料含鉛是不受歡迎的。因為焊料僅包含 錫而且將擴散至具有薄銅層的晶片中，所以使用無鉛焊料需要較厚的銅層。此製程的明顯缺點包含BLM層邊緣的最終配置之尺寸控制，而且由於濕蝕刻的關係，傾向在每個邊緣底切銅的最頂層大約10微米，降低C4結構的黏著截面以及造成可靠度風險。目前C4焊料凸塊方法的另一個問題是，以晶片頂部的鋁接點作為BLM/C4結構的著陸墊，以增加結構拉伸測試的可靠度。鋁墊是昂貴的，而且與晶片的銅金屬化製程不相容。
本發明的目的是提供一種BLM/C4的改良結構，其不需要鋁墊且不會降低BLM與C4焊料凸塊間結合的整體性以及可靠度。
本發明的另一個目的是提供一種具有無鉛C4焊料之改良的BLM/C4結構。
本發明的再一目的是提供一種改良的BLM/C4結構，使得BLM結構是包含在晶片內，且做為C4的捕捉墊(capture pad)。
本發明的附加目的是提供一種改良的BLM/C4結構，其與晶片金屬化製程相容，而且不需要濕蝕刻製程。
在BLM/C4結構的兩個具體實施例中，本發明的目的是提供亦作為晶片最終金屬化的BLM結構。
前述及其他目的可藉由形成BLM結構作為於鈍化層中或下方的捕捉墊，並且延伸至或者與晶片金屬化最終層共存，而不需要***鋁層與也不需濕蝕刻。捕捉墊的形成係使用鑲嵌(damascene)技術在鈍化層中或其下方產生凹洞，然後使用BLM填充凹洞。詳細地以具體實施例說明，鈍化層沉積在晶片上後，接著進行蝕刻，且較佳地透過光阻遮罩以氟電漿等向蝕刻，藉由雙鑲嵌技術在鈍化層產生較低較小的凹洞，以及較高較大的凹洞。在此實施例中，較低凹洞是一溝槽，其作為一通孔(via)且延伸至晶片中的最終金屬層。沉積BLM在凹洞內，以形成至少一通孔以及C4凸塊的捕捉墊。在其他實施例中，捕捉墊形成於晶片的最終絕緣層中，且作為捕捉墊以及晶片的金屬化最終層的雙重功能。在其他實施例中，較低凹洞可以溝槽的形式出現，而且作為到晶片次終金屬化的通孔，並且可藉由雙或者單鑲嵌技術而形成。
為更瞭解本發明及其實施例，首先描述圖1-4的習知技術。圖1(習知技術)顯示來自晶圓(未顯示)的晶片10的上部。晶片10包含一上絕緣層11，於此為二氧化矽，包含銅金屬化最終層級或層12。沉積於上絕緣層11與銅層12上的是鈍化層13A,13B,13C與13D。鈍化層13A,13B與13C形成有一通孔14。鋁(Al)墊15是包含在鈍化層13A-13D中，且經由通孔14延伸至銅層12。其他大型通孔14形成於鈍化層13D的上部且延伸至鋁層。此處，鈍化層13A-13D分別是氮化矽、氧化矽、氮化矽以及聚亞醯胺(polyimide)。
如圖2(習知技術)所示，球限金屬化(BLM)形成有三層，包含例如鈦鎢合金(TiW)的底部黏著層17。此黏著層的其他材料是鉻、鉭、鎢、鈦、氮化鈦、氮化鉭、鋯或者這些材料的組合。中間層18是一反應阻障層，可由融熔焊料為可焊接的，但反應緩慢到允許多次回流循環而不會完全消耗。此層的材料是鉻、鉻銅、銅、鋁、鎳或任何包含一種或多種這些材料的金屬，而且使用物理氣相沉積法(PVD)、濺鍍法或蒸鍍法沉積後，此層通常具有數千埃至施數微米間的厚度範圍。BLM的頂部層19是可濕性焊料，這允許簡易焊料可濕 性而且與焊料快速反應的特性。鉻銅是一般使用的材料，而且在電鍍法沉積後，該層厚度係在數百至數千埃的範圍內，在一些情形中，該層厚度可高達微米等級。BLM層與通孔14的表面共形，且黏著層17接觸鋁墊15。圖案化在BLM層19上之光阻層，以形成一開口(未顯示)對準鋁墊15與最終銅金屬層12。焊料21，此處是鉛錫，係電鍍在開口內。
參閱圖3(習知技術)所示，光阻20經由灰化(ashing)剝除或移除，而且鎢鈦合金層17受到濕蝕刻或者電蝕刻至聚亞醯胺的鈍化層13D為止。如圖3(習知技術)以及圖4(習知技術)所示，習知製程的缺點在於移除BLM 16，在沉積的焊料21下方會有大約10微米的底切。BLM利用濕蝕刻移除，且分別如圖所示在焊料21和焊料凸塊22的下方底切。底切影響BLM 16與焊料凸塊22間結合的可靠度。在圖4(習知技術)中，焊料已經回流以形成C4凸塊22。
現在根據本發明之一較佳具體實施例，圖5顯示來自晶圓(未顯示)的晶片30的上部，其具有一絕緣層31(於此為氧化矽)與一金屬化最終層32(於此為銅)。於絕緣層31與最終金屬化32的 上表面的是鈍化層(在此為33)，其包含四層，如33A,33B,33C與33D，各層分別為氮化矽(SiN)、二氧化矽(SiO2 )、氮化矽(SiN)及一厚度。藉由圖案光阻遮罩34與雙鑲嵌製程，使用氟基電漿等向性蝕刻鈍化層33A-33D，以形成圖6顯示的結構，由於藉由等向性蝕刻劑在所有方向均勻蝕刻，光阻層34與下方厚鈍化層33D由於厚度的關係，實質上以相同量橫向蝕刻與縱向蝕刻，因此完整蝕刻鈍化層33D以產生一凹洞35。一系列的溝槽36形成於較薄的鈍化層33A-33C中，延伸至金屬化層32(於此為銅)。選替地，鈍化層33A-33D可非等向性蝕刻以形成連續的較低凹洞90而不是溝槽36，如圖10A所示。
包含沉積的BLM材料之捕捉墊37係顯示在圖7，於此為一範例說明，捕捉墊37由底部至頂部的材料為厚度大約50nm的氮化鉭(TaN)、厚度大約150nm的鎢鈦合金、厚度大約400nm的鈦以及厚度大約500nm的銅。銅是相對地厚，且作為防止錫擴散至晶片的阻障層，並且可針對目的修改厚度與組成。此鑲嵌製程免除濕蝕刻製程與所導致的底切，因此尺寸控制與可靠度不再是問題。在本實施例中，藉由化學/機械研磨製程平坦化捕捉墊37與共同存在的頂部表面鈍化層33D， 然後沉積一焊料金屬，較佳地係由藉由轉移製程由玻璃基板轉移無鉛焊料金屬置捕捉墊37，且將焊料金屬回流為C4凸塊38，如圖8所顯示。轉移製程詳細描述於「低成本晶圓凸塊(low-cost wafer bumping)」論文中，其內容併至說明書的先前技術作為參考。
如圖9所示，圖5-8之本發明較佳具體實施例之改良如下。在較佳的無鉛焊料轉移至捕捉墊37之前，沉積薄鈍化層39(於此為氮化矽(SiN))以及較厚鈍化層40(於此為聚亞醯胺(polyimide))在厚鈍化層33D上。形成鈍化層39與40後，焊料材料轉移至捕捉墊37，而且回流以形成C4凸塊38，如圖10顯示。
根據本發明之另一個具體實施例，如圖11所示，晶片50形成有包含捕捉墊52的上絕緣層51。捕捉墊52除了捕捉墊的功能外，也作為最終金屬化層級或層。在初沉積絕緣層51時利用雙鑲嵌製程，經由光阻遮罩(未顯示)非等向性或方向性蝕刻，以形成溝槽54於上絕緣層51內，以及形成一上凹洞55。溝槽54與上凹洞55以BLM材料填充以形成捕捉墊52。溝槽54可作為到金屬化次終層(second to last level)56的通孔，雖然溝槽 54顯示於絕緣層51的較低部份中，仍可藉由較低部份的凹洞加以取代，如圖12A所顯示，且通孔(未顯示)可形成於遠離捕捉墊的地方。在絕緣層51與捕捉墊52表面實施化學/機械研磨製程後，沉積一鈍化層57，於此包含層57A、57B、57C與57D。較佳地層57A為氮化矽層，57B為氧化矽層、57C為氮化矽層與57D為聚亞醯胺。較大通孔58是形成於鈍化層內，且對準以及延伸至捕捉墊，如圖11顯示。於本實施例中，轉移製程用於轉移焊料59至連接到抵達捕捉墊52之通孔58，而且焊料59較佳是無鉛焊料。焊料59是回流以形成圖12的焊料凸塊C4結構60。
圖13顯示本發明之另一具體實施例，其為圖11與圖12實施例的改良。晶片70包含上絕緣層71，捕捉墊72將形成於其中。相似於圖11與圖12的具體實施例，捕捉墊72也具有晶片的金屬化最終層(於此為Cu)的功能。在此功能中，捕捉墊72係連接到絕緣層71A中的金屬化下一層級或層73。使用雙鑲嵌製程，非等向性乾蝕刻上絕緣層71以於此層中形成凹洞，如圖13所示，其包含5個溝槽72A-72E。一或多個溝槽也作為到金屬化下一層級73的通孔。溝槽的側壁以較佳地是氮化鉭(TaN)的黏著層74作襯墊，並且以較佳 地是鉭與銅的金屬75填充。在填充這些溝槽後，使用第2次鑲嵌製程，在溝槽72A-72E上方的上絕緣層71非等向性乾蝕刻一凹洞(未顯示)。首先從頂部至底部使用50nm氮化鉭(TaN)、150nm氮化鉭與400nm氮化鉭的BLM材料77作襯墊後，凹洞以銅金屬78填充。然後，在銅填充凹洞78以及鄰近的絕緣層71的表面進行化學機械研磨。以銅填充凹洞當作最終的金屬化層，應該具有至少0.5微米厚，且可能具有5微米的厚度，而較佳厚度為2微米。鈍化層80在此從底部至頂部包含氮化矽80A、二氧化氮80B、氮化矽80C與聚亞醯胺80D，其沉積在經研磨的表面而且形成有到銅填充凹洞或捕捉墊72的一較大通孔81。類似圖11與圖12的具體實施例，焊料82較佳是無鉛焊料，經由通孔81沉積至捕捉墊72。數種沉積技術可用於沉積焊料82，描述於「低成本晶圓凸塊(Low-cost wafer bumping)」的轉移製程是較佳沉積方法。焊料82回流以形成圖14的焊料凸塊82或C4結構。
如同在較低部分鈍化層33中形成溝槽的修改，一連續溝槽(未顯示)藉由非等向性蝕刻形成，並且以包含銅的BLM金屬化90填充，如同圖10A所顯示。連接到晶片的金屬化最終層之通 孔並非捕捉墊37的一部分，而且遠離捕捉墊以連接金屬化的最終層(未顯示)。相同地，圖12的溝槽係加以修改以藉由非等向性蝕刻形成連續較低凹洞在晶片的上絕緣層51中，並且以包含銅的BLM金屬化91填充，如圖12A所示。再者，連接到晶片的金屬化次終層之通孔並非具有焊料凸塊60的捕捉墊55之一部分，而且遠離捕捉墊55以連接金屬化次終層(未顯示)。
本發明已藉由實施例加以描述，熟習此技藝者應該瞭解本發明可在所附申請專利範圍的精神與範圍內的改良情形下實施。因此，本發明實施例不限定於已描述與已說明的明確形式，而用於包含所有改良不偏離本發明的精神與範疇。
10‧‧‧晶片
11‧‧‧上絕緣層
12‧‧‧銅金屬層
13A‧‧‧鈍化層
13B‧‧‧鈍化層
13C‧‧‧鈍化層
13D‧‧‧鈍化層
14‧‧‧通孔
15‧‧‧鋁墊
16‧‧‧BLM
17‧‧‧底部黏著層
18‧‧‧中間層
19‧‧‧頂部層
20‧‧‧光阻
21‧‧‧焊料
22‧‧‧焊料凸塊
30‧‧‧晶片
31‧‧‧絕緣層
32‧‧‧金屬化最終層
33‧‧‧鈍化層
34‧‧‧圖案光阻遮罩
33A‧‧‧鈍化層
33B‧‧‧鈍化層
33C‧‧‧鈍化層
33D‧‧‧鈍化層
35‧‧‧凹洞
36‧‧‧溝槽
37‧‧‧捕捉墊
38‧‧‧C4凸塊
39‧‧‧薄鈍化層
40‧‧‧厚鈍化層
50‧‧‧晶片
51‧‧‧上絕緣層
52‧‧‧捕捉墊
54‧‧‧溝槽
55‧‧‧上凹洞
57A‧‧‧氮化矽層
57B‧‧‧氧化矽層
57C‧‧‧氮化矽層
57D‧‧‧聚亞醯胺
58‧‧‧通孔
59‧‧‧焊料
60‧‧‧焊料凸塊
70‧‧‧晶片
71‧‧‧上絕緣層
71A‧‧‧絕緣層
72‧‧‧捕捉墊
73‧‧‧金屬層
74‧‧‧黏著層
75‧‧‧金屬
72A-72E‧‧‧溝槽
77‧‧‧BLM材料
78‧‧‧銅金屬
80‧‧‧鈍化層
80A‧‧‧氮化矽
80B‧‧‧二氧化氮
80C‧‧‧氮化矽
80D‧‧‧聚亞醯胺
81‧‧‧通孔
82‧‧‧焊料凸塊
83‧‧‧通孔
90‧‧‧凹洞
91‧‧‧BLM金屬化
為使本發明之較佳具體實施例之目的、方向及優點之敘述更加詳盡與完備，可參照下列描述並配合圖式說明：
圖1(習知技術)是顯示部分的積體電路晶片之截面圖，係具有最終金屬層於晶片中，以及具有鋁金屬層的數個鈍化層，鋁金屬設置於鈍化層中及上方，並且經由通孔連接最終金屬層，上鈍 化層形成有到鋁金屬層的一開口通孔。
圖2(習知技術)是顯示包含圖1的部分積體電路晶片之截面圖，而且顯示BLM層在鈍化層上以及顯影光阻圖案在BLM層上，且描繪出於最終金屬與鋁金屬上且以焊料填充的區域。
圖3(習知技術)是顯示包含圖2的部分積體電路晶片之截面圖，而且顯示濕蝕刻製程移除或者剝除光阻以及光阻下方之BLM結構。
圖4(習知技術)是顯示包含圖3的部分積體電路晶片之截面圖，而且顯示回流至焊料凸塊結構的焊料。
圖5是顯示本發明較佳具體實施例的部分積體電路晶片之截面圖，其具有最終金屬層被鈍化層覆蓋在晶片內，以及顯影的光阻圖案係藉由鑲嵌法形成溝槽在鈍化層內，以形成凸柱到最終金屬層。
圖6是本發明較佳具體實施例之截面圖，其包含圖5的下部結構，以及顯示移除凸柱與外部溝槽邊緣上的上鈍化層，及藉由鑲嵌法在溝槽上 方形成一凹洞。
圖7是本發明較佳具體實施例之截面圖，其包含圖6移除光阻後的結構，以及顯示藉由雙鑲嵌法以BLM材料填充溝槽與凹洞，以及BLM之上表面或補捉墊與在頂鈍化層表面之平坦化層。
圖8是本發明較佳具體實施例之截面圖，其包含圖7的結構，而且顯示焊料設置於捕捉墊上並回流以形成一焊料凸塊。
圖9是本發明第二具體實施例之截面圖，其包含圖7的捕捉墊部分，而且顯示一薄絕緣層係由捕捉墊表面上的鈍化層與鄰近絕緣層所覆蓋，且兩者皆圖案化以形成連接到BLM的一開口通孔。
圖10是本發明第二具體實施例之截面圖，其包含圖9的結構，而且顯示設置於圖9通孔中之回流焊料。
圖11是本發明第三具體實施例的截面圖，其中捕捉墊形成於晶片內，且亦作為具有溝槽或到次終金屬化之通孔的金屬化最終層。
圖12是本發明第三具體實施例的截面圖，其包含圖11的結構，而且顯示設置於圖11通孔內的回流焊料。
圖13是本發明第四具體實施例的截面圖，其中捕捉墊形成於晶片內，並藉由單鑲嵌法形成溝槽結構並以BLM材料填充，接著沉積一襯層，而後形成上凹洞且以BLM材料填充，溝槽結構作為到晶片內的金屬化次終層的通孔。
圖14是本發明第四具體實施例的截面圖，其包含圖13的結構，而且顯示設置於圖13通孔內的回流焊料。
圖10A是本發明的圖10的改良結構的截面圖，其藉由BLM材料的連續層取代底部凹洞的溝槽。
圖12A是本發明的圖12的改良結構的截面圖，其藉由BLM材料的連續層取代底部凹洞內的溝槽。
30‧‧‧晶片
31‧‧‧絕緣層
32‧‧‧最終金屬層
33‧‧‧鈍化層
33A‧‧‧氮化矽(SiN)
33B‧‧‧二氧化矽(SiO2 )
33C‧‧‧氮化矽(SiN)
38‧‧‧焊料凸塊

Claims (41)

  1. 一種製造一積體電路晶片的方法，其中該晶片藉由該晶片表面的不含鉛(Pb-free)之區域陣列焊料凸塊實體地且電性地連接一載板封裝之一基板，該方法包含下列步驟：製造一電路，其包含位於該晶片內金屬化；在該晶片的頂部表面沉積具一層厚層及三層位於該厚層下之較薄層的絕緣層；在沉積該絕緣層後使用一雙鑲嵌製程，以在該絕緣層而蝕刻出一較低較小的凹洞及一供捕捉墊用之較高較大的凹洞，該較低較小的凹洞對準且延伸至位於該晶片內的金屬化；持續使用該雙鑲嵌製程，以球限金屬化填充該較低及較高之凹洞，以形成供焊料凸塊用的一捕捉墊以及一通至位於該晶片內之金屬化之通孔(via)；沉積不含鉛之焊料在該捕捉墊上；以及迴流該焊料以形成一焊料凸塊。
  2. 如申請專利範圍第1項所述之方法，其中該經沉積之絕緣層是一鈍化層，且該捕捉墊形成於該鈍化層內且該通孔延伸至該晶片內該金屬化之最終層。
  3. 如申請專利範圍第1項所述之方法，其中該經沉積之絕緣層是該晶片的最頂層，且該捕捉墊形成於該絕緣層內且該通孔延伸到該晶片內該金屬化的次終層，且作為一捕捉墊與該晶片內該金屬化之最終層兩者。
  4. 如申請專利範圍第1項之方法，其中該鈍化層係受到等向性蝕刻，以致於完全移除該厚層以形成該凹洞，且該三層較薄層僅部分側向蝕刻以形成多個溝槽。
  5. 如申請專利範圍第1項之方法，其中該最終金屬化層包含銅，且該球限金屬化的上部包含銅。
  6. 如申請專利範圍第1項之方法，其中該鈍化層為約1.5微米厚。
  7. 如申請專利範圍第1項之方法，其中該焊料的沉積係藉由轉移該捕捉墊大小的一焊料量至該捕捉墊。
  8. 如申請專利範圍第1項之方法，其中該絕緣層與該球限金屬化或該捕捉墊的上表面係受到化學/機械研磨以將該兩個表面平坦化。
  9. 如申請專利範圍第2項之方法，其中該球限金屬化包含約50nm的氮化鉭(TaN)、約150nm的鎢鈦合金(TiW)、約400nm的鈦(Ti)以及約500nm的銅(Cu)，該銅作為防止該不含鉛之焊料金屬化到達該晶片的障壁。
  10. 如申請專利範圍第2項之方法，其中在形成該捕捉墊之後且該焊料轉移至該捕捉墊之前，沉積一額外鈍化層於該絕緣層上。
  11. 如申請專利範圍第3項之方法，其中該最終金屬化層及捕捉墊係在沉積該絕緣層前形成。
  12. 一種製造一積體電路晶片的方法，其中該晶片藉由該晶片表面的區域陣列焊料凸塊實體地且電性地連 接一載板封裝之一基板，該方法包含下列步驟：製造該晶片內的該電路，其具有一最終金屬化層或捕捉墊形成於該晶片頂部或表面的一絕緣層內，該絕緣層包含一層厚層及位於該厚層下之三層較薄層；沉積一鈍化層在該絕緣層與該最終金屬化層或捕捉墊上；使用一雙鑲嵌製程等向蝕刻該絕緣層，以形成與溝槽對準且延伸至該最終金屬化層的凹洞；沉積焊料在該捕捉墊上且與該鈍化層之側壁直接實質接觸；以及迴流該焊料以形成一焊料凸塊。
  13. 一種積體電路晶片，其中該晶片藉由該晶片表面的區域陣列焊料凸塊實體地且電性地連接一載板封裝之一基板，包含：一積體電路晶片，包含於該晶片內金屬化；一在該晶片的上部絕緣層，其具一層厚層及於該厚層之下的三層較薄層；一捕捉墊，包含一位於該絕緣層內供不含鉛之焊料凸塊用之球限金屬化，且是直接連接該晶片中的一金屬化層，該球限金屬化包括一足以作為該不含鉛之焊料進入該晶片之擴散障壁的厚上部銅(Cu)層；以及一位於該捕捉墊上的不含鉛之焊料凸塊。
  14. 如申請專利範圍第13項之積體電路晶片，其中該絕緣層是一鈍化層，且該捕捉墊位於該鈍化層內。
  15. 如申請專利範圍第13項之積體電路晶片，其中該絕緣層是該晶片的最後絕緣層，且該捕捉墊位於該絕緣層內並作為捕捉墊與該晶片的金屬化最終層的雙重功用。
  16. 如申請專利範圍第15項之積體電路晶片，其中該捕捉墊包含至少一通孔，且該通孔連接該金屬化之次終層。
  17. 如申請專利範圍第13項之積體電路晶片，其中該絕緣層是位於該晶片頂部上的該鈍化層。
  18. 如申請專利範圍第15項之積體電路晶片，其中該捕捉墊位於該晶片的該最後絕緣層內，且該焊料凸塊是與該鈍化層之側壁直接實質地接觸。
  19. 如申請專利範圍第17項之積體電路晶片，其中該焊料凸塊係與該鈍化層之側壁直接實質地接觸。
  20. 如申請專利範圍第13項之積體電路晶片，其中該球限金屬化包括一介於至少0.5微米及5微米厚之範圍的厚上部銅(Cu)層，該銅層係足以作為防止該不含鉛之焊料進入該晶片的擴散障壁。
  21. 一種形成一積體電路晶片的方法，其中該晶片被適應為藉由該晶片表面的之區域陣列焊料凸塊實體地且電性地連接一載板封裝之一基板，該方法包含下列步驟：製造一電路，其包含於該晶片內金屬化；沉積一絕緣層在該晶片的頂部表面； 使用一鑲嵌程序蝕刻該絕緣層，沉積一上部包含銅之多層球限金屬化以形成一捕捉墊及一至該晶片中之金屬化的通孔，以及平坦化該捕捉墊及該同延絕緣層，其中該蝕刻步驟包含使用一經圖案化之光阻遮罩，遮罩該絕緣層並使用電漿將其蝕刻，以於該絕緣層中產生一較低凹洞一與該較低凹洞對準之較高部凹洞，該較低凹洞對準及延伸至該晶片中之金屬化，其中該較高凹洞比該較低凹洞大；沉積不含鉛之焊料於該捕捉墊上；及迴流該焊料以形成一焊料凸塊。
  22. 如申請專利範圍第21項之方法，其中該沉積一絕緣層於該晶片之上表面的步驟包含，將一層厚層及於該厚層下之三層較薄層沉積於該晶片之上表面上。
  23. 如申請專利範圍第21項的方法，其中該經沉積的絕緣層為一鈍化層，且該捕捉墊係形成於該鈍化層中，且該通孔延伸至該晶片中之金屬化的最終層。
  24. 如申請專利範圍第21項的方法，其中該經沉積的絕緣層為該晶片之頂層，且該捕捉墊係形成於該絕緣層中，且該通孔延伸至該晶片中之金屬化的次終層並作為捕捉墊及該晶片中之金屬化最終層的雙重功能。
  25. 如申請專利範圍第24項之方法，包含等向蝕刻該鈍化層以致於完全移除該厚層以形成該凹洞，而該三 層較薄層僅被部分側向蝕刻以形成多個溝槽。
  26. 如申請專利範圍第24項之方法，其中該最終金屬化層包含銅，且該球限金屬化之上部包含銅。
  27. 如申請專利範圍第24項之方法，其中該鈍化層為約1.5微米厚。
  28. 如申請專利範圍第21項之方法，其中該沉積不含鉛之焊料的步驟包含轉移該捕捉墊大小的一不含鉛之焊料量至該捕捉墊。
  29. 如申請專利範圍第21項之方法，其中該平坦化步驟包含化學/機械研磨。
  30. 如申請專利範圍第22項之方法，其中該球限金屬化包含約50nm的氮化鉭(TaN)、約150nm的鎢鈦合金(TiW)、約400nm的鈦(Ti)以及約500nm的銅(Cu)，該銅作為防止該不含鉛之焊料金屬化到達該晶片的障壁。
  31. 如申請專利範圍第22項之方法，其中於該不含鉛之焊料被轉移至該捕捉墊前，該額外之鈍化層被沉積於該絕緣層，並具有一通孔至該捕捉墊。
  32. 如申請專利範圍第23項之方法，包含於沉積該鈍化層前，形成該最終金屬化層。
  33. 一種積體電路晶片，其中該晶片藉由該晶片表面的之區域陣列焊料凸塊實體地且電性地連接至一載板封裝之一基板，包含一積體電路晶片，其包括於該晶片中金屬化； 一包括一多層球限金屬化的捕捉墊，其係供一焊料凸塊設置於絕緣層並直接連接至該晶片中之一金屬化層；以及一不含鉛之焊料凸塊設置於該捕捉墊上，該捕捉墊具有與該焊料墊相接觸之一上部，以及一與該金屬化層相接觸之較低部，其中該上部之長度比該較低部大。
  34. 如申請專利範圍第33項之積體電路晶片，其中該絕緣層為一鈍化層且該捕捉墊係位於該鈍化層中。
  35. 如申請專利範圍第33項之積體電路晶片，其中該絕緣層為該晶片之最終絕緣層，且該捕捉墊係位於該絕緣層中，並作為捕捉墊及該晶片之金屬化的最終層之雙重功用。
  36. 如申請專利範圍第33項之積體電路晶片，其中該絕緣層包含一層厚層及於該厚層下之三層較薄層。
  37. 如申請專利範圍第35項之積體電路晶片，其中該捕捉墊包含至少一通孔，且該通孔係連接至該金屬化之次終層。
  38. 如申請專利範圍第33項之積體電路晶片，其中絕緣層係該晶片之頂部的鈍化層。
  39. 如申請專利範圍第35項之積體電路晶片，其中該捕捉墊係於該晶片之最終絕緣層中，且該焊料凸塊係與該鈍化層之側壁直接實質接觸。
  40. 如申請專利範圍第38項之方法，其中該焊料凸塊係 與該鈍化層之側壁直接實質接觸。
  41. 如申請專利範圍第33項之積體電路晶片，其中該球限金屬化包括一介於至少0.5微米至5微米厚之範圍內的厚上部銅(Cu)層，且足以作為防止該不含鉛之焊料進入該晶片中之擴散障壁。
TW096113388A 2006-04-26 2007-04-16 形成ｃ４連接於積體電路晶片和所致元件的方法 TWI416639B (zh)

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WO2007127816A2 (en) 2007-11-08
EP2020023A2 (en) 2009-02-04
EP2020023A4 (en) 2012-09-19
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