TWI415197B - 用於無鉛及少鉛之可控制坍塌晶片連接焊塊的無底切球限金屬製程 - Google Patents

用於無鉛及少鉛之可控制坍塌晶片連接焊塊的無底切球限金屬製程 Download PDF

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TWI415197B
TWI415197B TW097104629A TW97104629A TWI415197B TW I415197 B TWI415197 B TW I415197B TW 097104629 A TW097104629 A TW 097104629A TW 97104629 A TW97104629 A TW 97104629A TW I415197 B TWI415197 B TW I415197B
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Taiwan
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layer
forming
conductive material
barrier
metal
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TW097104629A
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TW200901336A (en
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Timothy H Daubenspeck
Jeffrey P Gambino
Christopher D Muzzy
Wolfgang Sauter
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Ibm
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Publication of TW200901336A publication Critical patent/TW200901336A/zh
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Description

用於無鉛及少鉛之可控制坍塌晶片連接焊塊的無底切球限金屬製程
本發明係有關一種半導體結構及其之製造方法。詳言之，本發明係有關一種包括有金屬閘極和高k值閘極介電質的多層閘極堆疊，該閘極堆疊可作為互補金氧半導體(complementary metal oxide semiconductor,CMOS)裝置的元件使用。本發明此多層閘極堆疊具有較可靠之較低的電荷捕陷和閘極漏電流劣變。本發明也係關於使用能與現今CMOS技術互補之處理步驟來製造這類多層閘極堆疊的方法。
聚矽是標準CMOS元件的標準材料，同時業界也持續開發以聚矽閘極來製造CMOS元件的技術，並將其廣泛用在半導體產業中。使用聚矽閘極的優點之一為這類矽系閘極可承受高溫。但是，使用聚矽閘極也有一些缺點。例如，因為聚耗盡效應(poly－depletion effect)和相對高的電子層電阻，使得經常用在CMOS裝置中的聚矽閘極，漸漸變成通道長度在0.1微米或以下之晶片效能的閘極因素。聚矽閘極的另一項問題是聚矽閘極中的摻質(例如，碳)可輕易地穿過薄閘極介電質而擴散，導致元件效能被進一步劣變。
為了避免上述聚矽閘極的相關問題，有人建議以單一金屬來取代聚矽閘極。雖然已有人提出這類技術，但高k值(即，介電常數大於4.0)層上的單一金屬，有兩項關於可靠性的重要議題需要加以考量。與一閘極堆疊(其包括一金屬閘極和一高k值閘極介電質)相關的可靠性議題為電荷捕陷所誘發的閥值電位(Vt)變動。在這類內含金屬之閘極堆中的另一項可靠性議題為長時間電壓迫下所出現的閘極漏電流劣變。
電荷捕陷和閘極漏電流劣變兩者均會衝擊元件的長期穩定性及必需將其降低的需求，方能在CMOS技術中實施高k值/金屬閘極堆疊。
綜觀以上，亟需提供一種可有效地降低電荷捕陷和閘極漏電流劣變之閘極堆疊(其包括有一位在一高k介電質上的金屬閘極)。
申請人意外地發現在一高k值閘極堆疊中，一種氮化金屬閘極其金屬與氮之間(例如，Ti/N)的組成比例明顯影響閘極堆疊之可靠性特徵(即，電荷捕陷和閘極漏電流劣變)。對於金屬氮比例低於1.1之氮化金屬閘極來說，其可明顯改善高k值閘極堆疊的可靠性。
特別是，本發明提供一具有低電荷捕陷和閘極漏電流劣變之多層閘極堆疊。「低電荷捕陷」一詞在此係指在施加約8.5兆伏特1000秒時，其閥值電位(Vt)小於或等於50.0毫伏特之一半導體元件。「低閘極漏電流」一詞在此係指不會隨著電位應力而劣變的閘極電流，亦即，δ Jg (t)/Jg (0)小於或等於1.0。
一般來說，本發明提供一多層閘極堆疊，其自底部到頂部包括有：一金屬含氮層，位在一高k閘極介電質之一表面上，該金屬含氮層內的金屬與氮之組成比例小於1.1；及一含矽導體，直接位在該金屬含氮層之一表面上。
該金屬含氮層之金屬係選自週期表中第IVB、VB、VIB或VIIB族元素。一般來說，該金屬含氮層為TiN。
在本發明某些實施方式中，有一交界層直接位在該高k值閘極介電質下方。「高k值」閘極介電質是指介電常數在4.0以上的介電材料。「交界層(interfacial layer)」在本文中代表包含至少一半導體原子(例如，矽和氧)的絕緣層材料。SiO2 、SiON為可用在本發明中的不同類型的交界層。
上述的多層閘極堆疊可用來作為一CMOS結構的組件。詳言之，本發明提供一種半導體結構，包含：一半導體結構；和至少一圖案化的多層閘極堆疊，位在該半導體結構之一表面上，其中該至少一圖案化的多層閘極堆疊包含，從底部到頂部：一金屬含氮層，位在一高k閘極介電質之一表面上，該金屬含氮層內的金屬與氮之組成比例小於1.1；及一含矽導體，直接位在該金屬含氮層之一表面上。
在本發明某些實施方式中，一交界層係直接位在該半導體結構之一表面上的高k閘極介電質下方。在本發明另一實施方式中，一矽化物接點是直接位在該含矽導體頂部。在本發明另一實施方式中，該含矽導體為n－型摻雜。在本發明另一實施方式中，該含矽導體為p－型摻雜。本發明較佳是使用p－型摻雜。
除了提供多層閘極堆疊作為CMOS裝置的元件外，本發明還提供此多層閘極堆疊的製造方法。一般來說，本發明方法與現行CMOS製程相容，且包含：在一高k閘極介電質之一表面上形成一金屬含氮層，該金屬含氮層內的金屬與氮之組成比例小於1.1；及直接在該金屬含氮層之一表面上形成一含矽導體。
在本發明某些實施方式中，該高k閘極介電質是直接位在一交界層之一表面上。在本發明另一實施方式中，該高k閘極介電質是直接位在一半導體基板之一表面上。在本發明另一實施方式中，至少該金屬含氮層與含矽導體是以微影及蝕刻加以圖案化。在本發明另一實施方式中，該圖案化堆疊包括至少該金屬含氮層與含矽導體，以作為CMOS裝置的元件。在此實施方式中，可利用傳統可自我對齊的矽化製程在該含矽導體頂部形成一矽化金屬接點。
以下將參照詳係說明和附圖來解釋本發明，其可提供一具有低電荷捕陷和閘極漏電流劣變之多層閘極堆疊，該層閘極堆疊包含至少一金屬閘極和一高k閘極介電質。本發明圖示僅作為闡述本發明參考之用，因此並未以等比例方式製作。
在以下說明中，為能充分了解本發明，因此揭示了許多特定細節，例如特定結構、組件、材料、尺寸、處理步驟和技術。但是，習知技藝人士也能了解可在沒有這些細節情況下實施本發明。在其他情況下，本說明則未納入一些習知的處理步驟或結構細節。
須知，在此當諸如一層、區域或基板的元件被指稱為在另一元件之「上(on)」或「上方(over)」時，其可直接位在該元件之上(directly on)或是其中尚有其他元件存在。相反的，當一元件被指稱為直接位在另一元件之「上(directly on)」或「上方(directly over)」時，係指其中並沒有其他元件存在。須知，在此當一元件被指稱為被「連接(connected to)」或「耦接(coupled to)」至另一元件時，其可直接連接或耦接至另一元件或是其中尚有其他元件存在。相反的，當一元件被指稱為被「直接連接(directly connected to)」或「直接耦接(directly coupled to)」至另一元件時，表示其中沒有其他元件存在。
如上述，本發明提供一多層閘極堆疊，其包括至少一金屬閘極和一高k閘極介電質，且具有低電荷捕陷和閘極漏電流劣變。「低電荷捕陷(low charging trapping)」一詞在此係指在施加每平方公分約8.5兆伏特1000秒時，其閥值電位(Vt)的變化小於或等於50.0毫伏特之一半導體元件。「低閘極漏電流(low gate leakage)」一詞在此係指不會隨著電位應力而劣變的閘極電流，亦即，δ Jg (t)/Jg (0)小於或等於1.0。
發明人意外地發現在一金屬氮化物閘極中，諸如Ti/N之類的金屬和氮的組成比，會明顯影響高k閘極堆疊的可靠性特性，即電荷捕陷和閘極漏電流。當金屬/氮間的比值低於1.1時，可明顯改善高k閘極堆疊的可靠性。特別是，本發明提供一多層閘極堆疊，其自底部到頂部包括：一金屬含氮層，位在一高k閘極介電質之一表面上，該金屬含氮層內的金屬與氮之組成比例小於1.1；及一含矽導體，直接位在該金屬含氮層之一表面上。
該金屬含氮層之金屬係選自週期表中第IVB、VB、VIB或VIIB族元素。一般來說，該金屬含氮層為TiN。
在本發明某些實施方式中，有一交界層(interfacial layer)直接位在該高k值閘極介電質下方。「高k值」閘極介電質是指介電常數(相對於真空來說)在4.0以上的介電材料。「交界層」在本文中代表包含至少一半導體原子(例如，矽和氧)的絕緣層材料。SiO2 、SiON為可用在本發明中的不同類型的交界層。
上述的多層閘極堆疊可用來作為一CMOS結構的元件。詳言之，本發明提供一種半導體結構，包含：一半導體結構；和至少一圖案化的多層閘極堆疊，位在該半導體結構之一表面上，其中該至少一圖案化的多層閘極堆疊包含，從底部到頂部：一金屬含氮層，位在一高k閘極介電質之一表面上，該金屬含氮層內的金屬與氮之組成比例小於1.1；及一含矽導體，直接位在該金屬含氮層之一表面上。
以下將詳細說明本發明的這些和其他特點。請參照第1－5圖，其示出本發明用來在半導體基板表面上形成CMOS元件(即，FET)之處理步驟。第1圖示出一最初的膜層堆疊結構，包括位在一半導體基板10表面上之一可有可無(但較佳是含有)的交界層12，及位在該可有可無的交界層12上的一高k值閘極介電質14。雖然第1圖示出此膜層堆疊結構，但本發明也涵蓋一種可直接在半導體基板10表面上生成高k值閘極介電質14的膜層堆疊結構。
可用來實施本發明的半導體基板10包含(但不限於)以下任一種半導體材料：Si、Ge、SiGe、SiC、SiGeC、Ga、GaAs、InAs、InP、及所有其他由IV/IV、III/V或II/VI化合物所形成的半導體。半導體基板10也包含例如Si/SiGe或絕緣層上覆半導體(如，絕緣層上覆矽(SOI)或絕緣層上覆矽鍺(SGOI))。在本發明某些實施方式中，半導體基板10較佳是由含矽半導體材料組成，例如包含矽的半導體材料。半導體基板10可包含摻質、不包含摻質或同時包含有或無摻質的區域兩者。
半導體基板10可以是被拉伸(stretched)、未被拉伸(unstretched)、或兩者的組合。此外，半導體基板10可以包括有以下任一結晶方位：{100}、{110}、{111}或其之組合。或者，此半導體基板10可以是包括至少兩不同結晶方位之平坦表面的混合基板。此種混合基板可以下列技術來製造：例如，2003年6月17日申請的美國專利申請案第10/250,241號(美國公開案第2004256700A1)、2003年12月2日申請的美國專利申請案第10/725,850號(美國公開案第20050116290A1)及2003年10月29日申請的美國專利申請案第10/696,634號(美國專利第7,023,055號)，其揭示內容併入本文作為參考。
半導體基板10也包括一第一摻雜區(n－或p－型摻雜)和一第二摻雜區(n－或p－型摻雜)。為使圖式清楚起見，該些摻雜區並未被特意揭示在圖示中。第一摻雜區和第二摻雜區可以相同，或是具有不同的導電性和/或摻雜濃度。這些摻雜區即為習知的「井(wells)」。
之後在半導體基板10上形成至少一隔絕區(未示出)。 此隔絕區可以是一種溝渠隔絕區或場效氧化物隔絕區。以習知技藝人士熟知的傳統溝渠隔絕技術(例如，微影蝕刻及以溝渠介電質來充填該溝渠)來形成溝渠隔絕區。或者，在充填溝渠之前，先形成襯墊層，在充填溝渠之後，實施一緊密化製程以及平坦化製程。可用一般稱為「局部氧化矽處理」的方式來形成場效氧化物。須知，當周圍閘極區域具有相反導電性時，一般需要至少一隔絕區來提供周圍閘極區域間彼此隔絕。周圍閘極區域可具有相同的導電性(亦即，均為n－或p－型)，或者，其可具有不同的導電性(亦即，一為n－型，另一為p－型)。
之後，一般使用熱製程(例如，氧化或氮氧化)、沉積製程(例如，化學氣相沉積(CVD)、電漿輔助CVD、原子層沉積(ALD)、蒸鍍、濺鍍及化學溶液沉積)或其之組合，在半導體基板10頂部形成一交界層12(但不一定必須)。或者，使用一沉積製程及氮化處理來形成一交界層12。
此交界層12一般具有約4.0~20間的介電常數，但最常見的是約4.5~18間的介電常數。此交界層12的厚度一般在約0.1~5 nm間，又以約0.2~2.5 nm間最常見。
在本發明一實施方式中，此交界層12為以濕化學氧化方式所形成之厚度在約0.6~0.8 nm間的氧化矽層。此濕化學氧化處理包括在65℃下以由氫氧化銨、過氧化氫及水(比例為1：1：5)所形成的混合物，來處理一乾淨的半導體表面(例如，HF－半導體表面)。或者，也可在臭氧化水溶液中處理該HF－半導體表面來形成此交界層12，其中臭氧的濃度一般在約2 ppm~40 ppm間變化。
接著，在此交界層12(如果有的話)的一表面上形成高k值閘極介電質14或是直接在半導體基板10(如果交界層12不存在的話)的表面上形成高k值閘極介電質14。「高k值」代表一絕緣層的介電常數大於4.0，一般在7.0或更高。在整份說明書中，當述及介電常數時，均是指真空狀態下。可使用諸如氧化、氮化、氮氧化之類的熱成長製程來型成此高k值閘極介電質14。或者，可利用諸如CVD、電漿輔助CVD、金屬有機化學氣相沉積(MOCVD)、原子層沉積(ALD)、蒸鍍、反應性濺鍍、化學溶液沉積及其他類似製程之類的沉積製程，來形成高k值閘極介電質14。也可使用上述製程的組合來形成高k值閘極介電質14。
在本發明中使用的高k值閘極介電質14包括(但不限於)：一種氧化物、氮化物、氧氮化物、和/或矽化物(包括金屬矽酸鹽及氮化金屬矽酸鹽)。在一實施方式中，此高k值閘極介電質14較佳是包括一種氧化物，如HfO2 、ZrO2 、Al2 O3 、TiO2 、La2 O3 、SrTiO3 、LaAlO3 、Y2 O3 、Ga2 O3 、GdGaO及其之組合。此高k值閘極介電質14的最佳實例包括HfO2 、矽酸鋡或氧氮化矽鋡。
此高k值閘極介電質14的實際厚度可改變，但一般情況下，其厚度在約0.5~10 nm間，其中以約1.0~3 nm間的厚度最好。
接下來，如第2圖所示，直接在高k值閘極介電質14的表面上生成一金屬含氮層16。依據本發明，申請人發現當金屬和氮的組成份比例小於1.1時，可獲得具有較低的電荷捕陷和閘極漏電流之閘極堆疊，其中又以金屬和氮的組成份比例小於1.08最佳。在一更佳實施方式中，在金屬含氮層16中的金屬和氮的組成份比例小於或等於1.03。
詳言之，此金屬含氮層16包括選自週期表第IVB、VB、VIB或VIIB族的金屬。一般來說，此金屬含氮層16包括Ti、V、Zr、Nb、Mo、Hf、Ta、W或Re，其中又以Ti最佳。此金屬含氮層16的厚度可以不同，但一般在約0.5~200 nm間，其中又以約2 nm到20 nm最常見。
可利用濺鍍製程來製造具有上述金屬與氮之組成比例的金屬含氮層16，包括：先提供一金屬標靶(其包含週期表第IVB、VB、VIB或VIIB族的金屬)，和一包括有氬氣(Ar)及氮氣(N2 )的氣體環境。可利用改變製程參數的方式來控制濺鍍得的金屬含氮層16中的金屬與氮之比例。舉例來說，可控制濺鍍過程中氬氣/氮氣流之比例來控制所得金屬含氮層16中的金屬與氮之比例。在這類實施方式中，可利用提供氬氣與氮氣流之比例在約1.0至約0.1間，來獲得具有金屬與氮之比例小於1.1的金屬含氮層16。更佳是，利用提供氬氣與氮氣流之比例在約0.75，來獲得具有金屬與氮之比例小於1.1的金屬含氮層16。
接著，使用上述的氣體環境，從該金屬標靶中濺鍍形成具有上述金屬與氮之組成比例的金屬含氮層16。可使用任何習知的濺鍍設備來實施此一濺鍍製程。此外，可用於本發明的金屬標靶包括上述之任一金屬來源。
在形成金屬含氮層16之後，在其頂部形成一含矽導體18。所得包括有含矽導體18之結構係如第3圖所示。詳言之，以諸如PVD、CVD或蒸鍍之類的沉積技術，在金屬含氮層16頂部形成一層毯覆的含矽導體層18。
用來形成導体18的含矽材料可包括以單晶、多晶或無定形形式存在的Si或SiGe合金。較佳是，使用多晶矽來形成本發明的含矽導體層18。也可使用上述材料的組合。該毯覆的含矽導體層18可以含有或不含有摻質。如果含有摻質的話，可使用原位摻雜技術來形成。或者，可利用沉積、離子佈植和回火硬化，來形成有摻質的含矽層。此離子佈植及回火硬化可發生在後續用來將材料堆疊圖案化的蝕刻步驟之前或之後。摻雜含矽層將使所形成的閘極導體的功函數產生偏移。nMOSFETs可用的摻雜離子實例包括週期表第VA族元素(當形成pMOSFETs時，則可使用週期表第IIIA族元素)。
可視所使用的沉積製程，來決定是否要改變此時所沉積的含矽導體層18的厚度，亦即，高度。一般來說，含矽導體層18的垂直厚度約在20 nm到180 nm間，其中又以約40 nm到150 nm的厚度最常見。
之後，以微影蝕刻來圖案化第3圖所示之閘極堆疊結構。雖然第4圖僅示出一單一圖樣的閘極堆疊50，但本發明事實上也涵蓋多個圖樣化的閘極堆疊50。當有多個圖樣化的閘極堆疊50被形成時，該些閘極堆疊的尺寸(即，長度)可能相同，或是可具有不同大小，以改善元件效能。
第4圖示出一圖案化的結構，其包括一圖案化的硬遮罩22，位在含矽導體層18的表面上。此圖案化的硬遮罩22可被保留在最終結構內或是可利用能選擇性地將此圖案化的硬遮罩22從結構中移除的傳統剝除方法來移除此圖案化的硬遮罩22。剩下的圖示中是假設已將此圖案化的硬遮罩22從結構中移除，以便提供一可供後續形成金屬矽化物接點在含矽導體層18頂端的平台。
本發明所採用的光微影蝕刻步驟可以是此領域中習知的微影蝕刻製程。舉例來說，此微影蝕刻步驟包括在含矽導體層18頂端形成一光阻或一硬遮罩之材料堆疊及一光阻。如果有的話，該硬遮罩包含諸如二氧化矽之類的氧化物，或諸如氮化矽之類的氮化物，至於光阻則包含任一習知的光阻材料(有機、無機或其之混合物)。當有一硬遮罩存在時，可以包括CVD、PECVD、蒸鍍、化學溶液沉積等傳統方法來形成此硬遮罩。或者，可利用熱處理方法，例如氧化或氮化，來形成此硬遮罩。光阻則可利用任一傳統方法來形成，例如CVD、PECVD、蒸鍍或旋塗等。
待在含矽導體層18表面形成至少該光阻之後，將光阻暴露在欲求圖樣(即，閘極導體圖樣)的光照下並以傳統的光阻顯影劑加以顯影。
可用在本發明的蝕刻步驟包括乾蝕刻、濕蝕刻或其之組合。「乾蝕刻」意指以下之一：反應性離子蝕刻(RIE)、離子束蝕刻、電漿蝕刻和雷射磨蝕。濕蝕刻包括可專一地(selectively)移除閘極堆疊之各種材料的化學性蝕刻劑。
所用的蝕刻處理一般(但非永遠)是對下層高k閘極介電質14具有專一選擇性，因此，此蝕刻步驟不會從閘極堆疊中移除高k閘極介電質14和交界層12。在某些實施方式中，如第4圖所示，此蝕刻步驟可用來移除一部份的高k閘極介電質14和交界層12，這些部份是未受先前蝕刻之閘極堆疊材料層所保護的部份。
接著，一般來說(並非永遠)，可在每一圖樣化的閘極區域50之外露的側壁上形成至少一隔絕物24(spacer 24)，參見第5圖。此至少一隔絕物24係由諸如氧化物、氮化物、氧氮化物和/或其之任一組合所組成的絕緣物。應使用不含氫氣的製程來製造此至少一隔絕物24。
此至少一隔絕物24的寬度必須足夠寬，使得源極與汲極接點(將接續形成)不會侵入閘極堆疊50邊緣下方。一般來說，當此至少一隔絕物24的寬度(從底部量的時候)在約20~80 nm間時，此源極與汲極矽化物不會侵入閘極堆疊50邊緣下方。
在形成隔絕物之前，可利用將閘極堆疊50暴露在熱氧化、氮化或氧氮化處理下，使得此閘極堆疊50可被額外地加以鈍化。此鈍化步驟可在閘極堆疊50周圍形成一薄層的鈍化材料(未示出)。可以此步驟取代前述形成隔絕物24的步驟或與該步驟一同使用。當與形成隔絕物24的步驟一同使用時，待閘極堆疊50被鈍化後才能形成隔絕物。
之後在基板內形成源極/汲極擴散區26(有或無隔絕物存在)。使用離子佈植法和回火硬化處理來形成此源極/汲極擴散區26。回火硬化處理可活化先前被離子佈植法佈植在該區內的摻質。離子佈植法和回火硬化處理的反應條件已為習知技術。第5圖即示出此源極/汲極擴散區26。
源極/汲極擴散區26也可包括在施行源極/汲極佈植之前，使用傳統延伸佈植法所形成的延伸佈植區(未單獨標示)。在此延伸佈植之後，可施行活化性的回火硬化，或是使用相同的回火硬化循環將延伸佈植和源極/汲極佈植期間所佈植的摻質加以活化。在此也涵蓋鹵素佈植物。此源極/汲極延伸佈植一般較源極/汲極區域來得淺，且其之一邊緣可與該圖案化閘極堆疊50之一邊緣對齊。
接著，如果之前並未移除的話，此時可利用能專一性地移除絕緣材料的化學蝕刻製程將高k閘極介電質14和交界層12的外露部分加以移除。此蝕刻步驟停在半導體基板10的上表面。雖然可使用任何一種化學蝕刻劑來移除高k閘極介電質14和交界層12的外露部分，但在一實施方式中，則是以稀釋的氫氟酸(diluted hydrofluoric acid,DHF)來進行石刻。
第5圖也示出在源極/汲極擴散區26與含矽導體18的頂端有一矽化物接觸區28。此矽化物接觸區28是使用習知的矽化處理製造的。
矽化處理包括與其他諸如C、Ge、Si等等之類的合金添加劑在欲被矽化的區域頂端形成諸如Co、Ti、W、Ni、Pt或其合金之導電與耐火金屬(conductive and refractory metal)。可使用諸如CVD、PECVD、濺鍍、蒸鍍或電鍍等傳統的技術。或者，可在金屬層上方形成一層阻障層來保護金屬使不會氧化。額外的阻障層的實例包括，例如，SiN、TiN、TaN、TiON及其之組合等。在沉積金屬之後，讓結構接受至少一第一回火硬化處理(可造成所沉積金屬與矽獲其他半導體材料反應)，接著生成金屬矽化物(或更普遍是在金屬半導體合金上)。此回火硬化處理一般在約250℃到約800℃的溫度下進行，其中又以約400℃到約550℃的溫度最常見。
在某些實施方式中，第一次回火硬化可形成富含金屬的矽化物相，其對選擇性蝕刻具有高度可耐性。當生成富含金屬的矽化物相時，就需要實施第二次更高溫的回火硬化處理，以形成低電阻性的矽化物。在其他實施方式中，第一次回火硬化即已足夠形成低電阻性的矽化物。
在第一次回火硬化後，使用習知的蝕刻處理(如，濕蝕刻、反應性離子蝕刻(RIE)、離子束蝕刻或電漿蝕刻)來將沉積金屬中未反應的部份及剩餘的部份加以移除。
如果需要的話，在蝕刻處理後，可再實施第二次回火硬化。此第二次回火硬化一般是在比第一次回火硬化更高的溫度下實施。此附加式的第二次回火硬化的操作溫度通常在約550℃到約900℃間。
須知，本發明的方法可在一代替性閘極處理和上述處理中實施。
更進一步的CMOS處理包括與金屬內連線共同形成生產線後端(back－end－of－the－line,BEOL)內連層的處理方法，已是此領域中的習知技術。
下列實施例僅係為了闡述本發明概念，本發明範疇並不僅限於此。
實施例
在此實施例中，係於矽晶圓表面上形成各種聚矽/TiN/HfO2 /SiO2 堆疊。利用對矽晶圓施行氧化來形成SiO2 交界層，此SiO2 交界層的厚度大約1 nm。之後，以MOCVD在SiO2 交界層上形成厚約3 nm的HfO2 介電層。接著，在Ar/N2 的氣體環境下，從Ti標靶濺鍍形成TiN層。此濺鍍製程是在一長拋型系統內進行(基板與標靶間相隔約300 nm)並控制氬氣與氮氣流，以改變鈦與氮的組成比例。特別是，濺鍍形成的TiN層中鈦對氮的比例可約為1.34(Ar/N2 的流速比為15/10)、1.0(Ar/N2 的流速比為15/20)和1.03(Ar/N2 的流速比為15/30)。之後，沉積形成聚矽層並進行非－原位摻雜(doped ex－situ)。
第6圖為上述具有漸變之Ti/N組成比之氧化物/HfOx /TiN nFETs之閥值電位偏移對應力電場之關係圖。此圖示出TiN組成對於電荷捕陷的依賴關係。如所示，隨著Ti/N組成比降低，電荷捕陷誘發的閥值電位偏移也跟著下降，此比例是利用雷瑟弗向後散射(Rutherford Backscattering,RBS)法來決定的。第7圖上述具有漸變之Ti/N組成比之氧化物/HfOx /TiN nFETs之閘極漏電流對應力時間之關係圖。此圖示出TiN組成對於閘極漏電流劣變的影響。如所示，Ti/N比值愈高，在施加應力約30秒後，閘極漏電流會隨著應力時間增加而增加，相反的，在Ti/N比值低的情況下，就沒有這樣的現象。因此，可利用降低Ti/N比值來抑制閘極漏電流劣變。
綜上所述，申請人發現Ti/N比值對於電荷捕陷和閘極漏電流劣變兩者都有影響。當Ti/N比值低於1.1時，可顯著地改善高－k值閘極堆疊的可靠性。
雖然已參考前述實施態樣對本發明進行了描述，但是，很明顯的，根據前面的描述，許多替代性變化和變體對於本領域技術人員來說是顯而易見的。因此，本發明包含所有落入所附權利要求的精神和範疇之內的這樣的替代性變化和變體。
10．．．半導體基板
12．．．交界層
14．．．高k值閘極介電質
16．．．金屬含氮層
18．．．含矽導體
20．．．已圖案化的硬遮罩
22．．．硬遮罩
24．．．隔絕物
26．．．源極/汲極擴散區
28．．．矽化物接觸區
50．．．閘極堆疊
通過參照附圖來詳細描述優選的實施方案，本發明的上述目的和其他優點將會變得更加顯而易見，其中：第1~5圖為本發明基本處理步驟的示意圖；第6圖為具有漸變之Ti/N組成比之氧化物/HfOx /TiN nFETs之閥值電位偏移對應力電場之關係圖；第7圖是具有具有漸變之Ti/N組成比之氧化物/HfOx /TiN nFETs之閘極漏電流對應力時間之關係圖。
10．．．半導體基板
12．．．交界層
14．．．高k值閘極介電質
16．．．金屬含氮層
18．．．含矽導體
24．．．隔絕物
26．．．源極/汲極擴散區
28．．．矽化物接觸區

Claims (17)

  1. 一種形成一半導體晶片之一接觸電極的方法，該方法包含以下步驟：形成一保護層於一金屬接墊表面上；在該保護層中形成一錐形開口而露出該金屬接墊表面，以定出一連接焊塊的一位置，其中該錐形開口周圍之該保護層之一錐形側壁的至少一部分覆蓋於該金屬接墊表面上；直接形成一阻障材料襯層於該圖案化之保護層之該錐形側壁以及該金屬接墊表面上，該阻障材料襯層共形於含有該錐形側壁之該圖案化之保護層的一表面上；填充一導電材料層至該已含該阻障材料襯層之錐形開口內，及形成一導電材料層於該保護層表面上方形成之阻障材料襯層上；藉由研磨來移除該保護層表面上一部分的該導電材料層和該阻障材料襯層而形成一導電材料栓塞，該導電材料栓塞之一表面實質上與一最終保護層之一表面共平面以及填充該錐形開口，其中該研磨步驟止於該阻障材料襯層的一部分；形成一擴散阻障層於該導電材料栓塞實質上共平面的表面上；提供一焊錫材料至該擴散阻障層之一表面；以及處理該焊錫材料，以在該擴散阻障層上形成該連接焊 塊，同時不施行一遮罩步驟，該方法可縮小一晶片之間距及提高該連接焊塊的機械穩定性。
  2. 如申請專利範圍第1項所述之形成接觸電極的方法，其中該形成擴散阻障層的步驟包含利用一無電鍍覆技術。
  3. 如申請專利範圍第2項所述之形成接觸電極的方法，其中該阻障材料襯層包含一阻障材料堆疊結構，該移除一部分的導電材料層和阻障材料襯層之步驟包含：進行一化學機械研磨(CMP)步驟，其中該CMP步驟移除該阻障材料襯層堆疊結構之該些導電材料層的一上層。
  4. 如申請專利範圍第3項所述之形成接觸電極的方法，其中該進行CMP步驟以移除該些導電材料層之上層的步驟包含停止於該阻障材料堆疊結構之剩餘導電材料層的一表面。
  5. 如申請專利範圍第4項所述之形成接觸電極的方法，更包含以反應離子蝕刻(RIE)移除該連接焊塊位置旁的該阻障材料堆疊結構之該些導電材料層的剩餘部份。
  6. 如申請專利範圍第3項所述之形成接觸電極的方法，其中該阻障材料堆疊結構之該些導電材料層的上層包含鉻 (Cr)、銅(Cu)或上述之合金。
  7. 如申請專利範圍第6項所述之形成接觸電極的方法，其中該阻障材料堆疊結構之該些導電材料層的剩餘部分包含鈦(Ti)、鎢(W)或上述之合金。
  8. 如申請專利範圍第1項所述之形成接觸電極的方法，其中該擴散阻障層包含鎳(Ni)。
  9. 如申請專利範圍第1項所述之形成接觸電極的方法，其中該提供焊錫材料的步驟包含利用一無電鍍覆技術來沉積該焊錫材料。
  10. 如申請專利範圍第1項所述之形成接觸電極的方法，其中該形成保護層於該金屬接墊表面上的步驟包含形成一單一通孔開口而露出該金屬接墊表面。
  11. 一種連接焊塊，位於一半導體晶片之一金屬接墊的一表面，該連接焊塊包含：一保護層，形成於該金屬接墊表面上，該保護層包括位於該金屬接墊表面上的一溝渠開口，用以定義該連接焊塊的一位置；一阻障材料襯層，形成於該溝渠開口內，該阻障材料襯 層之表面部分實質上與該連接焊塊位置旁的該保護層之一表面共平面；一導電材料栓塞，填充該已形成有該阻障材料襯層的溝渠開口，該導電材料栓塞之一表面與該保護層之一表面共平面；一擴散阻障層，形成該導電材料栓塞在該連接焊塊位置處實質上共平面的表面上；以及一焊塊，形成在該擴散阻障層之一表面上，其中該阻障材料襯層不具底切，如此可縮小間距及提高該連接焊塊的機械穩定性。
  12. 如申請專利範圍第11項所述之連接焊塊，其中該保護層包含一或多個介電材料層。
  13. 如申請專利範圍第11項所述之連接焊塊，其中該金屬接墊之一材料包含銅(Cu)或鋁(Al)。
  14. 如申請專利範圍第11項所述之連接焊塊，其中該金屬接墊形成在一低k內連線介電材料層中。
  15. 如申請專利範圍第11項所述之連接焊塊，其中該阻障材料襯層包含一堆疊結構，該堆疊結構包括一含有銅(Cu)、鉻(Cr)或上述之合金的上層；和一含有鈦(Ti)、鎢(W) 或上述之合金的下阻障材料層。
  16. 如申請專利範圍第15項所述之連接焊塊，其中該阻障材料層堆疊結構更包含一中間導電材料層，位於該上層與該下阻障材料層之間。
  17. 如申請專利範圍第11項所述之連接焊塊，其中該導電材料栓塞包含銅(Cu)。
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