TWI413965B - Shift register and display device having the same - Google Patents

Shift register and display device having the same Download PDF

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Publication number
TWI413965B
TWI413965B TW093106055A TW93106055A TWI413965B TW I413965 B TWI413965 B TW I413965B TW 093106055 A TW093106055 A TW 093106055A TW 93106055 A TW93106055 A TW 93106055A TW I413965 B TWI413965 B TW I413965B
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Taiwan
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transistor
gate
clock signal
pull
receiving
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TW093106055A
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Chinese (zh)
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TW200502908A (en
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Seung-Hwan Moon
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Samsung Display Co Ltd
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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C18/00—Rotary-piston pumps specially adapted for elastic fluids
    • F04C18/30—Rotary-piston pumps specially adapted for elastic fluids having the characteristics covered by two or more of groups F04C18/02, F04C18/08, F04C18/22, F04C18/24, F04C18/48, or having the characteristics covered by one of these groups together with some other type of movement between co-operating members
    • F04C18/34—Rotary-piston pumps specially adapted for elastic fluids having the characteristics covered by two or more of groups F04C18/02, F04C18/08, F04C18/22, F04C18/24, F04C18/48, or having the characteristics covered by one of these groups together with some other type of movement between co-operating members having the movement defined in group F04C18/08 or F04C18/22 and relative reciprocation between the co-operating members
    • F04C18/344—Rotary-piston pumps specially adapted for elastic fluids having the characteristics covered by two or more of groups F04C18/02, F04C18/08, F04C18/22, F04C18/24, F04C18/48, or having the characteristics covered by one of these groups together with some other type of movement between co-operating members having the movement defined in group F04C18/08 or F04C18/22 and relative reciprocation between the co-operating members with vanes reciprocating with respect to the inner member
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C25/00—Adaptations of pumps for special use of pumps for elastic fluids
    • F04C25/02—Adaptations of pumps for special use of pumps for elastic fluids for producing high vacuum
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C29/00—Component parts, details or accessories of pumps or pumping installations, not provided for in groups F04C18/00 - F04C28/00
    • F04C29/04—Heating; Cooling; Heat insulation
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C29/00—Component parts, details or accessories of pumps or pumping installations, not provided for in groups F04C18/00 - F04C28/00
    • F04C29/12—Arrangements for admission or discharge of the working fluid, e.g. constructional features of the inlet or outlet
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C2210/00—Fluid
    • F04C2210/22—Fluid gaseous, i.e. compressible
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
    • F04C—ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT MACHINES FOR LIQUIDS; ROTARY-PISTON, OR OSCILLATING-PISTON, POSITIVE-DISPLACEMENT PUMPS
    • F04C2240/00—Components
    • F04C2240/40—Electric motor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S415/00—Rotary kinetic fluid motors or pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S417/00—Pumps

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

PURPOSE: A shift register and a display device having the same are provided to reduce the number of external bus lines. CONSTITUTION: The shift register includes a plurality of stages generating a gate signal to a plurality of gate lines of a display device in sequence. According to each stage, the first pull-up driver(230) generates the first control signal in response to an output signal or a control signal of a prior stage. A pull-up unit(210) generates an output signal of a current stage in response to the first power clock and the first control signal. The second pull-up driver(250) generates the second control signal in response to the first power clock and the second power clock. And the third pull-up driver(240) drives in response to the output signal of a following stage by being connected to a low level port.

Description

位移暫存器及具有位移暫存器之顯示裝置Displacement register and display device with displacement register

本發明有關於在一顯示裝置中產生掃描信號的一閘極驅動器，更明確而言，有關在一閘極驅動器中能以減少數量的外部匯流排線操作的一位移暫存器、與使用此一位移暫存器的顯示裝置。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a gate driver for generating a scan signal in a display device, and more particularly to a shift register capable of operating with a reduced number of external bus bars in a gate driver, and using this A display device for a displacement register.

例如液晶顯示裝置的影像顯示裝置通常具有使用一薄膜封裝(tape carrier package,TCP)的一閘極驅動器、玻璃晶片(COG)等。然而，在此顯示裝置中，改善設計效力及減少閘極驅動器電路與顯示裝置的製造成本是不容易。For example, an image display device of a liquid crystal display device generally has a gate driver, a glass wafer (COG), or the like using a tape carrier package (TCP). However, in this display device, it is not easy to improve the design efficiency and reduce the manufacturing cost of the gate driver circuit and the display device.

若要減緩困難度，發展例如不具有一閘極驅動器積體電路(IC)的閘極驅動技術。換句話說，一顯示裝置具有不是在顯示面板以積體電路形式安裝的一閘極驅動，而是整個在一部分顯示面板上形成的。此閘極驅動元件的結構在此描述中稱為"較少閘極IC結構"。在較少閘極IC結構中，通常使用無定形矽薄膜電晶體(非晶矽TFTs)。非晶矽TFT範例可在美國專利案號5,517,542及共同讓與的韓國專利案號2002-3398(或韓國公開公告案2002-66962)中找到。具較少閘極IC結構的傳統閘極驅動元件包括一或多個化移暫存器，以提供掃描信號給一顯示面板。To alleviate the difficulty, for example, a gate driving technique that does not have a gate driver integrated circuit (IC) is developed. In other words, a display device has a gate drive that is not mounted in the form of an integrated circuit on the display panel, but is formed entirely on a portion of the display panel. The structure of this gate drive element is referred to herein as "less gate IC structure." In the case of fewer gate IC structures, amorphous germanium film transistors (amorphous germanium TFTs) are commonly used. An example of an amorphous germanium TFT can be found in U.S. Patent No. 5,517,542 and commonly assigned Korean Patent No. 2002-3398 (or Korean Patent Publication No. 2002-66962). A conventional gate drive component having fewer gate IC structures includes one or more shift registers to provide a scan signal to a display panel.

圖1描述一傳統位移暫存器單級電路圖。請即參考圖1，一傳統位移暫存器單級100包括一上拉元件110、一下拉元件120、一上拉驅動元件130、與一下拉驅動元件140。單級 100能響應一前級的一掃描開始信號STV或一輸出信號而產生一閘極信號(或掃描信號)。在單級100是一位移暫存器的第一級情況，單級100可接收掃描開始信號STV以輸出閘極信號。對照下，在單級100不是一位移暫存器的第一級的情況，單級100可接收從一前級產生的一閘極信號以輸出閘極信號。具有此單級的一位移暫存器是安裝在一顯示裝置的一TFT面盤。Figure 1 depicts a single-stage circuit diagram of a conventional shift register. Referring to FIG. 1, a conventional displacement register single stage 100 includes a pull-up element 110, a pull-down element 120, a pull-up drive element 130, and a pull-down drive element 140. Single-stage The 100 can generate a gate signal (or a scan signal) in response to a scan start signal STV or an output signal of a previous stage. In the case where the single stage 100 is the first stage of a shift register, the single stage 100 can receive the scan start signal STV to output the gate signal. In contrast, in the case where the single stage 100 is not the first stage of a shift register, the single stage 100 can receive a gate signal generated from a previous stage to output a gate signal. A displacement register having this single stage is a TFT face plate mounted on a display device.

圖2描述包括如圖1所示多級的一傳統位移暫存器方塊圖。請即參考圖1與2，位移暫存器174具有：'N'級SRC1 -SRCN ，以分別產生'N'個閘極信號(或掃描信號)GOUT1 -GOUTN ；與一虛擬級SRCN+1 ，以將一控制信號提供給前級。多級SRC1 -SRCN 的每一級可接收第一與第二時脈信號CKV、CKVB、高與接地位準電壓VDD、VSS以當作閘極關閉與導通電壓VON、VOFF、與來自下一級輸出的一控制信號。Figure 2 depicts a block diagram of a conventional shift register including multiple stages as shown in Figure 1. Referring to Figures 1 and 2, the shift register 174 has: 'N' stages SRC 1 - SRC N to generate 'N' gate signals (or scan signals) GOUT 1 - GOUT N respectively ; and a virtual stage SRC N+1 to provide a control signal to the pre-stage. Each stage of the multi-stage SRC 1 -SRC N can receive the first and second clock signals CKV, CKVB, the high and ground level voltages VDD, VSS as the gate turn-off and turn-on voltages VON, VOFF, and from the next stage A control signal that is output.

特別是，第一級可接收除了前述信號之外的一掃描開始信號STV，以輸出用以選擇第一閘極線的第一閘極信號GOUT1 。第一閘極信號GOUT1 亦提供給第二級的一輸入端。除了前述信號之外，第二級SRC2 能從第一級接收第一閘極信號GOUT1 ，以輸出用以選擇第二閘極線的第二閘極信號GOUT2 。第二閘極信號GOUT2 亦提供給第三級SRC3 的輸入端。在類似方式中，除了其他時脈與電壓信號之外，第N級SRCN 能從一第(N-1)級接收第(N-1)閘極信號與來自虛擬級SRCN+1 的一控制信號，以輸出用於選擇第N閘極信號 GOUTN 。In particular, the first stage may receive a scan start signal STV other than the aforementioned signal to output a first gate signal GOUT 1 for selecting the first gate line. The first gate signal GOUT 1 is also provided to an input of the second stage. In addition to the foregoing signals, the second stage SRC 2 can receive the first gate signal GOUT 1 from the first stage to output a second gate signal GOUT 2 for selecting the second gate line. The second gate signal GOUT 2 is also provided to the input of the third stage SRC 3 . In a similar manner, in addition to the other clock and voltage signals, the Nth stage SRC N can receive the (N-1)th gate signal from the (N-1)th stage and the one from the virtual stage SRC N+1 . The control signal is output to select the Nth gate signal GOUT N .

圖3是圖1的位移暫存器信號波形圖。請即參考圖1-3，在位移暫存器174的一單級可接收第一或第二時脈信號CKV/CKVB，即是，即是奇數級可接收第一時脈信號CKV，且偶數級可接收第二時脈信號CKVB，其中該第二時脈信號CKVB的相位是與第一時脈信號CKV相反。位移暫存器174可連續產生一TFT基板閘極線的閘極信號。第一與第二時脈信號CKV、CKVB能從一時序控制器(未在圖顯示)的一輸出信號獲得。通常，時序控制器的輸出信號具有從0伏特至3伏特範圍的振幅，並能在-8伏特至24伏特範圍內放大，以驅動非晶矽TFT。第一與第二時脈信號可使用放大的輸出信號。3 is a waveform diagram of the shift register of FIG. 1. Referring to FIG. 1-3, the first or second clock signal CKV/CKVB can be received in a single stage of the shift register 174, that is, the odd-numbered stage can receive the first clock signal CKV, and the even number The stage can receive the second clock signal CKVB, wherein the phase of the second clock signal CKVB is opposite to the first clock signal CKV. The displacement register 174 can continuously generate a gate signal of a TFT substrate gate line. The first and second clock signals CKV, CKVB can be obtained from an output signal of a timing controller (not shown). Typically, the output signal of the timing controller has an amplitude in the range from 0 volts to 3 volts and can be amplified in the range of -8 volts to 24 volts to drive the amorphous germanium TFT. The first and second clock signals can use an amplified output signal.

如前述，具有使用非晶矽電晶體的較少閘極IC結構之一傳統位移暫存器需要至少五條匯流排線：一匯流排線用於傳送掃描開始信號STV，且該掃描開始信號STV是在一水平方向的一開始信號；一匯流排線用於傳送第一時脈信號CKV以施加閘極關閉電壓，其中該匯流排線連接到奇數閘極線；一匯流排線用於傳送第二時脈信號CKVB以施加閘極關閉信號，其中該匯流排線連接到偶數閘極線；及一些匯流排線用以將高與接地位準電壓VDD、VSS提供給該等單級的每一者。五條匯流排線經由安裝有源極驅動器積體電路TCP的一虛擬接腳而連接到一顯示面板的閘極驅動IC區域，或五條匯流排線連接在顯示面板，而該顯示面連接到閘極驅動區域。As described above, a conventional shift register having a small gate IC structure using an amorphous germanium transistor requires at least five bus bars: a bus bar for transmitting a scan start signal STV, and the scan start signal STV is a start signal in a horizontal direction; a bus line for transmitting a first clock signal CKV to apply a gate turn-off voltage, wherein the bus line is connected to an odd gate line; and a bus line is used to transmit a second line Clock signal CKVB to apply a gate turn-off signal, wherein the bus bar is connected to an even gate line; and some bus bars are used to provide high and ground level voltages VDD, VSS to each of the single stages . The five bus bars are connected to the gate driving IC region of a display panel via a dummy pin of the source driver integrated circuit TCP, or five bus bars are connected to the display panel, and the display surface is connected to the gate Drive area.

然而，傳統位移暫存器具有包括下列問題。需要用以形成一跳線以將信號與電力傳送給每一級的的一分開空間。尤其，在具有一增加有效顯示區域的小窄面液晶顯示面板中，匯流排線空間會受限制。且當五條或多條匯流排線經由TCP或FPC形成，TCP的虛擬空間與FPC的寬度會增加，所以製造成本會增加，且匯流排線的空間會是受限制。此外，當非晶矽電晶體用於一閘極驅動器電路時，非晶矽電晶體會在例如閘極導通與關閉電壓VON、VOFF的直流偏壓狀態中損壞。結果，非晶矽電晶體發生故障。此外，非晶矽電晶體需要例如-14伏特至20伏特的一大電壓差，所以顯示面板的金屬墊塊會由於大電壓差而損壞。尤其是，當顯示面板受到高溫度與濕氣時，金屬墊塊便會被侵蝕，或者不必要之電路徑會由於濕氣而在金屬墊塊間形成。However, conventional displacement registers have the following problems. A separate space is needed to form a jumper to transmit signals and power to each stage. In particular, in a small narrow-face liquid crystal display panel having an increased effective display area, the bus bar space is limited. And when five or more bus lines are formed via TCP or FPC, the virtual space of the TCP and the width of the FPC increase, so the manufacturing cost increases, and the space of the bus line is limited. In addition, when an amorphous germanium transistor is used in a gate driver circuit, the amorphous germanium transistor is damaged in a DC bias state such as gate turn-on and turn-off voltages VON, VOFF. As a result, the amorphous germanium transistor fails. In addition, amorphous germanium transistors require a large voltage difference of, for example, -14 volts to 20 volts, so the metal pads of the display panel may be damaged due to large voltage differences. In particular, when the display panel is subjected to high temperatures and moisture, the metal pads are eroded, or unnecessary electrical paths may be formed between the metal blocks due to moisture.

先前技術的前述及其缺點與不足能透過使用根據本發明的位移暫存器與顯示裝置而克服或減輕。在一具體實施例中，用以將閘極信號提供給在一顯示裝置中對應閘極線的位移暫存器包括複數個單級，以連續產生閘極信號，其中該等單級的每一級包括：一第一上拉驅動元件，以響應一相鄰前級的輸出信號而產生一第一控制信號或一控制信號；一上拉元件，以響應一第一時脈信號與第一控制信號而產生一電流輸出信號；一第二上拉驅動元件，以響應第一時脈信號與一第二時脈信號而產生至少一第二控制信號；與一第三上拉驅動元件，其連接到一低位準端，以響 應一相鄰後級的輸出信號而操作。該單級亦包括一下拉元件，以響應第二時脈信號而操作。位移暫存器可在顯示面板的選擇區域與顯示面板整個形成。The foregoing and its disadvantages and deficiencies of the prior art can be overcome or mitigated by the use of the displacement register and display device in accordance with the present invention. In one embodiment, the displacement register for providing a gate signal to a corresponding gate line in a display device includes a plurality of single stages to continuously generate a gate signal, wherein each stage of the single stage The method includes: a first pull-up driving component to generate a first control signal or a control signal in response to an output signal of an adjacent front stage; and a pull-up component to respond to a first clock signal and the first control signal Generating a current output signal; a second pull-up driving component to generate at least one second control signal in response to the first clock signal and a second clock signal; and a third pull-up driving component connected to a low position, ringing It should operate with an output signal from an adjacent stage. The single stage also includes a pull-down element that operates in response to the second clock signal. The displacement register can be formed entirely in the selected area of the display panel and the display panel.

第二上拉驅動元件包括：一第一電晶體，其具有接收該閘極信號的一閘極與連接在接收第一時脈信號端與接收第二時脈信號間的一傳導路徑，其中一第二電晶體連接在該接收第一時脈信號端與第一電晶體之間，第二電晶體的工作如同二極體；及一第三電晶體，其具有接收第二時脈信號的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一與第二電晶體共同節點間的一傳導路徑，其中該共同節點連接到第三上拉驅動元件。第三上拉驅動元件包括：一第一電晶體，其具有連接到第一控制信號的兩端；一第二電晶體，其具有連接到第二上拉驅動元件共同節點的一閘極與連接在第一電晶體與第二時脈信號間的一傳導路徑；一第三電晶體，其具有連接到相鄰後級輸出信號的一閘極與連接在上拉元件與低位準端間的一傳導路徑；與一電容器，其連接在上拉元件與電流輸出信號之間。The second pull-up driving component includes: a first transistor having a gate receiving the gate signal and a conducting path connected between receiving the first clock signal end and receiving the second clock signal, wherein one a second transistor is coupled between the receiving first clock signal terminal and the first transistor, the second transistor operates as a diode; and a third transistor having a second clock signal received The gate is coupled to a conduction path between the first and second transistor common nodes receiving the first clock signal end and the second pull-up driving element, wherein the common node is coupled to the third pull-up driving element. The third pull-up driving component includes: a first transistor having two ends connected to the first control signal; and a second transistor having a gate and a connection connected to a common node of the second pull-up driving component a conduction path between the first transistor and the second clock signal; a third transistor having a gate connected to the output signal of the adjacent subsequent stage and a connection between the pull-up element and the low-level end a conductive path; and a capacitor connected between the pull-up element and the current output signal.

在另一具體實施例中，第二上拉驅動元件包括：一第一電晶體，其具有接收閘極信號的一閘極與連接在一接收第一時脈信號端與一接收第二時脈信號端間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號端的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一電晶體間的一傳導路徑，其中第二上拉驅動元件的第一與第二電晶體的一共同節點連接到第一上拉驅動元件的 保持電晶體的閘極；一第三電晶體，其具有接收第二時脈信號的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一與第二電晶體共同節點間的一傳導路徑；一第四電晶體，其具有接收閘極信號的一閘極與連接在接收第一時脈信號端與接收第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在接收第一時脈信號端與控制件的第四電晶體之間，其中第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到第二電晶體的閘極；及一第六電晶體，其具有連接到第二節點的一閘極與連接在接收第一時脈信號端與第四與第五電晶體共同節點間的傳導路徑。In another embodiment, the second pull-up driving component includes: a first transistor having a gate receiving the gate signal and connected to receive the first clock signal end and receive the second clock signal a conductive path between the signal terminals; a second transistor having a gate receiving a second transistor control signal end and a first transistor connected to the first clock signal terminal and the second pull-up driving component a conductive path between the first and second transistors of the second pull-up driving element connected to the first pull-up driving element Holding a gate of the transistor; a third transistor having a gate receiving the second clock signal and first and second transistors connected to the first clock signal end and the second pull-up driving element a conductive path between the common nodes; a fourth transistor having a gate receiving the gate signal and a conducting path connected between the receiving the first clock signal end and receiving the second clock signal end; a five-electrode connected between the first clock signal receiving the first clock signal end and the fourth transistor of the control member, wherein the fifth transistor operates as a diode and a common node of the fourth and fifth transistors is connected a gate to the second transistor; and a sixth transistor having a gate connected to the second node and conducting between the first clock signal receiving terminal and the fourth and fifth transistor common node path.

在另一具體實施例中，第二上拉驅動元件包括：一第一電晶體，其具有接收閘極信號的一閘極與連接在一接收第一時脈信號端與一接收第二時脈信號端間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一電晶體間的一傳導路徑，其中第二上拉驅動元件的第一與第二電晶體的一共同節點連接到第一上拉驅動元件的保持電晶體的閘極；一第三電晶體，其具有接收第二時脈信號的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一與第二電晶體共同節點間的一傳導路徑；一第四電晶體，其具有接收閘極信號的一閘極與連接在接收第一時脈信號端與接收第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在接收第一時脈信號端與控制件的第 四電晶體之間，其中第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到第二電晶體的閘極；一第六電晶體，其具有連接到第二節點的一閘極與連接在接收第一時脈信號端與第四與第五電晶體共同節點間的一傳導路徑；及一第七電晶體，其具有連接到第四與第五電晶體共同節點的一閘極與連接在第一節點與一輸出閘極信號端間的一傳導路徑。In another embodiment, the second pull-up driving component includes: a first transistor having a gate receiving the gate signal and connected to receive the first clock signal end and receive the second clock signal a conductive path between the signal terminals; a second transistor having a gate receiving a second transistor control signal and a first transistor connected to the first clock signal terminal and the second pull-up driving component a conductive path between the first and second transistors of the second pull-up driving element connected to the gate of the first pull-up driving element holding the transistor; a third transistor having the receiving a gate of the second clock signal and a conduction path connected between the first and second transistor common nodes receiving the first clock signal end and the second pull-up driving element; a fourth transistor having a gate for receiving the gate signal and a conduction path connected between the first clock signal receiving end and the receiving second clock signal end; a fifth transistor connected to receive the first clock signal end and controlling Piece Between the four transistors, wherein the fifth transistor operates as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a connection a gate of the second node and a conduction path connected between the first clock signal terminal and the fourth and fifth transistor common nodes; and a seventh transistor having a fourth and fifth electricity connection A gate of the common node of the crystal and a conduction path connected between the first node and an output gate signal terminal.

在仍然另一具體實施例中，第二上拉驅動元件包括一第一電晶體，其具有接收閘極信號的一閘極與連接在接收第一時脈信號端接收第二時脈信號端間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一電晶體間的一傳導路徑，其中第二上拉驅動元件的第一與第二電晶體的一共同節點連接到第一上拉驅動元件的保持電晶體的閘極；一第三電晶體，其具有接收第二時脈信號的一閘極與連接在接收第一時脈信號端與第二上拉驅動元件的第一與第二電晶體的共同節點間的一傳導路徑；一第四電晶體，其具有接收閘極信號的一閘極與連接在接收第一時脈信號端與接收第二時脈信號端間的一傳導路徑；一第五電晶體連接在接收第一時脈信號端與控制件的第四電晶體之間，其中第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到第二電晶體的閘極；一第六電晶體，其具有連接到第二節點的一閘極與連接在接收第一時脈信號端與第四與第五電晶體共同節點間的一傳導路 徑；及一第七電晶體，其具有連接到第一與第二電晶體共同節點的一閘極與連接在第一節點與一輸出閘極信號端間的一傳導路徑。In still another specific embodiment, the second pull-up driving component includes a first transistor having a gate receiving the gate signal and connecting between receiving the first clock signal terminal and receiving the second clock signal terminal a conductive path; a second transistor having a gate receiving a second transistor control signal and a gate connected between the first transistor receiving the first clock signal end and the second pull-up driving component a conductive path, wherein a common node of the first and second transistors of the second pull-up driving element is connected to a gate of the first pull-up driving element that holds the transistor; and a third transistor that has a second receiving time a gate of the pulse signal and a conduction path connected between the first node of the first clock signal and the first and second transistors of the second pull-up driving element; a fourth transistor having a receiving gate a gate of the pole signal is connected to a conduction path between the receiving first clock signal end and receiving the second clock signal end; a fifth transistor is connected to receive the first clock signal end and the fourth of the control member Between the transistors, the fifth of which The body works like a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second node and connected Receiving a conduction path between the first clock signal end and the fourth and fifth transistor common nodes And a seventh transistor having a gate connected to the common node of the first and second transistors and a conduction path connected between the first node and an output gate signal terminal.

本發明的這些及其他目的、特徵與優點可從下列連同附圖描述的具體實施例而變得更明顯。These and other objects, features and advantages of the present invention will become apparent from

本發明的詳細描述具體實施例將在此揭示。然而，在此揭示的特殊結構與功能細節點只描述本發明具體實施例的目的。DETAILED DESCRIPTION OF THE INVENTION The specific embodiments are disclosed herein. However, the specific structural and functional details disclosed herein are merely illustrative of the specific embodiments of the invention.

圖4是根據本發明的一具體實施例而描述一位移暫存器方塊圖。位移暫存器包括：'N'級ASRC1 -ASRCN ，用以分別產生閘極信號(或掃描信號)GOUT1 -GOUTN ；與一虛擬級ASRCN+1 ，用以產生當作一控制信號以提供給前級ASRCN 的一虛擬閘極信號GDUMMY。4 is a block diagram depicting a shift register in accordance with an embodiment of the present invention. The shift register includes: 'N' level ASRC 1 -ASRC N for generating a gate signal (or scan signal) GOUT 1 -GOUT N respectively ; and a virtual stage ASRC N+1 for generating a control The signal is supplied to a virtual gate signal GDUMMY of the pre-stage ASRC N.

當一顯示面板(例如，液晶顯示面板)形成時，位移暫存器會在相平面上形成。顯示平面具在閘極線(或掃描線)與資料線所定義區域上形成的切換裝置。位移暫存器可輸出閘極信號GOUT1 -GOUTN ，其每一信號是當作一掃描信號提供給該等切換裝置之對應一者。When a display panel (for example, a liquid crystal display panel) is formed, the displacement register is formed on the phase plane. The display plane has switching means formed on the gate line (or scan line) and the area defined by the data line. The shift register can output gate signals GOUT 1 -GOUT N , each of which is provided as a scan signal to a corresponding one of the switching devices.

在位移暫存器中，該等ASRC1 -ASRCN 級的每一者具有第一與第二時脈端CK1 、CK2 ，用以接收外部提供的第一與第二時脈信號CKV、CKVB。第一與第二時脈信號CKV、CKV的每一者是彼此反相。相對級ASRC1 -ASRCN 亦具有：第一至第三控制信號CT1 -CT3 ，以接收對應的控制信號及一輸出 端OUT，以產生相對閘極信號GOUT1 -GOUTN 。In the shift register, each of the ASRC 1 -ASRC N stages has first and second clock terminals CK 1 , CK 2 for receiving externally provided first and second clock signals CKV, CKVB. Each of the first and second clock signals CKV, CKV is inverted from each other. The relative stages ASRC 1 -ASRC N also have first to third control signals CT 1 -CT 3 for receiving corresponding control signals and an output terminal OUT to generate relative gate signals GOUT 1 -GOUT N .

特別是，第一級ASRC1 是分別經由第一與第二時脈端CK1 、CK2 而接收第一與第二時脈信號CKV、CKVB。第一級ASRC1 亦經由第一與第三控制端CT1 、CT3 而接收一掃描開始信號STV及接收經由第二控制端CT2 而從下一級ASRC2 產生的一第二閘極信號GOUT2 。然後，第一級ASRC1 能輸出第一閘極信號GOUT1 以選擇第一閘極線。第一閘極信號GOUT1 亦提供給第二級ASRC2 的第一控制端CT1 。In particular, the first stage ASRC 1 receives the first and second clock signals CKV, CKVB via the first and second clock terminals CK 1 , CK 2 , respectively. The first stage ASRC 1 also receives a scan start signal STV via the first and third control terminals CT 1 , CT 3 and a second gate signal GOUT generated from the next stage ASRC 2 via the second control terminal CT 2 . 2 . Then, the first stage ASRC 1 can output the first gate signal GOUT 1 to select the first gate line. The first gate signal GOUT 1 is also supplied to the first control terminal CT 1 of the second stage ASRC 2 .

第二級ASRC2 是分別經由第二與第一時脈端CK2 、CK1 而接收第一與第二時脈信號CKV、CKVB。第二級ASRC2 是經由第一控制端CT1 而接收從第一單級ASRC1 產生的第一閘極信號GOUT1 與經由第二控制端CT2 而從第三級ASRC3 產生的一第三閘極信號GOUT3 。第二級ASRC2 亦經由第三控制端CT3 接收掃描開始信號STV。然後，第二級ASRC2 可輸出第二閘極信號GOUT2 以選擇第二閘極線。第二閘極信號GOUT2 是提供給第三級ASRC3 的第一控制端CT1 。The second stage ASRC 2 receives the first and second clock signals CKV, CKVB via the second and first clock terminals CK 2 , CK 1 , respectively. The second stage is the ASRC 2 receives the first gate signal GOUT generated from the first single-stage ASRC 1 via a first control terminal CT 1 1 to produce a second ASRC 3 and from the third stage via a second control terminal CT Three gate signal GOUT 3 . 2 also via the third control terminal of the second stage ASRC CT 3 receives the scan start signal STV. Then, the second stage ASRC 2 can output the second gate signal GOUT 2 to select the second gate line. The second gate signal GOUT 2 is supplied to the first control terminal CT 1 of the third stage ASRC 3 .

在類似方式中，第N級ASRCN 能分別經由第二與第一時脈端CK2 、CK1 而接收第一與第二時脈信號CKV、CKVB。第N級ASRCN 能經由第二控制端CT2 而接收從虛擬級ASRCN+1 產生的虛擬閘極信號GDUMMY。第N級ASRCN 亦經由第三控制端CT3 而接收掃描開始信號STV。第N級ASRCN 可輸出第N閘極信號GOUTN 以選擇第N閘極線。第N閘極信號GOUTN 亦提供給虛擬級ASRCN+1 的一第一控制端CT1 。In a similar manner, the Nth stage ASRC N can receive the first and second clock signals CKV, CKVB via the second and first clock terminals CK 2 , CK 1 , respectively. The Nth stage ASRC N can receive the virtual gate signal GDUMMY generated from the virtual stage ASRC N+1 via the second control terminal CT 2 . The Nth stage ASRC N also receives the scan start signal STV via the third control terminal CT 3 . The Nth stage ASRC N can output the Nth gate signal GOUT N to select the Nth gate line. The Nth gate signal GOUT N is also provided to a first control terminal CT 1 of the virtual stage ASRC N+ 1 .

在本發明的此具體實施例中，位移暫存器只需要三條匯 流排線以接收掃描開始信號STV、與第一與第二時脈信號CK、CKVB，以輸出用以選擇閘極線的閘極信號GOUT1 -GOUTN 。換句話說，位移暫存器不需要匯流排線接收在傳統位移暫存器中需要的接地位準與高位準電壓。In this embodiment of the invention, the shift register only needs three bus bars to receive the scan start signal STV and the first and second clock signals CK, CKVB to output the gate for selecting the gate line. The pole signal GOUT 1 -GOUT N . In other words, the displacement register does not require the bus bar to receive the ground level and high level voltage required in the conventional shift register.

透過減少在一位移暫存器的匯流排線數，由於在匯流排線間的耦合的雜訊能被減少，並獲得用以設計閘極驅動電路(或掃描驅動電路)的邊際。而且，可減少濕氣所引起的連接墊塊損害。By reducing the number of bus bars in a shift register, the noise of the coupling between the bus bars can be reduced, and the margin for designing the gate drive circuit (or scan drive circuit) can be obtained. Moreover, the damage of the connection pad caused by moisture can be reduced.

圖5描述圖4的位移暫存器單級電路圖，且圖6描述具有圖5單級的一位移暫存器電路圖。請即參考圖5與6，位移暫存器級200包括一上拉元件210、一下拉元件220、與第一、第二、第三上拉驅動元件230、250、240。極200可透過使用掃描開始信號STV與前級與下一級的輸出信號而輸出一閘級信號(或掃描信號)。FIG. 5 depicts a single stage circuit diagram of the shift register of FIG. 4, and FIG. 6 depicts a shift register circuit diagram having a single stage of FIG. Referring to Figures 5 and 6, the displacement register stage 200 includes a pull-up element 210, a pull-down element 220, and first, second, and third pull-up drive elements 230, 250, 240. The pole 200 can output a gate signal (or a scan signal) by using the scan start signal STV and the output signals of the previous stage and the next stage.

上拉元件210包括第一NMOS電晶體M1，其一汲極(或一第二電流電極)電連接到一第一時脈電端CK1；一源極(或第一電流電極)電連接到一輸出端GOUT。上拉元件210輸出閘極信號GOUT[N]。The pull-up element 210 includes a first NMOS transistor M1, a drain (or a second current electrode) is electrically connected to a first clock electrical terminal CK1; a source (or first current electrode) is electrically connected to the Output GOUT. The pull-up element 210 outputs a gate signal GOUT[N].

下拉元件220包括第二與第三NMOS電晶體M2、M3。第二NMOS電晶體M2具有一汲極與一閘極，此兩電極係電連接到輸出端GOUT。第三NMOS電晶體M3具有：一汲極，其電連接到第二NMOS電晶體M2的一源極；一源極極，其電連接到第一NMOS電晶體M1的汲極；及一閘極，其電連接到第二時脈信號端CK2。在下拉元件220中，第二NMOS電 晶體M2是如同二極體操作。The pull-down element 220 includes second and third NMOS transistors M2, M3. The second NMOS transistor M2 has a drain and a gate, and the two electrodes are electrically connected to the output terminal GOUT. The third NMOS transistor M3 has: a drain electrically connected to a source of the second NMOS transistor M2; a source pole electrically connected to the drain of the first NMOS transistor M1; and a gate, It is electrically connected to the second clock signal terminal CK2. In the pull-down element 220, the second NMOS Crystal M2 is operated like a diode.

第一上拉驅動元件230包括一第四NMOS電晶體M4。第四NMOS電晶體M4的閘極與汲極係電連接到一第一控制端CT1。第四NMOS電晶體M4的一源極係電連接到第一節點N1的電容器C。The first pull-up driving element 230 includes a fourth NMOS transistor M4. The gate and the drain of the fourth NMOS transistor M4 are electrically connected to a first control terminal CT1. A source of the fourth NMOS transistor M4 is electrically connected to the capacitor C of the first node N1.

第二上拉驅動零件250包括第八至第十NMOS電晶體M8-M10。第八NMOS電晶體M8包括：一源極，其經由第二節點N2而電連接到第二時脈信號端CK2及一閘極，其電連接到輸出端GOUT。第九NMOS電晶體M9包括共同連接到第一時脈信號端CK1的汲極與閘極。第九NMOS電晶體M9的一源極係電連接到第八NMOS電晶體M8的汲極。第十NMOS電晶體M10包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二時脈信號端CK2；及一源極，其電連接到第八NMOS電晶體M8的汲極與第九NMOS電晶體M9的源極。The second pull-up driving part 250 includes eighth to tenth NMOS transistors M8-M10. The eighth NMOS transistor M8 includes a source electrically connected to the second clock signal terminal CK2 and a gate via the second node N2, which is electrically connected to the output terminal GOUT. The ninth NMOS transistor M9 includes a drain and a gate connected in common to the first clock signal terminal CK1. A source of the ninth NMOS transistor M9 is electrically connected to the drain of the eighth NMOS transistor M8. The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the first The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9.

在此具體實施例中，第八NMOS電晶體M8具有大於第九NMOS電晶體M9的大小。換句話說，第八NMOS電晶體M8具有通道寬度(W)與通道長度(L)的比(W/L)是大於第九NMOS電晶體M9的比。當閘極信號GOUTN 是在一高位準狀態時，第八NMOS電晶體M8與第九NMOS電晶體M9可能同時導通。在此情況，一低位準輸入需要在第六NMOS電晶體M6的閘極上維持，以執行保持功能。為了要入將此達成，第八NMOS電晶體M8的W/L比要大於第九NMOS電晶體M9的W/L比。In this embodiment, the eighth NMOS transistor M8 has a larger size than the ninth NMOS transistor M9. In other words, the eighth NMOS transistor M8 has a ratio of the channel width (W) to the channel length (L) (W/L) which is greater than the ratio of the ninth NMOS transistor M9. When the gate signal GOUT N is in a high level state, the eighth NMOS transistor M8 and the ninth NMOS transistor M9 may be simultaneously turned on. In this case, a low level input needs to be maintained on the gate of the sixth NMOS transistor M6 to perform the hold function. In order to achieve this, the W/L ratio of the eighth NMOS transistor M8 is larger than the W/L ratio of the ninth NMOS transistor M9.

第三上拉驅動元件240包括一電容器C與第四至第七NMOS電晶體M5-M7。電容器C電連接到第一NMOS電晶體M1的一閘極與輸出端GOUT。第五NMOS電晶體M5的汲極與閘極係電連接到在第一節點N1的電容器C。第六NMOS電晶體M6的一汲極係電連接到第五NMOS電晶體M5的一源極。第六NMOS電晶體M6的一閘極係電連接到第一時脈信號端CK1。第六NMOS電晶體M6的一源極係電連接到一第二節點N2，其中該第二節點N2連接到一第二時脈信號端CK2。The third pull-up driving element 240 includes a capacitor C and fourth to seventh NMOS transistors M5-M7. The capacitor C is electrically connected to a gate of the first NMOS transistor M1 and an output terminal GOUT. The drain and gate of the fifth NMOS transistor M5 are electrically connected to the capacitor C at the first node N1. A drain of the sixth NMOS transistor M6 is electrically connected to a source of the fifth NMOS transistor M5. A gate of the sixth NMOS transistor M6 is electrically connected to the first clock signal terminal CK1. A source of the sixth NMOS transistor M6 is electrically connected to a second node N2, wherein the second node N2 is connected to a second clock signal terminal CK2.

第七NMOS電晶體M7的一汲極係電連接到在第一節點N1的電容器C。第七NMOS電晶體M7的一閘極係電連接到一第二控制端CT2。第七NMOS電晶體M7的一源極係電連接到一低位準端CT3或STV信號。在第三上拉驅動元件240中，第四與第五NMOS電晶體M5是如同二極體操作。A drain of the seventh NMOS transistor M7 is electrically connected to the capacitor C at the first node N1. A gate of the seventh NMOS transistor M7 is electrically connected to a second control terminal CT2. A source of the seventh NMOS transistor M7 is electrically coupled to a low level CT3 or STV signal. In the third pull-up driving element 240, the fourth and fifth NMOS transistors M5 operate as a diode.

當第一NMOS電晶體M1使用一非晶矽電晶體實施時，它便具有低電子移動率，所以第一NMOS電晶體M1需要有一足夠大小，以提供具一顯示裝置閘極線掃描信號，其中該等掃描信號在例如從大約20伏特到大約-14伏特範圍中具有一高電壓差。例如，在大約12.1吋(30.734公分)大小的一液晶顯示裝置的情況中，一閘極線的寄生電容是從大約250 pF至大約300 pF。在第一NMOS電晶體M1使用根據4微米最小設計規則所設計的一非晶矽電晶體實施的情況中，第一NMOS電晶體M1需要大約4微米通道長度(L)與大約5500微米通道寬度(W)。因此，在第一NMOS電晶體M1的閘極與汲 極之間的寄生電容會增加。When the first NMOS transistor M1 is implemented using an amorphous germanium transistor, it has a low electron mobility, so the first NMOS transistor M1 needs to have a sufficient size to provide a gate scan signal with a display device, wherein The scan signals have a high voltage difference in the range of, for example, from about 20 volts to about -14 volts. For example, in the case of a liquid crystal display device having a size of about 12.1 Å (30.734 cm), the parasitic capacitance of a gate line is from about 250 pF to about 300 pF. In the case where the first NMOS transistor M1 is implemented using an amorphous germanium transistor designed according to the 4 micron minimum design rule, the first NMOS transistor M1 requires a channel length (L) of about 4 micrometers and a channel width of about 5500 micrometers ( W). Therefore, the gate and the 汲 of the first NMOS transistor M1 The parasitic capacitance between the poles will increase.

在第一NMOS電晶體M1的閘極與汲極之間的寄生電容是大約3 pF的情況中，因為寄生電容是與從大約20伏特至大約-14伏特範圍的時脈信號CKV、CKVB電耦合，所以第一NMOS電晶體M1將不會正確操作，且它的工作如同一耦合電容器，如此可將一閘極信號施加到第一NMOS電晶體M1。如果沒有裝置將耦合電容器維持具有閘極關閉電壓VOFF，第一NMOS電晶體M1的一閘極電壓會在從大約20伏特至大約-14伏特範圍，且第一NMOS電晶體M1能產生具有'20伏特-Vth'最大值的一輸出(在此，Vth是第一NMOS電晶體M1的一閘極臨界電壓)。當此一輸出提供給一液晶顯示面板的閘極線時，顯示品質便會惡化。In the case where the parasitic capacitance between the gate and the drain of the first NMOS transistor M1 is about 3 pF, since the parasitic capacitance is electrically coupled with the clock signals CKV, CKVB ranging from about 20 volts to about -14 volts. Therefore, the first NMOS transistor M1 will not operate correctly, and it operates as the same coupling capacitor, so that a gate signal can be applied to the first NMOS transistor M1. If there is no device to maintain the coupling capacitor with the gate-off voltage VOFF, a gate voltage of the first NMOS transistor M1 may range from about 20 volts to about -14 volts, and the first NMOS transistor M1 can produce '20 An output of the volt-Vth' maximum (here, Vth is a gate threshold voltage of the first NMOS transistor M1). When this output is supplied to the gate line of a liquid crystal display panel, the display quality is deteriorated.

本發明的位移暫存器透過使用第六NMOS電晶體M6與第三NMOS電晶體M3以在第一NMOS電晶體M1的閘極上維持閘極關閉電壓VOFF而解決此一問題。第六NMOS電晶體M6執行將第一NMOS電晶體M1的閘極維持閘極關閉電壓VOFF的一保持操作。而且，在除了第一NMOS電晶體M1產生一主動閘極信號以激勵一對應像素時間週期之外的時間中，第三NMOS電晶體M3會將從第一NMOS電晶體M1的輸出閘極信號GOUT[N]下拉到閘極關閉電壓VOFF位準(或接地電壓位準)。The displacement register of the present invention solves this problem by using the sixth NMOS transistor M6 and the third NMOS transistor M3 to maintain the gate-off voltage VOFF on the gate of the first NMOS transistor M1. The sixth NMOS transistor M6 performs a holding operation of maintaining the gate of the first NMOS transistor M1 at the gate-off voltage VOFF. Moreover, in a time other than the first NMOS transistor M1 generating an active gate signal to excite a corresponding pixel time period, the third NMOS transistor M3 will output the gate signal GOUT from the first NMOS transistor M1. [N] Pull down to the gate turn-off voltage VOFF level (or ground voltage level).

在操作期間，從一前級提供的先前閘極信號GOUT[N-1]施加在如同二極體工作的第四NMOS電晶體M4操作。第四NMOS電晶體M4可接收如同一運送信號的先前閘極信號 GOUT[N-1]。第八NMOS電晶體M8能以一高位準的目前閘極信號GOUT[N]導通；結果，第六NMOS電晶體M6會關閉。另一方面，當目前閘極信號GOUT[N]是非活動狀態(即是，一低位準)時，第八NMOS電晶體M8便會維特一關閉狀態。在此情況，第九NMOS電晶體M9會如同二極體工作，所以一高位準信號能施加在第六NMOS電晶體M6。當第一時脈信號CK1是一低位準狀態，且第二時脈信號CK2是在一高位準狀態時，第十NMOS電晶體M10便會導通，所以一低位準信號能施加在第六NMOS電晶體M6。結果，第二上拉驅動元件240能將具有與第一時脈信號CK1相同相位的一控制信號提供給第六NMOS電晶體M6。During operation, the previous gate signal GOUT[N-1] supplied from a previous stage is applied to the fourth NMOS transistor M4 operating as a diode. The fourth NMOS transistor M4 can receive the previous gate signal as the same carrier signal GOUT[N-1]. The eighth NMOS transistor M8 can be turned on with a high level of the current gate signal GOUT[N]; as a result, the sixth NMOS transistor M6 is turned off. On the other hand, when the current gate signal GOUT[N] is inactive (ie, a low level), the eighth NMOS transistor M8 will be in a closed state. In this case, the ninth NMOS transistor M9 operates as a diode, so a high level signal can be applied to the sixth NMOS transistor M6. When the first clock signal CK1 is in a low level state, and the second clock signal CK2 is in a high level state, the tenth NMOS transistor M10 is turned on, so a low level signal can be applied to the sixth NMOS battery. Crystal M6. As a result, the second pull-up driving element 240 can supply a control signal having the same phase as the first clock signal CK1 to the sixth NMOS transistor M6.

由於NMOS電晶體的大電容，所以第一NMOS電晶體M1可執行維持一低位準的功能。當第一時脈信號CKV從一低位準狀態改變成一高位準狀態時，第六NMOS電晶體M6便可執行保持操作，以避免第一NMOS電晶體M1的一閘極電壓變成一較高臨界電壓。明確而言，當第一時脈信號CKV從一低位準狀態改變成一高位準狀態時，目前閘極信號GOUT[N]會在一高位準狀態，藉使第八NMOS電晶體M8導通。因此，既然第六NMOS電晶體M6的閘極是在一低位準狀態，所以電連接到第八NMOS電晶體M8汲極的第六NMOS電晶體M6會關閉。Due to the large capacitance of the NMOS transistor, the first NMOS transistor M1 can perform a function of maintaining a low level. When the first clock signal CKV changes from a low level state to a high level state, the sixth NMOS transistor M6 can perform a holding operation to prevent a gate voltage of the first NMOS transistor M1 from becoming a higher threshold voltage. . Specifically, when the first clock signal CKV changes from a low level state to a high level state, the current gate signal GOUT[N] will be in a high level state, and the eighth NMOS transistor M8 is turned on. Therefore, since the gate of the sixth NMOS transistor M6 is in a low level state, the sixth NMOS transistor M6 electrically connected to the drain of the eighth NMOS transistor M8 is turned off.

第七NMOS電晶體M7能經由它的閘極而接收下一閘極信號GOUT[N+1]，並響應下一閘極信號GOUT[N+1]而將電容器C放電到閘極關閉電壓位準VOFF。當第七NMOS電晶體 M7導通時，閘極關閉電壓位準VOFF的掃描開始信號STV能施加在第七NMOS電晶體M7的源極。The seventh NMOS transistor M7 can receive the next gate signal GOUT[N+1] via its gate and discharge the capacitor C to the gate turn-off voltage level in response to the next gate signal GOUT[N+1] Quasi VOFF. When the seventh NMOS transistor When M7 is turned on, the scan start signal STV of the gate turn-off voltage level VOFF can be applied to the source of the seventh NMOS transistor M7.

如前述，具有非晶矽電晶體的位移暫存器在沒有可供應閘極關閉電壓VOFF與閘極導通電壓VON的分開電壓線而可產生閘極信號。As described above, the displacement register having the amorphous germanium transistor can generate a gate signal without a separate voltage line that can supply the gate turn-off voltage VOFF and the gate turn-on voltage VON.

圖7是根據本發明另一具體實施例而描述一位移暫存器單級電路圖，且圖8描述包括圖7單級的一位移暫存器電路圖。在圖7中，與圖5顯示的相同元件是以相同參考數字表示，並可避免重複描述，因此，不詳細描述。FIG. 7 is a single-stage circuit diagram of a shift register according to another embodiment of the present invention, and FIG. 8 is a circuit diagram of a shift register including a single stage of FIG. In FIG. 7, the same elements as those shown in FIG. 5 are denoted by the same reference numerals, and a repetitive description may be avoided, and thus, a detailed description will not be given.

請即參考圖7與8，本發明的一位移暫存器單級包括一上拉元件210、一下拉元件220、一第一第一上拉驅動元件230、一第二上拉驅動元件350、與一第三上拉驅動元件240。單級300可透過使用一掃描開始信號STV、一前級的先前輸出信號GOUT[N-1]、與下一級的下一輸出信號GOUT[N+1]而輸出一閘極信號(或掃描信號)。在此具體實施例中，上拉元件210、下拉元件220、第一上拉驅動元件230、與第三上拉驅動元件240具有分別與上拉元件210、下拉元件220、第一上拉驅動元件230、與圖5第三上拉驅動元件240實質相同的功能與結構。因此，有關圖7的上拉元件210、下拉元件220、與第一上拉驅動元件230的進一步描述將省略。Referring to FIGS. 7 and 8, a single stage of a displacement register of the present invention includes a pull-up element 210, a pull-down element 220, a first first pull-up driving element 230, a second pull-up driving element 350, And a third pull-up driving element 240. The single stage 300 can output a gate signal (or a scan signal by using a scan start signal STV, a previous output signal GOUT[N-1] of the previous stage, and a next output signal GOUT[N+1] of the next stage. ). In this embodiment, the pull-up element 210, the pull-down element 220, the first pull-up driving element 230, and the third pull-up driving element 240 have a pull-up element 210, a pull-down element 220, and a first pull-up driving element, respectively. 230, substantially the same function and structure as the third pull-up driving element 240 of FIG. Therefore, further description regarding the pull-up element 210, the pull-down element 220, and the first pull-up driving element 230 of FIG. 7 will be omitted.

第二上拉驅動元件350包括第八至第十三NMOS電晶體M8-M13。第八NMOS電晶體M8包括：一源極，其電連接到第二節點N2，且該第二節點N2連接到第二時脈信號端 CK2；及一閘極，其電連接到輸出端GOUT。第九NMOS電晶體M9包括：一汲極，其電連接到第一時脈信號端CK1；及一源極，其電連接到第八NMOS電晶體M8的一汲極。第十NMOS電晶體M10包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二時脈信號端CK2；及一源極，其電連接到第八NMOS電晶體M8的汲極與第九NMOS電晶體M9的源極。The second pull-up driving element 350 includes eighth to thirteenth NMOS transistors M8-M13. The eighth NMOS transistor M8 includes: a source electrically connected to the second node N2, and the second node N2 is connected to the second clock signal end CK2; and a gate electrically connected to the output terminal GOUT. The ninth NMOS transistor M9 includes: a drain electrically connected to the first clock signal terminal CK1; and a source electrically connected to a drain of the eighth NMOS transistor M8. The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the first The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9.

第十一NMOS電晶體M11包括：一源極，其電連接到第二時脈信號端CK2；及一閘極，其電連接到第八NMOS電晶體M8的閘極。第十二NMOS電晶體M12包括：汲極與閘極，其共同連接到第一時脈信號端CK1；及一源極，其電連接到第九NMOS電晶體M9的閘極與第十一NMOS電晶體M11的汲極。第十三NMOS電晶體M13包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二時脈信號端CK2；及一源極，其電連接到第十一NMOS電晶體M11的汲極與第十二NMOS電晶體M12的源極。The eleventh NMOS transistor M11 includes: a source electrically connected to the second clock signal terminal CK2; and a gate electrically connected to the gate of the eighth NMOS transistor M8. The twelfth NMOS transistor M12 includes: a drain and a gate connected to the first clock signal terminal CK1 in common; and a source electrically connected to the gate of the ninth NMOS transistor M9 and the eleventh NMOS The drain of the transistor M11. The thirteenth NMOS transistor M13 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to The drain of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12.

操作上，當目前閘極信號GOUT[N]是在一主動狀態(即是，一高位準狀態)，所以第八NMOS電晶體M8導通時，第六NMOS電晶體M6便會維持關閉狀態。在此情況，一低電壓便會施加在第九NMOS電晶體M9的閘極。明確而言，既然第八NMOS電晶體M8與第十一NMOS電晶體M11的閘極能接收電電流輸出信號GOUT[N]，所以他們會導通。因此，電連接到第八NMOS電晶體M8汲極與第十一NMOS電晶體M11汲極的第九NMOS電晶體M9會關閉，藉此增加通道阻 抗。因此，即使當第九NMOS電晶體M9與第八NMOS電晶體M8同時導通，一低位準信號能施加在第六NMOS電晶體M6。In operation, when the current gate signal GOUT[N] is in an active state (ie, a high level state), the sixth NMOS transistor M6 is maintained in a closed state when the eighth NMOS transistor M8 is turned on. In this case, a low voltage is applied to the gate of the ninth NMOS transistor M9. Specifically, since the gates of the eighth NMOS transistor M8 and the eleventh NMOS transistor M11 can receive the electrical current output signal GOUT[N], they are turned on. Therefore, the ninth NMOS transistor M9 electrically connected to the drain of the eighth NMOS transistor M8 and the drain of the eleventh NMOS transistor M11 is turned off, thereby increasing the channel resistance. anti. Therefore, even when the ninth NMOS transistor M9 and the eighth NMOS transistor M8 are simultaneously turned on, a low level signal can be applied to the sixth NMOS transistor M6.

當目前閘極信號GOUT[N]是在一非主動狀態(即是，一低位準狀態)時，第八NMOS電晶體M8便維特關閉狀態，且第六NMOS電晶體M6能在它的閘極上接收一控制信號，且該控制信號的相位是與第一時脈信號CKV相同。明確而言，既然第二時脈信號端CK2是在一主動狀態，所以電連接到第二時脈信號端CK2的第十NMOS電晶體M10與第十三NMOS電晶體M13會導通。因此，第九NMOS電晶體M9的閘極是一低位準，藉使第六NMOS電晶體M6關閉。When the current gate signal GOUT[N] is in an inactive state (ie, a low level state), the eighth NMOS transistor M8 is in a Veter state, and the sixth NMOS transistor M6 can be on its gate. A control signal is received, and the phase of the control signal is the same as the first clock signal CKV. Specifically, since the second clock signal terminal CK2 is in an active state, the tenth NMOS transistor M10 and the thirteenth NMOS transistor M13 electrically connected to the second clock signal terminal CK2 are turned on. Therefore, the gate of the ninth NMOS transistor M9 is at a low level, so that the sixth NMOS transistor M6 is turned off.

在此具體實施例中，具有第八至第十三NMOS電晶體M8-M13的第二上拉驅動元件350能產生使第六NMOS電晶體M6導通以執行一保持操作的控制信號。In this embodiment, the second pull-up driving element 350 having the eighth to thirteenth NMOS transistors M8-M13 can generate a control signal that turns on the sixth NMOS transistor M6 to perform a holding operation.

第一NMOS電晶體M1可執行將第一時脈信號CKV取樣的功能。換句話說，第一NMOS電晶體M1可透過寄生電容執行第一時脈信號CKV維持一低位準的功能。而且，當第一時脈信號CKV從一低位準改變成一高位準時，第六NMOS電晶體M6便會執行保持操作。換句話說，第六NMOS電晶體M6可避免第一NMOS電晶體M1的閘極超過第一NMOS電晶體M1的臨界電壓。The first NMOS transistor M1 can perform a function of sampling the first clock signal CKV. In other words, the first NMOS transistor M1 can perform a function of maintaining a low level of the first clock signal CKV through the parasitic capacitance. Moreover, when the first clock signal CKV is changed from a low level to a high level, the sixth NMOS transistor M6 performs a holding operation. In other words, the sixth NMOS transistor M6 can prevent the gate of the first NMOS transistor M1 from exceeding the threshold voltage of the first NMOS transistor M1.

當第九NMOS電晶體M9的W/L比增加時，用以使第六NMOS電晶體M6導通的時間常數便會減少。在此具體實施例中，第九NMOS電晶體M9的W/L比大於第八NMOS電晶體 M8，如此便減少第六NMOS電晶體M6的時間常數。When the W/L ratio of the ninth NMOS transistor M9 is increased, the time constant for turning on the sixth NMOS transistor M6 is reduced. In this embodiment, the W/L ratio of the ninth NMOS transistor M9 is greater than the eighth NMOS transistor. M8, thus reducing the time constant of the sixth NMOS transistor M6.

圖9是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖，且圖10描述包括圖9單級的一位移暫存器電路圖。請即參考圖9與10，單級400包括一上拉元件210、一下拉元件220、一第一上拉驅動元件430、一第二上拉驅動元件440、與一第三上拉驅動元件450。單級400可接收第一與第二時脈信號CKV、CKVB、前級與下一級GOUT[N-1]、GOUT[N+1]輸出的閘極信號、與掃描開始信號STV以輸出閘極信號GOUT[N]。在此具體實施例中，上拉元件210與下拉元件220的功能與結構是實質與圖5的上拉元件210與下拉元件220相同，因此，省略詳細描述。9 is a single-stage circuit diagram of a shift register in accordance with another embodiment of the present invention, and FIG. 10 depicts a shift register circuit diagram including a single stage of FIG. Referring to FIGS. 9 and 10 , the single stage 400 includes a pull-up element 210 , a pull-down element 220 , a first pull-up drive component 430 , a second pull-up drive component 440 , and a third pull-up drive component 450 . . The single stage 400 can receive the first and second clock signals CKV, CKVB, the gate signals of the preamplifier and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output the gate Signal GOUT[N]. In this embodiment, the functions and structures of the pull-up element 210 and the pull-down element 220 are substantially the same as the pull-up element 210 and the pull-down element 220 of FIG. 5, and thus, a detailed description is omitted.

第一上拉驅動元件430包括一第六NMOS電晶體M6、一第七NMOS電晶體M7、與一電容器C。相較於圖5的暫存器級，圖5的第三上拉驅動元件240的第五NMOS電晶體M5未包括在圖9的具體實施例。The first pull-up driving component 430 includes a sixth NMOS transistor M6, a seventh NMOS transistor M7, and a capacitor C. The fifth NMOS transistor M5 of the third pull-up driving element 240 of FIG. 5 is not included in the specific embodiment of FIG. 9 as compared to the register stage of FIG.

在第三上拉驅動元件450中，第四NMOS電晶體M4具有：閘極與汲極，其共同連接到第一控制信號CT1以接收先前閘極信號GOUT[N-1]及一源極，其電連接到第一節點N1，且該第一節點N1連接到在上拉元件210中的第一NMOS電晶體M1的閘極。第六NMOS電晶體M6包括：一汲極，其電連接到第一節點N1；一源極，其電連接到輸出端GOUT與一閘極，以接收來自第二上拉驅動元件440的信號。In the third pull-up driving element 450, the fourth NMOS transistor M4 has: a gate and a drain, which are commonly connected to the first control signal CT1 to receive the previous gate signal GOUT[N-1] and a source, It is electrically connected to the first node N1, and the first node N1 is connected to the gate of the first NMOS transistor M1 in the pull-up element 210. The sixth NMOS transistor M6 includes: a drain electrically connected to the first node N1; a source electrically coupled to the output terminal GOUT and a gate to receive a signal from the second pull-up driving component 440.

第七NMOS電晶體M7包括：一汲極，其電連接到第一節點N1；一源極，其電連接到第三控制端CT3以接收掃描開 始信號STV；及一閘極，其連接到第二控制端CT2以接收來自下一級的下一閘極信號GOUT[N+1]。電容器C是電連接在第一節點N1與輸出端GOUT之間。The seventh NMOS transistor M7 includes: a drain electrically connected to the first node N1; a source electrically connected to the third control terminal CT3 to receive the scan The start signal STV; and a gate connected to the second control terminal CT2 to receive the next gate signal GOUT[N+1] from the next stage. The capacitor C is electrically connected between the first node N1 and the output terminal GOUT.

第二上拉驅動元件440包括第八、第九與第十NMOS電晶體M8、M9、M10。第八NMOS電晶體M8包括：一源極，其電連接到到第二節點N2，且該第二節點N2連接到第二時脈信號端CK2以接收第二時脈信號CKVB；及一閘極，其電連接到輸出端GOUT與第六NMOS電晶體M6的源極。The second pull-up driving element 440 includes eighth, ninth, and tenth NMOS transistors M8, M9, M10. The eighth NMOS transistor M8 includes: a source electrically connected to the second node N2, and the second node N2 is coupled to the second clock signal terminal CK2 to receive the second clock signal CKVB; and a gate It is electrically connected to the output terminal GOUT and the source of the sixth NMOS transistor M6.

第九NMOS電晶體M9包括一源極，其電連接到第八NMOS電晶體M8的一汲極；及汲極與閘極，其共同連接到第一時脈信號端CK1以接收第一時脈信號CKV。第十NMOS電晶體M10包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二時脈信號端CK2；及一源極，其電連接到第八NMOS電晶體M8的汲極與第九NMOS電晶體M9的源極。第十NMOS電晶體M10的源極亦電連接到第六NMOS電晶體M6的閘極。The ninth NMOS transistor M9 includes a source electrically connected to a drain of the eighth NMOS transistor M8, and a drain and a gate connected in common to the first clock signal terminal CK1 to receive the first clock. Signal CKV. The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the first The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9. The source of the tenth NMOS transistor M10 is also electrically connected to the gate of the sixth NMOS transistor M6.

操作上，第八NMOS電晶體M8能響應目前閘極信號GOUT[N]而導通或關閉。當目前閘極信號GOUT[N]是在一主動狀態(即是，一高位準)時，第八NMOS電晶體M8便會維特一導通狀態，所以第六NMOS電晶體M6會關閉。另一方面，當目前閘極信號GOUT[N]是在一非主動狀態(即是，一低位準)時，第八NMOS電晶體M8便會維特一關閉狀態。在此情況，具有與第一時脈信號CKV相同相位的一控制信號可施加於來自第二上拉驅動元件440的第六NMOS電晶體 M6。換句話說，既然第九NMOS電晶體M9能如同二極體工作，所以當第一時脈信號CKV是在一高位準狀態時，高位準信號便能施加在第六NMOS電晶體M6。當第一時脈信號CKV是在一低位準狀態時，與第一時脈信號CKV反相的第二時脈信號CKVB是在一高位準狀態，所以第十NMOS電晶體M10會導通。結果，一低位準信號能施加在第六NMOS電晶體M6。因此，第二上拉驅動元件440可將具有與第一時脈信號CKV相同相位的一控制信號提供給第六NMOS電晶體M6的閘極。In operation, the eighth NMOS transistor M8 can be turned on or off in response to the current gate signal GOUT[N]. When the current gate signal GOUT[N] is in an active state (ie, a high level), the eighth NMOS transistor M8 will be in a conducting state, so the sixth NMOS transistor M6 will be turned off. On the other hand, when the current gate signal GOUT[N] is in an inactive state (ie, a low level), the eighth NMOS transistor M8 will be in a closed state. In this case, a control signal having the same phase as the first clock signal CKV can be applied to the sixth NMOS transistor from the second pull-up driving element 440. M6. In other words, since the ninth NMOS transistor M9 can operate as a diode, when the first clock signal CKV is in a high level state, a high level signal can be applied to the sixth NMOS transistor M6. When the first clock signal CKV is in a low level state, the second clock signal CKVB inverted from the first clock signal CKV is in a high level state, so the tenth NMOS transistor M10 is turned on. As a result, a low level signal can be applied to the sixth NMOS transistor M6. Therefore, the second pull-up driving element 440 can supply a control signal having the same phase as the first clock signal CKV to the gate of the sixth NMOS transistor M6.

在此具體實施例中，當第六NMOS電晶體M6維持關閉狀態時，一高位準電壓便會施加在第六NMOS電晶體M6的源極，且當第六NMOS電晶體M6維持導通狀態時，一低位準電壓便會施加在第六NMOS電晶體M6的源極。In this embodiment, when the sixth NMOS transistor M6 is maintained in the off state, a high level voltage is applied to the source of the sixth NMOS transistor M6, and when the sixth NMOS transistor M6 is maintained in the on state, A low level voltage is applied to the source of the sixth NMOS transistor M6.

圖11是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖，且圖12描述包括圖11單級的一位移暫存器電路圖。請即參考圖11與12，單級500包括一上拉元件210、一下拉元件220、一第一上拉驅動元件430、一第二上拉驅動元件350與一第三上拉驅動元件440。單級500可接收第一與第二時脈信號CKV、CKVB、與從前級與下一級GOUT[N-1]、GOUT[N+1]輸出的閘極信號、與掃描開始信號STV，以輸出閘極信號GOUT[N]。11 is a single-stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention, and FIG. 12 depicts a shift register circuit diagram including a single stage of FIG. Referring to FIGS. 11 and 12, the single stage 500 includes a pull-up component 210, a pull-down component 220, a first pull-up drive component 430, a second pull-up drive component 350, and a third pull-up drive component 440. The single stage 500 can receive the first and second clock signals CKV, CKVB, the gate signals output from the previous stage and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output Gate signal GOUT[N].

在此具體實施例中，上拉元件210與下拉元件220的功能與結構是實質與圖5的上拉元件210與下拉元件220相同。圖11的第一上拉驅動元件430與第三上拉上拉驅動元件440的 功能與結構是實質與圖9的第一上拉驅動元件430與第三上拉驅動元件450相同。圖11的第二上拉驅動元件350的功能與結構是實質與圖7的第二上拉驅動元件350相同。因此，上拉元件210、下拉元件220、第一上拉驅動元件430與第三上拉驅動元件440的詳細描述將省略。In this particular embodiment, the function and structure of pull-up element 210 and pull-down element 220 are substantially the same as pull-up element 210 and pull-down element 220 of FIG. The first pull-up driving element 430 of FIG. 11 and the third pull-up pull-up driving element 440 The function and structure are substantially the same as the first pull-up driving element 430 and the third pull-up driving element 450 of FIG. The function and structure of the second pull-up drive element 350 of FIG. 11 is substantially the same as the second pull-up drive element 350 of FIG. Therefore, a detailed description of the pull-up element 210, the pull-down element 220, the first pull-up driving element 430, and the third pull-up driving element 440 will be omitted.

在此具體實施例中，第九NMOS電晶體M9的大小(即是，W/L比)較大於第八NMOS電晶體M8。此是因為如果第九NMOS電晶體M9的大小會較小於第八NMOS電晶體M8，使第六NMOS電晶體M6導通的時間常數便會增加。因此，第九NMOS電晶體M9的大小會較大於第八NMOS電晶體M8的大小，以減少時間常數。In this embodiment, the size of the ninth NMOS transistor M9 (ie, the W/L ratio) is larger than the eighth NMOS transistor M8. This is because if the size of the ninth NMOS transistor M9 is smaller than that of the eighth NMOS transistor M8, the time constant for turning on the sixth NMOS transistor M6 is increased. Therefore, the size of the ninth NMOS transistor M9 is larger than the size of the eighth NMOS transistor M8 to reduce the time constant.

圖13是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖，且圖14描述包括圖13單級的一位移暫存器電路圖。請即參考圖13與14，單級600包括一上拉元件210、一下拉元件220、一第一上拉驅動元件230、一第二上拉驅動元件640、與一第三上拉驅動元件240。單級600可接收第一與第二時脈信號CKV、CKVB、從前級與下一級GOUT[N-1]、GOUT[N+1]輸出的閘極信號、與掃描開始信號STV，以輸出閘極信號GOUT[N]。Figure 13 is a single stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention, and Figure 14 depicts a shift register circuit diagram including a single stage of Figure 13. Referring to FIGS. 13 and 14, the single stage 600 includes a pull-up element 210, a pull-down element 220, a first pull-up drive component 230, a second pull-up drive component 640, and a third pull-up drive component 240. . The single stage 600 can receive the first and second clock signals CKV, CKVB, the gate signals output from the previous stage and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output the gate The pole signal GOUT[N].

在此具體實施例中，上拉元件210、下拉元件220、第一上拉驅動元件230與第三上拉驅動元件240的功能與結構是實質與圖5的下拉元件220、第一上拉驅動元件230與一三上拉驅動元件240相同。因此，將省略詳細描述以避免重複。In this embodiment, the functions and structures of the pull-up element 210, the pull-down element 220, the first pull-up driving element 230, and the third pull-up driving element 240 are substantially the same as the pull-down element 220 of FIG. 5, and the first pull-up driving. Element 230 is identical to a three pull-up drive element 240. Therefore, the detailed description will be omitted to avoid redundancy.

第二上拉驅動元件640包括第八至第十四NMOS電晶體 M8-M14。第八NMOS電晶體M8包括一源極，其電連接到第二節點，且該第二節點連接到第二時脈信號端CK2以接收第二時脈信號CKVB；及一閘極，其電連接到輸出端GOUT。第九NMOS電晶體M9包括：一汲極，其電連接到第一時脈信號端CK1以接收第一時脈信號CKV及一源極，其電連接到第八NMOS電晶體M8的一汲極。第十NMOS電晶體M10包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二節點N2的第二時脈信號端CK2；及一源極，其電連接到第八NMOS電晶體M8的汲極與第九NMOS電晶體M9的源極。第十NMOS電晶體M10的源極亦連接到第六NMOS電晶體M6的閘極。The second pull-up driving element 640 includes eighth to fourteenth NMOS transistors M8-M14. The eighth NMOS transistor M8 includes a source electrically connected to the second node, and the second node is connected to the second clock signal terminal CK2 to receive the second clock signal CKVB; and a gate electrically connected To the output GOUT. The ninth NMOS transistor M9 includes: a drain electrically connected to the first clock signal terminal CK1 to receive the first clock signal CKV and a source electrically connected to a drain of the eighth NMOS transistor M8 . The tenth NMOS transistor M10 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2 of the second node N2; and a source, It is electrically connected to the drain of the eighth NMOS transistor M8 and the source of the ninth NMOS transistor M9. The source of the tenth NMOS transistor M10 is also connected to the gate of the sixth NMOS transistor M6.

第十一NMOS電晶體M11包括：一源極，其電連接到第二時脈信號端CK2；及一閘極，其電連接到第八NMOS電晶體M8的閘極。第十二NMOS電晶體M12包括：一源極，其電連接到第九NMOS電晶體M9的閘極與第十一NMOS電晶體M11的汲極；及汲極與閘極，其共同連接到第一時脈信號端CK1。The eleventh NMOS transistor M11 includes: a source electrically connected to the second clock signal terminal CK2; and a gate electrically connected to the gate of the eighth NMOS transistor M8. The twelfth NMOS transistor M12 includes: a source electrically connected to the gate of the ninth NMOS transistor M9 and the drain of the eleventh NMOS transistor M11; and the drain and the gate, which are connected to the first One clock signal terminal CK1.

第十三NMOS電晶體M13電包括：一汲極，其電連接到第一時脈信號CK1；一閘極，其電連接到第二時脈信號CK2；及一源極，其電連接到第十一NMOS電晶體M11的一汲極與第十二NMOS電晶體M12的一源極。第十四NMOS電晶體M14電包括：一汲極，其電連接到第一節點N1；一閘極，其電連接到第十二與第十三NMOS電晶體M12、M13的源極、與第九NMOS電晶體M9的閘極；及一源極，其電連接 到輸出端GOUT。The thirteenth NMOS transistor M13 includes: a drain electrically connected to the first clock signal CK1; a gate electrically connected to the second clock signal CK2; and a source electrically connected to the first A drain of the eleven NMOS transistor M11 and a source of the twelfth NMOS transistor M12. The fourteenth NMOS transistor M14 includes: a drain electrically connected to the first node N1; a gate electrically connected to the sources of the twelfth and thirteenth NMOS transistors M12, M13, and The gate of the nine NMOS transistor M9; and a source, the electrical connection To the output GOUT.

如圖13所示，即使當施加在第十四NMOS電晶體M14的閘極電連接到輸出端GOUT的一電壓不同於施加在第六NMOS電晶體M6閘極的電壓，使第六NMOS電晶體M6導通的一電壓可產生。As shown in FIG. 13, even when a voltage applied to the gate of the fourteenth NMOS transistor M14 is electrically connected to the output terminal GOUT is different from the voltage applied to the gate of the sixth NMOS transistor M6, the sixth NMOS transistor is made. A voltage that is turned on by M6 can be generated.

在此具體實施例中，第一NMOS電晶體M1可執行將第一時脈信號CKV取樣的功能。換句話說，由於NMOS電晶體的一電容，所以第一NMOS電晶體M1可執行一取樣功能以維持低位準。當第一時脈信號CKV從一低位準改變成一高位準時，第六NMOS電晶體M6可執行保持操作，例如避免第一NMOS電晶體M1的閘極超過第一NMOS電晶體M1的臨界電壓。In this embodiment, the first NMOS transistor M1 can perform the function of sampling the first clock signal CKV. In other words, due to a capacitance of the NMOS transistor, the first NMOS transistor M1 can perform a sampling function to maintain a low level. When the first clock signal CKV changes from a low level to a high level, the sixth NMOS transistor M6 can perform a holding operation, for example, to prevent the gate of the first NMOS transistor M1 from exceeding the threshold voltage of the first NMOS transistor M1.

圖15是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖，且圖16描述包括圖15單級的一位移暫存器電路圖。Figure 15 is a single stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention, and Figure 16 depicts a shift register circuit diagram including a single stage of Figure 15.

請即參考圖15與16，單級700包括一上拉元件210、一下拉元件220、一第一上拉驅動元件230、一第二上拉驅動元件740與一第三上拉驅動元件240。單級700可接收第一與第二時脈信號CKV、CKVB、從前級與下一級GOUT[N-1]、GOUT[N+1]輸出的閘極信號、與掃描開始信號STV以輸出閘極信號GOUT[N]。在此具體實施例中，上拉元件210、下拉元件220、第一上拉驅動元件230與一第三上拉驅動元件240的功能與結構是實質與圖5的上拉元件210、下拉元件220、第一上拉驅動元件230與第三上拉驅動元件240相同。 因此，將省略詳細描述以避免重複。Referring to FIGS. 15 and 16, the single stage 700 includes a pull-up element 210, a pull-down element 220, a first pull-up drive element 230, a second pull-up drive element 740, and a third pull-up drive element 240. The single stage 700 can receive the first and second clock signals CKV, CKVB, the gate signals output from the previous stage and the next stage GOUT[N-1], GOUT[N+1], and the scan start signal STV to output the gate Signal GOUT[N]. In this embodiment, the functions and structures of the pull-up element 210, the pull-down element 220, the first pull-up driving element 230, and the third pull-up driving element 240 are substantially the same as the pull-up element 210 and the pull-down element 220 of FIG. The first pull-up driving element 230 is the same as the third pull-up driving element 240. Therefore, the detailed description will be omitted to avoid redundancy.

第二上拉驅動元件740包括第八至第十四NMOS電晶體M8-M14。第八NMOS電晶體M8包括：一源極，其電連接到第二時脈信號端CK2；及一閘極，其電連接到輸出端GOUT。第九NMOS電晶體M9包括：一汲極，其電連接到第一時脈信號端CK1；及一源極，其電連接到第八NMOS電晶體M8的一汲極。The second pull-up driving element 740 includes eighth to fourteenth NMOS transistors M8-M14. The eighth NMOS transistor M8 includes: a source electrically connected to the second clock signal terminal CK2; and a gate electrically connected to the output terminal GOUT. The ninth NMOS transistor M9 includes: a drain electrically connected to the first clock signal terminal CK1; and a source electrically connected to a drain of the eighth NMOS transistor M8.

第十NMOS電晶體包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二時脈信號端CK2；及一源極，其電連接到第八NMOS電晶體M8的汲極與第九NMOS電晶體M9的源極。第十一NMOS電晶體M11包括：一源極，其電連接到第二時脈信號端CK2及一閘極，其電連接到第八NMOS電晶體M8的閘極。The tenth NMOS transistor comprises: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to the eighth The drain of the NMOS transistor M8 and the source of the ninth NMOS transistor M9. The eleventh NMOS transistor M11 includes a source electrically connected to the second clock signal terminal CK2 and a gate electrically connected to the gate of the eighth NMOS transistor M8.

第十二NMOS電晶體M12包括：一源極，其電連接到第九NMOS電晶體M9的閘極；及汲極與閘極，其共同連接到第一時脈信號端CK1。第十三NMOS電晶體M13包括：一汲極，其電連接到第一時脈信號端CK1；一閘極，其電連接到第二時脈信號端CK2；及一源極，其電連接到第十一NMOS電晶體M11的汲極與第十二NMOS電晶體M12的源極。The twelfth NMOS transistor M12 includes: a source electrically connected to the gate of the ninth NMOS transistor M9; and a drain and a gate connected in common to the first clock signal terminal CK1. The thirteenth NMOS transistor M13 includes: a drain electrically connected to the first clock signal terminal CK1; a gate electrically connected to the second clock signal terminal CK2; and a source electrically connected to The drain of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12.

第十四NMOS電晶體M14電包括：一汲極，其電連接到輸出端GOUT；一閘極，其電連接到第九與第十NMOS電晶體M9與M10的源極；及一源極，其電連接到第三上拉驅動元件與電容器(C)末端部分的第四NMOS電晶體M4汲極。The fourteenth NMOS transistor M14 includes: a drain electrically connected to the output terminal GOUT; a gate electrically connected to the sources of the ninth and tenth NMOS transistors M9 and M10; and a source, It is electrically connected to the third pull-up driving element and the fourth NMOS transistor M4 of the end portion of the capacitor (C).

如圖15所示，即使當施加在電連接到輸出端GOUT[N]的第十四NMOS電晶體M14閘極的一電壓是不同於施加在第六NMOS電晶體M6的閘極，其中該第六NMOS電晶體M6電連接到如同二極體工作的第五NMOS電晶體M5，以產生使第六NMOS電晶體M6導通的一電壓。As shown in FIG. 15, even when a voltage applied to the gate of the fourteenth NMOS transistor M14 electrically connected to the output terminal GOUT[N] is different from the gate applied to the sixth NMOS transistor M6, wherein the first The six NMOS transistor M6 is electrically coupled to a fifth NMOS transistor M5 that operates as a diode to generate a voltage that turns on the sixth NMOS transistor M6.

在此具體實施例中，第一NMOS電晶體M1可執行將第一時脈信號CKV取樣的功能。換句話說，由於NMOS電晶體的一電容，所以第一NMOS電晶體M1可執行一取樣功能以維持低位準。當第一時脈信號CKV從一低位準改變成一高位準時，第六NMOS電晶體M6可避免第一NMOS電晶體M1的閘極超過臨界電壓。In this embodiment, the first NMOS transistor M1 can perform the function of sampling the first clock signal CKV. In other words, due to a capacitance of the NMOS transistor, the first NMOS transistor M1 can perform a sampling function to maintain a low level. When the first clock signal CKV changes from a low level to a high level, the sixth NMOS transistor M6 can prevent the gate of the first NMOS transistor M1 from exceeding the threshold voltage.

圖17是根據本發明的另一具體實施例而描述一位移暫存器電路圖。請即參考圖17，位移暫存器包括'N'級BSRC1 -BSRCN 與一虛擬級BSRCN+1 。BSRC1 -BSRCN 分別輸出閘極信號(或掃描信號)GOUT1 -GOUTN ，且虛擬級BSRCN+1 可產生一虛擬閘極信號GDUMMY。Figure 17 is a circuit diagram depicting a shift register in accordance with another embodiment of the present invention. Referring to FIG. 17, the shift register includes an 'N' level BSRC 1 -BSRC N and a virtual level BSRC N+1 . BSRC 1 -BSRC N outputs a gate signal (or scan signal) GOUT 1 -GOUT N , respectively, and a virtual stage BSRC N+1 generates a virtual gate signal GDUMMY.

第一級BSRC1 能分別經由第一與第二時脈信號端CK1 、CK2 而從一外部裝置接收第一與第二時脈信號CKV、CKVB。第一級BSRC1 亦經由第一與第三控制端CT1 、CT3 而接收一掃描開始信號STV。第一級BSRC1 亦經由第二控制端CT2 而接收從第二級BSRC2 產生的第二閘極信號GOUT2 。然後，第一級BSRC1 能經由輸出端OUT而產生第一閘極信號GOUT1 。第一閘極信號GOUT1 亦提供給第二級BSRC2 的第一控制端CT1 。The first stage BSRC 1 can receive the first and second clock signals CKV, CKVB from an external device via the first and second clock signal terminals CK 1 , CK 2 , respectively. The first stage BSRC 1 also receives a scan start signal STV via the first and third control terminals CT 1 , CT 3 . A second gate signal of the first stage also BSRC 1 via the second control terminal CT 2 generated from the received second stage BSRC 2 GOUT 2. Then, the first stage BSRC 1 can generate the first gate signal GOUT 1 via the output terminal OUT. The first gate signal GOUT 1 is also supplied to the first control terminal CT 1 of the second stage BSRC 2 .

第二級BSRC2 能分別經由第二與第一時脈信號端CK2 、CK1 而接收從外部裝置產生的第一與第二時脈信號CKV、CKVB。第二級BSRC2 亦經由第一控制端CT1 而接收從第一級BSRC1 產生的第一閘極信號GOUT1 。第二級BSRC2 亦經由一第二控制端CT2 而接收從第三級BSRC3 產生的第三閘極信號GOUT3 。第二級BSRC2 亦經由第三控制端CT3 接收一閘極關閉電壓VOFF。然後，第二級BSRC2 能經由輸出端OUT而產生第二閘極信號GOUT2 。第二閘極信號GOUT2 亦提供給第三級BSRC3 的第一控制端CT1 。The second stage BSRC 2 can receive the first and second clock signals CKV, CKVB generated from the external device via the second and first clock signal terminals CK 2 , CK 1 , respectively. A first gate signal of a second stage via a first BSRC 2 also receives a control terminal CT 1 generated from the first stage BSRC 1 GOUT 1. The second stage BSRC 2 also receives the third gate signal GOUT 3 generated from the third stage BSRC 3 via a second control terminal CT 2 . The second stage also BSRC 2 via the third control terminal CT 3 receives a gate-off voltage VOFF. Then, the second stage BSRC 2 can generate the second gate signal GOUT 2 via the output terminal OUT. The second gate signal GOUT 2 is also supplied to the first control terminal CT 1 of the third stage BSRC 3 .

在類似方式中，第N級BSRCN 能經由第一與第二時脈信號端CK1 、CK2 而從一外部裝置接收第一與第二時脈信號CKV、CKVB。第N級RSRCN 亦經由第一控制端CT1 接收來自前級的閘極信號。第N級BSRCN 亦經由一第二控制端CT2 而接收從虛擬級BSRCN+1 產生的虛擬閘極信號GDUMMY。第N級BSRCN 亦經由一第三控制端CT3 而接收閘極關閉電壓VOFF。然後，第N級BSRCN 能經由輸出端OUT而產生第N閘極信號GOUTN ，且閘極信號GOUTN 提供給虛擬級BSRCN+1 的一第一控制端CT1 。In a similar manner, the Nth stage BSRC N can receive the first and second clock signals CKV, CKVB from an external device via the first and second clock signal terminals CK 1 , CK 2 . Also the RSRC stage N N first control terminal CT 1 receives the gate signal from the preceding stage via. The Nth stage BSRC N also receives the virtual gate signal GDUMMY generated from the virtual stage BSRC N+1 via a second control terminal CT 2 . The Nth stage BSRC N also receives the gate off voltage VOFF via a third control terminal CT 3 . Then, the Nth stage BSRC N can generate the Nth gate signal GOUT N via the output terminal OUT, and the gate signal GOUT N is supplied to a first control terminal CT 1 of the virtual stage BSRC N+ 1 .

在此具體實施例中，位移暫存器只接收掃描開始信號STV、第一與第二時脈信號CKV、CKVB、與閘極關閉電壓信號VOFF，以輸出用以選擇閘極線的閘極信號。透過使用此具體實施例的位移暫存器，因為外部電壓線的數量減少，所以匯流排線的數量會減少。此外，優點是可在顯示面板中提供閘極驅動電路(或掃描驅動電路)設計的邊際，並 減少或避免由於濕氣造成連接墊塊的任何損害。In this embodiment, the shift register receives only the scan start signal STV, the first and second clock signals CKV, CKVB, and the gate turn-off voltage signal VOFF to output a gate signal for selecting the gate line. . By using the displacement register of this embodiment, the number of bus lines is reduced because the number of external voltage lines is reduced. In addition, there is an advantage that the margin of the design of the gate driving circuit (or scan driving circuit) can be provided in the display panel, and Reduce or avoid any damage to the connection pads due to moisture.

在此具體實施例中，位移暫存器單級可使用前述圖5至16的任一級予以實施。在圖5顯示級的情況是使用在圖17的位移暫存器，第二級至第(N+1)級的每一級可接收閘極關閉電壓VOFF而不是掃描開始信號STV。In this particular embodiment, the single stage of the displacement register can be implemented using any of the stages of Figures 5 through 16 described above. The case of the stage shown in Fig. 5 is that the shift register of Fig. 17 is used, and each of the second to (N+1)th stages can receive the gate turn-off voltage VOFF instead of the scan start signal STV.

圖18描述包括本發明單級的一顯示面板電路圖。請即參考圖18，顯示面板1000包括一顯示區域DA與一週邊區域PA。顯示面板1000可將影像顯示在顯示區域DA。用以驅動顯示面板1000的驅動器電路是配置在週邊區域PA。液晶顯示面板1000亦包括彼此面對的下基板與上基板，且一液晶層是在下基板與上基板之間***。Figure 18 depicts a circuit diagram of a display panel including a single stage of the present invention. Referring to FIG. 18, the display panel 1000 includes a display area DA and a peripheral area PA. The display panel 1000 can display an image on the display area DA. The driver circuit for driving the display panel 1000 is disposed in the peripheral area PA. The liquid crystal display panel 1000 also includes a lower substrate and an upper substrate facing each other, and a liquid crystal layer is interposed between the lower substrate and the upper substrate.

複數條資料線DL與閘極線GL是在顯示區域DA形成。資料線DL是以第一方向配置，且閘極線GL是以第二方向配置，其中第二方向是實質垂直於第一方向。如同切換裝置工作的一薄膜電晶體1100係電連接到該等資料線DL的每一者、與該等閘極線GL的每一者。切換裝置1100包括：一汲極，其電連接到一像素電極1200；一閘極，其電連接到該等閘極線GL的對應一者；及一源極，其電連接到該等資料線DL的對應一者。影像資料能經由資料線DL與切換裝置1100而傳送給素電極1200。The plurality of data lines DL and the gate lines GL are formed in the display area DA. The data line DL is configured in a first direction, and the gate line GL is disposed in a second direction, wherein the second direction is substantially perpendicular to the first direction. A thin film transistor 1100 operating as a switching device is electrically connected to each of the data lines DL and each of the gate lines GL. The switching device 1100 includes: a drain electrically connected to a pixel electrode 1200; a gate electrically connected to a corresponding one of the gate lines GL; and a source electrically connected to the data lines One of the DL's. The image data can be transmitted to the prime electrode 1200 via the data line DL and the switching device 1100.

一資料驅動元件1400配置在週邊區域PA。資料驅動元件1400係電連接到資料線DL，以將影像資料施加到切換裝置1100的源極。一閘極驅動元件1300亦配置在週邊區域PA。閘極驅動元件1300是例如透過圖4或圖17顯示的位移暫存 器實施。閘極驅動元件1300係電連接到閘極線GL，所以來自閘極驅動元件1300的閘極驅動信號能施加在對應切換裝置1100。A data driving element 1400 is disposed in the peripheral area PA. The data driving element 1400 is electrically connected to the data line DL to apply image data to the source of the switching device 1100. A gate driving element 1300 is also disposed in the peripheral area PA. The gate driving element 1300 is temporarily stored, for example, through the displacement shown in FIG. 4 or FIG. Implemented. The gate driving element 1300 is electrically connected to the gate line GL, so the gate driving signal from the gate driving element 1300 can be applied to the corresponding switching device 1100.

閘極驅動元件(即是，一位移暫存器)1300包括複數個單級。該等單級的每一者係電連接到該等閘極線GL的對應一者，所以從一單級輸出的一掃描信號(或閘極驅動信號)能經由該等閘極線GL的對應一者而施加在該等切換裝置對應一者的一閘極1100。當掃描信號施加在切換裝置1100的閘極時，資料驅動元件1400能響應掃描信號而將影像資料提供給對應像素電極1200。顯示面板的位移暫存器1300具有前面圖5-16描述任一具體實施例的單級。The gate drive component (i.e., a shift register) 1300 includes a plurality of single stages. Each of the single stages is electrically connected to a corresponding one of the gate lines GL, so a scan signal (or gate drive signal) output from a single stage can pass through the gate lines GL. One is applied to a gate 1100 corresponding to one of the switching devices. When the scan signal is applied to the gate of the switching device 1100, the data driving element 1400 can supply the image data to the corresponding pixel electrode 1200 in response to the scan signal. The displacement register 1300 of the display panel has a single stage of any of the specific embodiments described above with respect to Figures 5-16.

此外，前述位移暫存器可用於一有機電激發光顯示面板、以及沒有閘極IC結構的一液晶顯示面板。In addition, the aforementioned shift register can be used for an organic electroluminescent display panel and a liquid crystal display panel without a gate IC structure.

根據本發明描述位移暫存器與顯示裝置的具體實施例，鑑於前述，修改與變化可由熟諳此技者達成。因此，了解到本發明能以除了在此描述之外的方式實施，而且是在文後申請專利範圍所述的範圍內。Specific embodiments of the displacement register and display device are described in accordance with the present invention, and modifications and variations will be apparent to those skilled in the art in view of the foregoing. Therefore, it is to be understood that the invention may be practiced otherwise than as described herein.

100,200,300,400,500,600,700‧‧‧位移暫存器單級100,200,300,400,500,600,700‧‧‧Displacement register single stage

130‧‧‧上拉驅動元件130‧‧‧ Pull-up drive components

110,210‧‧‧上拉元件110,210‧‧‧ Pull-up components

120,220‧‧‧下拉元件120,220‧‧‧ Pull-down components

140‧‧‧下拉驅動元件140‧‧‧ Pull-down drive components

230,430‧‧‧第一上拉驅動元件230,430‧‧‧First pull-up drive component

250,350,640,740‧‧‧第二上拉驅動元件250,350,640,740‧‧‧Second pull-up drive components

240‧‧‧第三上拉驅動元件240‧‧‧ Third pull-up drive component

1000‧‧‧顯示面板1000‧‧‧ display panel

1100‧‧‧薄膜電晶體1100‧‧‧film transistor

1400‧‧‧資料驅動元件1400‧‧‧ data drive components

1200‧‧‧像素電極1200‧‧‧pixel electrode

1300‧‧‧閘極驅動元件1300‧‧‧ gate drive components

本揭示將以下列參考附圖而詳細描述具體實施例，其中：圖1描述一傳統位移暫存器單級電路圖；圖2描述一傳統位移暫存器的方塊圖；圖3是圖1的位移暫存器信號波形圖式；圖4是根據本發明的一具體實施例而描述一位移暫存器方塊圖； 圖5描述圖4的位移暫存器單級電路圖；圖6描述圖4的位移暫存器電路圖；圖7是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖；圖8描述包括圖7單級的一位移暫存器電路圖；圖9是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖；圖10描述包括圖9單級的一位移暫存器電路圖；圖11是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖；圖12描述包括圖11單級的一位移暫存器電路圖；圖13是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖；圖14描述包括圖13單級的一位移暫存器電路圖；圖15是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖；圖16描述包括圖15單級的一位移暫存器電路圖；圖17是根據本發明的另一具體實施例而描述一位移暫存器單級電路圖；及圖18描述包括圖17單級的一位移暫存器電路圖。The present invention will be described in detail below with reference to the accompanying drawings in which: FIG. 1 illustrates a single-stage circuit diagram of a conventional displacement register; FIG. 2 depicts a block diagram of a conventional displacement register; FIG. 3 is a displacement of FIG. a register waveform diagram of a register; FIG. 4 is a block diagram depicting a shift register in accordance with an embodiment of the present invention; 5 is a single-stage circuit diagram of the displacement register of FIG. 4; FIG. 6 is a circuit diagram of the displacement register of FIG. 4; FIG. 7 is a single-stage circuit diagram for describing a displacement register according to another embodiment of the present invention; 8 is a circuit diagram of a displacement register including a single stage of FIG. 7; FIG. 9 is a single-stage circuit diagram for describing a displacement register according to another embodiment of the present invention; FIG. 10 is a diagram showing a displacement of a single stage including FIG. FIG. 11 is a single-stage circuit diagram of a shift register according to another embodiment of the present invention; FIG. 12 is a circuit diagram of a shift register including a single stage of FIG. 11; FIG. 13 is a circuit diagram of a shift register including a single stage of FIG. Another embodiment shows a single-stage circuit diagram of a shift register; FIG. 14 depicts a shift register circuit diagram including a single stage of FIG. 13; and FIG. 15 depicts a displacement temporary storage according to another embodiment of the present invention. Figure 16 depicts a shift register circuit diagram including a single stage of Figure 15; Figure 17 is a single stage circuit diagram depicting a shift register in accordance with another embodiment of the present invention; and Figure 18 depicts 17 single-stage one-position register Road map.

(無元件代表符號)(no component symbol)

Claims (22)

一種用以在一顯示裝置中將閘極信號提供給對應閘極線之位移暫存器，該位移暫存器分別包含複數個單級，以連續產生該等閘極信號，該等單級的每一者包含：一第一上拉驅動元件，其響應一相鄰前級的輸出信號或一控制信號以產生一第一控制信號；一上拉元件，其響應一第一時脈信號與該第一控制信號而產生一電流輸出信號；一第二上拉驅動元件，其響應施加於該上拉元件之該第一時脈信號且響應於一第二時脈信號以產生至少一第二控制信號；及一第三上拉驅動元件，其連接到一低位準端，以響應一相鄰後級的一輸出信號而操作。 A shift register for providing a gate signal to a corresponding gate line in a display device, the shift register respectively comprising a plurality of single stages for continuously generating the gate signals, the single-stage Each includes: a first pull-up driving component responsive to an output signal of a neighboring pre-stage or a control signal to generate a first control signal; a pull-up component responsive to a first clock signal and the a first control signal to generate a current output signal; a second pull-up driving component responsive to the first clock signal applied to the pull-up element and responsive to a second clock signal to generate at least a second control And a third pull-up drive component coupled to a low level terminal for operation in response to an output signal of an adjacent subsequent stage. 如申請專利範圍第1項之位移暫存器，其進一步包含響應該第二時脈信號操作的一下拉元件。 The shift register of claim 1, further comprising a pull-down element responsive to the second clock signal operation. 如申請專利範圍第2項之位移暫存器，其中該第二上拉驅動元件包括：一第一電晶體，其具有接收閘極信號的一閘極與連接在接收該第一時脈信號端與接收第二時脈信號端之間的一傳導路徑；一第二電晶體，其連接在該用以接收第一時脈信號端與該第一電晶體之間，該第二電晶體的工作如同二極體；及一第三電晶體，其具有接收該第二時脈信號的一閘極 與連接在用以接收該第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體共同節點之間的一傳導路徑，其中該共同節點連接到該第三上拉驅動元件。 The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive the first clock signal end And a conductive path between the signal receiving the second clock signal; a second transistor connected between the terminal for receiving the first clock signal and the first transistor, the working of the second transistor Like a diode; and a third transistor having a gate receiving the second clock signal And a conductive path connected between the first and second transistor common nodes for receiving the first clock signal end and the second pull-up driving element, wherein the common node is connected to the third pull-up driving element. 如申請專利範圍第3項之位移暫存器，其中該第三上拉驅動元件包括：一第一電晶體，其具有連接到該第一控制信號的兩端；一第二電晶體，其具有連接到該第二上拉驅動元件共同節點的一閘極與連接在該第一電晶體與該第二時脈信號之間的一傳導路徑；一第三電晶體，其具有連接到相鄰後級輸出端信號的一閘極與連接在該上拉元件與低位準端之間的一傳導路徑；及一電容器，其連接在該上拉元件與該電流輸出信號之間。 The displacement register of claim 3, wherein the third pull-up driving element comprises: a first transistor having two ends connected to the first control signal; and a second transistor having a second transistor a gate connected to the common node of the second pull-up driving component and a conductive path connected between the first transistor and the second clock signal; a third transistor having a connection to the adjacent a gate of the stage output signal and a conduction path connected between the pull-up element and the low level terminal; and a capacitor connected between the pull-up element and the current output signal. 如申請專利範圍第4項之位移暫存器，其中該低位準端連接到一接地位準信號(VSS)或一掃描開始(STV)信號。 The shift register of claim 4, wherein the low level terminal is connected to a ground level signal (VSS) or a scan start (STV) signal. 如申請專利範圍第5項之位移暫存器，其中該上拉元件包括一第一電晶體，該第一電晶體具有接收該第一控制信號的一閘極與連接在接收第一時脈信號端與輸出閘極信號端之間的一傳導路徑。 The shift register of claim 5, wherein the pull-up element comprises a first transistor, the first transistor having a gate receiving the first control signal and being connected to receive the first clock signal A conduction path between the terminal and the output signal terminal. 如申請專利範圍第6項之位移暫存器，其中該下拉元件包括： 一第一電晶體，該第一電晶體具有連接到輸出閘極信號端的兩端；及一第二電晶體，該第二電晶體具有連接到該第二時脈信號的一閘極與在該第二電晶體與該第一時脈信號間連接的一傳導路徑。 For example, the displacement register of claim 6 of the patent scope, wherein the pull-down component comprises: a first transistor having two ends connected to the output gate signal terminal; and a second transistor having a gate connected to the second clock signal and a conduction path connecting the second transistor to the first clock signal. 如申請專利範圍第7項之位移暫存器，其中該提供給奇數級的第一時脈信號，與該提供給偶數級的第一時脈具有彼此相反的相位。 The shift register of claim 7, wherein the first clock signal supplied to the odd-numbered stages has a phase opposite to the first clock supplied to the even-numbered stages. 如申請專利範圍第8項之位移暫存器，其中該提供給奇數級的第二時脈信號與該提供給偶數級的第二時脈信號具有彼此相反的相位。 The shift register of claim 8 wherein the second clock signal supplied to the odd stage and the second clock signal supplied to the even stage have opposite phases to each other. 如申請專利範圍第1項之位移暫存器，其中該控制信號是一STV信號。 For example, the displacement register of claim 1 is wherein the control signal is an STV signal. 如申請專利範圍第2項之位移暫存器，其中該第二上拉驅動元件包括：一第一電晶體，其具有接收該閘極信號的一閘極與在接收第一時脈信號端與接收第二時脈信號端間連接的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的一閘極與在接收第一時脈信號端與第二上拉驅動元件的第一電晶體間連接的一傳導路徑，該第二上拉驅動元件的第一與第二電晶體共同節點連接到該第一上拉驅動元件保持電晶體的一閘極；一第三電晶體，其具有接收該第二時脈信號的一閘極 與在接收第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體共同節點間連接的一傳導路徑；一第四電晶體，其具有接收閘極信號的一閘極與在接收第一時脈信號端與接收第二時脈信號端間連接的一傳導路徑；一第五電晶體，其連接在接收第一時脈信號端與該第二上拉驅動元件的第四電晶體之間，該第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到該第二電晶體的閘極；及一第六電晶體，其具有連接到第二時脈信號的一閘極與在接收該第一時脈信號端與第四及第五電晶體共同節點間連接的一傳導路徑。 The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and receiving the first clock signal end Receiving a conduction path of the connection between the ends of the second clock signal; a second transistor having a gate receiving the second transistor control signal and receiving the first clock signal end and the second pull-up driving component a conductive path connecting the first transistors, the first and second transistor common nodes of the second pull-up driving component are connected to the first pull-up driving component to maintain a gate of the transistor; a third a crystal having a gate receiving the second clock signal And a conductive path connected between the first clock signal terminal and the first and second transistor common nodes of the second pull-up driving component; a fourth transistor having a gate receiving the gate signal And a conductive path connected between receiving the first clock signal end and receiving the second clock signal end; a fifth transistor connected to receive the first clock signal end and the second pull-up driving component Between the four transistors, the fifth transistor operates as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; and a sixth transistor having And connecting a gate of the second clock signal to a conductive path connecting the first clock signal end and the fourth and fifth transistor common nodes. 如申請專利範圍第2項之位移暫存器，其中該第二上拉驅動元件包括：一第一電晶體，其具有接收該閘極信號的一閘極與連接在一接收第一時脈信號端與一接收第二時脈信號端間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的該第一電晶體間的一傳導路徑，該第二上拉驅動元件的第一與第二電晶體之共同節點連接到該第一上拉驅動元件的一保持電晶體的閘極；一第三電晶體，其具有接收該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元 件的第一與第二電晶體共同節點間的一傳導路徑；一第四電晶體，其具有接收閘極信號的一閘極與連接在該接收第一時脈信號端與該接收第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在接收該第一時脈信號端與該第二上拉驅動元件的第四電晶體之間，該第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到該第二電晶體的閘極；一第六電晶體，其具有連接到該第二時脈信號的一閘極與連接在該接收第一時脈信號端與第四與第五電晶體共同節點間的一傳導路徑；及一第七電晶體，其具有連接到第四與第五電晶體共同節點的一閘極與連接在該第一上拉驅動元件與一輸出閘極信號端間的一傳導路徑。 The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive the first clock signal And a conductive path between the terminal and the receiving end of the second clock signal; a second transistor having a gate receiving the second transistor control signal and connected to the receiving the first clock signal end and the second a conductive path between the first transistors of the pull-up driving component, wherein the common node of the first and second transistors of the second pull-up driving component is connected to a gate of the first pull-up driving component that holds the transistor a third transistor having a gate receiving the second clock signal and connected to the receiving first clock signal end and the second pull-up driving element a conductive path between the first and second transistors of the common node; a fourth transistor having a gate receiving the gate signal and connected to the receiving the first clock signal end and the receiving second a conduction path between the pulse signal ends; a fifth transistor connected between the first transistor receiving the first clock signal end and the fourth transistor of the second pull-up driving element, the fifth transistor working as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second clock signal and connected Receiving a conduction path between the first clock signal end and the common node of the fourth and fifth transistors; and a seventh transistor having a gate and a connection connected to the common node of the fourth and fifth transistors a conduction path between the first pull-up driving component and an output gate signal terminal. 如申請專利範圍第2項之位移暫存器，其中該第二上拉驅動元件包括：一第一電晶體，其具有接收閘極信號的一閘極與連接在一接收第一時脈信號端與一接收第二時脈信號端間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一電晶體間的一傳導路徑，該第二上拉驅動元件的第一與第二電晶體共同節點連接到該第一上拉驅動元件的一保持電晶體的閘極； 一第三電晶體，其具有接收該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體共同節點間的一傳導路徑；一第四電晶體，其具有接收閘極信號的一閘極與連接在該接收第一時脈信號端與該第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在該接收第一時脈信號端與該第二上拉驅動元件的第四電晶體之間，該第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到該第二電晶體的閘極；一第六電晶體，其具有連接到該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該等第四與第五電晶體共同節點間的一傳導路徑；及一第七電晶體，其具有連接到該等第一與第二電晶體共同節點的一閘極與在連接在該第一上拉驅動元件與一輸出閘極信號端間的一傳導路徑。 The shift register of claim 2, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive the first clock signal end And a conductive path between the receiving end of the second clock signal; a second transistor having a gate receiving a second transistor control signal and connected to the receiving the first clock signal end and the second Pulling a conductive path between the first transistors of the driving element, the first and second transistors of the second pull-up driving element are commonly connected to a gate of the first pull-up driving element that holds the transistor; a third transistor having a gate receiving the second clock signal and being connected between the receiving first clock signal terminal and the first and second transistor common nodes of the second pull-up driving component a conductive path; a fourth transistor having a gate receiving the gate signal and a conduction path connected between the receiving first clock signal end and the second clock signal end; a fifth transistor Connected between the first clock signal receiving end and the fourth transistor of the second pull-up driving element, the fifth transistor operates as a diode, and one of the fourth and fifth transistors a common node is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second clock signal and connected to the fourth clock signal terminal and the fourth a conductive path between the common nodes of the fifth transistor; and a seventh transistor having a gate connected to the common node of the first and second transistors and being connected to the first pull-up driving component A conduction path between the output signal terminals. 一種用以將影像顯示在一顯示面板之顯示裝置，其包含：複數個像素，其各具有經由一掃描信號掃描的一切換元件；及一位移暫存器，其用以將閘極信號提供給該顯示面板的對應閘極線，該位移暫存器包含複數個單級，以分別連續產生閘極信號，該等單級的每一者包含：一第一上拉驅動元件，其響應一相鄰前級的輸出信 號或一控制信號而產生一第一控制信號；一上拉元件，其響應一第一時脈信號與該第一控制信號而產生一電流輸出信號；一第二上拉驅動元件，其響應施加於該上拉元件之該第一時脈信號且響應於一第二時脈信號而產生至少一第二控制信號；及一第三上拉驅動元件，該第三上拉驅動元件連接到一低位準端，以響應一相鄰後級的輸出信號而操作。 A display device for displaying an image on a display panel, comprising: a plurality of pixels each having a switching element scanned via a scan signal; and a shift register for providing a gate signal a corresponding gate line of the display panel, the shift register includes a plurality of single stages to continuously generate gate signals respectively, each of the single stages comprising: a first pull-up driving element, which responds to one phase Output signal of the adjacent front stage a first control signal is generated by a signal or a control signal; a pull-up element generates a current output signal in response to a first clock signal and the first control signal; and a second pull-up driving element responsive to the application And generating, by the first clock signal of the pull-up element, at least one second control signal in response to a second clock signal; and a third pull-up driving component, the third pull-up driving component is connected to a low position The quasi-end operates in response to an output signal of an adjacent subsequent stage. 如申請專利範圍第14項之顯示裝置，其進一步包含一下拉元件，以響應該第二時脈信號而操作。 The display device of claim 14, further comprising a pull-down element operative in response to the second clock signal. 如申請專利範圍第15項之顯示裝置，其中該第二上拉驅動元件包括：一第一電晶體，其具有接收閘極信號的一閘極與連接在一接收第一時脈信號端與一接收第二時脈信號端間的一傳導路徑；一第二電晶體，其連接在該第一時脈信號與該第一電晶體之間，該第二電晶體的工作如同二極體；及一第三電晶體，其具有接收該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體共同節點間的一傳導路徑，其中該共同節點連接到該第三上拉驅動元件。 The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate receiving the gate signal and being connected to receive a first clock signal end and a Receiving a conduction path between the ends of the second clock signal; a second transistor connected between the first clock signal and the first transistor, the second transistor working as a diode; and a third transistor having a gate receiving the second clock signal and being connected between the receiving first clock signal terminal and the first and second transistor common nodes of the second pull-up driving component a conduction path, wherein the common node is coupled to the third pull up drive element. 如申請專利範圍第16項之顯示裝置，其中該第三上拉驅動元件包括：一第一電晶體，其具有連接到該第一控制信號的兩 端；一第二電晶體，其具有連接到該第二上拉驅動元件共同節點的一閘極與連接在該第一電晶體與該第二時脈信號間的一傳導路徑；一第三電晶體，其具有連接到該相鄰後級輸出信號的一閘極與連接在該上拉元件與該低位準端間的一傳導路徑；及一電容器，其連接在該上拉元件與該電流輸出信號之間。 The display device of claim 16, wherein the third pull-up driving element comprises: a first transistor having two connected to the first control signal a second transistor having a gate connected to a common node of the second pull-up driving component and a conducting path connected between the first transistor and the second clock signal; a crystal having a gate connected to the output signal of the adjacent subsequent stage and a conduction path connected between the pull-up element and the low-level terminal; and a capacitor connected to the pull-up element and the current output Between the signals. 如申請專利範圍第17項之顯示裝置，其中該上拉元件包括一第一電晶體，其具有接收該第一控制信號的一閘極與連接在一接收第一時脈信號端與一輸出閘極信號端間的一傳導路徑，且該下拉元件包括：一第一電晶體，其具有連接到一輸出閘極信號端的兩端；與一第二電晶體，其具有連接到該第二時脈信號的一閘極與連接在該第二電晶體與該第一時脈信號間的一傳導路徑。 The display device of claim 17, wherein the pull-up element comprises a first transistor having a gate receiving the first control signal and connected to receive a first clock signal end and an output gate a conduction path between the signal terminals, and the pull-down element includes: a first transistor having two ends connected to an output gate signal end; and a second transistor having a second clock connected thereto a gate of the signal and a conduction path connected between the second transistor and the first clock signal. 如申請專利範圍第18項之顯示裝置，其中該提供給奇數級的第一時脈信號與該提供給偶數級的第一時脈信號具有彼此相反的相位，且該提供給奇數級的第二時脈信號與該提供給偶數級的第二時脈信號具有彼此相反的相位。 The display device of claim 18, wherein the first clock signal supplied to the odd-numbered stage and the first clock signal supplied to the even-numbered stage have phases opposite to each other, and the second clock is supplied to the odd-numbered stage The clock signal and the second clock signal supplied to the even-numbered stages have opposite phases to each other. 如申請專利範圍第15項之顯示裝置，其中該第二上拉驅動元件包括：一第一電晶體，其具有接收該閘極信號的一閘極與連 接在一接收第一時脈信號端與一接收第二時脈信號間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一電晶體間的一傳導路徑，該第二上拉驅動元件的第一與第二電晶體的一共同節點連接到該第一上拉驅動元件的一保持電晶體的閘極；一第三電晶體，其具有接收該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體共同節點間的一傳導路徑；一第四電晶體，其具有接收該閘極信號的一閘極與連接在該接收第一時脈信號端與該接收第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在該接收第一時脈信號端與該第二上拉驅動元件的第四電晶體之間，該第五電晶體的工作如同二極體，且該等第四與第五電晶體的一共同節點連接到乾第二電晶體的閘極；及一第六電晶體，其具有連接到該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該等第四與第五電晶體共同節點間的一傳導路徑。 The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate and a connection for receiving the gate signal Connected to a conductive path between the receiving first clock signal end and a receiving second clock signal; a second transistor having a gate receiving a second transistor control signal and being connected to the receiving a conduction path between a clock signal end and a first transistor of the second pull-up driving component, a common node of the first and second transistors of the second pull-up driving component being connected to the first pull-up a gate of the driving element holding the transistor; a third transistor having a gate for receiving the second clock signal and connected to the receiving first clock signal end and the second pull-up driving element a conductive path between the common nodes of the first and second transistors; a fourth transistor having a gate receiving the gate signal and connected to the receiving first clock signal end and the receiving second clock a conductive path between the signal terminals; a fifth transistor connected between the receiving first first clock signal end and the fourth transistor of the second pull-up driving element, the fifth transistor working as two a polar body, and a common one of the fourth and fifth transistors a point connected to the gate of the dry second transistor; and a sixth transistor having a gate connected to the second clock signal and connected to the first clock signal terminal and the fourth pair A conduction path between the common nodes of the fifth transistor. 如申請專利範圍第15項之顯示裝置，其中第二上拉驅動元件包括：一第一電晶體，其具有接收該閘極信號的一閘極與連接一接收第一時脈信號端與一接收第二時脈信號端間 的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一電晶體間的一傳導路徑，該第二上拉驅動元件的第一第二電晶體的一共同節點連接到該第一上拉驅動元件保持電晶體的閘極；一第三電晶體，其具有接收該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體的該共同節點間的一傳導路徑；一第四電晶體，其具有接收該閘極信號的一閘極與連接在該接收第一時脈信號端與接收該第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在該接收第一時脈信號端與該第二上拉驅動元件的第四電晶體之間，該第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到該第二電晶體的閘極；一第六電晶體，其具有連接該第二時脈信號的一閘極與連接在該接收第一時脈信號端與第四與第五電晶體共同節點間的一傳導路徑；及一第七電晶體，其具有連接到第四與第五電晶體共同節點的一閘極與連接在該第一上拉驅動元件與一輸出閘極信號端間的一傳導路徑。 The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate for receiving the gate signal and a receiving terminal for receiving the first clock signal and receiving Second clock signal end a conductive path; a second transistor having a gate receiving a second transistor control signal and being coupled between the first transistor receiving the first clock signal and the first transistor of the second pull-up driving component a conductive path, a common node of the first second transistor of the second pull-up driving component is connected to the first pull-up driving component to maintain the gate of the transistor; and a third transistor having the second receiving a gate of the clock signal and a conduction path connected between the first node of the first clock signal and the common node of the first and second transistors of the second pull-up driving element; a fourth transistor; The device has a gate for receiving the gate signal and a conduction path connected between the receiving the first clock signal end and receiving the second clock signal end; a fifth transistor connected to the receiving first Between the clock signal end and the fourth transistor of the second pull-up driving element, the fifth transistor operates as a diode, and a common node of the fourth and fifth transistors is connected to the second electrode a gate of a crystal; a sixth transistor having a connection a gate of the second clock signal and a conduction path connected between the receiving first clock signal end and the fourth and fifth transistors common node; and a seventh transistor having a fourth connection a gate of the common node of the fifth transistor and a conduction path connected between the first pull-up driving component and an output gate signal terminal. 如申請專利範圍第15項之顯示裝置，其中該第二上拉驅動元件包括： 一第一電晶體，其具有接收該閘極信號的一閘極與連接在一接收第一時脈信號端與接收第二時脈信號間的一傳導路徑；一第二電晶體，其具有接收一第二電晶體控制信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的該第一電晶體間的一傳導路徑，該第二上拉驅動元件的第一與第二電晶體的一共同節點連接到該第一上拉驅動元件的一保持電晶體的閘極；一第三電晶體，其具有接收該第二時脈信號的一閘極與連接在該接收第一時脈信號端與該第二上拉驅動元件的第一與第二電晶體的共同節點間的一傳導路徑；一第四電晶體，其具有接收該閘極信號的一閘極與連接在該接收第一時脈信號端與該接收第二時脈信號端間的一傳導路徑；一第五電晶體，其連接在該接收第一時脈信號端與該第二上拉驅動元件的該第四電晶體之間，該第五電晶體的工作如同二極體，且第四與第五電晶體的一共同節點連接到該第二電晶體的閘極；一第六電晶體，其具有連接到該第二時脈信號的一閘極與連接在該接收第一時脈信號端與第四與第五電晶體共同節點間的一傳導路徑；及一第七電晶體，其具有連接到第一與第二電晶體共同節點的一閘極與連接在一第一上拉驅動元件與一輸出閘極信號端間的一傳導路徑。The display device of claim 15, wherein the second pull-up driving component comprises: a first transistor having a gate for receiving the gate signal and a conduction path connected between receiving the first clock signal end and receiving the second clock signal; a second transistor having a receiving a gate of a second transistor control signal and a conduction path connected between the receiving first clock signal terminal and the first transistor of the second pull-up driving component, the second pull-up driving component a common node of the first and second transistors is coupled to a gate of the first pull-up driving element that holds the transistor; a third transistor having a gate and a connection for receiving the second clock signal Receiving a conduction path between the first clock signal end and a common node of the first and second transistors of the second pull-up driving element; a fourth transistor having a gate for receiving the gate signal And a conductive path connected between the receiving first clock signal end and the receiving second clock signal end; a fifth transistor connected to the receiving first clock signal end and the second pull-up The fifth transistor between the fourth transistors of the driving element Working as a diode, and a common node of the fourth and fifth transistors is connected to the gate of the second transistor; a sixth transistor having a gate connected to the second clock signal And a conductive path connected between the receiving first clock signal end and the fourth and fifth transistors common node; and a seventh transistor having a gate connected to the common node of the first and second transistors The pole is connected to a conduction path between a first pull-up driving component and an output gate signal terminal.
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