TWI412022B - Recursive discrete cosine transform and inverse discrete cosine transform system - Google Patents

Recursive discrete cosine transform and inverse discrete cosine transform system Download PDF

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TWI412022B
TWI412022B TW099146935A TW99146935A TWI412022B TW I412022 B TWI412022 B TW I412022B TW 099146935 A TW099146935 A TW 099146935A TW 99146935 A TW99146935 A TW 99146935A TW I412022 B TWI412022 B TW I412022B
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discrete cosine
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TW201227717A (en
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Sheau Fang Lei
Shin Chi Lai
Po Yin Cheng
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Univ Nat Cheng Kung
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Abstract

The invention provides a recursive discrete cosine transform and inverse discrete cosine transform system. The first unit receives N digital signals and performs operation on the N digital signals to generate first temporal signals. The second unit performs an operation on the first temporal signals to generate second temporal signals. An IDCT-II unit performs operation on the second temporal signals to generate third temporal signals. The third unit performs an operation on third temporal signals to generate first output signals. The fourth unit performs an operation on the first output signals to generate second output signals. When the N digital signals are the input of the system, the first output signals are the discrete cosine transform of the N digital signals, and when first temporal signals are the input of the system, the second output signals are the inverse discrete cosine transform of the first temporal signals.

Description

遞迴式離散餘弦正、逆轉換之系統 Recursive discrete cosine forward and inverse conversion system

本發明係關於數位訊號處理之技術領域，尤指一種遞迴式離散餘弦正、逆轉換之系統。 The invention relates to the technical field of digital signal processing, in particular to a recursive discrete cosine forward and inverse conversion system.

由於數位訊號處理的技術日趨發達，在日常生活中可以很方便地獲取信息和享受各種多媒體資訊。基於子帶分析/合成(subband analysis/synthesis)方法，改良型離散餘弦轉換(modified discrete cosine transform,MDCT)和逆改良型離散餘弦轉換(inverse modified discrete cosine transform,IMDCT)已廣泛應用在各種音頻編解碼標準上。 Due to the increasingly developed technology of digital signal processing, it is convenient to obtain information and enjoy various multimedia information in daily life. Based on the subband analysis/synthesis method, the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT) have been widely used in various audio coding. Decoding standard.

於AC-3、MP3和AAC解碼中，濾波器組(Filter bank)佔了各個解碼器的大部分運算複雜度，而濾波器組主要功能是將音訊從頻譜訊號轉到時間軸訊號，其係執行逆改良型離散餘弦轉換(Inverse Modified Discrete Cosine Transform,IMDCT)；而原始的逆改良型離散餘弦轉換(IMDCT)方法複雜度為資料的倍，當中N為窗口長度(window length)。 In AC-3, MP3 and AAC decoding, the filter bank accounts for most of the computational complexity of each decoder, and the main function of the filter bank is to transfer audio from the spectrum signal to the time axis signal. Perform inverse modified Discrete Cosine Transform (IMDCT); the original inverse modified discrete cosine transform (IMDCT) method is complex. Times, where N is the window length.

各編解碼標準則有規定轉換窗口長度(window length)的大小，就長窗而言，MP3解碼需要36點，數字無線電的先進音頻編碼(digital radio mondiale advanced audio coding,DRM AAC)需要1920點，MPEG-2/4先進音頻編碼(MPEG-2/4 AAC)則需要2048點，因此增加運算的複雜度。雖然習知技術有使用平行技術的改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMCT)設計，其係基於蝴蝶型態的設計架構，但這樣的設計提高了電路架構的資料頻寬和控制的複雜度。同時在MPEG-2/4先進音頻編碼(MPEG-2/4 AAC)和數字無線電的先進音頻編碼(DRM AAC)的格式限制下，平行架構的電路設計是不恰當的，如果採用完全平行架構(fully parallel)實現則會有硬體面積過大的問題。 Each codec standard specifies the size of the window length. For long windows, MP3 decoding requires 36 points, and the digital radio mondiale advanced Audio coding, DRM AAC) requires 1920 points, and MPEG-2/4 advanced audio coding (MPEG-2/4 AAC) requires 2048 points, thus increasing the complexity of the operation. Although the prior art has improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMCT) designs using parallel techniques, which are based on a butterfly-type design architecture, such designs increase the data frequency of the circuit architecture. The complexity of the width and control. At the same time, under the format constraints of MPEG-2/4 Advanced Audio Coding (MPEG-2/4 AAC) and Digital Radio Advanced Audio Coding (DRM AAC), the parallel architecture circuit design is not appropriate if a fully parallel architecture is used ( Fully parallel implementation will have a problem of excessive hardware area.

於Chiang & Liu在Signal Processing Letters,IEEE,vol.3 pp.116-118,1996所發表的「Regressive implementations for the forward and inverse MDCT in MPEG audio coding」論文中，提出以正弦(sinusoidal)遞迴架構為核心，來計算改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)的方法。而Nikolajevic & Fettweis在Signal Processing,IEEE Transactions on,vol.51,pp.1439-1444,2003所提出的「Computation of forward and inverse MDCT using Clenshaw's recurrence formula」論文中，則是根據Clenshaw遞迴架構為核心來設計通用長度(general length)的改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)的方法。 In the paper "Regressive implementations for the forward and inverse MDCT in MPEG audio coding" published by Chiang & Liu in Signal Processing Letters, IEEE, vol. 3 pp. 116-118, 1996, a sinusoidal recursive architecture is proposed. As a core, a method for calculating improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) is performed. The paper "Computation of forward and inverse MDCT using Clenshaw's recurrence formula" proposed by Nikolajevic & Fettweis in Signal Processing, IEEE Transactions on, vol. 51, pp. 1439-1444, 2003 is based on the Clenshaw recursive architecture. To design a general length of modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT).

在Chiang & Liu論文及Nikolajevic & Fettweis論文中，計算N點MDCT都需要個週期(cycles)才能得到運 算結果。為了加快運算處理速度，Chen et al.在Circuits and Systems II：Analog and Digital Signal Processing,IEEE Transactions on,vol.50,pp.38-45,2003所發表的「Recursive architectures for realizing modified discrete cosine transform and its inverse」論文中，提出一個有效率的架構，以Chebyshev多項式的想法來實現改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)的方法，其提出的架構算出每一點改良型離散餘弦轉換(MDCT)的運算結果只需要N/4個週期(cycles)，其係把核心部分的離散餘弦第四型(DCT-IV)型式轉換成離散餘弦第二型(DCT-II)和離散正弦第二型(DST-II)的型式。 In the Chiang & Liu paper and the Nikolajevic & Fettweis paper, the calculation of N-point MDCT is required. Cycles are required to get the result of the operation. In order to speed up the processing speed, Chen et al., "Recursive architectures for realizing modified discrete cosine transform and" in Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 50, pp. 38-45, 2003. In its inverse paper, an efficient architecture is proposed to implement the improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) methods with the Chebyshev polynomial idea. The proposed architecture calculates each improved type. The discrete cosine transform (MDCT) operation requires only N/4 cycles, which converts the discrete cosine fourth type (DCT-IV) pattern of the core part into discrete cosine type 2 (DCT-II) and Discrete sinusoidal type 2 (DST-II) type.

雖然Chen et al.論文提出的核心架構利用乘以倒數餘弦(inverse cosine)的係數來減少計算複雜度和增加資料的吞吐量(throughput)，但同樣的也增加信號的動態範圍，且降低改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMCT)定點算術運算的精確度。 Although the core architecture proposed by Chen et al. uses multiply the coefficient of inverse cosine to reduce computational complexity and increase data throughput, it also increases the dynamic range of the signal and reduces the improved The accuracy of discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMCT) fixed-point arithmetic operations.

Lei et al.在Consumer Electronics,2008.ISCE 2008.IEEE International Symposium所發表的論文「A high-precision algorithm for the forward and inverse MDCT using the unified recursive architecture」針對改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMCT)的運算提出了一個統一的架構，其乘法所使用的係為相同餘弦(cosine)的值。和Chiang and Liu、Chen et al.提出的方法比起來，Lei et al.的前處理有著較小的動態範圍，因此其核心的定點算術運算也會有比較高精確的運算。 其係把改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)由離散餘弦第四型(DCT-IV)的核心型式轉化成離散餘弦第二型(DCT-II)和離散正弦第二型(DST-II)的核心型式，因此改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)可以推導成相同的公式進而使用相同的核心架構。 Lei et al., "A high-precision algorithm for the forward and inverse MDCT using the unified recursive architecture" in Consumer Electronics, 2008. ISCE 2008. IEEE International Symposium for improved discrete cosine transform (MDCT) and inverse improvement The operation of the Discrete Cosine Transform (IMCT) proposes a unified architecture whose multiplication uses the same cosine value. Compared with the method proposed by Chiang and Liu and Chen et al., Lei et al.'s pre-processing has a small dynamic range, so its core fixed-point arithmetic operations will have more accurate operations. It transforms the modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) from the core form of discrete cosine fourth type (DCT-IV) into discrete cosine type 2 (DCT-II) and discrete sine The core type of the second type (DST-II), so the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT) can be derived into the same formula and use the same core architecture.

Lei et al.在Circuits and Systems II：Express Briefs,IEEE Transactions on,vol.56,pp.793-797,2009所發表的論文「Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC,AAC in DRM,and MP3 Codecs」更針對乘法使用的係數量去做化簡，並推導出以離散餘弦第四型(DCT-IV)為核心的改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)共架構方法，來達到使用最少的記憶體來儲存運算的係數。 Lei et al., Papers and Systems II: Express Briefs, IEEE Transactions on, vol. 56, pp. 793-797, 2009, "Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs" simplifies the amount of coefficients used in multiplication, and derives improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform with discrete cosine fourth type (DCT-IV) as the core. (IMDCT) A common architectural approach to storing the coefficients of the operation with minimal memory.

L.Lin et al.在Anti-counterfeiting,Security,and Identification in Communication,2009.ASID 2009.3rd International Conference on,2009,pp.156-159所發表的論文「Efficient architectures of MDCT/IMDCT implementation for MPEG audio codec」亦提出了高效率的方法，其將N點的改良型離散餘弦轉換(MDCT)函數拆解成奇/偶兩部分，再分別化簡成離散餘弦第四型(DCT-IV)的型式，然後以快速傅力葉轉換(FFT)來實現其核心架構。 L. Lin et al., "Efficient architectures of MDCT/IMDCT implementation for MPEG audio codec", Anti-counterfeiting, Security, and Identification in Communication, 2009. ASID 2009. 3rd International Conference on, 2009, pp. 156-159 A high-efficiency method is also proposed, which splits the modified discrete cosine transform (MDCT) function of point N into odd/even parts, and then reduces them into discrete cosine fourth type (DCT-IV), and then Fast Fourier Transform (FFT) to achieve its core architecture.

Lei et al.在IEEE Transactions on Circuits and Systems II：Express Briefs Vol.57,No.7,July 2010所發表的論文「Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms」設計核心採以現場可編程輯閘陣列(Field Programming Gate Array,FPGA)來實現硬體加速，其係遞迴和硬體實現的概念亦可有效的降低硬體需求，達到一個低成本的設計考量。 Lei et al.'s paper "Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms" published in IEEE Transactions on Circuits and Systems II: Express Briefs Vol.57, No.7, July 2010 The Field Programming Gate Array (FPGA) is used to implement hardware acceleration. The concept of recursive and hardware implementation can also effectively reduce the hardware requirements and achieve a low-cost design consideration.

儘管多年來離散餘弦正、逆轉換之系統已經發展許多，然而為能進一步降低運算複雜度，減少硬體成本、及提高資料計算之效能，前述具離散餘弦正、逆轉換之系統仍有予以改善之需要。 Although the system of discrete cosine forward and reverse conversion has been developed for many years, in order to further reduce the computational complexity, reduce the hardware cost, and improve the performance of data calculation, the above system with discrete cosine forward and reverse conversion still has improvement. Need.

本發明之主要目的係在提供一種遞迴式離散餘弦正、逆轉換之系統，其具有低運算複雜度，且使用少量的乘法係數使用量，並具有高效能的資料計算。 The main object of the present invention is to provide a recursive discrete cosine forward and inverse conversion system which has low computational complexity and uses a small amount of multiplication coefficient usage and has high performance data calculation.

依據本發明之一特色，本發明提出一種遞迴式離散餘弦正、逆轉換之系統，其係以反離散餘弦第二型(IDCT-II)為核心，該系統包含一第一運算單元、一第二運算單元、一反離散餘弦第二型(IDCT-II)單元、一第三運算單元、及一第四運算單元。該第一運算單元接收N個輸入數位訊號，對該N個數位訊號執行運算，以產生N/2個第一暫時訊號，當中，N為4的倍數之正整數。該第二運算單元連接至該第一運算單元，對該N/2個第一暫時訊 號執行排列運算，以產生N/2個第二暫時訊號。該反離散餘弦第二型(IDCT-II)單元連接至該第二運算單元，對該N/2個第二暫時訊號執行運算，以產生與該輸入數位訊號對應之N/2個第三暫時訊號。該第三運算單元連接至該IDCT-II單元，對該N/2個第三暫時訊號執行排列運算，以產生N/2個第一輸出數位訊號。該第四運算單元連接至該第三運算單元，對該N/2個第一輸出數位訊號執行排列運算，以產生N個第二輸出數位訊號；其中，當該系統的輸入為該N個輸入數位訊號時，該第三運算單元輸出之該N/2個第一輸出數位訊號係為與該N個輸入數位訊號對應之離散餘弦訊號，當該系統的輸入為該第一暫時訊號時，該第四運算單元輸出之該N個第二輸出數位訊號係為與該第一暫時訊號對應之反離散餘弦訊號。 According to a feature of the present invention, the present invention provides a recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising a first arithmetic unit, a a second arithmetic unit, an inverse discrete cosine second type (IDCT-II) unit, a third arithmetic unit, and a fourth arithmetic unit. The first computing unit receives N input digital signals, and performs operations on the N digital signals to generate N/2 first temporary signals, where N is a positive integer of a multiple of 4. The second computing unit is connected to the first computing unit, and the N/2 first temporary messages The number performs an arrangement operation to generate N/2 second temporary signals. The inverse discrete cosine second type (IDCT-II) unit is connected to the second operation unit, and performs operations on the N/2 second temporary signals to generate N/2 third temporary corresponding to the input digital signal. Signal. The third operation unit is connected to the IDCT-II unit, and performs an arrangement operation on the N/2 third temporary signals to generate N/2 first output digital signals. The fourth operation unit is connected to the third operation unit, and performs an arrangement operation on the N/2 first output digital signals to generate N second output digital signals; wherein, when the input of the system is the N inputs The digital output signal, the N/2 first output digital signals outputted by the third computing unit are discrete cosine signals corresponding to the N input digital signals, when the input of the system is the first temporary signal, The N second output digit signals output by the fourth computing unit are inverse discrete cosine signals corresponding to the first temporary signal.

依據本發明之另一特色，本發明提出一種遞迴式離散餘弦正、逆轉換之系統，其係以反離散餘弦第二型(IDCT-II)為核心，該系統包含一第一運算單元、一第二運算單元、一第三運算單元、一第四運算單元、一第一反離散餘弦第二型(IDCT-II)單元、一第二反離散餘弦第二型(IDCT-II)單元、一第五運算單元、一第六運算單元、及一第七運算單元。該第一運算單元接收N個輸入數位訊號，對該N個數位訊號執行運算，以產生N/2個第一暫時訊號，當中，N為8的倍數之正整數。該第二運算單元連接至該第一運算單元，對該N/2個第一暫時訊號執行排列運算，以產生N/2個第二暫時訊號。該第三運算單元連接至該第二運算單元，對該N/2個第二暫時訊號執行運算， 以產生N/4個第三暫時訊號及N/4個第四暫時訊號。該第四運算單元連接至該第三運算單元，對該N/4個第四暫時訊號執行運算，以產生N/4個第五暫時訊號。該第一反離散餘弦第二型(IDCT-II)單元連接至該第三運算單元，對該N/4個第三暫時訊號執行運算，以產生N/4個第六暫時訊號。該第二反離散餘弦第二型(IDCT-II)單元連接至該第四運算單元，對該N/4個第五暫時訊號執行運算，以產生N/4個第七暫時訊號。該第五運算單元連接至該第二反離散餘弦第二型(IDCT-II)單元，對該N/4個第七暫時訊號執行運算，以產生N/4個第八暫時訊號。該第六運算單元連接至該第一反離散餘弦第二型(IDCT-II)單元及該第五運算單元，對該N/4個第六暫時訊號及該N/4個第八暫時訊號執行運算，以產生N/2個第一輸出訊號。該第七運算單元連接至該第六運算單元，對該N/2個第一輸出訊號執行運算，以產生N個第二輸出訊號。其中，當該系統的輸入為該N個輸入數位訊號時，該第六運算單元輸出之該N/2個第一輸出訊號係為與該N個輸入數位訊號對應之離散餘弦訊號，當該系統的輸入為該第一暫時訊號時，該第七運算單元輸出之該N個第二輸出數位訊號係為與該第一暫時訊號對應之反離散餘弦訊號。 According to another feature of the present invention, the present invention provides a recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising a first arithmetic unit, a second arithmetic unit, a third arithmetic unit, a fourth arithmetic unit, a first inverse discrete cosine second type (IDCT-II) unit, a second inverse discrete cosine second type (IDCT-II) unit, a fifth arithmetic unit, a sixth arithmetic unit, and a seventh arithmetic unit. The first operation unit receives N input digital signals, and performs operations on the N digital signals to generate N/2 first temporary signals, where N is a positive integer of a multiple of 8. The second operation unit is connected to the first operation unit, and performs an arrangement operation on the N/2 first temporary signals to generate N/2 second temporary signals. The third operation unit is connected to the second operation unit, and performs an operation on the N/2 second temporary signals, To generate N/4 third temporary signals and N/4 fourth temporary signals. The fourth operation unit is connected to the third operation unit, and performs an operation on the N/4 fourth temporary signals to generate N/4 fifth temporary signals. The first inverse discrete cosine second type (IDCT-II) unit is connected to the third arithmetic unit, and performs an operation on the N/4 third temporary signals to generate N/4 sixth temporary signals. The second inverse discrete cosine second type (IDCT-II) unit is connected to the fourth arithmetic unit, and performs an operation on the N/4 fifth temporary signals to generate N/4 seventh temporary signals. The fifth arithmetic unit is coupled to the second inverse discrete cosine second type (IDCT-II) unit, and performs an operation on the N/4 seventh temporary signals to generate N/4 eighth temporary signals. The sixth arithmetic unit is connected to the first inverse discrete cosine second type (IDCT-II) unit and the fifth arithmetic unit, and performs the N/4 sixth temporary signals and the N/4 eighth temporary signals. Operate to generate N/2 first output signals. The seventh operation unit is connected to the sixth operation unit, and performs operations on the N/2 first output signals to generate N second output signals. Wherein, when the input of the system is the N input digit signals, the N/2 first output signals output by the sixth operation unit are discrete cosine signals corresponding to the N input digital signals, when the system When the input is the first temporary signal, the N second output digital signals output by the seventh computing unit are inverse discrete cosine signals corresponding to the first temporary signal.

圖1係本發明之遞迴式離散餘弦正、逆轉換之系統100之一實施例的示意圖。其係以反離散餘弦第二型(IDCT-II)為核心，該系統100包括一第一運算單元 110、一第二運算單元120、一反離散餘弦第二型(IDCT-II)單元130、一第三運算單元140、及一第四運算單元150。 1 is a schematic diagram of one embodiment of a system 100 of recursive discrete cosine forward and reverse conversions of the present invention. It is based on the inverse discrete cosine second type (IDCT-II), which includes a first arithmetic unit. 110. A second computing unit 120, an inverse discrete cosine second type (IDCT-II) unit 130, a third computing unit 140, and a fourth computing unit 150.

該第一運算單元110係接收N個輸入數位訊號(x[0~7])，對該N個數位訊號執行運算，以產生N/2個第一暫時訊號(p[0~3])，當中，N為4的倍數之正整數。為方便說明，於說明書及圖式中，係以N為8予以說明。 The first computing unit 110 receives N input digital signals (x[0~7]), and performs operations on the N digital signals to generate N/2 first temporary signals (p[0~3]). Where N is a positive integer of a multiple of four. For convenience of explanation, in the specification and the drawings, N is 8 to be described.

該第二運算單元120連接至該第一運算單元110，以對該N/2個第一暫時訊號(p[0~3])執行排列運算，而產生N/2個第二暫時訊號(z[0~3])。 The second operation unit 120 is connected to the first operation unit 110 to perform an arrangement operation on the N/2 first temporary signals (p[0~3]), and generates N/2 second temporary signals (z [0~3]).

該反離散餘弦第二型(IDCT-II)單元130連接至該第二運算單元120，以對該N/2個第二暫時訊號(z[0~3])執行運算，而產生與該輸入數位訊號(x[0~7])對應之N/2個第三暫時訊號(Z[0~3])。 The inverse discrete cosine second type (IDCT-II) unit 130 is connected to the second operation unit 120 to perform an operation on the N/2 second temporary signals (z[0~3]), and generate the input The digital signal (x[0~7]) corresponds to N/2 third temporary signals (Z[0~3]).

該第三運算單元140連接至該反離散餘弦第二型(IDCT-II)單元130，以對該N/2個第三暫時訊號(Z[0~3])執行排列運算，而產生N/2個第一輸出數位訊號(X[0~3])。 The third operation unit 140 is connected to the inverse discrete cosine second type (IDCT-II) unit 130 to perform an arrangement operation on the N/2 third temporary signals (Z[0~3]) to generate N/ 2 first output digital signals (X[0~3]).

該第四運算單元150連接至該第三運算單元140，以對該N/2個第一輸出數位訊號(X[0~3])執行排列運算，而產生N個第二輸出數位訊號(x’[0~7])。 The fourth operation unit 150 is connected to the third operation unit 140 to perform an arrangement operation on the N/2 first output digital signals (X[0~3]), and generate N second output digital signals (x) '[0~7]).

當該系統的輸入為該N個輸入數位訊號(x[0~7])時，該第三運算單元輸出之該N/2個第一輸出數位訊號(X[0~3])係為與該N個輸入數位訊號(x[0~7])對應之離散餘弦訊號。 When the input of the system is the N input digit signals (x[0~7]), the N/2 first output digit signals (X[0~3]) output by the third operation unit are The N input digital signals (x[0~7]) correspond to discrete cosine signals.

當該系統的輸入為該第一暫時訊號(p[0~3])時，該第四運算單元輸出之該N個第二輸出數位訊號(x’[0~7])係 為與該第一暫時訊號(p[0~3])對應之反離散餘弦訊號。此時，該第一暫時訊號(p[0~3])係由外部輸入，而非由該第一運算單元110所產生。 When the input of the system is the first temporary signal (p[0~3]), the N second output digital signals (x'[0~7]) output by the fourth computing unit are Is an inverse discrete cosine signal corresponding to the first temporary signal (p[0~3]). At this time, the first temporary signal (p[0~3]) is input from the outside, not generated by the first operation unit 110.

該N個實數輸入數位訊號(x[0~7])其改良型離散餘弦轉換(MDCT)轉換可用公式(1)表示： The modified real discrete cosine transform (MDCT) conversion of the N real number input digital signals (x[0~7]) can be expressed by the formula (1):

根據餘弦(cosine)的對稱性，可以把公式(1)化簡成公式(2)： 其中， 假設p[n]=z[n]+z[n+1]，n由N/2到1，將p[n]代回公式(1)中可以化簡成z[n]和X[k]的關係式，其化簡過程如公式(4)所示。 According to the symmetry of cosine, formula (1) can be reduced to formula (2): among them, Suppose p[n]=z[n]+z[n+1], n is from N/2 to 1, and p[n] is returned to the formula (1) and can be reduced to z[n] and X[k The relational formula, the simplification process is shown in formula (4).

令且代回公式(4)中，可以將z[n]和X[k]的關係改寫成式公式(5)；其中假設Z[k]如公式(6)所示，公式(4)可以化簡成較簡單的算式如公式(5)所示； make And In the formula (4), the relationship between z[n] and X[k] can be rewritten into the formula (5); where Z[k] is assumed to be as shown in equation (6), and equation (4) can be simplified. A simpler formula is shown in equation (5);

公式(6)為一個以反離散餘弦第二型(IDCT-II)為核心的型式，根據C.Che-Hong,L.Bin-Da,and Y.Jar-Ferr，在Circuits and Systems II：Analog and Digital Signal Processing,IEEE Transactions on,vol.50,pp.38-45,2003所發表的論文"Recursive architectures for realizing modified discrete cosine transform and its inverse"中所提出的架構，可將序列Z[k]頭尾相加，再套用三角函數對其做化簡，可以消除掉k的奇數項，只運算偶數項的值如式公式(8)所示；同理將序列Z[k]頭尾相減，再套用三角函數對其做化簡，可以消除掉k的偶數項如公式(9)所示。 Equation (6) is a type with the inverse discrete cosine type II (IDCT-II) as the core, according to C. Che-Hong, L. Bin-Da, and Y. Jar-Ferr, in Circuits and Systems II: Analog And Digital Signal Processing, IEEE Transactions on, vol. 50, pp. 38-45, 2003, published in the paper "Recursive architectures for realizing modified discrete cosine transform and its inverse", the sequence Z[k] Add the head and tail, and then apply the trigonometric function To simplify it, you can eliminate the odd number of k, and only calculate the value of the even term as shown in equation (8); similarly, subtract the head and tail of the sequence Z[k], and then apply the trigonometric function. To simplify it, you can eliminate the even term of k as shown in equation (9).

假設，公式(8)中PN/2-2[k]所表示的流程推導如公式(10)所示，公式(9)中Q N/2-2[k]所表示的流程推導如式公式(11)所示。 Hypothesis , the flow derivation represented by P N/2-2 [k] in the formula (8) is as shown in the formula (10), and the flow derivation represented by Q N /2-2 [ k ] in the formula (9) is as the formula (11) is shown.

根據前述所提到的推導過程由式公式(1)至公式(7)可知，改良型離散餘弦轉換(MDCT)的示意圖如圖2所示，圖2係N/4點改良型離散餘弦轉換(MDCT)的示意圖，當中，N以8為例。改良型離散餘弦轉換(MDCT)的反離散餘弦第二型(IDCT-II)核心架構示意圖由公式(10)至公式(11)表示，圖3係為反離散餘弦第二型(IDCT-II)核心架構130之方塊圖，其係由加法器310,311,312,320,321,322,323、乘法器313,314,315,324,325,326、延遲裝置316,317,327,328所組成。 According to the above-mentioned derivation process, from the formula (1) to the formula (7), a schematic diagram of the modified discrete cosine transform (MDCT) is shown in FIG. 2, and FIG. 2 is an N/4 point modified discrete cosine transform ( A schematic diagram of MDCT), where N is 8 as an example. The modified discrete cosine transform (MDCT) inverse discrete cosine second type (IDCT-II) core architecture is represented by equation (10) to equation (11), and Figure 3 is the inverse discrete cosine second type (IDCT-II) The block diagram of core architecture 130 is comprised of adders 310, 311, 312, 320, 321, 322, 323, multipliers 313, 314, 315, 324, 325, 326, delay devices 316, 317, 327, 328.

而N/2點輸入的逆改良型離散餘弦轉換(IMDCT)轉換如公式(12)所示。假設一個新的序列y[n]，其定義如公式(13a)及公式(13b)所示，代入套用到逆改良型離散餘弦轉換(IMDCT)的原始方程式可以化簡成離散餘弦第四型(DCT-IV)的型式，如公式(14)所示；再根據前述的推導流程如公式(4)至公式(7)，可以把公式(14)推導成以反離散餘弦第二型(IDCT-II)為核心的示意圖，圖4係N/4點逆改 良型離散餘弦轉換(IMDCT)的示意圖。其中改良型離散餘弦轉換(MDCT)與逆改良型離散餘弦轉換(IMDCT)差在改良型離散餘弦轉換(MDCT)需要先做對公式(3a)及公式(3b)，逆改良型離散餘弦轉換(IMDCT)需要做對應公式(13a)及公式(13b)，因此中間的推導流程可以共用，故依據圖2及圖4可以獲得圖1中本發明該遞迴式離散餘弦正、逆轉換之系統100之示意圖。 The inverse modified discrete cosine transform (IMDCT) conversion of the N/2 point input is shown in equation (12). Suppose a new sequence y[n] is defined as shown in equations (13a) and (13b), and the original equation applied to the inverse modified discrete cosine transform (IMDCT) can be reduced to the fourth form of discrete cosine ( The type of DCT-IV) is shown in formula (14); and according to the above derivation flow, such as formula (4) to formula (7), formula (14) can be deduced to be inverse discrete cosine type 2 (IDCT- II) is the core diagram, Figure 4 is the N/4 point inverse Schematic diagram of good-form discrete cosine transform (IMDCT). The improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) difference in the modified discrete cosine transform (MDCT) need to be done first on the formula (3a) and the formula (3b), inverse modified discrete cosine transform ( IMDCT) needs to make the corresponding formula (13a) and formula (13b), so the intermediate derivation process can be shared, so according to FIG. 2 and FIG. 4, the recursive discrete cosine forward and inverse conversion system 100 of the present invention in FIG. 1 can be obtained. Schematic diagram.

由於改良型離散餘弦轉換(MDCT)經過一次的前處理可以化簡成離散餘弦第四型(DCT-IV)的型式如公式(2)所示，而離散餘弦第四型(DCT-IV)的特性在於k與n對稱，運算出來的結果會是一樣的，而這樣推導的目的在於可以使前處理的運算更為快速、精簡，且核心統一以反離散餘弦第二型(IDCT-II)的型式來實現。 Since the modified discrete cosine transform (MDCT) can be reduced to a discrete cosine fourth type (DCT-IV) by one pre-processing, as shown in equation (2), and discrete cosine fourth type (DCT-IV) The characteristic is that k and n are symmetric, and the result of the operation will be the same, and the purpose of this derivation is to make the pre-processing operation faster and more streamlined, and the core is unified by the inverse discrete cosine type II (IDCT-II). The type is implemented.

由改良型離散餘弦轉換(MDCT)的前處理推導至反離散餘弦第二型(IDCT-II)型式的過程如公式(1)至公式(7)所示，此部分的處理需要N-1個加法運算，和N/2個乘法運算以及N/2個乘法係數使用量。 The process from the pre-processing of the modified discrete cosine transform (MDCT) to the inverse discrete cosine second type (IDCT-II) is shown in equations (1) through (7). The processing of this part requires N-1 Addition, and N/2 multiplication operations and N/2 multiplication coefficient usage.

由前面說明可知，該第一運算單元110、該N個輸入數位訊號(x[0~7])、與N/2個第一暫時訊號(p[0~3])係以下列公式描述： 當中，p[n]為該N/2個第一暫時訊號，x[n]為該N個輸入數位訊號。 As can be seen from the foregoing description, the first computing unit 110, the N input digital signals (x[0~7]), and the N/2 first temporary signals (p[0~3]) are described by the following formula: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals.

該第二運算單元120、該N/2個第一暫時訊號(p[0~3])與該N/2個第二暫時訊號(z[0~3])係以下列公式描述：p[n]=z[n]+z[n+1],for n=N/2-1 to 1，當中，z[n]為該N/2個第二暫時訊號(z[0~3])，p[n]為該N/2個第一暫時訊號(p[0~3])。 The second operation unit 120, the N/2 first temporary signals (p[0~3]) and the N/2 second temporary signals (z[0~3]) are described by the following formula: p[ n]=z[n]+z[n+1], for n=N/2-1 to 1, where z[n] is the N/2 second temporary signals (z[0~3]) , p[n] is the N/2 first temporary signals (p[0~3]).

該反離散餘弦第二型(IDCT-II)單元130、該N/2個第二暫時訊號(z[0~3])及該N/2個第三暫時訊號(Z[0~3])係以下列公式表示： 當中，Z[k]為該N/2個第三暫時訊號(Z[0~3])，z[n]為該N/2個第二暫時訊號(z[0~3])。 The inverse discrete cosine second type (IDCT-II) unit 130, the N/2 second temporary signals (z[0~3]), and the N/2 third temporary signals (Z[0~3]) It is expressed by the following formula: Where Z[k] is the N/2 third temporary signals (Z[0~3]), and z[n] is the N/2 second temporary signals (z[0~3]).

該第三運算單元140、該N/2個第三暫時訊號(Z[0~3])及該N/2個第一輸出數位訊號(X[0~3])係以下列公式表示： 當中，Z[k]為該N/2個第三暫時訊號(Z[0~3])，X[k]為該N/2個第一輸出數位訊號(X[0~3])。 The third operation unit 140, the N/2 third temporary signals (Z[0~3]), and the N/2 first output digital signals (X[0~3]) are expressed by the following formula: Where Z[k] is the N/2 third temporary signals (Z[0~3]), and X[k] is the N/2 first output digital signals (X[0~3]).

該第四運算單元150、該N/2個第一輸出數位訊號(X[0~3])及該N個第二輸出數位訊號(x[0~7])係以下列公式表示： 當中，x'[n]為該N個第二輸出數位訊號(x[0~7])，X[k]為該N/2個第一輸出數位訊號(X[0~3])。 The fourth computing unit 150, the N/2 first output digital signals (X[0~3]), and the N second output digital signals (x[0~7]) are represented by the following formula: Where x'[n] is the N second output digit signals (x[0~7]), and X[k] is the N/2 first output digit signals (X[0~3]).

為增加本發明該遞迴式離散餘弦正、逆轉換之系統100處理時序，可於該第二運算單元120增加一暫存器組160，以使該遞迴式離散餘弦正、逆轉換之系統100可平行化，惟該暫存器組160亦可不使用而不影響本發明之功能。 In order to increase the processing sequence of the recursive discrete cosine forward and reverse conversion system 100 of the present invention, a register group 160 may be added to the second operation unit 120 to enable the recursive discrete cosine forward and inverse conversion system. 100 can be parallelized, but the register set 160 can also be unused without affecting the functionality of the present invention.

圖5係本發明之遞迴式離散餘弦正、逆轉換之系統500之另一實施例之示意圖。其係為N/8點且以反離散餘弦第二型(IDCT-II)為核心，當中，N為8的倍數之正整數。該系統500包括一第一運算單元510、一第二運算單元520、一第三運算單元530、一第四運算單元540、一第一反離散餘弦第二型(IDCT-II)單元550、一第二反離散餘弦第二型(IDCT-II)單元560、一第五運算單元570、一第六運算單元580、及一第七運算單元590。於本實施例 中，係以N為16予以說明，但此並非為本發明之限制，熟於該技術者可依據本發明技術擴充至其他數目。 5 is a schematic diagram of another embodiment of a recursive discrete cosine forward and reverse conversion system 500 of the present invention. It is N/8 points and is based on the inverse discrete cosine second type (IDCT-II), where N is a positive integer of a multiple of 8. The system 500 includes a first computing unit 510, a second computing unit 520, a third computing unit 530, a fourth computing unit 540, a first inverse discrete cosine second type (IDCT-II) unit 550, and a The second inverse discrete cosine second type (IDCT-II) unit 560, a fifth arithmetic unit 570, a sixth arithmetic unit 580, and a seventh arithmetic unit 590. In this embodiment The description is made with N being 16 , but this is not a limitation of the present invention, and those skilled in the art can expand to other numbers according to the technology of the present invention.

該第一運算單元510接收N個輸入數位訊號(x[0~15])，以對該N個數位訊號執行運算，而產生N/2個第一暫時訊號(p[0~7])。 The first operation unit 510 receives N input digital signals (x[0~15]) to perform operations on the N digital signals, and generates N/2 first temporary signals (p[0~7]).

該第二運算單元520連接至該第一運算單元510，以對該N/2個第一暫時訊號(p[0~7])執行排列運算，而產生N/2個第二暫時訊號(z[0~7])。 The second operation unit 520 is connected to the first operation unit 510 to perform an arrangement operation on the N/2 first temporary signals (p[0~7]), and generates N/2 second temporary signals (z [0~7]).

該第三運算單元530連接至該第二運算單元520，以對該N/2個第二暫時訊號(z[0~7])執行運算，而產生N/4個第三暫時訊號(ze[0~3])及N/4個第四暫時訊號(zo[0~3])。 The third operation unit 530 is connected to the second operation unit 520 to perform an operation on the N/2 second temporary signals (z[0~7]) to generate N/4 third temporary signals (z e [0~3]) and N/4 fourth temporary signals (z o [0~3]).

該第四運算單元540連接至該第三運算單元530，以對該N/4個第四暫時訊號(zo[0~3])執行運算，而產生N/4個第五暫時訊號(zo[n](1))。 The fourth operation unit 540 is connected to the third operation unit 530 to perform an operation on the N/4 fourth temporary signals (z o [0~3]) to generate N/4 fifth temporary signals (z o [n] (1) ).

該第一反離散餘弦第二型(IDCT-II)單元550連接至該第三運算單元530，以對該N/4個第三暫時訊號(ze[0~3])執行運算，而產生N/4個第六暫時訊號(Ze[K])。 The first inverse discrete cosine second type (IDCT-II) unit 550 is connected to the third operation unit 530 to perform an operation on the N/4 third temporary signals (z e [0~3]) to generate N/4 sixth temporary signals (Z e [K]).

該第二反離散餘弦第二型(IDCT-II)單元560連接至該第四運算單元540，以對該N/4個第五暫時訊號(zo[n](1))執行運算，而產生N/4個第七暫時訊號(Zo[K](1))。 The second inverse discrete cosine second type (IDCT-II) unit 560 is connected to the fourth arithmetic unit 540 to perform an operation on the N/4 fifth temporary signals (z o [n] (1) ), and Generate N/4 seventh temporary signals (Z o [K] (1) ).

該第五運算單元570連接至該第二反離散餘弦第二型(IDCT-II)單元560，以對該N/4個第七暫時訊號(Zo[K](1))執行運算，而產生N/4個第八暫時訊號(Zo[K])。 The fifth arithmetic unit 570 is connected to the second inverse discrete cosine second type (IDCT-II) unit 560 to perform an operation on the N/4 seventh temporary signals (Z o [K] (1) ), and Generate N/4 eighth temporary signals (Z o [K]).

該第六運算單元580連接至該第一反離散餘弦第二型(IDCT-II)單元及該第五運算單元570，以對該N/4個第六暫時訊號(Ze[K])及該N/4個第八暫時訊號(Zo[K])執行運算，而產生N/2個第一輸出訊號(X[K])。 The sixth arithmetic unit 580 is connected to the first inverse discrete cosine second type (IDCT-II) unit and the fifth arithmetic unit 570 to the N/4 sixth temporary signals (Z e [K]) and The N/4 eighth temporary signals (Z o [K]) perform an operation to generate N/2 first output signals (X[K]).

該第七運算單元590連接至該第六運算單元580，以對該N/2個第一輸出訊號(X[K])執行運算，而產生N個第二輸出訊號(x'[n])。 The seventh operation unit 590 is connected to the sixth operation unit 580 to perform an operation on the N/2 first output signals (X[K]) to generate N second output signals (x'[n]) .

當該系統的輸入為該N個輸入數位訊號(x[0~15])時，該第六運算單元580輸出之該N/2個第一輸出訊號(X[K])係為與該N個輸入數位訊號(x[0~15])對應之離散餘弦訊號。 When the input of the system is the N input digit signals (x[0~15]), the N/2 first output signals (X[K]) output by the sixth operation unit 580 are associated with the N Enter the discrete cosine signal corresponding to the digital signal (x[0~15]).

當該系統的輸入為該第一暫時訊號(p[0~7])時，該第七運算單元590輸出之該N個第二輸出數位訊號(x’[0~15])係為與該第一暫時訊號(p[0~7])對應之反離散餘弦訊號。此時，該第一暫時訊號(p[0~7])係由外部輸入，而非由該該第一運算單元510所產生。 When the input of the system is the first temporary signal (p[0~7]), the N second output digit signals (x'[0~15]) output by the seventh operation unit 590 are The inverse temporary cosine signal corresponding to the first temporary signal (p[0~7]). At this time, the first temporary signal (p[0~7]) is input from the outside, not generated by the first operation unit 510.

根據公式(5)、公式(6)、公式(7)，可針對Z[k]中n的奇、偶分開討論如下： According to formula (5), formula (6), and formula (7), the odd and even splits of n in Z[k] can be discussed as follows:

當n為偶數(n=2n)，代入Z[k]公式(6)中可以得到如公式(15)的結果。由公式(15)，可以很明顯的看出Ze[k]為反離散餘弦第二型(IDCT-II)型式，其中可以發現當k=0至k=N/4-1時Ze[k]=Ze[N/2-1-k]，因此直接套用反離散餘弦第二型(IDCT-II)架構公式(6)至公式(9)，可以得到公式(16) 和式(17)的結果。其中PN/4-2[k]與QN/4-1[k]如公式(10)和公式(11)所示。 When n is an even number (n=2n), substituting into Z[k] equation (6) gives the result as in equation (15). From equation (15), it can be clearly seen that Z e [k] is an inverse discrete cosine second type (IDCT-II) type, in which it can be found that when k=0 to k=N/4-1, Ze[k] ]=Ze[N/2-1-k], so directly applying the inverse discrete cosine second type (IDCT-II) architecture formula (6) to formula (9), we can get the formulas (16) and (17) result. Where PN/4-2[k] and QN/4-1[k] are as shown in equations (10) and (11).

當中， ， (15) among, , (15)

當n為奇數(n=2n+1)，代入Z[k]公式(6)中，可以得到如公式(18)的結果，可以發現公式(18)為反離散餘弦第四型(IDCT-IV)型式，可藉由反離散餘弦第四型(IDCT-IV)化簡成反離散餘弦第二型(IDCT-II)的型式。假設zo[n]=zo[n](1)+zo[n+1](1)代入公式(18)中，其推導過程與結果如公式(19)所示。 When n is an odd number (n=2n+1) and substituted into Z[k] equation (6), the result of equation (18) can be obtained. It can be found that equation (18) is the fourth type of inverse discrete cosine (IDCT-IV). The type can be reduced to the inverse discrete cosine second type (IDCT-II) by inverse discrete cosine fourth type (IDCT-IV). Suppose z o [n]=z o [n] (1) +z o [n+1] (1) Substituting into equation (18), the derivation process and result are as shown in equation (19).

當中， ， (18) among, , (18)

假設zo[N/4](1)=0及，並代回公式(19)中，可以將zo[n](1)和Zo[k]的關係改寫成公式(10)，其中假設Zo[k]如公式(12)所示，可以化簡成較簡單的算式如下所示： Suppose z o [N/4] (1) =0 and And substituting back into the formula (19), the relationship between z o [n] (1) and Z o [k] can be rewritten into the formula (10), where Z o [k] is assumed to be as shown in the formula (12). The simpler formula that can be reduced to is as follows:

可以很明顯的看出公式(21)為反離散餘弦第二型(IDCT-II)型式，另一方面可以發現當k=0至k=N/4-1，時Zo[k](1)=Zo[N/2-1-k]，因此直接套用反離散餘弦第二型(IDCT-II)架構公式(6)至公式(9)，可以得到公式(23)和公 式(24)的結果。其中PN/4-2[k]與QN/4-1[k]如公式(10)和公式(11)所示。 It can be clearly seen that the formula (21) is the inverse discrete cosine second type (IDCT-II) type, on the other hand, it can be found that when k=0 to k=N/4-1, Zo[k](1) =Zo[N/2-1-k], so the result of formula (23) and formula (24) can be obtained by directly applying the inverse discrete cosine second type (IDCT-II) architecture formula (6) to formula (9). . Wherein P N/4-2 [k] and Q N/4-1 [k] are as shown in equations (10) and (11).

根據前述所提到的推導過程公式(15)至公式(14)，N/8點改良型離散餘弦轉換(MDCT)的示意圖如圖6所示，其中公式(16)、公式(17)、公式(23)、公式(24)組成反離散餘弦第二型(IDCT-II)核心架構，圖7係本發明反離散餘弦第二型(IDCT-II)核心架構550,560之方塊圖，其係由加法器510,511,512,520,521,522,523、乘法器513,514,515,524,525,526、延遲裝置516,517,527,528、及暫存器組518,529所組成。 According to the above-mentioned derivation process formulas (15) to (14), a schematic diagram of the N/8 point modified discrete cosine transform (MDCT) is shown in Fig. 6, where equation (16), formula (17), and formula (23), formula (24) constitutes the inverse discrete cosine second type (IDCT-II) core architecture, and FIG. 7 is a block diagram of the inverse discrete cosine second type (IDCT-II) core architecture 550, 560 of the present invention, which is added by The units are 510, 511, 512, 520, 521, 522, 523, multipliers 513, 514, 515, 524, 525, 526, delay devices 516, 517, 527, 528, and register sets 518, 529.

如圖7所示，其單一轉換資料流量(Data Throughput per Transformation,DTPT)為4和8，且運算速度為(N2/64+N/4)個週期。 As shown in FIG. 7, the Data Throughput Per Transformation (DTPT) is 4 and 8, and the operation speed is (N 2 /64 + N / 4) cycles.

N/2點輸入的送改良型離散餘弦轉換(IMDCT)方程式可以化簡成離散餘弦第四型(DCT-IV)的型式，如公式(12)至公式(14)所示，可以把公式(14)推導成以反離散餘 弦第二型(IDCT-II)為核心N/8點逆改良型離散餘弦轉換(IMDCT)的示意圖，圖8係本發明以反離散餘弦第二型(IDCT-II)為核心N/8點逆改良型離散餘弦轉換(IMDCT)的示意圖。由於改良型離散餘弦轉換(MDCT)與逆改良型離散餘弦轉換(IMDCT)都可拆解成離散餘弦第四型(DCT-IV)型式的方程式，差別在於改良型離散餘弦轉換(MDCT)要經過前處理的對折公式(3a)及公式(3b)，逆改良型離散餘弦轉換(IMDCT)需經過後處理的資料映射公式(13a)及公式(13b)，因此可以採用共同的架構來運算改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)，故依據圖6及圖8可以獲得圖5中本發明該遞迴式離散餘弦正、逆轉換之系統500之示意圖。 The improved discrete cosine transform (IMDCT) equation for the N/2 point input can be reduced to the discrete cosine fourth type (DCT-IV) type, as shown in equations (12) through (14). 14) Derivation into inverse discrete The second type of string (IDCT-II) is a schematic diagram of the core N/8 point inverse modified discrete cosine transform (IMDCT), and FIG. 8 is the N/8 point of the present invention with the inverse discrete cosine second type (IDCT-II) as the core. Schematic diagram of inverse modified discrete cosine transform (IMDCT). Since the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT) can be decomposed into the discrete cosine fourth type (DCT-IV) type equation, the difference is that the modified discrete cosine transform (MDCT) goes through The pre-processed bifurcation formula (3a) and formula (3b), inverse modified discrete cosine transform (IMDCT) require post-processing data mapping formula (13a) and formula (13b), so a common architecture can be used to calculate the improved type. Discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT), the schematic diagram of the recursive discrete cosine forward and inverse transform system 500 of the present invention in FIG. 5 can be obtained according to FIG. 6 and FIG.

由前述說明可知，該第一運算單元510、該N個輸入數位訊號(x[0~15])、與N/2個第一暫時訊號(p[0~7])係以下列公式描述： 當中，p[n]為該N/2個第一暫時訊號，x[n]為該N個輸入數位訊號。 As can be seen from the foregoing description, the first computing unit 510, the N input digital signals (x[0~15]), and the N/2 first temporary signals (p[0~7]) are described by the following formula: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals.

該第二運算單元520、該N/2個第一暫時訊號(p[0~7])與該N/2個第二暫時訊號(z[0~7])係以下列公式描述：p[n]=z[n]+z[n+1],for n=N/2-1 to 1， 當中，z[n]為該N/2個第二暫時訊號(z[0~7])，p[n]為該N/2個第一暫時訊號(p[0~7])。 The second operation unit 520, the N/2 first temporary signals (p[0~7]) and the N/2 second temporary signals (z[0~7]) are described by the following formula: p[ n]=z[n]+z[n+1],for n=N/2-1 to 1, Where z[n] is the N/2 second temporary signals (z[0~7]), and p[n] is the N/2 first temporary signals (p[0~7]).

該第三運算單元530、該N/2個第二暫時訊號(z[0~7])、該N/4個第三暫時訊號(ze[0~3])及該N/4個第四暫時訊號(zo[0~3])係以下列公式表示： 當中，z[n]為該N/2個第二暫時訊號(z[0~7])，ze[n]為該N/4個第三暫時訊號(ze[0~3])，zo[n]為該N/4個第四暫時訊號(zo[0~3])。 The third operation unit 530, the N/2 second temporary signals (z[0~7]), the N/4 third temporary signals (z e [0~3]), and the N/4th The four temporary signals (zo[0~3]) are expressed by the following formula: Where z[n] is the N/2 second temporary signals (z[0~7]), and z e [n] is the N/4 third temporary signals (z e [0~3]), z o [n] is the N/4 fourth temporary signals (z o [0~3]).

該第四運算單元540、該該N/4個第四暫時訊號(zo[0~3])及該N/4個第五暫時訊號(zo[n](1))係以下列公式表示：zo[n]=zo[n](1)+zo[n+1](1)，當中，zo[n]為該N/4個第四暫時訊號(zo[0~3])，zo[n](1)為該N/4個第五暫時訊號(zo[n](1))。 The fourth operation unit 540, the N/4 fourth temporary signals (z o [0~3]), and the N/4 fifth temporary signals (z o [n] (1) ) are based on the following formula Representation: z o [n]=z o [n] (1) +z o [n+1] (1) , where z o [n] is the N/4th fourth temporary signal (z o [0 ~3]), z o [n] (1) is the N/4 fifth temporary signals (z o [n] (1) ).

該第一反離散餘弦第二型(IDCT-II)單元550、該N/4個第三暫時訊號(ze[0~3])及該N/4個第六暫時訊號(Ze[K])係以下列公式表示： 當中，ze[n]為該N/4個第三暫時訊號(ze[0~3])，Ze[K]為該N/4個第六暫時訊號(Ze[K])。 The first inverse discrete cosine second type (IDCT-II) unit 550, the N/4 third temporary signals (z e [0~3]), and the N/4 sixth temporary signals (Z e [K ]) is expressed by the following formula: Where z e [n] is the N/4 third temporary signals (z e [0~3]), and Z e [K] is the N/4 sixth temporary signals (Z e [K]).

該第二反離散餘弦第二型(IDCT-II)單元560、該N/4個第五暫時訊號(zo[n](1))及該N/4個第七暫時訊號(Zo[K](1))係以下列公式表示： 當中，Zo[K](1)為該N/4個第七暫時訊號(Zo[K](1))，zo[n](1)為該N/4個第五暫時訊號(zo[n](1))。 The second inverse discrete cosine second type (IDCT-II) unit 560, the N/4 fifth temporary signals (z o [n] (1) ) and the N/4 seventh temporary signals (Z o [ K] (1) ) is expressed by the following formula: Where Z o [K] (1) is the N/4th seventh temporary signal (Z o [K] (1) ), z o [n] (1) is the N/4th fifth temporary signal ( z o [n] (1) ).

該第五運算單元570、該N/4個第七暫時訊號(Zo[K](1))及該N/4個第八暫時訊號(Zo[K])係以下列公式表示： 當中，Zo[K]為該N/4個第八暫時訊號(Zo[K])，Zo[K](1)為該N/4個第七暫時訊號(Zo[K](1))。 The fifth arithmetic unit 570, the N/4 seventh temporary signals (Z o [K] (1) ), and the N/4 eighth temporary signals (Z o [K]) are expressed by the following formula: Among them, Z o [K] is the N/4 eighth temporary signals (Z o [K]), and Z o [K] (1) is the N/4 seventh temporary signals (Z o [K] ( 1) ).

該第六運算單元580、該N/4個第六暫時訊號(Ze[K])、該N/4個第八暫時訊號(Zo[K])及該N/2個第一輸出訊號(X[K])係以下列公式表示： 當中，X[K]為該N/2個第一輸出訊號(X[K])，Z[K]為該N/4個第六暫時訊號(Ze[K])及該N/4個第八暫時訊號(Zo[K])的組合。 The sixth arithmetic unit 580, the N/4 sixth temporary signals (Z e [K]), the N/4 eighth temporary signals (Z o [K]), and the N/2 first output signals (X[K]) is expressed by the following formula: Where X[K] is the N/2 first output signals (X[K]), Z[K] is the N/4 sixth temporary signals (Z e [K]) and the N/4 The combination of the eighth temporary signal (Z o [K]).

該第七運算單元590、該N/2個第一輸出訊號(X[K])及該N個第二輸出訊號(x'[n])係以下列公式表示： 當中，x’[n]為該N個第二輸出數位訊號(x’[0~15])，X[k]為該N/2個第一輸出數位訊號(X[0~7])。 The seventh operation unit 590, the N/2 first output signals (X[K]), and the N second output signals (x'[n]) are expressed by the following formula: Where x'[n] is the N second output digit signals (x'[0~15]), and X[k] is the N/2 first output digit signals (X[0~7]).

本發明針對改良型離散餘弦轉換(MDCT)與逆改良型離散餘弦轉換(IMDCT)轉換提出基於反離散餘弦第二型(IDCT-II)為核心、快速且共架構的系統，目的在於減少數位編解碼器(codec)平台上改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)的硬體實現成本。 The present invention proposes a system based on inverse discrete cosine second type (IDCT-II) as a core, fast and common architecture for improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) conversion, with the aim of reducing digital programming. Hardware implementation cost of modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) on the decoder (codec) platform.

由圖5可以得知，此部分的前處理需要N-1個加法運算，和N/2個乘法運算以及N/2個乘法係數的使用量，再根據對Z[k]中n的奇、偶分開討論，推導成兩組以反離散餘弦第二型(IDCT-II)為核心的型式，此部分的前處理需要N/4-1個加法運算，和N/4個乘法運算以及N/4個乘法係數使用量。而圖7中的核心部分則是兩組反離散餘弦第二型(IDCT-II)的型式，其運算複雜度需要N/2+3個加法運算和N/4+2個乘法運算共輸出兩筆結果，總共運算N/8次算出所有結果，核心部分使用了3*N/8個乘法係數。 It can be seen from Fig. 5 that the preprocessing of this part requires N-1 addition operations, and N/2 multiplication operations and the usage of N/2 multiplication coefficients, and then according to the oddity of n in Z[k] Even discussed separately, deduced into two groups with the inverse discrete cosine second type (IDCT-II) as the core, the preprocessing of this part requires N/4-1 addition operations, and N/4 multiplication operations and N/ 4 multiplication factor usage. The core part of Figure 7 is the two types of inverse discrete cosine second type (IDCT-II). The computational complexity requires N/2+3 addition operations and N/4+2 multiplication operations to output two. The result of the pen is calculated by a total of N/8 operations, and the core part uses 3*N/8 multiplication coefficients.

表4.1和表4.2為各方法的加法使用量，分別對改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)做說明。同時，表4.3和表4.4為各方法的乘法使用量，也 一樣分別對改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)做說明。每份表格分別針對前/後處理(Pre-/Post- processing)、核心運算(Recursive kernel)、總運算量(Total)做統計，以及最後一攔，根據本發明之技術為基準來統計其他方法額外增加的運算量之百分比例(Increase(%))。 Tables 4.1 and 4.2 show the additive usage of each method, and illustrate the modified discrete cosine transform (MDCT) and the inverse modified discrete cosine transform (IMDCT). At the same time, Tables 4.3 and 4.4 are the multiplications of each method, also The modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) are described separately. Each table is separately counted for Pre-/Post-processing, Recursive kernel, Total, and last block, and other methods are counted based on the technology of the present invention. An example of a percentage of the additional amount of computation (Increase (%)).

由之前的介紹可以得知，針對改良型離散餘弦轉換(MDCT)方法而言L.Lin et al.方法的前處理需要使用N個加法運算而核心需要使用3*N2/8+N/2個加法運算，Lei et al.的前處理需要使用5*N/4-1個加法運算而核心需要使用3*N2/8個加法運算，Lei et al.的前處理需要使用7*N/4-2個加法運算而核心需要使用3*N2/16個加法運算，本發明之技術的前處理需要使用5*N/4-2的加法運算，而核心需要使用N2/8+3*N/4個加法運算。 It can be known from the previous introduction that for the modified discrete cosine transform (MDCT) method, the preprocessing of the L.Lin et al. method requires N addition operations and the core needs to use 3*N 2 /8+N/2 For addition, the pre-processing of Lei et al. requires 5*N/4-1 additions and the core requires 3*N 2 /8 additions. The pre-processing of Lei et al. requires 7*N/ 4-2 additions and the core needs to use 3*N 2 /16 addition operations. The pre-processing of the technique of the present invention requires the addition of 5*N/4-2, and the core needs to use N 2 /8+3 *N/4 addition operations.

針對改良型離散餘弦轉換(MDCT)方法而言，前述方法的前處理都減少N/2個加法運算而核心部分的加法運算量則是相同的，表4.1和表4.2則是針對2048點來做為比較依據。 For the modified discrete cosine transform (MDCT) method, the pre-processing of the above method reduces N/2 addition operations and the addition amount of the core part is the same. Table 4.1 and Table 4.2 are for 2048 points. For comparison purposes.

由表4.1和表4.2中可以看出本發明的整體的加法總運算量是最少的，比起Lei et al.提出的方法在改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)兩方面分別減少了49.52%和49.61%的加法使用量。本發明和L.Li et al.比起來，則是減少了198.26%的加法使用量。由表4.2中可以看出Lei et al.以及本發明之技術是比較好的選擇。 It can be seen from Tables 4.1 and 4.2 that the overall additive total computation of the present invention is minimal, compared to the method proposed by Lei et al. in modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT). Both sides reduced the use of addition by 49.52% and 49.61% respectively. Compared with L. Li et al., the present invention reduces the amount of addition used by 198.26%. It can be seen from Table 4.2 that Lei et al. and the technique of the present invention are better choices.

對改良型離散餘弦轉換(MDCT)方法而言，L.Lin et al.方法的前處理需要使用N個乘法運算，而其核心需要使用N2/8+N/2個乘法運算。Lei et al.方法的前處理需要使用N/2個乘法運算，而核心需要使用N2/8+N/2個乘法運算，Lei et al.方法的前處理需要使用3*N/4個乘法運算，而核 心需要使用N2/16+N/2個乘法運算，本發明的前處理需要使用3*N/4的乘法運算，而核心需要使用N2/16+N/2個乘法運算。 For the modified discrete cosine transform (MDCT) method, the preprocessing of the L.Lin et al. method requires N multiplication operations, and its core needs to use N 2 /8+N/2 multiplication operations. The preprocessing of the Lei et al. method requires N/2 multiplication operations, while the core needs to use N 2 /8+N/2 multiplication operations. The preprocessing of the Lei et al. method requires 3*N/4 multiplications. The operation requires the core to use N 2 /16+N/2 multiplication operations. The pre-processing of the present invention requires the use of 3*N/4 multiplication operations, while the core requires N 2 /16+N/2 multiplication operations.

針對改良型離散餘弦轉換(MDCT)方法而言，前述方法的前處理和核心部分的乘法運算量則是相同的，表4.3和表4.4則是針對2048點來做為比較依據。 For the modified discrete cosine transform (MDCT) method, the preprocessing of the foregoing method and the multiplication of the core part are the same, and Tables 4.3 and 4.4 are based on 2048 points.

表4.3和表4.4中可以看出，本發明技術和Lei et al.的總乘法運算量是相同的。其他的方法則比本發明技術多出了將近一倍或更多的乘法使用量。 As can be seen in Tables 4.3 and 4.4, the total multiplication amount of the technique of the present invention and Lei et al. is the same. Other methods have nearly doubled or more multiplication usage than the present invention.

由表4.1至表4.4的統計數據來觀察，本發明的改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)方法和其他近期的論文做比較的結果分析，在運算複雜度上使用了少量的加法和乘法運算，這也表示著對於同樣點數的改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉換(IMDCT)，本發明的方法可以更快速、有效率的得到運算結果。 Observed from the statistical data in Tables 4.1 to 4.4, the improved discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) methods of the present invention are compared with other recent papers in terms of computational complexity. A small number of addition and multiplication operations are used, which also means improved differential discrete cosine transform (MDCT) and inverse modified discrete cosine transform (IMDCT) for the same number of points, and the method of the present invention can obtain operations more quickly and efficiently. result.

其次，針對各方法的乘法係數使用量做評估比較，針對改良型離散餘弦轉換(MDCT)方法而言，L.Lin et al.方法的前處理需要使用N個乘法係數使用量，而核心需要使用3*N/4個乘法係數使用量，Lei et al.的前處理需要使用N/2個乘法係數使用量，而核心需要使用N個乘法係數使用量，Lei et al.的前處理需要使用3*N/4個乘法係數使用量，而核心需要使用N/2個乘法係數使用量，本發明技術的前處理需要使用3*N/4的乘法係數使用量，而核心需要使用3*N/8個乘法係數使用量。針對改良型離散餘弦轉換(MDCT)方法而言，前述方法的前處理和核心部分的乘法係數使用量是相同的。 Secondly, for the comparison of the multiplication coefficient usage of each method, for the improved discrete cosine transform (MDCT) method, the preprocessing of the L.Lin et al. method requires the use of N multiplication coefficients, and the core needs to be used. 3*N/4 multiplication coefficient usage, Lei et al.'s pre-processing requires N/2 multiplication coefficient usage, while the core needs to use N multiplication coefficient usage, and Lei et al.'s pre-processing needs to use 3 *N/4 multiplication coefficient usage, and the core needs to use N/2 multiplication coefficient usage. The preprocessing of the present technology requires 3*N/4 multiplication coefficient usage, and the core needs to use 3*N/ 8 multiplication factor usage. For the modified discrete cosine transform (MDCT) method, the preprocessing of the foregoing method and the multiplication coefficient usage of the core portion are the same.

表4.5和表4.6為各方法的乘法係數使用量分析，分別為改良型離散餘弦轉換(MDCT)和逆改良型離散餘弦轉 換(IMDCT)的乘法係數使用量分析。表4.5中Lai et al.提出的方法使用最少的記憶體來儲存運算的係數，這是其所提出來的方法特點；除了Lai et al.之外，Lei et al.比本發明技術多出11%的乘法係數使用量，其它方法則是多出30%以上的乘法係數使用量。 Tables 4.5 and 4.6 are the multiplicative coefficient usage analysis of each method, which are modified discrete cosine transform (MDCT) and inverse modified discrete cosine transform. Change (IMDCT) multiplication factor usage analysis. The method proposed by Lai et al. in Table 4.5 uses the least amount of memory to store the coefficients of the operation, which is the characteristic of the proposed method; in addition to Lai et al., Lei et al. is 11 more than the technique of the present invention. The multiplication factor usage of %, the other method is more than 30% of the multiplication factor usage.

由公式(1)，可知需要N個記憶體來儲存輸入的N筆資料x[n]，公式(2)對改良型離散餘弦轉換(MDCT)的對稱性 做化簡之後，所需儲存的運算資料p[n]只需花費N/2個記憶體來儲存運算結果，由於x[n]序列化簡成p[n]後便不再使用，因此可以寫回儲存原始輸入的記憶體位置中，而剩下的N/2個記憶體可以當作暫存之後運算的位置，達到交替使用的目的並節省額外記憶體的需求。公式(4)的運算中將p[n]序列化簡成z[n]序列，公式(5)中的z[n]也只需使用到N/2個記憶體來儲存運算結果。在公式(15)和公式(18)中，將z[n]序列化簡成ze[n]和zo[n]兩個序列，分別需要N/4個記憶體來儲存運算結果，ze[n]的運算資料直接饋入核心做運算，而序列zo[n]則需再做一次前處理化簡成zo[n](1)序列，如公式(19)所示，而zo[n](1)序列需要N/4個記憶體來儲存運算結果之後饋入核心做運算。兩部分核心輸出的結果分別需要N/4個記憶體來儲存運算結果來儲存Ze[k]和Zo[k](1)兩個序列。最後，在經過後處理輸出最後的N/2筆的運算資料。可以得知，按照這樣的評估結果，本發明至多只需要N個記憶體就可以儲存所有運算過程的資料。 From equation (1), it can be seen that N memory is needed to store the input N data x[n], and equation (2) is used to simplify the symmetry of the modified discrete cosine transform (MDCT). The data p[n] only needs N/2 memory to store the operation result. Since the x[n] serialization is simply p[n], it is no longer used, so it can be written back to the memory location where the original input is stored. And the remaining N/2 memory can be used as the location of the operation after the temporary storage, to achieve the purpose of alternate use and save the need for additional memory. In the operation of equation (4), p[n] is serialized into a z[n] sequence, and z[n] in equation (5) also uses N/2 memories to store the operation result. In equations (15) and (18), z[n] is serialized into two sequences z e [n] and z o [n], respectively, requiring N/4 memory to store the operation result, z The operation data of e [n] is directly fed into the core for operation, and the sequence z o [n] needs to be pre-processed to simplify the z o [n] (1) sequence, as shown in equation (19). z o [n] (1) The sequence requires N/4 memory to store the result of the operation and feed it to the core for operation. The results of the two core outputs require N/4 memory to store the operation results to store the two sequences Z e [k] and Z o [k] (1) . Finally, after the post-processing, the final N/2 pen data is output. It can be known that, according to such evaluation results, the present invention can store data of all calculation processes by only requiring N memories at most.

按照這樣的評估方式，可以得知L.Li et al.和Lei et al.一樣只需要N個記憶體就可以儲存所有運算過程的資料。而逆改良型離散餘弦轉換(IMDCT)的推導過程，套用前述的評估方式可以得知L.Li et al.和和Lei et al.以及本發明技術的方法只需要N個記憶體就可以儲存所有運算過程的資料。 According to this evaluation method, it can be known that L. Li et al. and Lei et al. only need N memories to store data of all calculation processes. The derivation process of inverse modified discrete cosine transform (IMDCT) can be found by L.Li et al. and Lei et al. and the method of the present invention can store all of only N memory. Information on the calculation process.

綜上所述，本發明的方法主要有三大特點。 In summary, the method of the present invention has three main features.

1.低運算複雜度：根據表4.1~表4.4的統計數據來看，本發明的方法其前處理和核心的運算量和其他方法相比較起來是最少量的。 1. Low computational complexity: According to the statistical data of Tables 4.1 to 4.4, the method of the present invention has the least amount of pre-processing and core computation compared with other methods.

2.少量的乘法係數使用量：根據表4.5~表4.6的統計數據來看，本發明方法除了Lai et al.外，和其他方法相比較起來使用的乘法係數使用量是最少量的。 2. A small amount of multiplication factor usage: According to the statistical data of Tables 4.5 to 4.6, the method of the present invention uses the multiplicative coefficient used in comparison with other methods in addition to Lai et al.

3.高效能的資料計算：根據表4.7~表4.8的統計數據來看，本發明方法的DTPT為最多且運算週期為最短。 3. High-performance data calculation: According to the statistical data of Tables 4.7 to 4.8, the DTPT of the method of the present invention is the most and the calculation cycle is the shortest.

由上述可知，本發明無論就目的、手段及功效，在在均顯示其迥異於習知技術之特徵，極具實用價值。惟應注意的是，上述諸多實施例僅係為了便於說明而舉例而已，本發明所主張之權利範圍自應以申請專利範圍所述為準，而非僅限於上述實施例。 From the above, it can be seen that the present invention is extremely useful in terms of its purpose, means, and efficacy, both of which are different from those of the prior art. It should be noted that the various embodiments described above are merely illustrative for ease of explanation, and the scope of the invention is intended to be limited by the scope of the claims.

100‧‧‧遞迴式離散餘弦正、逆轉換之系統 100‧‧‧Return-type discrete cosine forward and reverse conversion systems

110‧‧‧第一運算單元 110‧‧‧First arithmetic unit

120‧‧‧第二運算單元 120‧‧‧Second arithmetic unit

130‧‧‧反離散餘弦第二型(IDCT-II)單元 130‧‧‧Inverse Discrete Cosine Type II (IDCT-II) Unit

140‧‧‧第三運算單元 140‧‧‧ third arithmetic unit

150‧‧‧第四運算單元 150‧‧‧ fourth arithmetic unit

310,311,312,320,321,322,323‧‧‧加法器 310,311,312,320,321,322,323‧‧‧Adder

313,314,315,324,325,326‧‧‧乘法器 313,314,315,324,325,326‧‧‧multiplier

316,317,327,328‧‧‧延遲裝置 316,317,327,328‧‧‧ delay device

500‧‧‧遞迴式離散餘弦正、逆轉換之系統 500‧‧‧Return-type discrete cosine forward and reverse conversion systems

510‧‧‧第一運算單元 510‧‧‧First arithmetic unit

520‧‧‧第二運算單元 520‧‧‧Second arithmetic unit

530‧‧‧第三運算單元 530‧‧‧ third arithmetic unit

540‧‧‧第四運算單元 540‧‧‧ fourth arithmetic unit

550‧‧‧第一反離散餘弦第二型(IDCT-II)單元 550‧‧‧First Inverse Discrete Cosine Type II (IDCT-II) Unit

560‧‧‧第二反離散餘弦第二型(IDCT-II)單元 560‧‧‧Second Inverse Discrete Cosine Type II (IDCT-II) unit

570‧‧‧第五運算單元 570‧‧‧ fifth arithmetic unit

580‧‧‧第六運算單元 580‧‧‧ sixth arithmetic unit

590‧‧‧第七運算單元 590‧‧‧ seventh arithmetic unit

510,511,512,520,521,522,523‧‧‧加法器 510, 511, 512, 520, 521, 522, 523 ‧ ‧ adders

513,514,515,524,525,526‧‧‧乘法器 513,514,515,524,525,526‧‧‧multiplier

516,517,527,528‧‧‧延遲裝置 516,517,527,528‧‧‧ delay device

518,529‧‧‧暫存器組 518, 529‧‧ ‧ register group

圖1係本發明之一遞迴式離散餘弦正、逆轉換之系統之一實施例之示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic illustration of one embodiment of a recursive discrete cosine forward and reverse conversion system of the present invention.

圖2係本發明N/4點改良型離散餘弦轉換(MDCT)的示意圖。 2 is a schematic diagram of an N/4 point modified discrete cosine transform (MDCT) of the present invention.

圖3係本發明離散正弦第二型(IDCT-II)核心架構之方塊圖。 3 is a block diagram of the discrete sinusoidal second type (IDCT-II) core architecture of the present invention.

圖4係本發明N/4點逆改良型離散餘弦轉換(IMDCT)的示意圖。 4 is a schematic diagram of an N/4-point inverse modified discrete cosine transform (IMDCT) of the present invention.

圖5係本發明之遞迴式離散餘弦正、逆轉換之系統之另一實施例之示意圖。 Figure 5 is a schematic illustration of another embodiment of a system for recursive discrete cosine forward and inverse conversion of the present invention.

圖6係本發明N/8點改良型離散餘弦轉換(MDCT)的示意圖。 Figure 6 is a schematic illustration of an N/8 point modified discrete cosine transform (MDCT) of the present invention.

圖7係本發明反離散餘弦第二型(IDCT-II)核心架構之方塊圖。 7 is a block diagram of the core architecture of the inverse discrete cosine second type (IDCT-II) of the present invention.

圖8係本發明N/8點逆改良型離散餘弦轉換(IMDCT)的示意圖。 Figure 8 is a schematic illustration of an N/8 point inverse modified discrete cosine transform (IMDCT) of the present invention.

100‧‧‧遞迴式離散餘弦正、逆轉換之系統 100‧‧‧Return-type discrete cosine forward and reverse conversion systems

110‧‧‧第一運算單元 110‧‧‧First arithmetic unit

120‧‧‧第二運算單元 120‧‧‧Second arithmetic unit

130‧‧‧反離散餘弦第二型單元 130‧‧‧Anti-discrete cosine second type unit

140‧‧‧第三運算單元 140‧‧‧ third arithmetic unit

150‧‧‧第四運算單元 150‧‧‧ fourth arithmetic unit

Claims (11)

一種遞迴式離散餘弦正、逆轉換之系統，其係以反離散餘弦第二型(IDCT-II)為核心，該系統包含：一第一運算單元，其接收N個輸入數位訊號，對該N個數位訊號執行運算，以產生N/2個第一暫時訊號，當中，N為4的倍數之正整數；一第二運算單元，連接至該第一運算單元，對該N/2個第一暫時訊號執行排列運算，以產生N/2個第二暫時訊號；一反離散餘弦第二型(IDCT-II)單元，連接至該第二運算單元，對該N/2個第二暫時訊號執行運算，以產生與該輸入數位訊號對應之N/2個第三暫時訊號；一第三運算單元，連接至該反離散餘弦第二型(IDCT-II)單元，對該N/2個第三暫時訊號執行排列運算，以產生N/2個第一輸出數位訊號；以及一第四運算單元，連接至該第三運算單元，對該N/2個第一輸出數位訊號執行排列運算，以產生N個第二輸出數位訊號；其中，當該系統的輸入為該N個輸入數位訊號時，該第三運算單元輸出之該N/2個第一輸出數位訊號係為與該N個輸入數位訊號對應之離散餘弦訊號，當該系統的輸入為該第一暫時訊號時，該第四運算單元輸出之該N個第二輸出數位訊號係為與該第一暫時訊號對應之反離散餘弦訊號。 A recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising: a first arithmetic unit that receives N input digital signals, The N digital signals perform an operation to generate N/2 first temporary signals, wherein N is a positive integer of a multiple of 4; a second arithmetic unit is connected to the first operational unit, and the N/2 A temporary signal performs an arrangement operation to generate N/2 second temporary signals; an inverse discrete cosine second type (IDCT-II) unit is connected to the second arithmetic unit, and the N/2 second temporary signals are Performing an operation to generate N/2 third temporary signals corresponding to the input digital signal; a third arithmetic unit connected to the inverse discrete cosine second type (IDCT-II) unit, the N/2 The third temporary signal performs an arrangement operation to generate N/2 first output digital signals; and a fourth arithmetic unit is coupled to the third operational unit to perform an arrangement operation on the N/2 first output digital signals to Generating N second output digital signals; wherein, when the input of the system is the N When the digital signal is input, the N/2 first output digital signals output by the third computing unit are discrete cosine signals corresponding to the N input digital signals. When the input of the system is the first temporary signal, The N second output digit signals output by the fourth computing unit are inverse discrete cosine signals corresponding to the first temporary signal. 如申請專利範圍第1項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第一運算單元、該N個輸入數位訊號、與N/2個第一暫時訊號係以下列公式描述： 當中，p[n]為該N/2個第一暫時訊號，x[n]為該N個輸入數位訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 1, wherein the first operation unit, the N input digit signals, and the N/2 first temporary signals are according to the following formula description: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals. 如申請專利範圍第2項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第二運算單元、該N/2個第一暫時訊號與該N/2個第二暫時訊號係以下列公式描述：p[n]=z[n]+z[n+1],for n=N/2-1 to 1，當中，z[n]為該N/2個第二暫時訊號，p[n]為該N/2個第一暫時訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 2, wherein the second computing unit, the N/2 first temporary signals, and the N/2 second temporary signal systems It is described by the following formula: p[n]=z[n]+z[n+1], for n=N/2-1 to 1, where z[n] is the N/2 second temporary signals, p[n] is the N/2 first temporary signals. 如申請專利範圍第3項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該反離散餘弦第二型(IDCT-II)單元、該N/2個第二暫時訊號及該N/2個第三暫時訊號係以下列公式表示： 當中，Z[k]為該N/2個第三暫時訊號，z[n]為該N/2個第二暫時訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 3, wherein the inverse discrete cosine second type (IDCT-II) unit, the N/2 second temporary signals, and the N The /2 third temporary signals are expressed by the following formula: Where Z[k] is the N/2 third temporary signals, and z[n] is the N/2 second temporary signals. 如申請專利範圍第4項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第三運算單元、該N/2個第 三暫時訊號及該N/2個第一輸出數位訊號係以下列公式表示： 當中，Z[k]為該N/2個第三暫時訊號，X[k]為該N/2個第一輸出數位訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 4, wherein the third operation unit, the N/2 third temporary signals, and the N/2 first output digital signals It is expressed by the following formula: Where Z[k] is the N/2 third temporary signals, and X[k] is the N/2 first output digital signals. 如申請專利範圍第5項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第四運算單元、該N/2個第一輸出數位訊號及該N個第二輸出數位訊號係以下列公式表示： 當中，x'[n]為該N個第二輸出數位訊號，X[k]為該N/2個第一輸出數位訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 5, wherein the fourth operation unit, the N/2 first output digital signals, and the N second output digital signals are Expressed by the following formula: Where x'[n] is the N second output digit signals, and X[k] is the N/2 first output digit signals. 一種遞迴式離散餘弦正、逆轉換之系統，其係以反離散餘弦第二型(IDCT-II)為核心，該系統包含：一第一運算單元，其接收N個輸入數位訊號，對該N個數位訊號執行運算，以產生N/2個第一暫時訊號，當中，N為8的倍數之正整數；一第二運算單元，連接至該第一運算單元，對該N/2個第一暫時訊號執行排列運算，以產生N/2個第二暫時訊號； 一第三運算單元，連接至該第二運算單元，對該N/2個第二暫時訊號執行運算，以產生N/4個第三暫時訊號及N/4個第四暫時訊號；一第四運算單元，連接至該第三運算單元，對該N/4個第四暫時訊號執行運算，以產生N/4個第五暫時訊號；一第一反離散餘弦第二型(IDCT-II)單元，連接至該第三運算單元，對該N/4個第三暫時訊號執行運算，以產生N/4個第六暫時訊號；一第二反離散餘弦第二型(IDCT-II)單元，連接至該第四運算單元，對該N/4個第五暫時訊號執行運算，以產生N/4個第七暫時訊號；一第五運算單元，連接至該第二反離散餘弦第二型(IDCT-II)單元，對該N/4個第七暫時訊號執行運算，以產生N/4個第八暫時訊號；一第六運算單元，連接至該第一反離散餘弦第二型(IDCT-II)單元及該第五運算單元，對該N/4個第六暫時訊號及該N/4個第八暫時訊號執行運算，以產生N/2個第一輸出訊號；以及一第七運算單元，連接至該第六運算單元，對該N/2個第一輸出訊號執行運算，以產生N個第二輸出訊號；其中，當該系統的輸入為該N個輸入數位訊號時，該第六運算單元輸出之該N/2個第一輸出訊號係為與該N個輸入數位訊號對應之離散餘弦訊號，當該系統的輸入為該第一暫時訊號時，該第七運算單元輸出之該N個第二輸 出數位訊號係為與該第一暫時訊號對應之反離散餘弦訊號。 A recursive discrete cosine forward and inverse conversion system, which is based on an inverse discrete cosine second type (IDCT-II), the system comprising: a first arithmetic unit that receives N input digital signals, Performing operations on the N digital signals to generate N/2 first temporary signals, where N is a positive integer of a multiple of 8; a second arithmetic unit is coupled to the first operational unit, to the N/2 Performing an arrangement operation on a temporary signal to generate N/2 second temporary signals; a third computing unit, connected to the second computing unit, performing operations on the N/2 second temporary signals to generate N/4 third temporary signals and N/4 fourth temporary signals; The operation unit is connected to the third operation unit, and performs an operation on the N/4 fourth temporary signals to generate N/4 fifth temporary signals; a first inverse discrete cosine second type (IDCT-II) unit And connecting to the third operation unit, performing an operation on the N/4 third temporary signals to generate N/4 sixth temporary signals; and a second inverse discrete cosine second type (IDCT-II) unit, connecting Up to the fourth computing unit, performing an operation on the N/4 fifth temporary signals to generate N/4 seventh temporary signals; and a fifth arithmetic unit connected to the second inverse discrete cosine second type (IDCT) -II) unit, performing an operation on the N/4 seventh temporary signals to generate N/4 eighth temporary signals; a sixth arithmetic unit connected to the first inverse discrete cosine second type (IDCT-II And the fifth arithmetic unit performs an operation on the N/4 sixth temporary signals and the N/4 eighth temporary signals to generate N/2 An output signal; and a seventh arithmetic unit connected to the sixth operational unit, performing operations on the N/2 first output signals to generate N second output signals; wherein, when the input of the system is the N When the digital signal is input, the N/2 first output signals output by the sixth computing unit are discrete cosine signals corresponding to the N input digital signals. When the input of the system is the first temporary signal, The N second inputs output by the seventh computing unit The digital signal is an inverse discrete cosine signal corresponding to the first temporary signal. 如申請專利範圍第7項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第一運算單元、該N個輸入數位訊號、與N/2個第一暫時訊號係以下列公式描述： 當中，p[n]為該N/2個第一暫時訊號，x[n]為該N個輸入數位訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 7 , wherein the first operation unit, the N input digit signals, and the N/2 first temporary signals are according to the following formula description: Where p[n] is the N/2 first temporary signals, and x[n] is the N input digital signals. 如申請專利範圍第8項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第二運算單元、該N/2個第一暫時訊號與該N/2個第二暫時訊號係以下列公式描述：p[n]=z[n]+z[n+1],for n=N/2-1 to 1，當中，z[n]為該N/2個第二暫時訊號，p[n]為該N/2個第一暫時訊號；該第三運算單元、該N/2個第二暫時訊號、該N/4個第三暫時訊號及該N/4個第四暫時訊號係以下列公式表示： 當中，z[n]為該N/2個第二暫時訊號，ze[n]為該N/4個第三暫時訊號，zo[n]為該N/4個第四暫時訊號；該第四運算單 元、該N/4個第四暫時訊號及該N/4個第五暫時訊號係以下列公式表示：zo[n]=zo[n](1)+zo[n+1](1)，當中，zo[n]為該N/4個第四暫時訊號，zo[n](1)為該N/4個第五暫時訊號。 The recursive discrete cosine forward and reverse conversion system of claim 8, wherein the second computing unit, the N/2 first temporary signals, and the N/2 second temporary signal systems It is described by the following formula: p[n]=z[n]+z[n+1], for n=N/2-1 to 1, where z[n] is the N/2 second temporary signals, p[n] is the N/2 first temporary signals; the third computing unit, the N/2 second temporary signals, the N/4 third temporary signals, and the N/4 fourth temporary signals It is expressed by the following formula: Where z[n] is the N/2 second temporary signals, z e [n] is the N/4 third temporary signals, and z o [n] is the N/4 fourth temporary signals; The fourth arithmetic unit, the N/4 fourth temporary signals, and the N/4 fifth temporary signals are represented by the following formula: z o [n]=z o [n] (1) +z o [n+ 1] (1) , where z o [n] is the N/4 fourth temporary signals, and z o [n] (1) is the N/4 fifth temporary signals. 如申請專利範圍第9項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第一反離散餘弦第二型(IDCT-II)單元、該N/4個第三暫時訊號及該N/4個第六暫時訊號係以下列公式表示： 當中，ze[n]為該N/4個第三暫時訊號，Ze[K]為該N/4個第六暫時訊號；該第二反離散餘弦第二型(IDCT-II)單元、該N/4個第五暫時訊號及該N/4個第七暫時訊號係以下列公式表示： 當中，Zo[K](1)為該N/4個第七暫時訊號，zo[n](1)為該N/4個第五暫時訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 9, wherein the first inverse discrete cosine second type (IDCT-II) unit, the N/4 third temporary signals and The N/4 sixth temporary signals are expressed by the following formula: Where z e [n] is the N/4 third temporary signals, Z e [K] is the N/4 sixth temporary signals; the second inverse discrete cosine second type (IDCT-II) unit, The N/4 fifth temporary signals and the N/4 seventh temporary signals are expressed by the following formula: Among them, Z o [K] (1) is the N/4 seventh temporary signals, and z o [n] (1) is the N/4 fifth temporary signals. 如申請專利範圍第10項所述之遞迴式離散餘弦正、逆轉換之系統，其中，該第五運算單元、該N/4個第七暫時訊號及該N/4個第八暫時訊號係以下列公式表示： 當中，Zo[K]為該N/4個第八暫時訊號，Zo[K](1)為該N/4個第七暫時訊號；該第六運算單元、該N/4個第六暫時訊號、該N/4個第八暫時訊號及該N/2個第一輸出訊號係以下列公式表示： 當中，X[K]為該N/2個第一輸出訊號，Z[K]為該N/4個第六暫時訊號及該N/4個第八暫時訊號的組合；該第七運算單元、該N/2個第一輸出訊號及該N個第二輸出訊號係以下列公式表示： 當中，x’[n]為該N個第二輸出數位訊號，X[k]為該N/2個第一輸出數位訊號。 The system of recursive discrete cosine forward and reverse conversion according to claim 10, wherein the fifth arithmetic unit, the N/4 seventh temporary signals, and the N/4 eighth temporary signal system Expressed by the following formula: Where Z o [K] is the N/4 eighth temporary signals, Z o [K] (1) is the N/4 seventh temporary signals; the sixth arithmetic unit, the N/4 sixth The temporary signal, the N/4 eighth temporary signals, and the N/2 first output signals are expressed by the following formula: Wherein, X[K] is the N/2 first output signals, and Z[K] is a combination of the N/4 sixth temporary signals and the N/4 eighth temporary signals; the seventh arithmetic unit, The N/2 first output signals and the N second output signals are represented by the following formula: Where x'[n] is the N second output digit signals, and X[k] is the N/2 first output digit signals.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5907822A (en) * 1997-04-04 1999-05-25 Lincom Corporation Loss tolerant speech decoder for telecommunications
US6360200B1 (en) * 1995-07-20 2002-03-19 Robert Bosch Gmbh Process for reducing redundancy during the coding of multichannel signals and device for decoding redundancy-reduced multichannel signals
US6496795B1 (en) * 1999-05-05 2002-12-17 Microsoft Corporation Modulated complex lapped transform for integrated signal enhancement and coding
US20040078194A1 (en) * 1997-06-10 2004-04-22 Coding Technologies Sweden Ab Source coding enhancement using spectral-band replication

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6360200B1 (en) * 1995-07-20 2002-03-19 Robert Bosch Gmbh Process for reducing redundancy during the coding of multichannel signals and device for decoding redundancy-reduced multichannel signals
US5907822A (en) * 1997-04-04 1999-05-25 Lincom Corporation Loss tolerant speech decoder for telecommunications
US20040078194A1 (en) * 1997-06-10 2004-04-22 Coding Technologies Sweden Ab Source coding enhancement using spectral-band replication
US6496795B1 (en) * 1999-05-05 2002-12-17 Microsoft Corporation Modulated complex lapped transform for integrated signal enhancement and coding

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Sheau-Fang Lei, Shin-Chi Lai, Po-Yin Cheng, and Ching-Hsing Luo, " Low Complexity and Fast Computation for Recursive MDCT and IMDCT Algorithms," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL. 57, NO. 7, JULY 2010 *
Shin-Chi Lai, Sheau-Fang Lei, and Ching-Hsing Luo, " Common Architecture Design of Novel Recursive MDCT and IMDCT Algorithms for Application to AAC, AAC in DRM, and MP3 Codecs," IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 56, NO. 10, OCTOBER 2009 *

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