TWI408642B - Display, pixel circuitry and operating method of pixel circuitry - Google Patents
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本發明是有關於一種顯示技術，且特別是有關於一種顯示裝置、像素電路及像素電路的操作方法。 The present invention relates to a display technology, and more particularly to a display device, a pixel circuit, and a method of operating a pixel circuit.
平面顯示器，如：液晶顯示器(Liquid Crystal Display，LCD)、矽基液晶(Liquiid Crystal On Silicon，LCOS)顯示器等，其具有高畫質、體積小、重量輕、低驅動電壓、與低消耗功率等優點，因此廣泛使用於攝錄放影機、個人數位助理(Personal Digital Assistant，PDA)、行動電話、筆記型電腦、桌上型電腦顯示螢幕及薄型數位電視等消費性通訊或電子產品中，並逐漸取代陰極射線管(Cathode Ray Tube，CRT)而成為顯示器的主流技術。 Flat panel displays, such as liquid crystal displays (LCDs), liquid crystal on silicon (LCOS) displays, etc., which have high image quality, small size, light weight, low driving voltage, low power consumption, etc. Advantages, so it is widely used in consumer communication or electronic products such as video recorders, personal digital assistants (PDAs), mobile phones, notebook computers, desktop computer display screens and thin digital TVs. Gradually replace the cathode ray tube (CRT) and become the mainstream technology of the display.
一般而言，在矽基液晶顯示器以60 Hz的顯示頻率顯示畫面時，畫面會有閃爍的現象發生。為了降低畫面的閃爍現象，則會提高畫面的顯示頻率為120 Hz，以較高的顯示頻率抑制畫面的閃爍。其中，提高顯示頻率的方式可以為在二個畫面期間重複傳送相同畫面資料給源極驅動器，而源極驅動器則分別在此二個畫面期間以不同極性將相同畫面資料傳送給顯示面板。 In general, when a 矽-based liquid crystal display displays a picture at a display frequency of 60 Hz, a flickering phenomenon occurs. In order to reduce the flickering of the screen, the display frequency of the screen is increased to 120 Hz, and the flicker of the screen is suppressed with a higher display frequency. The method of increasing the display frequency may be to repeatedly transmit the same picture data to the source driver during the two picture periods, and the source driver respectively transmits the same picture data to the display panel with different polarities during the two pictures.
圖1A繪示為一傳統顯示器的系統方塊圖。請參照圖1，顯示裝置100包括時序控制器(timing controller,T-con)110、源極驅動器(source driver)120、閘極驅動器(gate driver)130及顯示面板(display panel)140。時序控制器110會輸出資料信號DD至源極驅動器120，而源極驅動器120會對應的輸出資料電壓至顯示面板140，其中資料電壓可以為正極性或負極性。此時，閘極驅動器130會受控於時序控制器110開啟顯示面板140的像素電路PX以接收資料電壓。接著，驅動顯示面板140的像素電路PX依據所儲存的資料電壓進行顯示。 1A is a block diagram of a system of a conventional display. Referring to FIG. 1, the display device 100 includes a timing controller (T-con) 110, a source driver 120, and a gate driver (gate). Driver) 130 and a display panel 140. The timing controller 110 outputs the data signal DD to the source driver 120, and the source driver 120 outputs a corresponding output voltage to the display panel 140, wherein the data voltage can be positive or negative. At this time, the gate driver 130 is controlled by the timing controller 110 to turn on the pixel circuit PX of the display panel 140 to receive the data voltage. Next, the pixel circuit PX that drives the display panel 140 is displayed in accordance with the stored data voltage.
圖1B繪示為圖1A的資料信號DD及像素電路PX的驅動時序圖。在畫面期間fp1的資料寫入期間dw1，資料信號DD會傳送畫面資料F1，其中畫面資料F1會包含第一像素資料D1。此時，源極驅動器120會對應第一像素資料D1輸出正極性資料電壓D1+至顯示面板140的像素電路PX。在畫面期間fp1的垂直空白期間vb1及畫面期間fp2的資料寫入期間dw2中，像素電路PX會受控制閘極驅動器130而依據正極性資料電壓D1+進行顯示。 FIG. 1B is a timing chart showing driving of the data signal DD and the pixel circuit PX of FIG. 1A. During the data writing period dw1 of the fp1 during the picture period, the data signal DD transmits the picture material F1, wherein the picture material F1 contains the first pixel data D1. At this time, the source driver 120 outputs the positive polarity data voltage D1+ to the pixel circuit PX of the display panel 140 corresponding to the first pixel data D1. In the data blanking period vb1 of the screen period fp1 and the data writing period dw2 of the screen period fp2, the pixel circuit PX is displayed by the gate driver 130 in accordance with the positive polarity data voltage D1+.
在畫面期間fp2的資料寫入期間dw2中，資料信號DD同樣會傳送畫面資料F1，而此時源極驅動器120會對應第一像素資料D1輸出負極性資料電壓D1-至顯示面板140的像素電路PX。在畫面期間fp2的垂直空白期間vb2及畫面期間fp3的資料寫入期間dw3中，像素電路PX會受控制閘極驅動器130而依據負極性資料電壓D1-進行顯示。 During the data writing period dw2 of the fp2 during the picture period, the data signal DD also transmits the picture data F1, and at this time, the source driver 120 outputs the negative polarity data voltage D1 to the pixel circuit of the display panel 140 corresponding to the first pixel data D1. PX. In the vertical blanking period vb2 of the screen period fp2 and the data writing period dw3 of the screen period fp3, the pixel circuit PX is subjected to display by the gate driver 130 in accordance with the negative polarity data voltage D1-.
依據上述，源極驅動器120會接收兩次畫面資料F1，以於不同畫面期間(如畫面期間fp1及fp2)分別輸出正極性資料電壓(如D1+)及負極性資料電壓(如D1-)。同 樣地，若顯示裝置100欲顯示包含第二像素資料D2的畫面資料F2時，則資料信號DD會傳送二次畫面資料F2至源極驅動器120，以分別產生正極性資料電壓(如D2+)及負極性資料電壓(如D2-)。並且，像素電路PX同樣會受控制閘極驅動器130而於不同期間依據正極性資料電壓(如D2+)及負極性資料電壓(如D2-)進行顯示。 According to the above, the source driver 120 receives the screen data F1 twice to output a positive polarity data voltage (such as D1+) and a negative polarity data voltage (such as D1-) during different picture periods (such as the picture periods fp1 and fp2). with For example, if the display device 100 is to display the screen data F2 including the second pixel data D2, the data signal DD transmits the secondary image data F2 to the source driver 120 to generate a positive polarity data voltage (such as D2+) and Negative data voltage (such as D2-). Moreover, the pixel circuit PX is also controlled by the gate driver 130 and is displayed according to a positive polarity data voltage (such as D2+) and a negative polarity data voltage (such as D2-) during different periods.
由於顯示器100的像素電路PX在一畫面期間只能儲存一資料電壓，因此對應同一像素資料的正極性資料電壓及負極性資料電壓則會分別在相鄰的兩個畫面期間傳送至像素電路PX。因此，在顯示器100提高畫面的顯示頻率的同時，連帶的會提高源極驅動器120的資料傳輸速率，進而使源極驅動器120的功率消耗對應的增加。並且，在資料傳輸速率過高時，源極驅動器120所接收的資料信號DD可能會有失真的情況產生。此時，則可增加源極驅動器120接收資料信號DD的接腳，以降低資料傳輸速率。但是，增加源極驅動器120接收資料信號DD的接腳不但會增加硬體配置的成本，並且源極驅動器120的電路亦須對應的修改，進而增加電路設計的成本。 Since the pixel circuit PX of the display 100 can only store one data voltage during one screen period, the positive polarity data voltage and the negative polarity data voltage corresponding to the same pixel data are respectively transmitted to the pixel circuit PX during the adjacent two picture periods. Therefore, while the display 100 increases the display frequency of the screen, the associated data transmission rate of the source driver 120 is increased, and the power consumption of the source driver 120 is correspondingly increased. Moreover, when the data transmission rate is too high, the data signal DD received by the source driver 120 may be distorted. At this time, the pin of the source driver 120 receiving the data signal DD can be increased to reduce the data transmission rate. However, increasing the pin of the source driver 120 receiving the data signal DD not only increases the cost of the hardware configuration, but also the circuit of the source driver 120 must be modified accordingly, thereby increasing the cost of the circuit design.
本發明提供一種顯示裝置、像素電路及其操作方法，其源極驅動器可依據一像素資料產生對應的第一極性資料電壓及第二極性資料電壓，像素電路可於同一時間接收並儲存第一極性資料電壓及第二極性資料電壓。 The invention provides a display device, a pixel circuit and a method for operating the same, wherein the source driver can generate a corresponding first polarity data voltage and a second polarity data voltage according to a pixel data, and the pixel circuit can receive and store the first polarity at the same time. Data voltage and second polarity data voltage.
本發明提出一種顯示裝置，其包括源極驅動器及像素電路。源極驅動器於第一畫面期間將第一像素資料轉換為第一極性資料電壓及第二極性資料電壓，以及於第二畫面期間將第二像素資料轉換為第三極性資料電壓及第四極性資料電壓。像素電路耦接源極驅動器。像素電路於第一畫面期間儲存第一極性資料電壓及第二極性資料電壓，於第二畫面期間的第一子期間與第二子期間分別顯示第一極性資料電壓及第二極性資料電壓，以及於第二畫面期間儲存第三極性資料電壓及第四極性資料電壓。 The invention provides a display device comprising a source driver and a pixel circuit. The source driver converts the first pixel data into the first polarity data voltage and the second polarity data voltage during the first picture, and converts the second pixel data into the third polarity data voltage and the fourth polarity during the second picture Data voltage. The pixel circuit is coupled to the source driver. The pixel circuit stores the first polarity data voltage and the second polarity data voltage during the first picture period, and displays the first polarity data voltage and the second polarity data voltage in the first sub-period and the second sub-period during the second picture period, respectively, and The third polarity data voltage and the fourth polarity data voltage are stored during the second picture period.
本發明另提出一種顯示裝置的像素電路，包括顯示單元及儲存單元。儲存單元包括第一寫入開關、第二寫入開關、第三寫入開關、第一記憶單元、第二記憶單元、第三記憶單元及切換單元。第一寫入開關的第一端連接至源極驅動器。第一記憶單元耦接第一寫入開關的第二端。第二寫入開關的第一端連接至源極驅動器。第二記憶單元耦接第二寫入開關的第二端。第三寫入開關的第一端連接至源極驅動器。第三記憶單元耦接第三寫入開關的第二端。切換單元的第一輸入端耦接第一記憶單元，切換單元的第二輸入端耦接第二記憶單元，切換單元的第三輸入端耦接第三記憶單元，以及切換單元的輸出端耦接至顯示單元。 The invention further provides a pixel circuit of a display device, comprising a display unit and a storage unit. The storage unit includes a first write switch, a second write switch, a third write switch, a first memory unit, a second memory unit, a third memory unit, and a switching unit. A first end of the first write switch is coupled to the source driver. The first memory unit is coupled to the second end of the first write switch. A first end of the second write switch is coupled to the source driver. The second memory unit is coupled to the second end of the second write switch. A first end of the third write switch is coupled to the source driver. The third memory unit is coupled to the second end of the third write switch. The first input end of the switching unit is coupled to the first memory unit, the second input end of the switching unit is coupled to the second memory unit, the third input end of the switching unit is coupled to the third memory unit, and the output end of the switching unit is coupled To the display unit.
本發明亦提出一種像素電路的操作方法，此操作方法包括下列步驟：於第一畫面期間，儲存第一像素資料的第一極性資料電壓及第二極性資料電壓；於第二畫面期間的第一子期間與第二子期間，分別將第一極性資料電壓及第 二極性資料電壓輸出給顯示單元；於第二畫面期間，儲存第二像素資料的第三極性資料電壓及第四極性資料電壓。 The present invention also provides a method for operating a pixel circuit. The method includes the steps of: storing a first polarity data voltage and a second polarity data voltage of the first pixel data during the first picture; During the sub-period and the second sub-period, the first polarity data voltage and the first The bipolar data voltage is output to the display unit; during the second picture, the third polarity data voltage and the fourth polarity data voltage of the second pixel data are stored.
基於上述，本發明實施例的顯示裝置、像素電路及其操作方法，其於像素電路可於一畫面期間中同時儲存兩筆對應同一像素資料且不同極性的資料電壓，並且依序輸出先前所儲存的兩筆不同極性的資料電壓。藉此，可降低源極驅動器的資料傳輸速率。 Based on the above, the display device, the pixel circuit, and the method for operating the same according to the embodiments of the present invention can simultaneously store two data voltages of different polarities corresponding to the same pixel data in a pixel period, and sequentially output the previously stored data. Two different polar data voltages. Thereby, the data transfer rate of the source driver can be reduced.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。 The above described features and advantages of the present invention will be more apparent from the following description.
現將詳細參考本發明之示範性實施例，在附圖中說明所述示範性實施例之實例。另外，凡可能之處，在圖式及實施方式中使用相同標號的元件/構件代表相同或類似部分。 DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings
圖2繪示為依據本發明一實施例之顯示裝置的系統方塊圖。請參照圖2，顯示裝置200包括時序控制器(timing controller,T-con)210、源極驅動器(source driver)220、閘極驅動器(gate driver)230及顯示面板(display panel)240。閘極驅動器230受控於時序控制器210，並且輸出第一掃描信號SC1或第二掃描信號SC2，以驅動顯示面板240內的像素電路Pix。其中，第一掃描信號SC1及第二掃描信號SC2於不同畫面期間中輸出，並且第一掃描信號SC1 及第二掃描信號SC2的數量取決於顯示面板240內像素電路Pix陣列的列數。 2 is a block diagram of a system of a display device in accordance with an embodiment of the present invention. Referring to FIG. 2 , the display device 200 includes a timing controller (T-con) 210 , a source driver 220 , a gate driver 230 , and a display panel 240 . The gate driver 230 is controlled by the timing controller 210 and outputs a first scan signal SC1 or a second scan signal SC2 to drive the pixel circuit Pix within the display panel 240. The first scan signal SC1 and the second scan signal SC2 are output during different picture periods, and the first scan signal SC1 The number of second scan signals SC2 depends on the number of columns of the pixel circuit Pix array in the display panel 240.
源極驅動器220接收時序控制器210所提供的資料信號DD，於一畫面期間提供對應的正極性資料信號DV+及負極性資料信號DV-給顯示面板240內被閘極驅動器230驅動的像素電路Pix，其中正極性資料信號DV+及負極性資料信號DV-可對應同一畫面，並且正極性資料信號DV+及負極性資料信號DV-的數量取決於顯示面板240內像素電路Pix陣列的行數。 The source driver 220 receives the data signal DD provided by the timing controller 210, and provides a corresponding positive polarity data signal DV+ and negative polarity data signal DV- during a picture period to the pixel circuit Pix driven by the gate driver 230 in the display panel 240. The positive polarity data signal DV+ and the negative polarity data signal DV- may correspond to the same picture, and the number of the positive polarity data signal DV+ and the negative polarity data signal DV- depends on the number of rows of the pixel circuit Pix array in the display panel 240.
當源極驅動器220供應對應的正極性資料信號DV+及負極性資料信號DV-給液晶顯示面板140內的所有像素電路之後，閘極驅動器230會輸出第一顯示信號SP1、第二顯示信號SP2、第三顯示信號SP3或第四顯示信號SP4，以驅動像素電路Pix進行畫面的顯示，其中第一顯示信號SP1、第二顯示信號SP2、第三顯示信號SP3或第四顯示信號SP4於時序上呈現不重疊。 After the source driver 220 supplies the corresponding positive polarity data signal DV+ and the negative polarity data signal DV- to all the pixel circuits in the liquid crystal display panel 140, the gate driver 230 outputs the first display signal SP1 and the second display signal SP2. The third display signal SP3 or the fourth display signal SP4 is used to drive the pixel circuit Pix to display the screen, wherein the first display signal SP1, the second display signal SP2, the third display signal SP3 or the fourth display signal SP4 are presented in time series Do not overlap.
此外，若像素電路Pix中的顯示元件為不發光元件，則顯示裝置200可更包括背光模組(backlight module)250以提供顯示面板440所需的面光源，藉以致使液晶顯示面板240顯示影像畫面給使用者觀看。 In addition, if the display element in the pixel circuit Pix is a non-light-emitting element, the display device 200 may further include a backlight module 250 to provide a surface light source required by the display panel 440, thereby causing the liquid crystal display panel 240 to display an image frame. Show it to the user.
圖3A繪示為圖2依據本發明第一實施例的像素電路Pix的電路示意圖。請參照圖3A，像素電路Pix包括儲存單元310及顯示單元320。儲存單元310包括第一寫入開關WSW1、第二寫入開關WSW2、第三寫入開關WSW3、 第四寫入開關WSW4、第一記憶單元311、第二記憶單元313、第三記憶單元315、第四記憶單元317及切換單元319。 FIG. 3A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the first embodiment of the present invention. Referring to FIG. 3A, the pixel circuit Pix includes a storage unit 310 and a display unit 320. The storage unit 310 includes a first write switch WSW1, a second write switch WSW2, a third write switch WSW3, The fourth write switch WSW4, the first memory unit 311, the second memory unit 313, the third memory unit 315, the fourth memory unit 317, and the switching unit 319.
請參照圖2及圖3A，第一寫入開關WSW1的第一端耦接源極驅動器220以接收正極性資料信號DV+所傳送的正極性資料電壓，並且第一寫入開關WSW1受控於第一掃描信號SC1。第一記憶單元311的第一端耦接第一寫入開關WSW1的第二端，而第一記憶單元311的第二端則接收第一參考電壓VR1。其中，第一記憶單元311經由第一寫入開關WSW1而儲存此正極性資料電壓。切換單元319的第一輸入端319a耦接第一記憶單元311。切換單元319依據第一顯示信號SP1於其輸出端319e輸出第一記憶單元311所儲存的正極性資料電壓。 Referring to FIG. 2 and FIG. 3A, the first end of the first write switch WSW1 is coupled to the source driver 220 to receive the positive polarity data voltage transmitted by the positive polarity data signal DV+, and the first write switch WSW1 is controlled by the first A scan signal SC1. The first end of the first memory unit 311 is coupled to the second end of the first write switch WSW1, and the second end of the first memory unit 311 receives the first reference voltage VR1. The first memory unit 311 stores the positive polarity data voltage via the first write switch WSW1. The first input end 319a of the switching unit 319 is coupled to the first memory unit 311. The switching unit 319 outputs the positive polarity data voltage stored by the first memory unit 311 at its output terminal 319e according to the first display signal SP1.
第二寫入開關WSW2的第一端耦接源極驅動器220以接收負極性資料信號DV-所傳送的負極性資料電壓，並且第二寫入開關WSW2受控於第一掃描信號SC1。第二記憶單元313的第一端耦接第二寫入開關WSW2的第二端，而第二記憶單元313的第二端則接收第一參考電壓VR1。其中，第二記憶單元313經由第二寫入開關WSW2而儲存此負極性資料電壓。切換單元319的第二輸入端319b耦接第二記憶單元313。切換單元319依據第二顯示信號SP2於其輸出端319e輸出第二記憶單元313所儲存的負極性資料電壓。 The first end of the second write switch WSW2 is coupled to the source driver 220 to receive the negative polarity data voltage transmitted by the negative polarity data signal DV-, and the second write switch WSW2 is controlled by the first scan signal SC1. The first end of the second memory unit 313 is coupled to the second end of the second write switch WSW2, and the second end of the second memory unit 313 receives the first reference voltage VR1. The second memory unit 313 stores the negative polarity data voltage via the second write switch WSW2. The second input end 319b of the switching unit 319 is coupled to the second memory unit 313. The switching unit 319 outputs the negative polarity data voltage stored by the second memory unit 313 at its output end 319e according to the second display signal SP2.
第三寫入開關WSW3的第一端耦接源極驅動器220以接收正極性資料電壓DV+所傳送的正極性資料電壓，並 且第三寫入開關WSW3受控於第二掃描信號SC2。第三記憶單元315的第一端耦接第三寫入開關WSW3的第二端，而第三記憶單元315的第二端則接收第一參考電壓VR1。其中，第三記憶單元315經由第三寫入開關WSW3而儲存此正極性資料電壓。切換單元319的第三輸入端319c耦接第三記憶單元315。切換單元319依據第三顯示信號SP3於其輸出端319e輸出第三記憶單元315所儲存的正極性資料電壓。 The first end of the third write switch WSW3 is coupled to the source driver 220 to receive the positive polarity data voltage transmitted by the positive polarity data voltage DV+, and And the third write switch WSW3 is controlled by the second scan signal SC2. The first end of the third memory unit 315 is coupled to the second end of the third write switch WSW3, and the second end of the third memory unit 315 receives the first reference voltage VR1. The third memory unit 315 stores the positive polarity data voltage via the third write switch WSW3. The third input end 319c of the switching unit 319 is coupled to the third memory unit 315. The switching unit 319 outputs the positive polarity data voltage stored by the third memory unit 315 at its output terminal 319e according to the third display signal SP3.
第四寫入開關WSW4的第一端耦接源極驅動器220以接收負極性資料電壓DV-所傳送的負極性資料電壓，並且第四寫入開關WSW4受控於第二掃描信號SC2。第四記憶單元317的第一端耦接第四寫入開關WSW4的第二端，而第四記憶單元317的第二端則接收第一參考電壓VR1。其中，第四記憶單元317經由第四寫入開關WSW3而儲存此負極性資料電壓。切換單元319的第四輸入端319d耦接第四記憶單元317。切換單元319依據第四顯示信號SP4於其輸出端319e輸出第四記憶單元317所儲存的負極性資料電壓。 The first end of the fourth write switch WSW4 is coupled to the source driver 220 to receive the negative polarity data voltage transmitted by the negative polarity data voltage DV-, and the fourth write switch WSW4 is controlled by the second scan signal SC2. The first end of the fourth memory unit 317 is coupled to the second end of the fourth write switch WSW4, and the second end of the fourth memory unit 317 receives the first reference voltage VR1. The fourth memory unit 317 stores the negative polarity data voltage via the fourth write switch WSW3. The fourth input end 319d of the switching unit 319 is coupled to the fourth memory unit 317. The switching unit 319 outputs the negative polarity data voltage stored by the fourth memory unit 317 at its output terminal 319e according to the fourth display signal SP4.
切換單元319包括第一顯示開關DSW1、第二顯示開關DSW2、第三顯示開關DSW3及第四顯示開關DSW4。第一顯示開關DSW1的第一端作為切換單元319的第一輸入端319a，第一顯示開關DSW1的第二端耦接切換單元319的輸出端319e，第一顯示開關DSW1受控於第一顯示信號SP1。第二顯示開關DSW2的第一端作為切換單元319 的第二輸入端319b，第二顯示開關DSW2的第二端耦接切換單元319的輸出端319e，第二顯示開關DSW2受控於第二顯示信號SP2。 The switching unit 319 includes a first display switch DSW1, a second display switch DSW2, a third display switch DSW3, and a fourth display switch DSW4. The first display switch DSW1 is coupled to the first input end 319a of the switching unit 319, the second end of the first display switch DSW1 is coupled to the output end 319e of the switching unit 319, and the first display switch DSW1 is controlled by the first display. Signal SP1. The first end of the second display switch DSW2 serves as the switching unit 319 The second input end 319b, the second end of the second display switch DSW2 is coupled to the output end 319e of the switching unit 319, and the second display switch DSW2 is controlled by the second display signal SP2.
第三顯示開關DSW3的第一端作為切換單元319的第三輸入端319c，第三顯示開關DSW3的第二端耦接切換單元319的輸出端319e，第三顯示開關DSW3受控於第三顯示信號SP3。第四顯示開關DSW4的第一端作為切換單元319的第四輸入端319d，第四顯示開關DSW4的第二端耦接切換單元319的輸出端319e，第四顯示開關受控於第四顯示信號SP4。 The first end of the third display switch DSW3 is the third input end 319c of the switching unit 319, the second end of the third display switch DSW3 is coupled to the output end 319e of the switching unit 319, and the third display switch DSW3 is controlled by the third display. Signal SP3. The first display of the fourth display switch DSW4 is the fourth input end 319d of the switching unit 319, the second end of the fourth display switch DSW4 is coupled to the output end 319e of the switching unit 319, and the fourth display switch is controlled by the fourth display signal. SP4.
顯示單元320包括顯示元件DP。顯示元件DP的一端耦接切換單元319的輸出端319e，以經由切換單元319接收第一記憶單元311所儲存的正極性資料電壓、第二記憶單元313所儲存的負極性資料電壓、第三記憶單元315所儲存的正極性資料電壓或第四記憶單元317所儲存負極性資料電壓。 The display unit 320 includes a display element DP. One end of the display element DP is coupled to the output end 319e of the switching unit 319 to receive the positive polarity data voltage stored by the first memory unit 311, the negative polarity data voltage stored by the second memory unit 313, and the third memory via the switching unit 319. The positive polarity data voltage stored by the unit 315 or the negative polarity data voltage stored by the fourth memory unit 317.
此外，顯示單元320可更包括顯示記憶單元321，其第一端耦接切換單元319的輸出端319e，而顯示記憶單元321的第二端則接收第二參考電壓VR2。在本實施例中，顯示元件DP例如是液晶電容DP。此液晶電容DP藉由像素電壓Vlc與共同電壓Vcom的電位差來驅動與變更液晶電容DP中的液晶角度。 In addition, the display unit 320 may further include a display memory unit 321, the first end of which is coupled to the output end 319e of the switching unit 319, and the second end of the display memory unit 321 receives the second reference voltage VR2. In the present embodiment, the display element DP is, for example, a liquid crystal capacitor DP. The liquid crystal capacitor DP drives and changes the liquid crystal angle in the liquid crystal capacitor DP by the potential difference between the pixel voltage Vlc and the common voltage Vcom.
圖3B繪示為依據本發明一實施例的顯示裝置200的驅動時序圖。請參照圖2、圖3A與圖3B，在本實施例中， 每一畫面期間(如FP1、FP2或FP3)包括資料寫入期間(如DW1、DW2或DW3)及垂直空白(vertical blanking)期間(如VB1、VB2或VB3)。在畫面期間FP1中，資料信號DD會傳送包含第一像素資料D1的畫面資料F1。源極驅動器220接收到第一像素資料D1時，會將第一像素資料D1轉換為正極性資料電壓D1+及負極性資料電壓D1-。此時，正極性資料信號DV+會傳送正極性資料電壓D1+，負極性資料信號DV-會傳送負極性資料電壓D1-。 FIG. 3B is a timing chart of driving of the display device 200 according to an embodiment of the invention. Please refer to FIG. 2, FIG. 3A and FIG. 3B. In this embodiment, Each picture period (such as FP1, FP2 or FP3) includes a data writing period (such as DW1, DW2 or DW3) and a vertical blanking period (such as VB1, VB2 or VB3). In the picture period FP1, the material signal DD transmits the picture material F1 containing the first pixel data D1. When receiving the first pixel data D1, the source driver 220 converts the first pixel data D1 into a positive polarity data voltage D1+ and a negative polarity data voltage D1-. At this time, the positive polarity data signal DV+ transmits the positive polarity data voltage D1+, and the negative polarity data signal DV- transmits the negative polarity data voltage D1-.
在畫面期間FP1中，第一掃描信號SC1會於資料寫入期間DW1中切換至高準位，第二掃描信號SC2會處於低準位。實際來說，第一掃描信號SC1處於高準位的時間會反比於第一掃描信號SC1的數量，並且第一掃描信號SC1處於高準位的時間互不重疊。並且，由於第二掃描信號SC2會處於低準位，因此第三寫入開關WSW3及第四寫入開關WSW4會處於截止狀態。當第一掃描信號SC1處於高準位時，第一寫入開關WSW1及第二寫入開關WSW2處於導通狀態。 In the picture period FP1, the first scan signal SC1 is switched to the high level in the data writing period DW1, and the second scanning signal SC2 is at the low level. Actually, the time at which the first scan signal SC1 is at the high level is inversely proportional to the number of the first scan signals SC1, and the times at which the first scan signal SC1 is at the high level do not overlap each other. Moreover, since the second scan signal SC2 is at a low level, the third write switch WSW3 and the fourth write switch WSW4 are in an off state. When the first scan signal SC1 is at the high level, the first write switch WSW1 and the second write switch WSW2 are in an on state.
假設第一掃描信號SC1處於高準位時，正極性資料信號DV+及負極性資料信號DV-為分別傳送正極性資料電壓D1+及負極性資料電壓D1-，則第一記憶單元311內的第一電容CS1經由第一寫入開關WSW1接收到正極性資料電壓D1+，因此第一電容CS1便於此時儲存電荷，以使第一電容CS1的跨壓約為正極性資料電壓D1+。並且，第二記憶單元313內的第二電容CS2經由第二寫入開關WSW2 接收到負極性資料電壓D1-，因此第二電容CS2便於此時儲存電荷，以使第二電容CS2的跨壓約為負極性資料電壓D1-。藉此，像素電路Pix可於一個畫面期間同時儲存正極性資料電壓D1+及負極性資料電壓D1-，以降低源極驅動器120的資料傳輸速率。 Assuming that the first scan signal SC1 is at a high level, the positive polarity data signal DV+ and the negative polarity data signal DV- are respectively transmitting the positive polarity data voltage D1+ and the negative polarity data voltage D1-, and then the first in the first memory unit 311 The capacitor CS1 receives the positive polarity data voltage D1+ via the first write switch WSW1, so the first capacitor CS1 facilitates storing the charge at this time such that the voltage across the first capacitor CS1 is approximately the positive data voltage D1+. And, the second capacitor CS2 in the second memory unit 313 is via the second write switch WSW2. The negative polarity data voltage D1- is received, so the second capacitor CS2 facilitates storing the charge at this time such that the voltage across the second capacitor CS2 is approximately the negative data voltage D1-. Thereby, the pixel circuit Pix can simultaneously store the positive polarity data voltage D1+ and the negative polarity data voltage D1- during one screen to reduce the data transmission rate of the source driver 120.
此外，在畫面期間FP1中，第一顯示信號SP1及第二顯示信號SP2會處於低準位，因此切換元319中的第一顯示開關DSW1及第二顯示開關DSW2會處於截止狀態。並且，在畫面期間FP1的前半期間FA1中，第三顯示信號SP3會於期間FA1中處於高準位，以使第三記憶單元315內的第三電容CS3所儲存的電壓會透過第三顯示開關DSW3傳送至液晶電容DP及顯示記憶單元231的第五電容CS5。此時，驅動液晶電容DP所需的電位差將由第三電容CS3、第五電容CS5以及液晶電容DP本身來繼續提供。 In addition, in the picture period FP1, the first display signal SP1 and the second display signal SP2 are at a low level, so the first display switch DSW1 and the second display switch DSW2 in the switching element 319 are in an off state. Moreover, in the first half period FA1 of the picture period FP1, the third display signal SP3 is at a high level during the period FA1, so that the voltage stored in the third capacitor CS3 in the third memory unit 315 passes through the third display switch. The DSW 3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 of the display memory unit 231. At this time, the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the third capacitor CS3, the fifth capacitor CS5, and the liquid crystal capacitor DP itself.
在畫面期間FP1的後半期間FB1中，第四顯示信號SP4會於期間FB1中處於高準位，使得第四記憶單元317內的第四電容CS4所儲存的電壓會透過第四顯示開關DSW4傳送至液晶電容DP及顯示記憶單元231的第五電容CS5。此時，驅動液晶電容DP所需的電位差將由第四電容CS4、第五電容CS5以及液晶電容DP本身來繼續提供。在本實施例中，第三電容CS3及第四電容CS4於畫面期間FP1中所儲存的電壓非顯示用的資料電壓，因此第三顯示開關DSW3及第四顯示開關DSW4的導通的影響在此 則忽略不作說明。在其他實施例中，顯示記憶單元231可以因為設計需求而被省略，而由第三電容CS3或第四電容CS4與液晶電容150本身保存資料電壓。 During the second half of the FP1 period FB1, the fourth display signal SP4 is at a high level during the period FB1, so that the voltage stored in the fourth capacitor CS4 in the fourth memory unit 317 is transmitted to the fourth display switch DSW4. The liquid crystal capacitor DP and the fifth capacitor CS5 of the display memory unit 231. At this time, the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the fourth capacitor CS4, the fifth capacitor CS5, and the liquid crystal capacitor DP itself. In this embodiment, the voltages stored in the third capacitor CS3 and the fourth capacitor CS4 in the screen period FP1 are not for display, so the influence of the conduction of the third display switch DSW3 and the fourth display switch DSW4 is here. Ignore it without explanation. In other embodiments, the display memory unit 231 may be omitted due to design requirements, and the data voltage is saved by the third capacitor CS3 or the fourth capacitor CS4 and the liquid crystal capacitor 150 itself.
在畫面期間FP2中，資料信號DD會傳送包含第二像素資料D2的畫面資料F2。源極驅動器220接收到第二像素資料D2時，會將第二像素資料D2轉換為正極性資料電壓D2+及負極性資料電壓D2-。此時，正極性資料信號DV+會傳送正極性資料電壓D2+，負極性資料信號DV-會傳送負極性資料電壓D2-。 In the picture period FP2, the material signal DD transmits the picture material F2 containing the second pixel data D2. When receiving the second pixel data D2, the source driver 220 converts the second pixel data D2 into a positive polarity data voltage D2+ and a negative polarity data voltage D2-. At this time, the positive polarity data signal DV+ transmits the positive polarity data voltage D2+, and the negative polarity data signal DV- transmits the negative polarity data voltage D2-.
在畫面期間FP2中，第一掃描信號SC1會處於低準位，第二掃描信號SC2會於資料寫入期間DW2中切換至高準位。實際來說，第二掃描信號SC2處於高準位的時間會反比於第二掃描信號SC2的數量，並且第二掃描信號SC2處於高準位的時間互不重疊。在畫面期間FP2中，由於第一掃描信號SC1會處於低準位，因此第一寫入開關WSW1及第二寫入開關WSW2會處於截止狀態。當第二掃描信號SC2處於高準位時，第三寫入開關WSW3及第四寫入開關WSW4處於導通狀態。 In the picture period FP2, the first scan signal SC1 is at a low level, and the second scan signal SC2 is switched to a high level in the data writing period DW2. Actually, the time when the second scan signal SC2 is at the high level is inversely proportional to the number of the second scan signals SC2, and the time when the second scan signal SC2 is at the high level does not overlap each other. In the picture period FP2, since the first scan signal SC1 is at a low level, the first write switch WSW1 and the second write switch WSW2 are in an off state. When the second scan signal SC2 is at the high level, the third write switch WSW3 and the fourth write switch WSW4 are in an on state.
假設第二掃描信號SC2處於高準位時，正極性資料信號DV+及負極性資料信號DV-為分別傳送正極性資料電壓D2+及負極性資料電壓D2-，則第三電容CS3經由第三寫入開關WSW3接收到正極性資料電壓D2+，因此第三電容CS3便於此時儲存電荷，以使第三電容CS3的跨壓約為正極性資料電壓D2+。並且，第四電容CS4經由第四寫入開 關WSW4接收到負極性資料電壓D2-，因此第四電容CS4便於此時儲存電荷，以使第四電容CS4的跨壓約為負極性資料電壓D2-。 Assuming that the second scan signal SC2 is at a high level, the positive polarity data signal DV+ and the negative polarity data signal DV- are respectively transmitting the positive polarity data voltage D2+ and the negative polarity data voltage D2-, and then the third capacitance CS3 is written via the third write. The switch WSW3 receives the positive polarity data voltage D2+, so the third capacitor CS3 facilitates storage of the charge at this time such that the voltage across the third capacitor CS3 is approximately the positive data voltage D2+. And, the fourth capacitor CS4 is opened via the fourth write The off WSW4 receives the negative polarity data voltage D2-, so the fourth capacitor CS4 facilitates storing the charge at this time so that the voltage across the fourth capacitor CS4 is approximately the negative data voltage D2-.
此外，在畫面期間FP2中，第三顯示信號SP3及第四顯示信號SP4會處於低準位，因此第三顯示開關DSW3及第四顯示開關DSW4會處於截止狀態。並且，在畫面期間FP2的前半期間FA2中，第一顯示信號SP1會於期間FA2中處於高準位，以使第一電容CS1所儲存的正極性資料電壓D1+會透過第一顯示開關DSW1傳送至液晶電容DP及第五電容CS5。此時，像素電壓Vlc會約等於正極性資料電壓D1+，而驅動液晶電容DP所需的電位差將由第一電容CS1、第五電容CS5以及液晶電容DP本身來繼續提供。 In addition, in the picture period FP2, the third display signal SP3 and the fourth display signal SP4 are at a low level, so the third display switch DSW3 and the fourth display switch DSW4 are in an off state. Moreover, in the first half period FA2 of the picture period FP2, the first display signal SP1 is at a high level during the period FA2, so that the positive polarity data voltage D1+ stored by the first capacitor CS1 is transmitted to the first display switch DSW1 to The liquid crystal capacitor DP and the fifth capacitor CS5. At this time, the pixel voltage Vlc will be approximately equal to the positive polarity data voltage D1+, and the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the first capacitor CS1, the fifth capacitor CS5, and the liquid crystal capacitor DP itself.
在畫面期間FP2的後半期間FB2中，第二顯示信號SP2會於期間FB2中處於高準位，使得第二電容CS2所儲存的負極性資料電壓D1-會透過第二顯示開關DSW2傳送至液晶電容DP及第五電容CS5。此時，像素電壓Vlc會約等於負極性資料電壓D1-，而驅動液晶電容DP所需的電位差將由第二電容CS2、第五電容CS5以及液晶電容DP本身來繼續提供。在其他實施例中，顯示記憶單元321可以因為設計需求而被省略，而由第一電容CS1或第二電容CS2與液晶電容150本身保存資料電壓。 During the second half of the FP2 period FB2, the second display signal SP2 is at a high level during the period FB2, so that the negative polarity data voltage D1 stored by the second capacitor CS2 is transmitted to the liquid crystal capacitor through the second display switch DSW2. DP and fifth capacitor CS5. At this time, the pixel voltage Vlc will be approximately equal to the negative data voltage D1-, and the potential difference required to drive the liquid crystal capacitor DP will continue to be provided by the second capacitor CS2, the fifth capacitor CS5, and the liquid crystal capacitor DP itself. In other embodiments, the display memory unit 321 may be omitted due to design requirements, and the data voltage is saved by the first capacitor CS1 or the second capacitor CS2 and the liquid crystal capacitor 150 itself.
在畫面期間FP3中，資料信號DD會傳送包含第三像素資料D3的畫面資料F3。源極驅動器220接收到第三像素資料D3時，會將第三像素資料D3轉換為正極性資料電 壓D3+及負極性資料電壓D3-。此時，正極性資料信號DV+會傳送正極性資料電壓D3+，負極性資料信號DV-會傳送負極性資料電壓D3-。 In the picture period FP3, the material signal DD transmits the picture material F3 including the third pixel data D3. When the source driver 220 receives the third pixel data D3, the third pixel data D3 is converted into a positive polarity data. Press D3+ and negative data voltage D3-. At this time, the positive polarity data signal DV+ transmits the positive polarity data voltage D3+, and the negative polarity data signal DV- transmits the negative polarity data voltage D3-.
在畫面期間FP3中，第一寫入開關WSW1、第二寫入開關WSW2、第三寫入開關WSW3、第四寫入開關WSW4、第一顯示開關DSW1、第二顯示開關DSW2、第三顯示開關DSW3及第四顯示開關DSW4的動作相似於畫面期間FP1所述。此時，第一電容CS1會透過第一寫入開關WSW1接收至正極性資料電壓D3+，第二電容CS2會透過第二寫入開關WSW2接收至負極性資料電壓D3+。並且，第三電容CS3所儲存的正極性資料電壓D2+會透過第三顯示開關DSW3於畫面期間FP3中的前半期間FA3傳送至液晶電容DP及第五電容CS5，致使像素電壓Vlc會約等於正極性資料電壓D2+。第四電容CS4所儲存的負極性資料電壓D2-會透過第四顯示開關DSW4於畫面期間FP3中的後半期間FB3傳送至液晶電容DP及第五電容CS5，致使像素電壓Vlc會約等於負極性資料電壓D2-。 In the picture period FP3, the first write switch WSW1, the second write switch WSW2, the third write switch WSW3, the fourth write switch WSW4, the first display switch DSW1, the second display switch DSW2, and the third display switch The actions of the DSW 3 and the fourth display switch DSW4 are similar to those described in the picture period FP1. At this time, the first capacitor CS1 is received to the positive polarity data voltage D3+ through the first write switch WSW1, and the second capacitor CS2 is received to the negative polarity data voltage D3+ through the second write switch WSW2. The positive polarity data voltage D2+ stored in the third capacitor CS3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the third display switch DSW3 during the first half period FA3 of the picture period FP3, so that the pixel voltage Vlc is approximately equal to the positive polarity. Data voltage D2+. The negative polarity data voltage D2- stored in the fourth capacitor CS4 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the fourth display switch DSW4 during the second half period FB3 of the picture period FP3, so that the pixel voltage Vlc is approximately equal to the negative polarity data. Voltage D2-.
依據上述，本發明實施例透過控制第一寫入開關WSW1、第二寫入開關WSW2、第三寫入開關WSW3、第四寫入開關WSW4、第一顯示開關DSW1、第二顯示開關DSW2、第三顯示開關DSW3及第四顯示開關DSW4的導通與否，致使第一電容CS1及第三電容CS3於不同畫面期間交替儲存對應不同像素資料的正極性資料電壓(如D1+、D2+或D3+)，以及交替輸出所儲存的正極性資料 電壓(如D1+、D2+或D3+)。並且，第二電容CS2及第四電容CS4不同畫面期間交替儲存對應不同像素資料的負極性資料電壓(如D1-、D2-或D3-)，以及交替輸出所儲存的負極性資料電壓(如D1-、D2-或D3-)。 According to the above, the embodiment of the present invention controls the first write switch WSW1, the second write switch WSW2, the third write switch WSW3, the fourth write switch WSW4, the first display switch DSW1, and the second display switch DSW2. The third display switch DSW3 and the fourth display switch DSW4 are turned on or off, so that the first capacitor CS1 and the third capacitor CS3 alternately store positive polarity data voltages (such as D1+, D2+ or D3+) corresponding to different pixel data during different screen periods, and Alternately output the stored positive polarity data Voltage (such as D1+, D2+ or D3+). Moreover, the second capacitor CS2 and the fourth capacitor CS4 alternately store negative polarity data voltages (such as D1-, D2- or D3-) corresponding to different pixel data during different screen periods, and alternately output the stored negative polarity data voltages (such as D1). -, D2- or D3-).
圖4繪示為圖2的源極驅動器220的電路示意圖。請參照圖2與圖4，在本實施例中，源極驅動器220包括位移暫存器420及多個資料通道410，並且資料通道410的數量與顯示面板240內像素電路Pix陣列的行數成正比。位移暫存器420依據啟動信號STH及時脈信號CLK依序輸出多個控制信號(例如控制信號COL1、COL2與COL3)。這些資料通道410同時接收資料信號DD並且分別接收其中一個控制信號(例如控制信號COL1)。這些資料通道410的電路結構皆相似，以下則以其中一個資料通道410為例作說明。 4 is a circuit diagram of the source driver 220 of FIG. 2. Referring to FIG. 2 and FIG. 4 , in the embodiment, the source driver 220 includes a displacement register 420 and a plurality of data channels 410 , and the number of data channels 410 and the number of rows of the pixel circuits Pix array in the display panel 240 are Just proportional. The shift register 420 sequentially outputs a plurality of control signals (for example, control signals COL1, COL2, and COL3) according to the start signal STH and the pulse signal CLK. These data channels 410 simultaneously receive the data signal DD and receive one of the control signals (eg, control signal COL1), respectively. The circuit structures of these data channels 410 are similar. The following describes one of the data channels 410 as an example.
資料通道410包括第一資料閂鎖器411、第二資料閂鎖器413、第一數位類比轉換器(Digital-to-Analog Converter,DAC)415及第二數位類比轉換器417。第一資料閂鎖器411的資料輸入端接收資料信號DD所傳遞的像素資料(如D1)，第一資料閂鎖器411的觸發端接收控制信號COL1。第二資料閂鎖器413的資料輸入端耦接第一資料閂鎖器411的資料輸出端，第二資料閂鎖器413的觸發端接收來自時序控制器210的閂鎖信號LAT。第一數位類比轉換器415及第二數位類比轉換器417的輸入端耦接第二資料閂鎖器413的資料輸出端。 The data channel 410 includes a first data latch 411, a second data latch 413, a first digital-to-analog converter (DAC) 415, and a second digital analog converter 417. The data input end of the first data latch 411 receives the pixel data (such as D1) transmitted by the data signal DD, and the trigger end of the first data latch 411 receives the control signal COL1. The data input end of the second data latch 413 is coupled to the data output end of the first data latch 411, and the trigger end of the second data latch 413 receives the latch signal LAT from the timing controller 210. The input ends of the first digital analog converter 415 and the second digital analog converter 417 are coupled to the data output end of the second data latch 413.
第一資料閂鎖器411會依據控制信號COL1決定是否鎖存資料信號DD所傳送的像素資料(如D1)。第一資料閂鎖器411將鎖存的像素資料D1輸出給第二資料閂鎖器413。第二資料閂鎖器413會依據閂鎖信號LAT決定是否鎖存所接收到的像素資料(如D1)。第二資料閂鎖器413將鎖存的像素資料D1輸出到數位類比轉換器415及417。而第一數位類比轉換器415會依據所接收到的像素資料(如D1)輸出正極性資料信號DV+，第二數位類比轉換器417會依據所接收到的像素資料(如D1)輸出負極性資料信號DV-。 The first data latch 411 determines whether to latch the pixel data (such as D1) transmitted by the data signal DD according to the control signal COL1. The first data latch 411 outputs the latched pixel data D1 to the second data latch 413. The second data latch 413 determines whether to latch the received pixel data (such as D1) according to the latch signal LAT. The second data latch 413 outputs the latched pixel data D1 to the digital to analog converters 415 and 417. The first digital analog converter 415 outputs a positive polarity data signal DV+ according to the received pixel data (such as D1), and the second digital analog converter 417 outputs negative polarity data according to the received pixel data (such as D1). Signal DV-.
在本實施例中，資料通道410更包括放大器419及421。放大器419的輸入端A耦接數位類比轉換器415的輸出端，放大器419的輸入端B耦接其輸出端C，而其輸出端C輸出正極性資料信號DV+，其中放大器419的電路結構可視為一電壓隨耦器(Voltage follower)。放大器421的電路結構相似於放大器419，而放大器421的輸入端A耦接數位類比轉換器417的輸出端，放大器421的輸出端C輸出負極性資料信號DV-。 In this embodiment, the data channel 410 further includes amplifiers 419 and 421. The input terminal A of the amplifier 419 is coupled to the output of the digital analog converter 415, the input terminal B of the amplifier 419 is coupled to the output terminal C thereof, and the output terminal C thereof outputs the positive polarity data signal DV+, wherein the circuit structure of the amplifier 419 can be regarded as A voltage follower. The circuit configuration of the amplifier 421 is similar to that of the amplifier 419, and the input terminal A of the amplifier 421 is coupled to the output of the digital analog converter 417, and the output terminal C of the amplifier 421 outputs the negative polarity data signal DV-.
圖5繪示為圖2依據本發明第二實施例的像素電路Pix的電路示意圖。請參照圖3A與圖5，第二實施例的電路運作原理相似於圖3A的第一實施例，但其不同之處在於切換單元511。在本實施例中，切換單元511包括第一電壓隨耦器521、第二電壓隨耦器523、第三電壓隨耦器525、第四電壓隨耦器527及導通開關CSW。第一電壓隨耦器 521的輸入端作為切換單元511的第一輸入端511a並耦接第一記憶單元311，第一電壓隨耦器521受控於第一顯示信號SP1。第二電壓隨耦器523的輸入端作為切換單元511的第二輸入端511b並耦接第二記憶單元313，第二電壓隨耦器523受控於第二顯示信號SP2。 FIG. 5 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a second embodiment of the present invention. Referring to FIG. 3A and FIG. 5, the circuit operation principle of the second embodiment is similar to that of the first embodiment of FIG. 3A, but differs in the switching unit 511. In the present embodiment, the switching unit 511 includes a first voltage follower 521, a second voltage follower 523, a third voltage follower 525, a fourth voltage follower 527, and a turn-on switch CSW. First voltage follower The input end of the 521 is the first input end 511a of the switching unit 511 and is coupled to the first memory unit 311. The first voltage follower 521 is controlled by the first display signal SP1. The input end of the second voltage follower 523 is used as the second input end 511b of the switching unit 511 and coupled to the second memory unit 313, and the second voltage follower 523 is controlled by the second display signal SP2.
第三電壓隨耦器525的輸入端作為切換單元511的第三輸入端511c並耦接第三記憶單元315，第三電壓隨耦器415受控於第三顯示信號SP3。第四電壓隨耦器527的輸入端作為切換單元511的第四輸入端511d並耦接第四記憶單元317，第四電壓隨耦器527受控於第四顯示信號SP4。導通開關CSW的第一端耦接第一電壓隨耦器521的輸出端、第二電壓隨耦器523的輸出端、第三電壓隨耦器525的輸出端及第四電壓隨耦器527的輸出端，導通開關CSW的第二端作為切換單元511的輸出端511e並耦接顯示單元320，導通開關CSW受控於第一顯示信號SP1、第二顯示信號SP2、第三顯示信號SP3及第四顯示信號SP4。其中，電壓隨耦器521、523、525及527可參照放大器419或421的電路來實現，在此則不在贅述。 The input end of the third voltage follower 525 is used as the third input end 511c of the switching unit 511 and coupled to the third memory unit 315, and the third voltage follower 415 is controlled by the third display signal SP3. The input end of the fourth voltage follower 527 is used as the fourth input end 511d of the switching unit 511 and coupled to the fourth memory unit 317, and the fourth voltage follower 527 is controlled by the fourth display signal SP4. The first end of the turn-on switch CSW is coupled to the output of the first voltage follower 521, the output of the second voltage follower 523, the output of the third voltage follower 525, and the fourth voltage follower 527. The output end, the second end of the conduction switch CSW serves as the output end 511e of the switching unit 511 and is coupled to the display unit 320. The conduction switch CSW is controlled by the first display signal SP1, the second display signal SP2, the third display signal SP3 and the The four display signal SP4. The voltage followers 521, 523, 525, and 527 can be implemented by referring to the circuits of the amplifiers 419 or 421, and are not described herein.
進一步來說，在電路設計中，電壓隨耦器(如521)一般為保持於運作的狀態，但於實際電路應用中，電壓隨耦器除了輸入端與輸出端，亦可具有致能(enable)接腳或電源接腳。透過對電壓隨耦器的致能接腳或電源接腳施加的電壓控制電壓隨耦器是否運作，亦即顯示信號可施加 於電壓隨耦器的致能接腳或電源接腳來控制電壓隨耦器是否運作。 Further, in the circuit design, the voltage follower (such as 521) is generally kept in operation, but in practical circuit applications, the voltage follower can be enabled in addition to the input and output. ) Pin or power pin. By controlling the voltage of the voltage follower or the power pin to control whether the voltage follower is operated, that is, the display signal can be applied. Control the voltage follower operation of the voltage follower enable pin or power pin.
依據上述及圖3B，第一電壓隨耦器521運作於畫面期間FP2的前半期間FA2，第二電壓隨耦器523運作於畫面期間FP2的後半期間FB2，第三電壓隨耦器525運作於畫面期間FP1的前半期間FA1及畫面期間FP3的前半期間FA3，第四電壓隨耦器527運作於畫面期間FP1的後半期間FB1及畫面期間FP3的後半期間FB3。 According to the above and FIG. 3B, the first voltage follower 521 operates in the first half period FA2 of the picture period FP2, the second voltage follower 523 operates in the second half period FB2 of the picture period FP2, and the third voltage follower 525 operates on the screen. In the first half period FA1 of the period FP1 and the first half period FA3 of the screen period FP3, the fourth voltage follower 527 operates in the second half period FB1 of the screen period FP1 and the second half period FB3 of the screen period FP3.
再者，電壓隨耦器521、523、525、527可隔絕輸入端與輸出端的電流。換言之，例如，在第一電壓隨耦器521運作時，可避免第一電容CS1與第五電容CS5及液晶電容DP發生電荷共享(charge sharing)效應。同樣地，第二電壓隨耦器523、第三電壓隨耦器525及第四電壓隨耦器527亦可避免上述之電荷分享效應。 Furthermore, the voltage followers 521, 523, 525, 527 can isolate the current at the input and output. In other words, for example, when the first voltage follower 521 operates, the charge sharing effect of the first capacitor CS1 and the fifth capacitor CS5 and the liquid crystal capacitor DP can be avoided. Similarly, the second voltage follower 523, the third voltage follower 525, and the fourth voltage follower 527 can also avoid the charge sharing effect described above.
圖6繪示為圖2依據本發明第三實施例的像素電路Pix的電路示意圖。請參照圖3A與圖6，第三實施例的電路運作原理相似於圖3A的第一實施例，但其不同之處在於第三實施例的儲存單元610。儲存單元610的切換單元611更包括緩衝器613，緩衝器613的輸入端耦接第一顯示開關DSW1的第二端、第二顯示開關DSW2的第二端、第三顯示開關DSW3的第二端及第四顯示開關DSW4的第二端，緩衝器613的輸出端作為切換單元611的輸出端並耦接液晶電容DP。其中，緩衝器613可以利用電壓隨耦器來實現，但不以此限制本發明實施例。藉此，可避免第一 電容CS1、第二電容CS2、第三電容CS3或第四電容CS4與第五電容CS5及液晶電容DP發生電荷共享效應。 FIG. 6 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a third embodiment of the present invention. Referring to FIG. 3A and FIG. 6, the circuit of the third embodiment operates in a similar manner to the first embodiment of FIG. 3A, but differs in the storage unit 610 of the third embodiment. The switching unit 611 of the storage unit 610 further includes a buffer 613. The input end of the buffer 613 is coupled to the second end of the first display switch DSW1, the second end of the second display switch DSW2, and the second end of the third display switch DSW3. And the second end of the fourth display switch DSW4, the output end of the buffer 613 is used as an output end of the switching unit 611 and coupled to the liquid crystal capacitor DP. The buffer 613 can be implemented by using a voltage follower, but does not limit the embodiment of the present invention. Thereby avoiding the first The capacitor CS1, the second capacitor CS2, the third capacitor CS3, or the fourth capacitor CS4 have a charge sharing effect with the fifth capacitor CS5 and the liquid crystal capacitor DP.
圖7A繪示為圖2依據本發明第四實施例的像素電路Pix的電路示意圖。請參照圖3A與圖7A，其不同之處為第四實施例的儲存單元710的第五寫入開關WSW5及切換單元711中的第五顯示開關DSW5。其中，第五寫入開關WSW5可視為第二寫入開關WSW2及第四寫入開關WSW4的組合，第五顯示開關DSW5可視為第二顯示開關DSW2及第四顯示開關DSW4的組合。 FIG. 7A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the fourth embodiment of the present invention. Please refer to FIG. 3A and FIG. 7A , which are different from the fifth write switch WSW5 of the storage unit 710 of the fourth embodiment and the fifth display switch DSW5 of the switching unit 711 . The fifth write switch WSW5 can be regarded as a combination of the second write switch WSW2 and the fourth write switch WSW4, and the fifth display switch DSW5 can be regarded as a combination of the second display switch DSW2 and the fourth display switch DSW4.
圖7B繪示為依據本發明另一實施例的顯示裝置的驅動時序圖。請參照圖2、圖7A與圖7B，在本實施例中，每一畫面期間(如FP4、FP5及FP6)同樣包括資料寫入期間(如DW4、DW5及DW6)及垂直空白期間(如VB4、VB5及VB6)，並且在此每一畫面期間(如FP4、FP5及FP6)的垂直空白期間(如VB4、VB5及VB6)排列於資料寫入期間(如DW4、DW5及DW6)之前。畫面期間FP4、FP5或FP6的第一掃描信號SC1、第二掃描信號SC2、資料信號DD、正極性資料信號DV+及負極性資料信號DV-的驅動波形相似於畫面期間FP1、FP2或FP3所述，故不再重述其細節部份。 FIG. 7B is a timing chart showing driving of a display device according to another embodiment of the present invention. Referring to FIG. 2, FIG. 7A and FIG. 7B, in this embodiment, each picture period (such as FP4, FP5, and FP6) also includes data writing periods (such as DW4, DW5, and DW6) and vertical blank periods (such as VB4). , VB5 and VB6), and the vertical blank periods (such as VB4, VB5, and VB6) during each picture period (such as FP4, FP5, and FP6) are arranged before the data writing period (such as DW4, DW5, and DW6). The driving waveforms of the first scan signal SC1, the second scan signal SC2, the data signal DD, the positive polarity data signal DV+, and the negative polarity data signal DV- of the FP4, FP5 or FP6 during the picture period are similar to those described in the picture period FP1, FP2 or FP3 Therefore, the details are not repeated.
在畫面期間FP4的資料寫入期間DW4中，第一寫入開關WSW1及第五寫入開關WSW5會依據第一掃描信號SC1而導通，以致於第一電容CS1會經由第一寫入開關WSW1接收並儲存正極性資料電壓D1+，第二電容CS2會 經由第五寫入開關WSW5接收並儲存負極性資料電壓D1-。並且，第三顯示信號SP3會處於高準位，而第一顯示信號SP1、第二顯示信號SP2及第四顯示信號SP4會處於低準位。此時，第三電容CS3所儲存的電壓會透過第三顯示開關DSW3傳送至液晶電容DP及第五電容CS5。在此假設第三電容CS3所儲存的電壓非顯示用的資料電壓，故像素電壓Vlc的改變則忽略。 During the data writing period DW4 of the picture period FP4, the first write switch WSW1 and the fifth write switch WSW5 are turned on according to the first scan signal SC1, so that the first capacitor CS1 is received via the first write switch WSW1. And store the positive data voltage D1+, the second capacitor CS2 will The negative polarity data voltage D1- is received and stored via the fifth write switch WSW5. Moreover, the third display signal SP3 will be at a high level, and the first display signal SP1, the second display signal SP2, and the fourth display signal SP4 will be at a low level. At this time, the voltage stored in the third capacitor CS3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the third display switch DSW3. It is assumed here that the voltage stored in the third capacitor CS3 is not the data voltage for display, so the change in the pixel voltage Vlc is ignored.
在畫面期間FP5的垂直空白期間VB5中，第二顯示信號SP2會處於高準位，而第一顯示信號SP1、第三顯示信號SP3及第四顯示信號SP4會處於低準位。此時，第二電容CS2所儲存的負極性資料電壓D1-會透過第五顯示開關DSW5傳送至液晶電容DP及第五電容CS5，致使像素電壓Vlc會約等於負極性資料電壓D1-。 During the vertical blank period VB5 of the screen period FP5, the second display signal SP2 will be at a high level, and the first display signal SP1, the third display signal SP3, and the fourth display signal SP4 will be at a low level. At this time, the negative polarity data voltage D1- stored by the second capacitor CS2 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the fifth display switch DSW5, so that the pixel voltage Vlc is approximately equal to the negative polarity data voltage D1-.
在畫面期間FP5的資料寫入期間DW5中，第三寫入開關WSW3及第五寫入開關WSW5處於導通狀態，而第三電容CS3會經由第三寫入開關WSW3接收並儲存正極性資料電壓D2+，第二電容CS2會經由第五寫入開關WSW5接收並儲存負極性資料電壓D2-。並且，第一顯示信號SP1會處於高準位，而第二顯示信號SP2、第三顯示信號SP3及第四顯示信號SP4會處於低準位。此時，第一電容CS1所儲存的正極性資料電壓D1+會透過第一顯示開關DSW1傳送至液晶電容DP及第五電容CS5，致使像素電壓Vlc會約等於正極性資料電壓D1+。 In the data writing period DW5 of the picture period FP5, the third write switch WSW3 and the fifth write switch WSW5 are in an on state, and the third capacitor CS3 receives and stores the positive polarity data voltage D2+ via the third write switch WSW3. The second capacitor CS2 receives and stores the negative polarity data voltage D2- via the fifth write switch WSW5. Moreover, the first display signal SP1 will be at a high level, and the second display signal SP2, the third display signal SP3, and the fourth display signal SP4 will be at a low level. At this time, the positive polarity data voltage D1+ stored by the first capacitor CS1 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the first display switch DSW1, so that the pixel voltage Vlc is approximately equal to the positive polarity data voltage D1+.
在畫面期間FP6的垂直空白期間VB6中，第四顯示信號SP4會處於高準位，而第一顯示信號SP1、第二顯示信號SP2及第三顯示信號SP3會處於低準位。此時，第二電容CS2所儲存的負極性資料電壓D2-同樣會透過第五顯示開關DSW5傳送至液晶電容DP及第五電容CS5，致使像素電壓Vlc會約等於負極性資料電壓D2-。 During the vertical blank period VB6 of the picture period FP6, the fourth display signal SP4 will be at a high level, and the first display signal SP1, the second display signal SP2, and the third display signal SP3 will be at a low level. At this time, the negative polarity data voltage D2- stored in the second capacitor CS2 is also transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the fifth display switch DSW5, so that the pixel voltage Vlc is approximately equal to the negative polarity data voltage D2-.
在畫面期間FP6的資料寫入期間DW6中，第一電容CS1會經由第一寫入開關WSW1接收並儲存正極性資料電壓D3+，第二電容CS2會經由第五寫入開關WSW5接收並儲存負極性資料電壓D3-。並且，第三電容CS3所儲存的正極性資料電壓D2+會透過第三顯示開關DSW3傳送至液晶電容DP及第五電容CS5，致使像素電壓Vlc會約等於正極性資料電壓D2+。 During the data writing period DW6 of the picture period FP6, the first capacitor CS1 receives and stores the positive polarity data voltage D3+ via the first write switch WSW1, and the second capacitor CS2 receives and stores the negative polarity via the fifth write switch WSW5. Data voltage D3-. The positive polarity data voltage D2+ stored in the third capacitor CS3 is transmitted to the liquid crystal capacitor DP and the fifth capacitor CS5 through the third display switch DSW3, so that the pixel voltage Vlc is approximately equal to the positive polarity data voltage D2+.
依據上述，本發明實施例透過控制第一寫入開關WSW1、第三寫入開關WSW3、第五寫入開關WSW5、第一顯示開關DSW1、第三顯示開關DSW3及第五顯示開關DSW5的導通與否，致使第一電容CS1及第三電容CS3於不同畫面期間交替儲存正極性資料電壓，以及交替輸出所儲存的正極性資料電壓。而第二電容CS2會儲存不同畫面的負極性資料電壓，並且於垂直空白期間輸出所儲存的負極性資料電壓。 According to the above, the embodiment of the present invention controls the conduction between the first write switch WSW1, the third write switch WSW3, the fifth write switch WSW5, the first display switch DSW1, the third display switch DSW3, and the fifth display switch DSW5. Otherwise, the first capacitor CS1 and the third capacitor CS3 are caused to alternately store the positive polarity data voltage during different screens, and alternately output the stored positive polarity data voltage. The second capacitor CS2 stores the negative data voltage of different screens, and outputs the stored negative data voltage during the vertical blank period.
圖8繪示為圖2依據本發明第五實施例的像素電路Pix的電路示意圖。請參照圖7A與圖8，第五實施例的電路運作原理相似於圖7A的第四實施例，但其不同之處在於儲 存單元810的切換單元811。切換單元811包括第一電壓隨耦器521、第三電壓隨耦器525、第五電壓隨耦器821及導通開關CSW，其中第一電壓隨耦器521、第三電壓隨耦器525及導通開關CSW可參照第二實施例的說明，在此則不再贅述。在本實施例中，第五電壓隨耦器821的輸入端作為切換單元811的第二輸入端以耦接第二記憶單元313，並且電壓隨耦器821受控於第二顯示信號SP2及第4顯示信號SP4，亦即電壓隨耦器821運作於圖7B的垂直空白期間VB5及VB6中。 FIG. 8 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a fifth embodiment of the present invention. Referring to FIG. 7A and FIG. 8, the circuit operation principle of the fifth embodiment is similar to the fourth embodiment of FIG. 7A, but the difference lies in the storage. The switching unit 811 of the storage unit 810. The switching unit 811 includes a first voltage follower 521, a third voltage follower 525, a fifth voltage follower 821, and a turn-on switch CSW, wherein the first voltage follower 521, the third voltage follower 525, and the turn-on The switch CSW can be referred to the description of the second embodiment, and details are not described herein again. In this embodiment, the input end of the fifth voltage follower 821 is used as the second input end of the switching unit 811 to be coupled to the second memory unit 313, and the voltage follower 821 is controlled by the second display signal SP2 and the 4 The display signal SP4, that is, the voltage follower 821 operates in the vertical blank periods VB5 and VB6 of FIG. 7B.
圖9繪示為圖2依據本發明第六實施例的像素電路Pix的電路示意圖。請參照圖7A與圖9，第六實施例的電路運作原理相似於圖7A的第四實施例，但其不同之處在於第六實施例的切換單元911更包括緩衝器613，其中緩衝器613可參照第三實施例的說明，在此則不再贅述。 FIG. 9 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a sixth embodiment of the present invention. Referring to FIG. 7A and FIG. 9, the circuit operation principle of the sixth embodiment is similar to that of the fourth embodiment of FIG. 7A, but the difference is that the switching unit 911 of the sixth embodiment further includes a buffer 613, wherein the buffer 613 Reference may be made to the description of the third embodiment, and details are not described herein again.
依據上述實施例，可彙整為一像素電路的驅動方法。圖10繪示為依據本發明一實施例的像素電路的操作方法的流程圖。請參照圖10，於第一畫面期間儲存第一像素資料的正極性資料電壓及負極性資料電壓(步驟S110)。於第二畫面期間的第一子期間與第二子期間，分別將第一像素資料的正極性資料電壓及負極性資料電壓輸出給顯示單元(步驟S120)。於第二畫面期間，儲存第二像素資料的正極性資料電壓及負極性資料電壓(步驟S130)。於第三畫面期間的第三子期間與第四子期間，分別將第二像素資料的正極性資料電壓及負極性資料電壓輸出給顯示單元 (步驟S140)。其中，上述步驟的細節可參照上述說明，在此則不再贅述。 According to the above embodiment, the driving method of one pixel circuit can be integrated. FIG. 10 is a flow chart showing a method of operating a pixel circuit in accordance with an embodiment of the invention. Referring to FIG. 10, the positive polarity data voltage and the negative polarity data voltage of the first pixel data are stored during the first screen period (step S110). The first sub-period and the second sub-period of the second picture period respectively output the positive polarity data voltage and the negative polarity data voltage of the first pixel data to the display unit (step S120). During the second screen period, the positive polarity data voltage and the negative polarity data voltage of the second pixel data are stored (step S130). Outputting the positive polarity data voltage and the negative polarity data voltage of the second pixel data to the display unit in the third sub-period and the fourth sub-period of the third picture period (Step S140). For details of the above steps, reference may be made to the above description, and details are not described herein again.
綜上所述，本發明實施例的顯示裝置、像素電路及其操作方法，其於像素電路中配置三個以上的電容，並且透過對應的控制寫入開關及切換單元，致使這些電容分別儲存對應的正極性資料電壓及負極性資料電壓，並且依序輸出所儲存的正極性資料電壓及負極性資料電壓。藉此，可降低源極驅動器的資料傳輸速率。並且，可在像素電路的切換單元中配置電壓隨耦器，以避免電荷共享的效應發生。 In summary, the display device, the pixel circuit, and the method for operating the same according to the embodiments of the present invention have three or more capacitors disposed in the pixel circuit, and the corresponding write control switches and the switching unit are respectively caused to cause the capacitors to be respectively stored correspondingly. The positive polarity data voltage and the negative polarity data voltage, and sequentially output the stored positive polarity data voltage and negative polarity data voltage. Thereby, the data transfer rate of the source driver can be reduced. Also, a voltage follower can be configured in the switching unit of the pixel circuit to avoid the effect of charge sharing.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。 Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
100、200‧‧‧顯示裝置 100, 200‧‧‧ display devices
110、210‧‧‧時序控制器 110, 210‧‧‧ timing controller
120、220‧‧‧源極驅動器 120, 220‧‧‧ source drive
130、230‧‧‧閘極驅動器 130, 230‧‧ ‧ gate driver
140、240‧‧‧顯示面板 140, 240‧‧‧ display panel
250‧‧‧背光模組 250‧‧‧Backlight module
310、510、610、710、810、910‧‧‧儲存單元 310, 510, 610, 710, 810, 910‧‧‧ storage units
311、313、315、317‧‧‧記憶單元 311, 313, 315, 317‧‧‧ memory unit
319、511、611、711、811、911‧‧‧切換單元 319, 511, 611, 711, 811, 911 ‧ ‧ switching unit
319a、319b、319c、319d、511a、511b、511c、511d、A、B‧‧‧輸入端 Inputs 319a, 319b, 319c, 319d, 511a, 511b, 511c, 511d, A, B‧‧
319e、511e、C‧‧‧輸出端 319e, 511e, C‧‧‧ outputs
320‧‧‧顯示單元 320‧‧‧ display unit
321‧‧‧顯示記憶單元 321‧‧‧ display memory unit
410‧‧‧資料通道 410‧‧‧ data channel
411‧‧‧位移暫存器 411‧‧‧Displacement register
413‧‧‧資料閂鎖器 413‧‧‧Information latch
415、417‧‧‧數位類比轉換器 415, 417‧‧‧Digital Analog Converter
419、421‧‧‧放大器 419, 421‧‧ amps
521、523、525、527、821‧‧‧電壓隨耦器 521, 523, 525, 527, 821‧‧‧ voltage followers
613‧‧‧緩衝器 613‧‧‧buffer
CS1~CS5‧‧‧電容 CS1~CS5‧‧‧ capacitor
D1~D3‧‧‧像素資料 D1~D3‧‧‧Pixel data
D1+、D1-、D2+、D2-、D3+、D3-‧‧‧資料電壓 D1+, D1-, D2+, D2-, D3+, D3-‧‧‧ data voltage
DD‧‧‧資料信號 DD‧‧‧Information signal
DP‧‧‧顯示元件/液晶電容 DP‧‧‧ display components / liquid crystal capacitors
DS‧‧‧顯示資料 DS‧‧‧Display information
DSW1~DSW5‧‧‧顯示開關 DSW1~DSW5‧‧‧ display switch
DV+、DV-‧‧‧資料信號 DV+, DV-‧‧‧ data signal
F1~F3‧‧‧畫面資料 F1~F3‧‧‧ screen data
FA1、FB1、FA2、FB2、FA3、FB3‧‧‧期間 FA1, FB1, FA2, FB2, FA3, FB3‧‧‧
fp1~fp3、FP1~FP6‧‧‧畫面期間 Fp1~fp3, FP1~FP6‧‧‧ during the screen
dw1~dw3、DW1~DW6‧‧‧資料寫入期間 Dw1~dw3, DW1~DW6‧‧‧ data writing period
vb1~vb3、VB1~VB6‧‧‧垂直空白期間 Vb1~vb3, VB1~VB6‧‧‧ vertical blank period
CLK‧‧‧時脈信號 CLK‧‧‧ clock signal
COL1~COL3‧‧‧控制信號 COL1~COL3‧‧‧ control signal
LAT‧‧‧閂鎖信號 LAT‧‧‧Latch signal
PX、Pix‧‧‧像素電路 PX, Pix‧‧‧ pixel circuits
SC1、SC2‧‧‧掃描信號 SC1, SC2‧‧‧ scan signals
SCW‧‧‧導通開關 SCW‧‧‧Switch
STH‧‧‧啟動信號 STH‧‧‧ start signal
SP1~SP4‧‧‧顯示信號 SP1~SP4‧‧‧ display signal
Vlc‧‧‧像素電壓 Vlc‧‧‧ pixel voltage
VR1、VR2‧‧‧參考電壓 VR1, VR2‧‧‧ reference voltage
Vcom‧‧‧共同電壓 Vcom‧‧‧Common voltage
WSW1~WSW5‧‧‧寫入開關 WSW1~WSW5‧‧‧Write switch
S110、S120、S130、S140‧‧‧步驟 S110, S120, S130, S140‧‧ steps
圖1A繪示為一傳統顯示器的系統方塊圖。 1A is a block diagram of a system of a conventional display.
圖1B繪示為圖1A的資料信號DD及像素電路PX的驅動時序圖。 FIG. 1B is a timing chart showing driving of the data signal DD and the pixel circuit PX of FIG. 1A.
圖2繪示為依據本發明一實施例之顯示裝置的系統方塊圖。 2 is a block diagram of a system of a display device in accordance with an embodiment of the present invention.
圖3A繪示為圖2依據本發明第一實施例的像素電路Pix的電路示意圖。 FIG. 3A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the first embodiment of the present invention.
圖3B繪示為依據本發明一實施例的顯示裝置200的驅動時序圖。 FIG. 3B is a timing chart of driving of the display device 200 according to an embodiment of the invention.
圖4繪示為圖2的源極驅動器220的電路示意圖。 4 is a circuit diagram of the source driver 220 of FIG. 2.
圖5繪示為圖2依據本發明第二實施例的像素電路Pix的電路示意圖。 FIG. 5 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a second embodiment of the present invention.
圖6繪示為圖2依據本發明第三實施例的像素電路Pix的電路示意圖。 FIG. 6 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a third embodiment of the present invention.
圖7A繪示為圖2依據本發明第四實施例的像素電路Pix的電路示意圖。 FIG. 7A is a schematic circuit diagram of the pixel circuit Pix of FIG. 2 according to the fourth embodiment of the present invention.
圖7B繪示為依據本發明另一實施例的顯示裝置200的驅動時序圖。 FIG. 7B is a timing chart showing driving of the display device 200 according to another embodiment of the present invention.
圖8繪示為圖2依據本發明第五實施例的像素電路Pix的電路示意圖。 FIG. 8 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a fifth embodiment of the present invention.
圖9繪示為圖2依據本發明第六實施例的像素電路Pix的電路示意圖。 FIG. 9 is a circuit diagram of the pixel circuit Pix of FIG. 2 according to a sixth embodiment of the present invention.
圖10繪示為依據本發明一實施例的像素電路的操作方法的流程圖。 FIG. 10 is a flow chart showing a method of operating a pixel circuit in accordance with an embodiment of the invention.
310‧‧‧儲存單元 310‧‧‧ storage unit
311、313、315、317‧‧‧記憶單元 311, 313, 315, 317‧‧‧ memory unit
319‧‧‧切換單元 319‧‧‧Switch unit
320‧‧‧顯示單元 320‧‧‧ display unit
321‧‧‧顯示記憶單元 321‧‧‧ display memory unit
CS1~CS5‧‧‧電容 CS1~CS5‧‧‧ capacitor
DP‧‧‧顯示元件/液晶電容 DP‧‧‧ display components / liquid crystal capacitors
DSW1~DSW4‧‧‧顯示開關 DSW1~DSW4‧‧‧ display switch
DV+、DV-‧‧‧資料信號 DV+, DV-‧‧‧ data signal
Pix‧‧‧像素電路 Pix‧‧‧pixel circuit
SC1、SC2‧‧‧掃描信號 SC1, SC2‧‧‧ scan signals
SP1~SP4‧‧‧顯示信號 SP1~SP4‧‧‧ display signal
Vlc‧‧‧像素電壓 Vlc‧‧‧ pixel voltage
VR1、VR2‧‧‧參考電壓 VR1, VR2‧‧‧ reference voltage
Vcom‧‧‧共同電壓 Vcom‧‧‧Common voltage
WSW1~WSW4‧‧‧寫入開關 WSW1~WSW4‧‧‧Write switch
Claims (19)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99125935A TWI408642B (en) | 2010-08-04 | 2010-08-04 | Display, pixel circuitry and operating method of pixel circuitry |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW99125935A TWI408642B (en) | 2010-08-04 | 2010-08-04 | Display, pixel circuitry and operating method of pixel circuitry |
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| TW201207803A TW201207803A (en) | 2012-02-16 |
| TWI408642B true TWI408642B (en) | 2013-09-11 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW536689B (en) * | 2001-01-18 | 2003-06-11 | Sharp Kk | Display, portable device, and substrate |
| TW578120B (en) * | 2001-07-14 | 2004-03-01 | Koninkl Philips Electronics Nv | Active matrix display devices |
| TW582010B (en) * | 2001-07-13 | 2004-04-01 | Koninkl Philips Electronics Nv | Active matrix array devices |
| TW200947023A (en) * | 2008-05-05 | 2009-11-16 | Au Optronics Corp | Pixel, display and the driving method thereof |
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2010
- 2010-08-04 TW TW99125935A patent/TWI408642B/en active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW536689B (en) * | 2001-01-18 | 2003-06-11 | Sharp Kk | Display, portable device, and substrate |
| TW582010B (en) * | 2001-07-13 | 2004-04-01 | Koninkl Philips Electronics Nv | Active matrix array devices |
| TW578120B (en) * | 2001-07-14 | 2004-03-01 | Koninkl Philips Electronics Nv | Active matrix display devices |
| TW200947023A (en) * | 2008-05-05 | 2009-11-16 | Au Optronics Corp | Pixel, display and the driving method thereof |
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| TW201207803A (en) | 2012-02-16 |
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