TWI406285B - Architecture of highly integrated semiconductor memory device - Google Patents
Architecture of highly integrated semiconductor memory device Download PDFInfo
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- TWI406285B TWI406285B TW098101821A TW98101821A TWI406285B TW I406285 B TWI406285 B TW I406285B TW 098101821 A TW098101821 A TW 098101821A TW 98101821 A TW98101821 A TW 98101821A TW I406285 B TWI406285 B TW I406285B
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- G—PHYSICS
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- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
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Abstract
Description
本發明係關於半導體裝置，且更特定言之，係關於高度積體化半導體記憶體裝置之架構，該高度積體化半導體記憶體裝置包括用於儲存資料之複數個記憶體庫及用於執行輸入/輸出操作之各種內部電路。The present invention relates to a semiconductor device, and more particularly to an architecture of a highly integrated semiconductor memory device including a plurality of memory banks for storing data and for performing Various internal circuits for input/output operations.
本發明主張分別於2008年1月18日及2008年11月13日申請之韓國專利申請案第10-2008-0005630號及第10-2008-0112700號之優先權，該等申請案以全文引用之方式併入。The present invention claims priority to Korean Patent Application No. 10-2008-0005630 and No. 10-2008-0112700, filed on Jan. 18, 2008, and on The way it is incorporated.
諸如雙資料速率同步DRAM(DDR SDRAM)之半導體記憶體裝置根據自資料處理器裝置(例如，中央處理器單元(CPU))接收之命令而儲存或輸出資料。當自CPU輸入讀取命令時，將資料儲存於對應於自CPU接收之位址的半導體記憶體裝置之記憶體單元中。當自CPU輸入寫入命令時，將資料自對應於自CPU接收之位址之記憶體單元輸出。A semiconductor memory device, such as a dual data rate synchronous DRAM (DDR SDRAM), stores or outputs data in accordance with commands received from a data processor device (eg, a central processing unit (CPU)). When a read command is input from the CPU, the data is stored in a memory unit corresponding to the semiconductor memory device of the address received from the CPU. When a write command is input from the CPU, the data is output from the memory unit corresponding to the address received from the CPU.
半導體記憶體裝置包括數千萬或更多記憶體單元。記憶體單元集合被稱為記憶體庫。半導體記憶體裝置中之記憶體庫之數目根據設計而不同且隨著開發半導體記憶體裝置以達成大容量而持續增加。Semiconductor memory devices include tens of millions or more of memory cells. A collection of memory cells is called a memory bank. The number of memory banks in a semiconductor memory device varies depending on the design and continues to increase as the semiconductor memory device is developed to achieve a large capacity.
圖1為說明習知半導體記憶體裝置之讀取及寫入操作之電路圖。為解釋便利起見，在圖1中，僅展示具有參考數字110之一個記憶體單元。1 is a circuit diagram illustrating read and write operations of a conventional semiconductor memory device. For the sake of convenience of explanation, in FIG. 1, only one memory unit having reference numeral 110 is shown.
將參看圖1來簡要地描述習知半導體記憶體裝置之讀取操作。The read operation of the conventional semiconductor memory device will be briefly described with reference to FIG.
當將讀取命令輸入至半導體記憶體裝置時，解碼所輸入之列位址以啟用對應字線WL。接著，接通記憶體單元110之單元電晶體T1，以使得電荷共用在單元電容器C1與位元線BL或位元線桿/BL之間發生。因此，在位元線BL與位元線桿/BL之間存在細微電壓差。When a read command is input to the semiconductor memory device, the input column address is decoded to enable the corresponding word line WL. Next, the cell transistor T1 of the memory cell 110 is turned on so that charge sharing occurs between the cell capacitor C1 and the bit line BL or the bit line bar /BL. Therefore, there is a slight voltage difference between the bit line BL and the bit line bar /BL.
位元線感應放大器120感應並放大該電壓差。亦即，當位元線BL之電位高於位元線桿/BL之電位時，將位元線BL之電壓放大至上拉電源電壓RTO且將位元線桿/BL之電壓放大至下拉電源電壓SB。相比而言，當位元線BL之電位低於位元線桿/BL之電位時，將位元線BL之電壓位準放大至下拉電源電壓SB且將位元線桿/BL之電壓位準放大至上拉電源電壓RTO。The bit line sense amplifier 120 senses and amplifies the voltage difference. That is, when the potential of the bit line BL is higher than the potential of the bit line bar /BL, the voltage of the bit line BL is amplified to the pull-up power supply voltage RTO and the voltage of the bit line bar /BL is amplified to the pull-down power supply voltage. SB. In contrast, when the potential of the bit line BL is lower than the potential of the bit line/BL, the voltage level of the bit line BL is amplified to the pull-down power supply voltage SB and the voltage level of the bit line/BL is Zoom in to the pull-up supply voltage RTO.
亦解碼所輸入之行位址以啟動行選擇信號YI。接著，啟用行選擇器130，以使得位元線BL及位元線桿/BL分別連接至片段輸入/輸出線SIO及片段輸入/輸出線桿/SIO。亦即，將位元線BL上之資料傳送至片段輸入/輸出線SIO且將位元線桿/BL上之資料傳送至片段輸入/輸出線桿/SIO。The input row address is also decoded to initiate the row select signal YI. Next, the row selector 130 is enabled such that the bit line BL and the bit line bar /BL are connected to the segment input/output line SIO and the segment input/output line bar /SIO, respectively. That is, the data on the bit line BL is transferred to the segment input/output line SIO and the data on the bit line bar /BL is transferred to the segment input/output line bar /SIO.
此後，回應於輸入/輸出控制信號CTR_IO而啟用輸入/輸出開關140，以使得片段輸入/輸出線SIO及片段輸入/輸出線桿/SIO連接至區域輸入/輸出線LIO及區域輸入/輸出線桿/LIO。亦即，將片段輸入/輸出線SIO上之信號傳送至區域輸入/輸出線LIO，且將片段輸入/輸出線桿/SIO上之信號傳送至區域輸入/輸出線桿/LIO。讀取驅動器150自區域輸入/輸出線LIO及區域輸入/輸出線桿/LIO接收資料以驅動全域輸入/輸出線GIO。Thereafter, the input/output switch 140 is enabled in response to the input/output control signal CTR_IO to connect the segment input/output line SIO and the segment input/output line/SIO to the area input/output line LIO and the area input/output line bar /LIO. That is, the signal on the segment input/output line SIO is transmitted to the area input/output line LIO, and the signal on the segment input/output line/SIO is transmitted to the area input/output line lever /LIO. The read driver 150 receives data from the area input/output line LIO and the area input/output line/LIO to drive the global input/output line GIO.
因此，回應於行選擇信號YI而將記憶體單元110中之資料分別自位元線BL及位元線桿/BL傳送至片段輸入/輸出線SIO及片段輸入/輸出線桿/SIO。回應於輸入/輸出控制信號CTR_IO而分別將片段輸入/輸出線SIO及片段輸入/輸出線桿/SIO上之資料傳送至區域輸入/輸出線LIO及區域輸入/輸出線桿/LIO。由讀取驅動器150將區域輸入/輸出線LIO及區域輸入/輸出線桿/LIO上之資料傳送至全域輸入/輸出線GIO。最終，將全域輸入/輸出線GIO上之資料經由對應輸入/輸出端子(未圖示)輸出至外部。Therefore, the data in the memory unit 110 is transmitted from the bit line BL and the bit line/BL to the segment input/output line SIO and the segment input/output line/SIO, respectively, in response to the row selection signal YI. The data on the segment input/output line SIO and the segment input/output line/SIO are respectively transmitted to the area input/output line LIO and the area input/output line lever/LIO in response to the input/output control signal CTR_IO. The data on the area input/output line LIO and the area input/output line/LIO is transferred to the global input/output line GIO by the read driver 150. Finally, the data on the global input/output line GIO is output to the outside via the corresponding input/output terminal (not shown).
與讀取操作相比，在寫入操作中，將自外部接收之資料反向傳送。亦即，經由全域輸入/輸出線GIO而傳送經由輸入/輸出端子輸入之資料，並由寫入驅動器160將其傳送至區域輸入/輸出線LIO及區域輸入/輸出線桿/LIO。接著，將資料傳送至片段輸入/輸出線SIO及片段輸入/輸出線桿/SIO、傳送至位元線BL及位元線桿/BL且最終儲存於記憶體單元110中。In the write operation, the data received from the outside is reversely transmitted in comparison with the read operation. That is, the data input via the input/output terminal is transmitted via the global input/output line GIO, and is transferred by the write driver 160 to the area input/output line LIO and the area input/output line lever/LIO. Next, the data is transferred to the segment input/output line SIO and the segment input/output line bar /SIO, to the bit line BL and the bit line bar /BL, and finally stored in the memory unit 110.
圖2為說明習知半導體記憶體裝置之記憶體庫結構之方塊圖。為解釋便利起見，將作為一實例而描述具有八個記憶體庫之半導體記憶體裝置。2 is a block diagram showing the structure of a memory bank of a conventional semiconductor memory device. For convenience of explanation, a semiconductor memory device having eight memory banks will be described as an example.
參看圖2，半導體記憶體裝置包括第一至第八記憶體庫及對應於各別記憶體庫之列控制電路區域及行控制電路區域及行控制電路區域。將作為一實例而描述第一記憶體庫210、對應於該第一記憶體庫210之第一列控制電路區域230及第一行控制電路區域250。Referring to FIG. 2, the semiconductor memory device includes first to eighth memory banks and column control circuit regions and row control circuit regions and row control circuit regions corresponding to respective memory banks. The first memory bank 210, the first column control circuit region 230 corresponding to the first memory bank 210, and the first row control circuit region 250 will be described as an example.
如上文中描述，第一記憶體庫210包括複數個記憶體單元。第一列控制電路區域230包括用於控制對第一記憶體庫210之列存取的電路，且第一行控制電路區域250包括用於控制對第一記憶體庫210之行存取的電路。As described above, the first memory bank 210 includes a plurality of memory cells. The first column of control circuit regions 230 includes circuitry for controlling access to the first bank of memory 210, and the first row of control circuit regions 250 includes circuitry for controlling access to the first bank of memory 210. .
雖然未具體圖示，但第一列控制電路區域230包括一列解碼器、一電源電壓控制器及一列冗餘控制器。列解碼器解碼自CPU接收之位址以選擇字線WL(見圖1)。電源電壓控制器控制施加至位元線感應放大器120之上拉電源電壓RTO及下拉電源電壓SB。此處，上拉電源電壓RTO及下拉電源電壓SB為基於外部電源電壓及接地電壓而產生之電壓。列冗餘控制器用一連接至正常記憶體單元之字線來替換連接至有缺陷之記憶體單元之另一字線。Although not specifically illustrated, the first column of control circuit regions 230 includes a column of decoders, a supply voltage controller, and a column of redundant controllers. The column decoder decodes the address received from the CPU to select the word line WL (see Figure 1). The power supply voltage controller controls the pull-up supply voltage RTO and the pull-down supply voltage SB applied to the bit line sense amplifier 120. Here, the pull-up power supply voltage RTO and the pull-down power supply voltage SB are voltages generated based on the external power supply voltage and the ground voltage. The column redundancy controller replaces another word line connected to the defective memory cell with a word line connected to the normal memory cell.
雖然未具體圖示，但第一行控制電路區域250包括一行解碼器、一讀取驅動器、一寫入驅動器及一行冗餘控制器。行解碼器解碼自CPU接收之位址以選擇對應記憶體單元之行選擇信號YI(見圖1)。讀取驅動器150(見圖1)根據讀取命令而輸出自記憶體庫讀取之資料。寫入驅動器160(見圖1)根據寫入命令而將自外部接收之資料傳送至對應記憶體庫。行冗餘控制器將對應於有缺陷之記憶體單元之行選擇信號YI替換成對應於正常記憶體單元之另一行選擇信號YI。此處，藉由將對應於有缺陷之記憶體單元之行位址替換成對應於正常記憶體單元之行位址來執行該行冗餘操作。Although not specifically illustrated, the first row of control circuit regions 250 includes a row of decoders, a read driver, a write driver, and a row of redundant controllers. The row decoder decodes the address received from the CPU to select the row select signal YI of the corresponding memory cell (see Figure 1). The read driver 150 (see FIG. 1) outputs the data read from the memory bank in accordance with the read command. The write driver 160 (see FIG. 1) transfers the data received from the outside to the corresponding memory bank in accordance with the write command. The row redundancy controller replaces the row select signal YI corresponding to the defective memory cell with another row select signal YI corresponding to the normal memory cell. Here, the row redundancy operation is performed by replacing the row address corresponding to the defective memory cell with the row address corresponding to the normal memory cell.
第一、第二、第五及第六記憶體庫沿列方向安置成一排。第三、第四、第七及第八記憶體庫亦沿列方向安置成一排。周邊電路區域270安置於第一、第二、第五及第六記憶體庫之集合與第三、第四、第七及第八記憶體庫之集合之間。The first, second, fifth and sixth memory banks are arranged in a row along the column direction. The third, fourth, seventh and eighth memory banks are also arranged in a row along the column direction. The peripheral circuit region 270 is disposed between the set of the first, second, fifth, and sixth memory banks and the set of the third, fourth, seventh, and eighth memory banks.
周邊電路區域270包括用於接收電源電壓、資料、位址、外部命令、時脈信號及其類似者之複數個端子(未圖示)及用於傳送經由該等端子而輸入之信號的複數個傳送線。半導體記憶體裝置基於經由該等端子而輸入之信號來執行各種操作。Peripheral circuit region 270 includes a plurality of terminals (not shown) for receiving power supply voltage, data, address, external commands, clock signals, and the like, and a plurality of signals for transmitting signals input via the terminals Transfer line. The semiconductor memory device performs various operations based on signals input via the terminals.
列控制電路區域及行控制電路區域亦分別包括複數個傳送線。該等傳送線包括電源電壓線、位址線及測試線。包括於列控制電路區域及行控制電路區域中之電路經由電源電壓線而接收電源電壓，經由位址線而接收位址且經由測試線而接收與各種測試操作有關之信號。亦即，第一至第八列控制電路區域中之每一者包括一電源電壓線、一位址線及一測試線，且第一至第八行控制電路區域中之每一者亦包括一電源電壓線、一位址線及一測試線。The column control circuit area and the row control circuit area also respectively include a plurality of transmission lines. The transmission lines include a power voltage line, an address line, and a test line. The circuitry included in the column control circuit region and the row control circuit region receives the supply voltage via the supply voltage line, receives the address via the address line, and receives signals related to various test operations via the test line. That is, each of the first to eighth column control circuit regions includes a power supply voltage line, a bit address line, and a test line, and each of the first to eighth line control circuit regions also includes a Power supply voltage line, one address line and one test line.
隨著半導體記憶體裝置變得高度積體化，正持續努力減小半導體記憶體裝置之晶片大小以改良生產力。實際上，隨著晶片大小減小，每晶圓之晶片數目增加，既而導致生產成本之節約。然而，在半導體記憶體裝置之習知記憶體庫結構中，因為用於每一列控制電路區域及行控制電路區域之電源電壓線、位址線及測試線，所以難以減小晶片大小。As semiconductor memory devices become highly integrated, efforts are continuing to reduce the wafer size of semiconductor memory devices to improve productivity. In fact, as the size of the wafer decreases, the number of wafers per wafer increases, resulting in savings in production costs. However, in the conventional memory bank structure of the semiconductor memory device, it is difficult to reduce the chip size because of the power supply voltage line, the address line, and the test line for each column of the control circuit region and the row control circuit region.
最近，隨著半導體記憶體裝置之容量增加，記憶體庫之數目增加且因此列控制電路區域及行控制電路區域之所需大小亦相應地增加。因此，電源電壓線、位址線及測試線之漸增數目對晶片大小施加負擔。Recently, as the capacity of semiconductor memory devices has increased, the number of memory banks has increased and thus the required size of the column control circuit regions and row control circuit regions has increased accordingly. Therefore, the increasing number of power supply voltage lines, address lines, and test lines imposes a burden on the wafer size.
本發明之例示性實施例係針對相鄰記憶體庫之列控制電路區域彼此相鄰地安置且相鄰記憶體庫之行控制電路區域亦彼此相鄰地安置的半導體記憶體裝置。本發明之例示性實施例亦係針對相鄰列控制電路區域共用預定傳送線且相鄰行控制電路區域亦共用預定傳送線之半導體記憶體裝置。An exemplary embodiment of the present invention is directed to a semiconductor memory device in which adjacent control memory regions are disposed adjacent to each other and adjacent control bank regions of the memory bank are also adjacent to each other. Exemplary embodiments of the present invention are also directed to semiconductor memory devices in which adjacent column control circuit regions share a predetermined transmission line and adjacent row control circuit regions also share a predetermined transmission line.
根據本發明之一態樣，提供一種半導體記憶體裝置，其包括：對應於第一記憶體庫之第一列控制電路區域；對應於第一記憶體庫之第一行控制電路區域；對應於第二記憶體庫且與第一列控制電路區域相鄰地安置之第二列控制電路區域；及對應於第三記憶體庫且與第一行控制電路區域相鄰地安置之第二行控制電路區域。According to an aspect of the present invention, a semiconductor memory device includes: a first column control circuit region corresponding to a first memory bank; a first row control circuit region corresponding to the first memory bank; a second memory bank and a second column of control circuit regions disposed adjacent to the first column of control circuit regions; and a second row of control corresponding to the third memory bank and disposed adjacent to the first row of control circuit regions Circuit area.
根據本發明之另一態樣，提供一種半導體記憶體裝置，其包括：具有複數個記憶體庫之第一庫群組及第二庫群組，該複數個記憶體庫各自具有分別與相鄰記憶體庫之列控制電路區域及行控制電路區域相鄰地安置之列控制電路區域及行控制電路區域；及安置於第一庫群組與第二庫群組之間以在第一及第二庫群組與端子之間傳送信號的周邊電路區域。According to another aspect of the present invention, a semiconductor memory device includes: a first bank group having a plurality of memory banks and a second bank group, each of the plurality of memory banks having respective adjacent to each other The control circuit area and the row control circuit area of the memory bank are adjacently arranged with the control circuit area and the row control circuit area; and are disposed between the first library group and the second library group for the first and the The peripheral circuit area where signals are transmitted between the second bank group and the terminal.
根據本發明之實施例，複數個記憶體庫之列控制電路區域彼此相鄰地安置，且複數個記憶體庫之行控制電路區域亦彼此相鄰地安置。因此，有可能共用原本要求用於各別列控制電路區域及各別行控制電路區域之傳送線。因此有可能對應於傳送線之減少之數目而減小晶片大小。According to an embodiment of the present invention, the plurality of memory bank column control circuit regions are disposed adjacent to each other, and the plurality of memory bank row control circuit regions are also disposed adjacent to each other. Therefore, it is possible to share the transmission lines originally required for the respective column control circuit regions and the respective row control circuit regions. It is therefore possible to reduce the wafer size corresponding to the reduction in the number of transmission lines.
此外，有可能減小周邊電路區域之長度且因此減小周邊電路區域中之傳送線之長度。因此，減小之長度之傳送線可引起減少之負載時間，且因此引起半導體記憶體裝置之較快速的操作。Furthermore, it is possible to reduce the length of the peripheral circuit area and thus the length of the transmission line in the peripheral circuit area. Thus, a reduced length of transmission line can result in reduced load time and, therefore, faster operation of the semiconductor memory device.
本發明之其他目的及優點可根據以下描述來加以理解且參看本發明之實施例而變得顯而易見。Other objects and advantages of the invention will be apparent from the description and appended claims.
圖3為說明根據本發明之一實施例的半導體記憶體裝置之記憶體庫結構之方塊圖。為解釋便利起見，將作為一實例而描述包括八個記憶體庫之半導體記憶體裝置。3 is a block diagram showing the structure of a memory bank of a semiconductor memory device in accordance with an embodiment of the present invention. For convenience of explanation, a semiconductor memory device including eight memory banks will be described as an example.
參看圖3，半導體記憶體裝置包括第一至第八記憶體庫。該等記憶體庫中之每一者具有一列控制電路區域及一行控制電路區域。在下文中，將作為一實例而描述第一記憶體庫310A及與該第一記憶體庫310A相鄰之第二及第五記憶體庫330A及350A。Referring to FIG. 3, the semiconductor memory device includes first to eighth memory banks. Each of the memory banks has a column of control circuit regions and a row of control circuit regions. Hereinafter, the first memory bank 310A and the second and fifth memory banks 330A and 350A adjacent to the first memory bank 310A will be described as an example.
第一記憶體庫310A在列方向上具有一第一列控制電路區域310B並在行方向上具有一第一行控制電路區域310C。相似地，第二記憶體庫330A在列方向上具有一第二列控制電路區域330B並在行方向上具有一第二行控制電路區域330C，且該第五記憶體庫350A在列方向上具有一第五列控制電路區域350B並在行方向上具有一第五行控制電路區域350C。The first memory bank 310A has a first column control circuit region 310B in the column direction and a first row control circuit region 310C in the row direction. Similarly, the second memory bank 330A has a second column control circuit region 330B in the column direction and a second row control circuit region 330C in the row direction, and the fifth memory bank 350A has one in the column direction. The fifth column controls the circuit region 350B and has a fifth row control circuit region 350C in the row direction.
該等列控制電路區域中之每一者包括用於控制對對應記憶體庫之列存取的電路，且該等行控制電路區域中之每一者包括用於控制對對應記憶體庫之行存取的電路。Each of the column control circuit regions includes circuitry for controlling access to a column of corresponding memory banks, and each of the row control circuit regions includes a row for controlling the corresponding memory bank Access to the circuit.
在下文中，將參看圖4及圖5來較詳細地描述該等列控制電路區域及該等行控制電路區域中之每一者。Hereinafter, each of the column control circuit regions and the row control circuit regions will be described in more detail with reference to FIGS. 4 and 5.
圖4為說明圖3中所描述之列控制電路區域之方塊圖。4 is a block diagram showing the area of the column control circuit described in FIG.
如圖示，列控制電路區域中之每一者包括一列解碼器410、一電源電壓控制器420及一列冗餘控制器430。列解碼器410解碼列位址資訊ROW_ADD以選擇字線WL(見圖1)。電源電壓控制器420在活動命令ACT中控制施加至位元線感應放大器120之上拉電源電壓RTO及下拉電源電壓SB(見圖1)。此處，上拉電源電壓RTO及下拉電源電壓SB為基於外部電源電壓及接地電壓而產生之電壓，且可經由共用電源電壓線而傳送，此情況將在下文中加以描述。列冗餘控制器430接收列位址資訊ROW_ADD並輸出列冗餘位址ROW_RADD以用於用一連接至正常記憶體單元之字線來替換連接至有缺陷之記憶體單元之另一字線。As shown, each of the column control circuit regions includes a column of decoders 410, a supply voltage controller 420, and a column of redundant controllers 430. Column decoder 410 decodes column address information ROW_ADD to select word line WL (see Figure 1). The power supply voltage controller 420 controls the pull-up supply voltage RTO and the pull-down supply voltage SB applied to the bit line sense amplifier 120 in the active command ACT (see FIG. 1). Here, the pull-up power supply voltage RTO and the pull-down power supply voltage SB are voltages generated based on the external power supply voltage and the ground voltage, and can be transmitted via the common power supply voltage line, which will be described later. The column redundancy controller 430 receives the column address information ROW_ADD and outputs a column redundancy address ROW_RADD for replacing another word line connected to the defective memory cell with a word line connected to the normal memory cell.
圖5為說明圖3中所描述之行控制電路區域之方塊圖。Figure 5 is a block diagram showing the area of the row control circuit depicted in Figure 3.
如圖示，行控制電路區域中之每一者包括一行解碼器510、一讀取驅動器520、一寫入驅動器530及一行冗餘控制器540。行解碼器510解碼行位址資訊COL_ADD以選擇對應記憶體單元之行選擇信號YI(見圖1)。讀取驅動器150(見圖1)根據讀取命令而將自記憶體庫讀取之資料(經由區域I/O線LIO)輸出至全域I/O線GIO。寫入驅動器160(見圖1)根據寫入命令而將經由全域I/O線GIO而自外部接收之資料傳送至對應記憶體庫(經由區域I/O線LIO)。行冗餘控制器將對應於有缺陷之記憶體單元之行位址資訊COL_ADD替換成對應於正常記憶體單元的行冗餘位址資訊COL_RADD。此處，藉由將對應於有缺陷之記憶體單元之行位址替換成對應於正常記憶體單元之行位址來執行該行冗餘操作。As shown, each of the row control circuit regions includes a row of decoders 510, a read driver 520, a write driver 530, and a row of redundancy controllers 540. The row decoder 510 decodes the row address information COL_ADD to select the row select signal YI of the corresponding memory cell (see Fig. 1). The read driver 150 (see FIG. 1) outputs the data read from the memory bank (via the area I/O line LIO) to the global I/O line GIO in accordance with the read command. The write driver 160 (see FIG. 1) transfers the data received from the outside via the global I/O line GIO to the corresponding memory bank (via the area I/O line LIO) in accordance with the write command. The row redundancy controller replaces the row address information COL_ADD corresponding to the defective memory cell with the row redundancy address information COL_RADD corresponding to the normal memory cell. Here, the row redundancy operation is performed by replacing the row address corresponding to the defective memory cell with the row address corresponding to the normal memory cell.
第一列控制電路區域310B及第五列控制電路區域350B彼此相鄰地安置，且第一行控制電路區域310C及第二行控制電路區域330C彼此相鄰地安置。因此，第一列控制電路區域310B及第五列控制電路區域350B可共用一傳送線，且第一行控制電路區域310C及第二行控制電路區域330C亦可共用一傳送線。此處，該共用傳送線可包括一電源電壓線、一位址線、一測試線及其類似者。The first column control circuit region 310B and the fifth column control circuit region 350B are disposed adjacent to each other, and the first row control circuit region 310C and the second row control circuit region 330C are disposed adjacent to each other. Therefore, the first column control circuit region 310B and the fifth column control circuit region 350B can share a transmission line, and the first row control circuit region 310C and the second row control circuit region 330C can also share a transmission line. Here, the common transmission line may include a power voltage line, a bit line, a test line, and the like.
在一習知半導體記憶體裝置中，出於結構原因，複數個列控制電路區域及複數個行控制電路區域中之每一者需要對應的電源電壓線、位址線及測試線。然而，在根據本發明之實施例的半導體記憶體裝置中，提供至記憶體庫之列控制電路區域及行控制電路區域分別與提供至相鄰於該記憶體庫之另一記憶體庫的列控制電路區域及行控制電路區域相鄰地安置。因此，電源電壓線、位址線及測試線可由相鄰列控制電路區域或相鄰行控制電路區域共用。因此，有可能減少傳送線之數目且因此減小半導體記憶體裝置之晶片大小。In a conventional semiconductor memory device, for structural reasons, each of a plurality of column control circuit regions and a plurality of row control circuit regions requires a corresponding supply voltage line, address line, and test line. However, in the semiconductor memory device according to the embodiment of the present invention, the column control circuit region and the row control circuit region provided to the memory bank and the column provided to another memory bank adjacent to the memory bank are respectively provided. The control circuit area and the row control circuit area are disposed adjacent to each other. Therefore, the power supply voltage line, the address line, and the test line can be shared by adjacent column control circuit regions or adjacent row control circuit regions. Therefore, it is possible to reduce the number of transmission lines and thus the wafer size of the semiconductor memory device.
隨著開發半導體記憶體裝置以達成大容量，自外部施加之位址之數目相應地增加。因此，現今進行位址之預解碼以有效地處理此大量之位址。半導體記憶體裝置可包括一用於預解碼之電路，該電路安置於所謂的"交叉電路區域"上。As semiconductor memory devices are developed to achieve large capacity, the number of addresses applied from outside is correspondingly increased. Therefore, pre-decoding of the address is performed today to efficiently process this large number of addresses. The semiconductor memory device can include a circuit for pre-decoding that is placed on a so-called "cross circuit region."
在下文中，在描述該交叉電路區域之前將描述一上部庫群組及一下部庫群組。上部庫群組指安置於周邊電路區域370之上方的電路。亦即，該上部庫群組包括第一記憶體庫310A、第二記憶體庫330A、第五記憶體庫350A及第六記憶體庫以及對應於該等記憶體庫之列控制電路區域及行控制電路區域。此外，上部庫群組包括一上部交叉電路區域390，在該上部交叉電路區域390中，列控制電路區域及行控制電路區域交叉。In the following, an upper library group and a lower library group will be described before describing the cross circuit area. The upper bank group refers to a circuit disposed above the peripheral circuit region 370. That is, the upper library group includes a first memory bank 310A, a second memory bank 330A, a fifth memory bank 350A, and a sixth memory bank, and a column control circuit region and row corresponding to the memory banks. Control circuit area. In addition, the upper bank group includes an upper cross circuit region 390 in which the column control circuit regions and the row control circuit regions intersect.
下部庫群組指安置於周邊電路區域370之下方的電路。亦即，下部庫群組包括第三、第四、第七及第八記憶體庫以及對應於該等記憶體庫之列控制電路區域及行控制電路區域。此外，下部庫群組可包括一下部交叉電路區域，在該下部交叉電路區域中，列控制電路區域及行控制電路區域交叉。The lower bank group refers to a circuit disposed below the peripheral circuit region 370. That is, the lower bank group includes the third, fourth, seventh, and eighth memory banks and the column control circuit regions and row control circuit regions corresponding to the memory banks. Further, the lower bank group may include a lower cross circuit region in which the column control circuit region and the row control circuit region intersect.
如圖3中所展示，記憶體庫中之每一者可經堆疊以減小周邊電路區域370之長度。有可能減小周邊電路區域370中之傳送線之長度。周邊電路區域370中之傳送線包括一用於在端子(未圖示)與包括於上部庫群組及下部庫群組中之電路之間傳送資料的全域輸入/輸出線(GIO)。全域輸入/輸出線長度之減小減少用於資料傳送之負載時間，既而改良操作速度。As shown in FIG. 3, each of the memory banks can be stacked to reduce the length of the peripheral circuit region 370. It is possible to reduce the length of the transmission line in the peripheral circuit region 370. The transmission line in peripheral circuit area 370 includes a global input/output line (GIO) for transferring data between terminals (not shown) and circuits included in the upper bank group and the lower bank group. The reduction in the length of the global input/output line reduces the load time for data transfer, which in turn improves the operating speed.
如上文中描述，半導體記憶體裝置可包括上部交叉電路區域390及下部交叉電路區域。出於說明目的，將在下文中作為一實例而描述上部交叉電路區域390。圖6為說明圖3中所描述之交叉電路區域之方塊圖。As described above, the semiconductor memory device can include an upper cross circuit region 390 and a lower cross circuit region. For purposes of illustration, the upper crossover circuit region 390 will be described below as an example. Figure 6 is a block diagram showing the cross circuit area depicted in Figure 3.
如圖示，上部交叉電路區域390包括一預解碼器600及一庫控制器620。該預解碼器600藉由預解碼位址資訊ADD而產生列位址資訊ROW_ADD及行位址資訊COL_ADD。庫控制器620回應於位址資訊ADD而產生一用於控制包括於上部庫群組中之記憶體庫的庫活動信號BANK_EN。亦即，回應於自上部交叉電路區域390輸出之庫啟動信號(未圖示)而啟用包括於上部庫群組中之記憶體庫。包括於上部庫群組中之列控制電路區域及行控制電路區域根據由上部交叉電路區域390預解碼之位址而操作。下部交叉電路區域亦可包括類似於上部交叉電路區域之電路的電路。As shown, the upper cross circuit area 390 includes a predecoder 600 and a library controller 620. The predecoder 600 generates column address information ROW_ADD and row address information COL_ADD by pre-decoding the address information ADD. The library controller 620 generates a library activity signal BANK_EN for controlling the memory banks included in the upper bank group in response to the address information ADD. That is, the memory bank included in the upper bank group is enabled in response to a bank enable signal (not shown) output from the upper cross circuit region 390. The column control circuit regions and row control circuit regions included in the upper bank group operate in accordance with the address pre-decoded by the upper cross circuit region 390. The lower cross circuit area may also include circuitry similar to the circuitry of the upper cross circuit area.
如圖3中所展示，半導體記憶體裝置包括一個上部交叉電路區域390及一個下部交叉電路區域。返回參看圖2，習知半導體記憶體裝置包括分別用於上部庫群組之此等區域(未圖示)中之兩者及用於下部庫群組之此等區域(未圖示)中之兩者。因此，習知半導體記憶體裝置包括至少四個群組之用於傳送位址之傳送線。然而，對於根據本實施例之半導體記憶體裝置而言，上部交叉電路區域390經由對應於上部庫群組之四個記憶體庫的共用傳送線而接收位址。類似地，下部交叉電路區域經由對應於四個記憶體庫之共用傳送線而接收位址。亦即，該半導體記憶體裝置僅需要分別對應於上部庫群組及下部庫群組的傳送線群組中之兩者。As shown in FIG. 3, the semiconductor memory device includes an upper crossover circuit region 390 and a lower crossover circuit region. Referring back to FIG. 2, a conventional semiconductor memory device includes two of the regions (not shown) for the upper bank group and the regions (not shown) for the lower bank group. Both. Therefore, conventional semiconductor memory devices include at least four groups of transmission lines for transmitting addresses. However, with the semiconductor memory device according to the present embodiment, the upper cross circuit region 390 receives the address via the common transfer line corresponding to the four memory banks of the upper bank group. Similarly, the lower cross circuit area receives the address via a common transmission line corresponding to the four memory banks. That is, the semiconductor memory device only needs to correspond to both of the group of transmission lines of the upper bank group and the lower bank group.
此外，交叉電路區域之所需數目亦自四減少至二，且因此傳送線(諸如，電源電壓線)之所需數目亦可減少。因此，隨著交叉電路區域之數目減少且因此傳送線之數目亦減少，有可能進一步減小半導體記憶體裝置之晶片大小。In addition, the required number of crossover circuit regions is also reduced from four to two, and thus the required number of transmission lines (such as power supply voltage lines) can also be reduced. Therefore, as the number of intersecting circuit regions is reduced and thus the number of transmission lines is also reduced, it is possible to further reduce the wafer size of the semiconductor memory device.
有可能上部庫群組之四個列控制電路區域共用每一可能的傳送線。在此狀況下，傳送線可跨越上部交叉電路區域390而安置。相似地，上部庫群組之四個行控制電路區域可共用每一可能的傳送線，且下部庫群組之列控制電路區域及行控制電路區域亦可共用每一可能的傳送線。It is possible that the four column control circuit regions of the upper bank group share every possible transmission line. In this case, the transfer line can be placed across the upper cross circuit region 390. Similarly, the four row control circuit regions of the upper bank group can share each possible transmission line, and the control circuit region and the row control circuit region of the lower bank group can also share every possible transmission line.
隨著半導體記憶體裝置變得高度積體化且記憶體庫之數目相應地增加，上文中描述的半導體記憶體裝置之組態可高度適用於減小半導體記憶體裝置之晶片大小。晶片大小之此減小允許每晶圓之晶片數目增加，既而導致生產成本之節約。As semiconductor memory devices become highly integrated and the number of memory banks increases accordingly, the configuration of the semiconductor memory devices described above can be highly adapted to reduce the wafer size of semiconductor memory devices. This reduction in wafer size allows an increase in the number of wafers per wafer, resulting in savings in production costs.
如上文中描述，在根據該等實施例之半導體記憶體裝置中，相鄰記憶體庫之列控制電路區域彼此相鄰地安置且相鄰記憶體庫之行控制電路區域亦彼此相鄰地安置以共用傳送線。因此，有可能減少傳送線之所需數目，藉此減小高度積體化之半導體記憶體裝置的晶片大小。As described above, in the semiconductor memory device according to the embodiments, the column control circuit regions of the adjacent memory banks are disposed adjacent to each other and the row control circuit regions of the adjacent memory banks are also disposed adjacent to each other. Shared transmission line. Therefore, it is possible to reduce the required number of transfer lines, thereby reducing the wafer size of the highly integrated semiconductor memory device.
記憶體庫亦經堆疊以減小周邊電路區域之大小。因此，有可能進一步減小半導體記憶體裝置之晶片大小並保證較快速之電路操作。The memory banks are also stacked to reduce the size of the peripheral circuit area. Therefore, it is possible to further reduce the wafer size of the semiconductor memory device and ensure faster circuit operation.
此外，藉由減小晶片大小，有可能增加每晶圓之晶片數目，既而導致生產成本之節約。In addition, by reducing the size of the wafer, it is possible to increase the number of wafers per wafer, resulting in savings in production costs.
舉例而言，雖然在上文中描述之實施例中已將列控制電路區域及行控制電路區域描述成共用電源電壓線、位址線及測試線，但亦有可能其共用其他可能的傳送線。For example, although the column control circuit region and the row control circuit region have been described as common supply voltage lines, address lines, and test lines in the embodiments described above, it is also possible that they share other possible transmission lines.
此外，雖然在上文中描述之實施例中已將安置於周邊電路區域370中之全域輸入/輸出線(GIO，未圖示)之長度描述成待加以縮短，但有可能周邊電路區域中之其他線之長度亦因為該周邊電路區域自身之長度經縮短(由於記憶體庫之堆疊所致)而得以縮短。Further, although the length of the global input/output line (GIO, not shown) disposed in the peripheral circuit region 370 has been described as being to be shortened in the embodiment described above, it is possible that other in the peripheral circuit region The length of the line is also shortened because the length of the peripheral circuit area itself is shortened (due to the stacking of the memory banks).
此外，記憶體庫之列控制電路區域及行控制電路區域的位置可根據設計而不同。Further, the positions of the control circuit area and the row control circuit area of the memory bank may vary depending on the design.
雖然已關於特定實施例而描述本發明，但對於熟習此項技術者而言將顯而易見的是，可在不脫離如由隨附[申請專利範圍]中所界定之本發明之精神及範疇的情況下進行各種改變及修改。Although the present invention has been described in terms of specific embodiments, it will be apparent to those skilled in the art that the invention may be practiced without departing from the spirit and scope of the invention as defined in the appended claims. Make various changes and modifications.
110．．．記憶體單元110. . . Memory unit
120．．．位元線感應放大器120. . . Bit line sense amplifier
130．．．行選擇器130. . . Row selector
140．．．輸入/輸出開關140. . . Input/output switch
150．．．讀取驅動器150. . . Read drive
160．．．寫入驅動器160. . . Write driver
210．．．第一記憶體庫210. . . First memory bank
230．．．第一列控制電路區域230. . . First column control circuit area
250．．．第一行控制電路區域250. . . First line control circuit area
270．．．周邊電路區域270. . . Peripheral circuit area
310A．．．第一記憶體庫310A. . . First memory bank
310B．．．第一列控制電路區域310B. . . First column control circuit area
310C．．．第一行控制電路區域310C. . . First line control circuit area
330A．．．第二記憶體庫330A. . . Second memory bank
330B．．．第二列控制電路區域330B. . . Second column control circuit area
330C．．．第二行控制電路區域330C. . . Second line control circuit area
350A．．．第五記憶體庫350A. . . Fifth memory bank
350B．．．第五列控制電路區域350B. . . Fifth column control circuit area
350C．．．第五行控制電路區域350C. . . Fifth line control circuit area
370．．．周邊電路區域370. . . Peripheral circuit area
390．．．上部交叉電路區域390. . . Upper cross circuit area
410．．．列解碼器410. . . Column decoder
420．．．電源電壓控制器420. . . Power supply voltage controller
430．．．列冗餘控制器430. . . Column redundancy controller
510．．．行解碼器510. . . Row decoder
520．．．讀取驅動器520. . . Read drive
530．．．寫入驅動器530. . . Write driver
540．．．行冗餘控制器540. . . Row redundant controller
600．．．預解碼器600. . . Predecoder
620．．．庫控制器620. . . Library controller
ACT．．．活動命令ACT. . . Active command
ADD．．．位址資訊ADD. . . Address information
BANK_EN．．．庫活動信號BANK_EN. . . Library activity signal
BL．．．位元線BL. . . Bit line
/BL．．．位元線桿/BL. . . Bit line pole
C1．．．單元電容器C1. . . Unit capacitor
COL_ADD．．．行位址資訊COL_ADD. . . Row address information
COL_RADD．．．行冗餘位址資訊COL_RADD. . . Row redundant address information
CTR_IO．．．輸入/輸出控制信號CTR_IO. . . Input/output control signal
GIO．．．全域輸入/輸出線GIO. . . Global input/output line
LIO．．．區域輸入/輸出線LIO. . . Area input/output line
/LIO．．．區域輸入/輸出線桿/LIO. . . Zone input/output pole
ROW_ADD．．．列位址資訊ROW_ADD. . . Column address information
ROW_RADD．．．列冗餘位址ROW_RADD. . . Column redundant address
RTO．．．上拉電源電壓RTO. . . Pull-up supply voltage
SB．．．下拉電源電壓SB. . . Pull down supply voltage
SIO．．．片段輸入/輸出線SIO. . . Fragment input/output line
/SIO．．．片段輸入/輸出線桿/SIO. . . Fragment input/output pole
T1．．．單元電晶體T1. . . Unit transistor
WL．．．字線WL. . . Word line
YI．．．行選擇信號YI. . . Row selection signal
圖1為說明典型半導體記憶體裝置之讀取及寫入操作之電路圖。1 is a circuit diagram illustrating read and write operations of a typical semiconductor memory device.
圖2為說明典型半導體記憶體裝置之記憶體庫結構之方塊圖。2 is a block diagram showing the structure of a memory bank of a typical semiconductor memory device.
圖3為說明根據本發明之一實施例的半導體記憶體裝置之記憶體庫結構之方塊圖。3 is a block diagram showing the structure of a memory bank of a semiconductor memory device in accordance with an embodiment of the present invention.
圖4為說明圖3中所描述之列控制電路區域之方塊圖。4 is a block diagram showing the area of the column control circuit described in FIG.
圖5為說明圖3中所描述之行控制電路區域之方塊圖。Figure 5 is a block diagram showing the area of the row control circuit depicted in Figure 3.
圖6為說明圖3中所描述之交叉電路區域之方塊圖。Figure 6 is a block diagram showing the cross circuit area depicted in Figure 3.
310A．．．第一記憶體庫310A. . . First memory bank
310B．．．第一列控制電路區域310B. . . First column control circuit area
310C．．．第一行控制電路區域310C. . . First line control circuit area
330A．．．第二記憶體庫330A. . . Second memory bank
330B．．．第二列控制電路區域330B. . . Second column control circuit area
330C．．．第二行控制電路區域330C. . . Second line control circuit area
350A．．．第五記憶體庫350A. . . Fifth memory bank
350B．．．第五列控制電路區域350B. . . Fifth column control circuit area
350C．．．第五行控制電路區域350C. . . Fifth line control circuit area
370．．．周邊電路區域370. . . Peripheral circuit area
390．．．上部交叉電路區域390. . . Upper cross circuit area
Claims (8)
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| KR1020080112700A KR100996187B1 (en) | 2008-01-18 | 2008-11-13 | Architecture of high integrated semiconductor memory apparatus |
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| KR20200109030A (en) * | 2019-03-12 | 2020-09-22 | 에스케이하이닉스 주식회사 | Semiconductor apparatus |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142492A (en) * | 1989-10-05 | 1992-08-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US20020105849A1 (en) * | 2001-02-06 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with improved data propagation characteristics of a data bus |
| US20030202404A1 (en) * | 2001-03-21 | 2003-10-30 | Matrix Semiconductor, Inc. | Memory device with row and column decoder circuits arranged in a checkboard pattern under a plurality of memory arrays |
| US20040057309A1 (en) * | 2001-06-04 | 2004-03-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5142492A (en) * | 1989-10-05 | 1992-08-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| US20020105849A1 (en) * | 2001-02-06 | 2002-08-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with improved data propagation characteristics of a data bus |
| US20030202404A1 (en) * | 2001-03-21 | 2003-10-30 | Matrix Semiconductor, Inc. | Memory device with row and column decoder circuits arranged in a checkboard pattern under a plurality of memory arrays |
| US20040057309A1 (en) * | 2001-06-04 | 2004-03-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| TW594775B (en) * | 2001-06-04 | 2004-06-21 | Toshiba Corp | Semiconductor memory device |
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| KR100996187B1 (en) | 2010-11-24 |
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