TWI401782B - 半導體裝置及多層配線基板 - Google Patents

半導體裝置及多層配線基板 Download PDF

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Publication number
TWI401782B
TWI401782B TW096131781A TW96131781A TWI401782B TW I401782 B TWI401782 B TW I401782B TW 096131781 A TW096131781 A TW 096131781A TW 96131781 A TW96131781 A TW 96131781A TW I401782 B TWI401782 B TW I401782B
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Taiwan
Prior art keywords
wiring
insulator
wiring layer
film
layer
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TW096131781A
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English (en)
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TW200830514A (en
Inventor
Tadahiro Ohmi
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Univ Tohoku Nat Univ Corp
Found Advancement Int Science
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Publication of TW200830514A publication Critical patent/TW200830514A/zh
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Publication of TWI401782B publication Critical patent/TWI401782B/zh

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    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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Description

半導體裝置及多層配線基板
本發明係關於具有IC、大型積體電路元件(LSI)等之多層配線構造的一種半導體裝置；且關於在包含半導體、導體、絕緣體至少其中之一的基板上具有多層配線構造的一種多層配線基板。
於IC或LSI等之半導體裝置中，隨著其中的各種元件趨向集聚化，配線長度與面積逐漸增加；為因應此種情形，業者採用多層配線構造。另外，於該等半導體裝置中，為因應進一步的高密度化，故配線圖案不斷細微化，且配線剖面積變小。另一方面，為實現高速動作，流到配線之電流有增加的傾向。亦即，於該等半導體裝置中，流到各配線之電流的密度有加大的傾向。
由於各配線之電流密度的增加將導致各種問題，首先，會使焦耳熱之產生量加大，且配線狀態變差等，因此有必要將配線所產生的熱有效率地去除。
又，此種半導體裝置的動作速度，由於配線的電阻值R和起因於配線的電容C二者之乘積，亦即RC時間常數而受到大幅限制。因此，欲將半導體裝置的動作速度提高時，不僅必須降低配線的電阻值R，也有必要減少電容C。
上述問題不僅存在於個別的多層配線構造半導體晶片，也存在於搭載有半導體晶片之半導體封裝體的多層配線構造上。並存在於具有安裝著許多半導體裝置的多層配線構造的基板(所謂印刷電路板等)；或者其他多層配線基板。亦即，其原因在於：即便於個別的半導體晶片中，將配線的熱去除，或使配線之電阻值R、電容C降低，以加快動作速度，若封裝體或配線基板之多層配線構造無法完善因應所產生的熱，或者若電阻值R、電容C較大，則整體而言，動作速度仍變慢，由於熱所形成之問題仍無法避免。
為解決上述問題，以往有許多發明提出多層配線構造。其中，就層間絕緣膜而言，採用SiO2 、Si3 N4 或聚醯亞胺等之高分子材料，設置熱通孔(thermal via)，用以將熱傳導係數大於層間絕緣膜之絕緣物(AlN)不僅充填到電連接層間的穿通孔，也充填到形成於層間絕緣膜的貫穿孔。藉此，以進行層間之熱傳導(例如請參照，專利文獻1：特開平9－129725號公報)。
又，以往所提案之其他多層配線構造中，有些為了使訊號傳送速度進一步加快，基於令層間絕緣部低介電常數化之目的，而將空氣利用作層間絕緣(例如請參照，專利文獻2：WO00/74135)。
專利文獻1：特開平9－129725號公報專利文獻2：WO00/74135
專利文獻1及2所提案之多層配線構造中，就熱通孔的材料而言，採用熱傳導係數較大之AlN(與Si3 N4 )。然而，由於AlN的介電常數非常大，達8.7(Si3 N4 係7.9)，因此即使於層間絕緣採用低介電常數的物質，仍會有使得平均介電常數加大的問題點。
因此，本發明之目的為：提供一種多層配線構造，其提供低介電常數的熱通孔，而能同時實現層間絕緣之低介電常數化、與高熱傳導係數化。
本發明之另一目的為：提供一種多層配線基板，其中，多層配線構造之層間絕緣可同時實現低介電常數化、及高熱傳導係數化。
本發明之又另一目的為：提供一種具有多層配線構造之半導體裝置，其中，該多層配線構造可同時實現低介電常數化、及高熱傳導係數化。
以下，記載本發明之態樣。
(第1態樣)依本發明之第1態樣，提供一種多層配線基板，於至少包含半導體、導體、絕緣體的其中之一的基板上具有多層配線構造；其特徵為：在該多層配線構造中的第1配線層及其上的第2配線層之間，夾設介電常數係平均2.5以下的氣體或絕緣物。又，在該第1配線層的至少一配線及該第2配線層的至少一配線之間，設置導電連接體；更在該第1配線層的既定配線及該第2配線層的既定配線之間，設置介電常數係5以下的絕緣物熱傳導體。
(第2態樣)在上述第1態樣之多層配線基板中，於該第1配線層及該第2配線層之間夾設絕緣物時，關於熱傳導係數較佳為，該絕緣物熱傳導體之值比該絕緣物之值更大。
(第3態樣)在上述第2態樣所形成多層配線基板中，夾設於該第1配線層及該第2配線層之間的絕緣物，可包含一種含碳及氟的材料層。此材料層較佳為，例如以氟碳層為主體之絕緣層。
(第4態樣)在上述第2態樣所形成多層配線基板中，夾設於該第1配線層及該第2配線層之間的絕緣物，可包含一種含碳及氫的材料層。此材料層較佳為，例如以碳氫化合物層為主體之絕緣層，或者混有氟碳層與碳氫化合物層之絕緣層。
(第5態樣)於該第1~第4之任一個態樣所形成多層配線基板中，該絕緣物熱傳導體可包含一種含矽、碳及氮的材料，例如包含SiCN。
(第6態樣)依本發明之第6態樣，提供一種半導體裝置，於形成有複數之半導體元件的基板上具有多層配線構造；其特徵為：在該多層配線構造中的第1配線層及其上的第2配線層之間，夾設介電常數係平均2.5以下的氣體或絕緣物。又，在該第1配線層的至少一配線及該第2配線層的至少一配線之間，設置所希望之導電連接體；更在該第1配線層的既定配線及該第2配線層的既定配線之間，設置介電常數係5以下的絕緣物熱傳導體。
(第7態樣)在上述第6態樣所形成半導體裝置中，於該第1配線層及該第2配線層之間夾設絕緣物時，關於熱傳導係數較佳為，該絕緣物熱傳導體之值比該絕緣物之值更大。
(第8態樣)在上述第7態樣所形成半導體裝置中，夾設於該第1配線層及該第2配線層之間的絕緣物，可包含一種含碳及氟的材料層。此材料層較佳為，例如以氟碳層為主體之絕緣層。
(第9態樣)在上述第7態樣所形成半導體裝置中，夾設於該第1配線層及該第2配線層之間的絕緣物，可包含一種含碳及氫的材料層。此材料層較佳為，例如以碳氫化合物層為主體之絕緣層，或者混有氟碳層與碳氫化合物層之絕緣層。
(第10態樣)於該第6~第9之任一個態樣所形成半導體裝置中，該絕緣物熱傳導體可包含一種含矽、碳及氮的材料，例如含SiCN。
依本發明，在該第1配線層及該第2配線層之間，夾設介電常數係平均2.5以下的氣體或絕緣物之同時，採用介電常數在5以下的絕緣物熱傳導體，以形成熱通孔。藉此，可實現低介電常數且高熱傳導係數之多層配線構造。
 實施發明之最佳形態
以下參照圖式，詳細說明本發明的實施形態。
依本發明之第1實施形態的半導體裝置，於包含半導體區域之基板上，至少具有第1配線層，以及其上之第2配線層。例如，如圖1所示，可在形成於矽基板100上之7層配線層101~107間，與最下層之配線層101與矽基板100間，以及最上層之配線層107與散熱裝置108間配置層間絕緣膜109~116。圖1中，為方便說明起見，配線層與層間絕緣膜二者的界線係省略其圖示。又，顯示於各配線層之左側的數值、顯示於各層間絕緣膜之右側的數值，係分別表示層厚、膜厚之例。而顯示於配線層101之下側、配線層106之上側的數值，係分別表示配線寬、配線間隔之例。
在此，所謂半導體裝置，係將電路或電子元件高密度地構成到1片基板上；亦即，意味著使用電晶體、電阻器、電容器等所集聚化而成，具體而言，係IC或LSI。
就基板而言，除形成有半導體元素之矽基板以外，也可利用例如金屬基板、一般半導體基板、玻璃或塑膠的絕緣基板，或者覆蓋絕緣膜以後，進一步覆蓋半導體膜之金屬基板、覆蓋半導體膜之絕緣基板等。
為了使此基板可作為導電性基板使用，較佳之實施型態為，將至少構成表面及/或背面之材料(Si或GaAs等半導體材料)的導電度設定在10－8 (Ω．cm)－1 以上。又，對於該基板之表面及/或背面，較佳為，藉由在其上製造各種元件等，盡可能使其呈現平坦面。就金屬而言，較佳為，Ta、Ti、W、Co、Mo、Hf、Ni、Zr、Cr、V、Pd、Au、Pt、Mn、Nb、Cu、Ag或Al。就半導體而言，較佳為，Si、Ge、GaAs或C(金剛石)。就覆蓋半導體膜之絕緣體而言，較佳為，SiO2(二氧化矽)、SiN(氮化矽)、AlN(氮化鋁)、Al2O3(氧化鋁)，或者由SiOXNY所構成之混合膜。就覆蓋絕緣膜以後，進一步覆蓋半導體膜之金屬而言，較佳為，Ta、Ti、W、Co、Mo、Hf、Ni、Zr、Cr、V、Pd、Au、Pt、Mn、Nb、Cu、Ag或Al。
當半導體裝置於包含半導體區域的基板上至少具有2個配線層時，可利用金屬配線或多晶矽、多晶矽化金屬(polycide)作為第1配線層及第2配線層的配線。使用於此配線之金屬薄膜，係藉由在高真空狀態下進行金屬蒸鍍或濺鍍，或者在高溫狀態下採用金屬氯化物等之CVD法所製造，俾於該配線與半導體表面間不會形成氧化物般之中間層。
就金屬薄膜之材料而言，可舉例如下。
矽半導體裝置中，例如有Al、Cr、W、Mo、Cu、Ag、Au、Ti、WSi2 、MoSi2 、TiSi2 、以該等材料為主成分之合金(如Cu－Mg合金、Cu－Nb合金、Cu－Al合金)，或者該等材料呈現層狀疊層之配線(如Al－Ti－Al、TiN－Al合金－TiN、W－Al合金－W)等。又，於GaAs半導體裝置中，則有Au、Al、Ni、Pt，或者以此等為主成分之合金。
尤其，因為以下的理由，於矽半導體裝置中，業者很著重採用Al、Cu、Ag、Au，或者以此等材料為主成分之合金。
(A)與電極材料應形成歐姆接觸；(B)與絕緣膜(SiO2 、Si3 N4 、Al2 O3 等)之貼緊度應良好；(C)導電率應較大；(D)加工應容易，而加工精度應較高；(E)化學性．物理性、甚至電性皆應穩定。
又，依本實施形態之半導體裝置中，於第1配線層及第2配線層之間具有電性絕緣的第1絕緣物(層間絕緣膜)。又，當基板與第1配線層間或者配線層與散熱裝置108間，具有3層以上之配線層時，於該等配線層間也設置層間絕緣膜，係屬當然。
如圖2所示，第1絕緣物包含底層201，以及形成於其上之CF(氟碳)膜202。
底層係由例如SiCN膜、Si3 N4 膜、SiCO膜、SiO2 膜、CH膜，或者此等膜之組合所構成的多層膜。而該等膜之介電常數在4以下；尤其，SiCO膜之介電常數在3以下，CH膜之介電常數在2.5以下。
CF膜202係藉由CVD所形成，例如，以氟碳化物氣體作為反應氣體，將其藉Xe或Kr電漿分解。或者，CF膜202亦可藉由另一種CVD所形成，將氟碳化物氣體藉Ar電漿分解。甚至，也可藉由依序進行該等CVD，製造為2層構造之CF膜(圖2之202a及202b)。又，相較於以Xe或Kr電漿所形成之CF膜，由Ar電漿所形成之CF膜具有較低的介電常數。但無論哪一種CF膜，其介電常數係在2以下，且亦有可能低到1.7左右。
就氟碳化物氣體而言，可採用通式Cn F2n (但n係2~8之整數)或Cn F2n －2 (n係2~8之整數)所表示不飽和脂肪族氟化物。尤佳為，可採用如下以通式C5 F8 所示之2類氟碳化物：一為包含八氟戊炔、八氟戊二烯、八氟環戊烯、八氟甲基丁二烯、八氟甲基丁炔、氟環丙烯或氟環丙烷之氟化碳；一為包含氟環丁烯或氟環丁烷之氟化碳等。
例如，將CF膜製造為2層構造時，藉Xe或Kr電漿，形成第1CF膜5~10nm；接著，藉Ar電漿，形成第2CF膜280~500nm。
又，形成CF膜以後，較佳之實施形態為，更在徐冷後，將氮氣導入Ar氣體所形成之電漿，以產生氮自由基(亦可僅藉由氮氣體，使電漿產生，而產生氮自由基)；而且，可藉由將CF膜之表面(厚1~5nm、較佳為2~3nm)氮化，以減少從該CF膜之表面脫氣的現象。藉此，可消除膜剝落，且可將介電常數控制於1.7~2.2之範圍。
又，徐冷時，於惰性氣體之環境氣體下，較佳係在1Torr(約133Pa)左右的減壓環境下進行。
另外，也可用CH膜，以取代CF膜，或者疊層於CF膜。CH膜可如上述，採較低之介電常數，設於2.5以下。CH膜係將C2 H2 或C2 H4 般之Cx Hy 氣體，與Ar等一起導入且電漿化，而以CVD成膜。
進而，層間絕緣膜可採由Si3 N4 膜、SiCN膜、SiCO膜、CH膜，或者該等膜之組合所構成的多層膜，且可形成於所形成之CF膜及/或CH膜的頂面。
如上述所構成之層間絕緣膜的介電常數，平均而言(整體而言)，係2.5以下而形成。
又，CH膜之熱傳導係數係0.13~0.21(W/mK)，比SiO2 之10.7~6.2(W/mK)更小2進位。此熱傳導之惡劣程度係藉由後述之熱通孔而得以解除。
於層間絕緣膜形成貫穿孔(未圖示)，用以將位於層間絕緣膜之上下的配線層的配線間(例如第1配線層及第2配線層二者的配線間)加以電性、熱性接觸。該貫穿孔又稱介層洞，一般而言，可採用光蝕刻方法而製造。其孔徑係依據位於上下位置的配線寬度而決定。該貫穿孔作為穿通孔使用，以電性連接配線間，或者作為模擬孔使用，以熱性連接配線間。
穿通孔(導電連接體)係在形成於層間絕緣膜之貫穿孔中，將導電物質加以充填而成。穿通孔之功能為：藉由第1絕緣物，使得電性分離而位於上下之配線間形成導通。因此，穿通孔僅限於設置在構成電路之必要位置上，不可設於任意位置。又，穿通孔可藉由公知的方法而形成。而且，穿通孔不僅可傳達電訊號，也可傳熱。
模擬孔(絕緣性熱傳導體)係在形成於層間絕緣膜之貫穿孔中，將第2絕緣物加以充填而成；而該第2絕緣物具有比第1絕緣物更大之熱傳導係數。模擬孔於藉由第1絕緣物而電性分離且位於上下之配線間，比起第1絕緣物，可將熱從一邊之配線往另一邊之配線更快速地傳達。因此，模擬孔又稱熱通孔。藉由設置熱通孔，當某一配線之溫度上升時，則迅速地將熱往其他配線傳達，且促進散熱，可抑制各配線產生異常的溫度上升。由於模擬孔係絕緣物，並不會傳達電訊號。從而，模擬孔可設置於任意位置。
就第2絕緣物而言，採用SiCN。SiCN之熱傳導係數高達100 W/mK左右，且即使使用CF膜作為層間絕緣膜，仍可實現充分之熱傳導。又，SiCN之介電常數係5以下(4.0左右)，且無須使層間絕緣膜的平均介電常數大幅提高。
SiCN例如可藉由採用SiH4 /C2 H4 /N2 之電漿處理而形成。又，也可使用有機矽烷，以取代矽烷氣體(SiH4 )/乙烯(C2 H4 )。
於本實施形態之半導體裝置的最上層，可設有散熱裝置108。散熱裝置係導電膜或鰭片構造等，例如以熱傳導係數較大之材料(如Ag、Cu、Au、Al、Ta、Mo)所製造。
依上述結構，將實質的層間絕緣膜之介電常數降低，確保快速之動作；而且，以熱傳導係數較高之SiCN將模擬孔導入配線間的各個重要位置。藉此，可抑制配線之溫度上升，而使配線的信賴度提高。又，可使用一種絕緣物，其介電係數在5以下，而熱傳導係數比CF膜及CH膜更高；以取代SiCN。
其次，說明本發明之第2實施形態。
圖3顯示，依本發明之第2實施形態之半導體裝置的部分結構。所圖示之半導體裝置係多層配線構造的積體電路，其在保留熱通孔(相當於第1實施形態之模擬孔)的狀態下，去除配線層間之層間絕緣膜，而藉由氣體形成層間絕緣。
詳言之，此半導體裝置包括p型基板301、CMOS構成用之n井302、nMOS之源極區303、nMOS之汲極區304、nMOS之閘絕緣膜305、nMOS之間電極306、nMOS之源極電極307、nMOS之汲極電極308。而半導體裝置又包括pMOS之汲極區309、pMOS之源極區310、pMOS之閘電極311、pMOS之閘絕緣膜312、pMOS之源極電極313、pMOS之汲極電極314。又，半導體裝置進一步包括元件分離區(SiO2 等)315、其上面側所形成之絕緣膜(SiO2 等)316、p型基板301之背面側所形成的背面電極317、1層以上之金屬配線318、導電通孔(相當於第1實施形態之穿通孔)319，以及熱通孔320。
圖3雖顯示，熱通孔320係將沿著圖之上下方向而相鄰的金屬配線318加以彼此連接；但為了提高構造的強度，亦可將沿著圖之左右方向而相鄰的金屬配線318加以彼此連接。
圖3的半導體裝置係使用Cu作為金屬配線。至於Cu配線，為降低其電阻係數，故採巨晶粒(Giant－grain)構造。藉由此金屬配線，以及採用氣體之層間絕緣，可將各配線之訊號延遲降低到1/8的程度。其原因為：相對於代表性層間絕緣膜之硼磷矽玻璃(BPSG，Boron－doped Phospho－Silicate Glass)的介電常數係4.0左右，於氣體(較佳為，熱傳導度較大之He)的介電常數較低，僅1.0。
金屬配線318及導電通孔319二者之表面由未圖示的氮化物(氮化鈦、氮化鉭或氮化矽等)所覆蓋。
導電通孔319係由電路設計決定穿入位置；另一方面，熱通孔320可穿到任意位置，係依據構造之堅固程度與配線溫度之上升程度等，而決定穿入位置。
接著，說明圖3之半導體裝置的製造方法。
對於該半導體裝置，先製造作為半導體裝置(半成品)，其具有BPSG以作為層間絕緣膜。於此之後，藉由去除BPSG即可得到該半導體裝置。因此，半成品的製造，係藉由與習知半導體裝置相同的方法所進行。熱通孔與導電通孔的形成，係如下而進行。
首先，說明熱通孔的形成方法。
如圖4A所示，於Cu(合金)配線401上，依序形成以下的層面：使Cu配線401之表面穩定化的導電性氮化膜(TiN或TaN等)402、較薄之Si3 N4 403、BPSG404、Si3 N4 405，以及作為介層洞形成用圖案的光阻406。又，Si3 N4 403、BPSG404、Si3 N4 405相當於層間絕緣膜。
接著，於平衡之電子漂移(BED，balanced electron drift)磁控電漿的活性離子蝕刻(RIE，Reactive Ion Etch)裝置中，當使用C4 F8 /CO/O2 /Ar氣體而蝕刻Si3 N4 403、BPSG404、Si3 N4 405時，將成為圖4B所示的狀態。又，藉由使用C4 F8 /CO/O2 /Xe(或Kr)氣體而進行蝕刻的最後步驟(將Si3 N4 405之殘餘蝕刻的步驟)，可充分減少對導電性氮化膜402之表面的損傷。
再來，藉由採用SiH4 /C2 H4 /N2 之電漿處理，而如圖4C所示地使SiCN407、408堆積。又，也可使用有機矽烷，以取代矽烷氣體(SiH4 )/乙烯(C2 H4 )。
接下來，當使用IPA(30%左右)/KF(10%左右)/H2 O溶液，進行0.5~3MHz程度百萬頻率超音波的照射處理時，將如圖4D所示，光阻406從Si3 N4 405剝離。其結果，堆積於光阻406上之SiCN408藉由移除而去除。此外，若有必要，則進行化學機械研磨(CMP，Chemical Mechanical Polishing)等平坦化處理。
如此一來，將可在BPSG404中形成熱通孔(SiCN)407。
配線層間為空氣的情況下，空氣之熱傳導係數係0.0241(W/mK)，且比SiO2 之10.7~6.2(W/mK)小於3進位。然而，SiCN之熱傳導係數約100(W/mK)，且可充分進行配線層間之熱傳導。而且，由於SiCN的介電常數係4左右，因此無須使層間絕緣部(空間)的平均介電常數大幅提高。
其次，說明用以形成導電通孔及配線的製程。形成導電通孔及配線時，業者採用金屬鑲嵌(damascene)或雙重金屬鑲嵌製程。如上述，採用Cu於配線上；亦可採用Al或Al合金於導電通孔上。然而在此，針對採用與配線相同Cu的情況，加以說明。
使用2段噴淋板微波電漿裝置，而與圖4B相同地，在Si3 N4 403、BPSG404、Si3 N4 405形成介層洞。
其次，於上述裝置，將基板電極的高頻電力調成0之同時，把導入之氣體切換成He/O2 、Kr/O2 或Kr/H2 O等，且透過輻射狀排列的槽型天線(RLSA，Radial Line Slot Antenna)而施加微波。藉此，使O＊ 及OH＊ 大量產生，而去除所堆積於表面與介層洞壁面之較薄的氟碳膜。
接著，為了在BPSG404之介層洞壁面形成一種用以抑制Cu擴散的氮化膜，因此放出NH3 /Ar(或Kr)，或者N2 /H2 /Ar(或Kr)等氣體，且藉由微波將高密度電漿激發。藉此，產生大量NH＊ ，且如圖5A所示，BPSG404之介層洞壁面的表面變成5~20nm左右之Si3 N4 409。
於此狀態下，從第1段噴淋板供應Ar、Kr、Xe等稀有氣體，且從第2段噴淋板與Ar載氣一起供應Cu供應源之Cu(hgac)(tmvs)、Cu(hgac)(teovs)等。因為由微波所進行之電漿激發，係於第1段噴淋板正下方距離數mm的位置所進行，而第2段噴淋板則位於擴散電漿區，故原料氣體不會被過度地分解。由於Ar＋、Kr＋、Xe＋及Ar＊ 、Kr＊ 、Xe＊ 相互地撞擊，幾乎皆受到激發或離子化；且藉由表面吸附後之離子照射，Cu膜堆積上來。於Cu之CMP處理或矽區域表面形成數μm之金剛石薄膜以後，進行一種設有研磨用凹槽圖案之金剛石研磨面所形成的研磨。其後，當以臭氧(COOH)2 進行清洗時，則如圖5B所示，形成灌封有Cu410之導電通孔。
Cu410的周圍由Si3 N4 409所包覆，Cu被抑制往BPSG404擴散。
又，在Cu410的表面，藉由熱CVD使TiN或TaN選擇性堆積到5~10nm左右起來時，可防止其氧化。
如此一來，可得到一種半成品，具有BPSG作為層間絕緣膜，且於BPSG之既定位置形成熱通孔及導電通孔。
接著，使用一種氣體，其添加無水HF氣體1~7%到至少將水分降低到1ppm之N2 或Ar等氣體中，以僅將作為層間絕緣膜之BPSG加以選擇性地去除。
HF分子係溶解於水，使得用以蝕刻SiO2 的HF2 － 離子產生。因此。去除BPSG之際，將吸附在晶圓表面的水分至少去除到單分子層以下。例如，在水分1ppm以下之N2 環境氣體，將晶圓烘烤(200℃以上，較佳為300℃以上)。其後，將晶圓溫度維持於120~140℃，以使得因BPSG及HF二者反應所產生之水(H2 O)不吸附在晶圓表面。
當HF氣體之濃度太低時，蝕刻速度將變得太慢；HF氣體之濃度太高時，則開始蝕刻SiO2 等，BPSG以外之部分。
配線由Si3 N4 、TaN、TiN等所包覆，且由於此等氮化物不會與HF氣體反應，故配線不會受到蝕刻。
如此一來，可製造圖3之半導體裝置。
【產業上利用性】
以上，針對半導體裝置的情況，說明實施例；但本發明可普遍適用於多層配線基板，其等在至少包含半導體、導體、絕緣體的其中之一的基板上具有多層配線構造，係屬當然。
100．．．矽基板
101－107．．．配線層
108．．．散熱裝置
109－116．．．層間絕緣膜
201．．．第1絕緣物之底層
202．．．CF(氟碳)膜
202a．．．CF膜之第1層
202b．．．CF膜之第2層
301．．．p型基板
302．．．CMOS構成用之n井
303．．．nMOS之源極區
304．．．nMOS之汲極區
305．．．nMOS之閘絕緣膜
306．．．nMOS之閘電極
307．．．nMOS之源極電極
308．．．nMOS之汲極電極
309．．．pMOS之汲極區
310．．．pMOS之源極區
311．．．pMOS之閘電極
312．．．pMOS之閘絕緣膜
313．．．pMOS之源極電極
314．．．pMOS之汲極電極
315．．．元件分離區(SiO2 等)
316．．．絕緣膜(SiO2 等)
317．．．背面電極
318．．．金屬配線
319．．．導電通孔
320．．．熱通孔
401．．．Cu(合金)配線
402．．．導電性氮化膜(TiN或TaN等)
403．．．Si3 N4
404．．．BPSG
405．．．Si3 N4
406．．．介層洞形成用圖案的光阻
407．．．熱通孔(SiCN)
408．．．SiCN
409．．．Si3 N4
410．．．Cu
C．．．電阻
R．．．電容
圖1顯示適用本發明之半導體裝置之概略結構的剖面圖。
圖2顯示依本發明之第1實施形態之半導體裝置所採用層間絕緣膜的結構的剖面圖。
圖3顯示依本發明之第2實施形態之半導體裝置的結構的部分剖面圖。
圖4A~4D用以說明圖3所示之半導體裝置的熱通孔之形成方法的說明圖。
圖5A~5B用以說明圖3所示之半導體裝置的導電通孔之形成方法的說明圖。
100．．．矽基板
101－107．．．配線層
108．．．散熱裝置
109－116．．．層間絕緣膜

Claims (10)

  1. 一種多層配線基板，於包含半導體、導體、絕緣體至少其中之一的基板上具有多層配線構造；其特徵為：在該多層配線構造中的第1配線層及其上的第2配線層之間，夾設介電常數為平均2.5以下的氣體或絕緣物；且在該第1配線層的至少一配線及該第2配線層的至少一配線之間，設置導電連接體；更於該第1配線層的既定配線和該第2配線層的既定配線之間，設置介電常數為5以下的絕緣物熱傳導體；該絕緣物熱傳導體包含一種含矽、碳及氮的材料。
  2. 如申請專利範圍第1項之多層配線基板，其中，在該第1配線層與該第2配線層之間夾設絕緣物，且該絕緣物熱傳導體之熱傳導係數比該絕緣物之熱傳導係數為大。
  3. 如申請專利範圍第2項之多層配線基板，其中，夾設在該第1配線層與該第2配線層之間的絕緣物，係包含一種含碳及氟的材料。
  4. 如申請專利範圍第2項之多層配線基板，其中，夾設在該第1配線層與該第2配線層之間的絕緣物，係包含一種含碳及氫的材料。
  5. 如申請專利範圍第1項之多層配線基板，其中，該絕緣物熱傳導體包含SiCN。
  6. 一種半導體裝置，於形成有複數之半導體元件的基板上具有多層配線構造；其特徵為： 在該多層配線構造中的第1配線層及其上的第2配線層之間，夾設介電常數係平均2.5以下的氣體或絕緣物；在該第1配線層的至少一配線及該第2配線層的至少一配線之間，設置導電連接體；更在該第1配線層的既定配線與該第2配線層的既定配線之間，設置介電常數係5以下的絕緣物熱傳導體；該絕緣物熱傳導體包含一種含矽、碳及氮的材料。
  7. 如申請專利範圍第6項之半導體裝置，其中，於該第1配線層及該第2配線層之間夾設絕緣物，且該絕緣物熱傳導體之熱傳導係數比該絕緣物之熱傳導係數更大。
  8. 如申請專利範圍第7項之半導體裝置，其中，夾設於該第1配線層及該第2配線層之間的絕緣物，係包含一種含碳及氟的材料。
  9. 如申請專利範圍第7項之半導體裝置，其中，夾設於該第1配線層及該第2配線層之間的絕緣物，係包含一種含碳及氫的材料。
  10. 如申請專利範圍第6項之半導體裝置，其中，該絕緣物熱傳導體包含SiCN。
TW096131781A 2006-08-28 2007-08-28 半導體裝置及多層配線基板 TWI401782B (zh)

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