TWI401768B - Electrostatic chuck containing buffer layer for reducing thermal stress - Google Patents
Electrostatic chuck containing buffer layer for reducing thermal stress Download PDFInfo
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- TWI401768B TWI401768B TW098130090A TW98130090A TWI401768B TW I401768 B TWI401768 B TW I401768B TW 098130090 A TW098130090 A TW 098130090A TW 98130090 A TW98130090 A TW 98130090A TW I401768 B TWI401768 B TW I401768B
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- Prior art keywords
- terminal
- buffer layer
- electrostatic chuck
- insulating member
- electrode
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
- H01L21/6833—Details of electrostatic chucks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02N—ELECTRIC MACHINES NOT OTHERWISE PROVIDED FOR
- H02N13/00—Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Jigs For Machine Tools (AREA)
Description
本發明之是有關於一種位於處理腔室中之靜電夾頭，且特別是有關一種以緩衝層覆蓋之靜電夾頭，用以在執行使用靜電夾頭之製程時降低熱應力，並使由於熱應力所導致之靜電夾頭之龜裂最小化。The present invention relates to an electrostatic chuck located in a processing chamber, and more particularly to an electrostatic chuck covered with a buffer layer for reducing thermal stress during the process of using the electrostatic chuck and for causing heat The crack of the electrostatic chuck caused by the stress is minimized.
一般而言，半導體裝置與例如液晶顯示器(LCD)裝置之平面板裝置之製程，係包含例如化學氣相沈積(CVD)之沈積製程以及例如反應性離子蝕刻製程之蝕刻製程。於上述沈積製程與蝕刻製程中，需要將例如矽晶圓與玻璃面板之基板固定至處理腔室中之電極板，俾能改善製程可靠度。靜電夾頭(ESC)通常用來將基板固定至處理腔室中之電極板。In general, the fabrication of semiconductor devices and planar device devices such as liquid crystal display (LCD) devices includes, for example, chemical vapor deposition (CVD) deposition processes and etching processes such as reactive ion etching processes. In the above deposition process and etching process, it is necessary to fix a substrate such as a germanium wafer and a glass panel to an electrode plate in a processing chamber, which can improve process reliability. Electrostatic chucks (ESC) are commonly used to secure substrates to electrode plates in processing chambers.
第1圖係為顯示在處理腔室中之習知靜電夾頭之剖面圖。Figure 1 is a cross-sectional view of a conventional electrostatic chuck shown in a processing chamber.
參見第1圖，習知之靜電夾頭100包含：一本體101，其包含鋁；一基底平板102，於其上固定地安置有一基板；一電極103，裝設於基底平板102之內部中並產生靜電力；一端子104，用以施加高電壓至前述電極；以及一絕緣構件105，其包圍端子104。Referring to FIG. 1 , a conventional electrostatic chuck 100 includes a body 101 including aluminum, a substrate plate 102 on which a substrate is fixedly disposed, and an electrode 103 disposed in the interior of the substrate plate 102 and produced. An electrostatic force; a terminal 104 for applying a high voltage to the electrode; and an insulating member 105 surrounding the terminal 104.
高電壓係經由端子104而從外部電源被施加至電極103，而靜電力可能產生於電極103。然後，基底平板102上之基板係藉由靜電力而被取出朝向基底平板102，並被固定至靜電夾頭100。The high voltage is applied to the electrode 103 from the external power source via the terminal 104, and an electrostatic force may be generated from the electrode 103. Then, the substrate on the substrate flat plate 102 is taken out toward the base flat plate 102 by electrostatic force, and is fixed to the electrostatic chuck 100.
於習知之沈積製程或蝕刻製程中，基底平板102係由處理腔室中之電漿所加熱，而靜電夾頭100之基底平板102通常由於處理腔室中之電漿之高溫而處在大熱應力之下。更明確而言，熱係從基底平板102被傳送至鋁本體101，從而使本體101朝所有方向呈現熱膨脹。因為本體101、基底平板102與絕緣構件105之熱係數通常彼此不同，所以熱應力係被施加至本體101、基底平板102及絕緣構件105。在習知之靜電夾頭100中，讓本體101、基底平板102與絕緣構件105彼此接觸之邊界區域之上端部A之熱應力達到最大化。In conventional deposition processes or etching processes, the substrate plate 102 is heated by the plasma in the processing chamber, and the substrate plate 102 of the electrostatic chuck 100 is typically hot due to the high temperature of the plasma in the processing chamber. Under stress. More specifically, the thermal system is transferred from the substrate plate 102 to the aluminum body 101 such that the body 101 exhibits thermal expansion in all directions. Since the thermal coefficients of the body 101, the base plate 102, and the insulating member 105 are generally different from each other, thermal stress is applied to the body 101, the base plate 102, and the insulating member 105. In the conventional electrostatic chuck 100, the thermal stress of the upper end portion A of the boundary region where the body 101, the base plate 102 and the insulating member 105 are in contact with each other is maximized.
因為基底平板102具有遠小於本體101與絕緣構件105的強度，所以在邊界區域之上端部A之熱應力對於基底平板102比對於本體101與絕緣構件105具有來得更多的影響，從而於靠近邊界區域之上部A之基底平板102之下部產生龜裂。當靜電夾頭100重複操作時，龜裂係成長至基底平板102之上部以及整體的基底平板102，而最後基底平板102由於龜裂而損壞。Since the base plate 102 has a strength much smaller than that of the body 101 and the insulating member 105, the thermal stress at the end portion A above the boundary region has more influence on the base plate 102 than on the body 101 and the insulating member 105, thereby being closer to the boundary. Cracks are formed in the lower portion of the base plate 102 at the upper portion A of the region. When the electrostatic chuck 100 is repeatedly operated, the cracks grow to the upper portion of the base plate 102 and the entire base plate 102, and finally the base plate 102 is damaged by the crack.
因此，對於能將由於熱應力所導致之龜裂最小化，藉以避免靜電夾頭之故障之改良之靜電夾頭，存在有強烈之需求。Therefore, there is a strong demand for an electrostatic chuck capable of minimizing cracks due to thermal stress and avoiding the failure of the electrostatic chuck.
實施示範例提供一種供ESC用之端子單元，其包含一緩衝層，用以在操作使用ESC之一製程時吸收熱應力；實施示範例亦提供端子單元之形成方法。The exemplary embodiment provides a terminal unit for ESC, which includes a buffer layer for absorbing thermal stress during operation of one of the ESC processes; and the exemplary embodiment also provides a method of forming the terminal unit.
實施示範例亦提供具有上述端子單元之ESC以及ESC之製造方法。The embodiment also provides a method of manufacturing the ESC and the ESC having the above terminal unit.
依據某些實施示範例，提供一種靜電夾頭(ESC)，其包含：一本體，具有一穿孔；一基底平板，配置於本體上，其中一基板係藉由一靜電力而固定至基底平板，該基底平板具有對應至本體之穿孔之一***部以及安置於基底平板之內部並經由***部而局部露出之一電極；一端子單元，具有經由本體之穿孔以及基底平板之***部而與電極接觸之一端子；以及一緩衝層，配置於端子與本體和基底平板之至少一者之間之一邊界區域，並吸收本體之熱應力。According to some embodiments, an electrostatic chuck (ESC) is provided, comprising: a body having a through hole; and a substrate plate disposed on the body, wherein a substrate is fixed to the substrate plate by an electrostatic force. The base plate has an insertion portion corresponding to the perforation of the body and disposed inside the base plate and partially exposing one of the electrodes via the insertion portion; a terminal unit having contact with the electrode via the through hole of the body and the insertion portion of the base plate And a buffer layer disposed at a boundary region between the terminal and at least one of the body and the base plate, and absorbing thermal stress of the body.
於一實施示範例中，本體包含一導電材料，而端子單元包含介設於本體與穿孔中之端子之間之一絕緣構件，俾能使緩衝層被配置於本體與絕緣構件之間之一邊界區域。緩衝層係更進一步被配置於絕緣構件與基底平板之間之一邊界區域。In an exemplary embodiment, the body includes a conductive material, and the terminal unit includes an insulating member interposed between the body and the terminal in the through hole, and the buffer layer is disposed at a boundary between the body and the insulating member. region. The buffer layer is further disposed in a boundary region between the insulating member and the base plate.
於一實施示範例中，基底平板與緩衝層包含基於陶瓷材料之材料。緩衝層之孔隙率係等於或高於基底平板之孔隙率。緩衝層之孔隙率係在大約2%至大約10%之範圍內。緩衝層之厚度係在大約100μm至大約250μm之範圍內。緩衝層之表面粗糙度係在大約0.1μm至大約2μm之範圍內。In an embodiment, the substrate plate and the buffer layer comprise a material based on a ceramic material. The porosity of the buffer layer is equal to or higher than the porosity of the substrate plate. The porosity of the buffer layer is in the range of from about 2% to about 10%. The thickness of the buffer layer is in the range of from about 100 μm to about 250 μm. The surface roughness of the buffer layer is in the range of from about 0.1 μm to about 2 μm.
依據某些實施示範例，提供一種供一靜電夾頭用之端子單元，其包含：一端子，電連接至一電源並施加一電力至一電極，用以產生一靜電力；一絕緣構件，局部包圍端子，俾能藉由絕緣構件而使端子能與外界環境電氣絕緣；以及一緩衝層，配置於端子與絕緣構件之至少一者上，並吸收由外界環境所施加之熱應力。According to some embodiments, there is provided a terminal unit for an electrostatic chuck, comprising: a terminal electrically connected to a power source and applying a power to an electrode for generating an electrostatic force; an insulating member, a portion The terminal is surrounded by the insulating member to electrically insulate the terminal from the external environment; and a buffer layer is disposed on at least one of the terminal and the insulating member and absorbs thermal stress applied by the external environment.
依據某些實施示範例，提供一種靜電夾頭之製造方法。準備具有一穿孔之一本體，並提供對應至穿孔之一端子單元。端子具有一緩衝層，用以吸收本體之表面上之熱應力。本體與端子單元可能彼此結合，以使端子單元貫穿此穿孔並凸出本體之一上表面。一下基底平板係形成於本體上，以使端子之一上表面露出，而一電極係形成於下基底平板上，以使電極與露出之端子單元接觸。一上基底平板係形成於下基底平板與電極上。In accordance with certain implementation examples, a method of making an electrostatic chuck is provided. A body having a perforation is prepared and a terminal unit corresponding to one of the perforations is provided. The terminal has a buffer layer for absorbing thermal stress on the surface of the body. The body and the terminal unit may be coupled to each other such that the terminal unit penetrates through the through hole and protrudes from an upper surface of the body. The base plate is formed on the body such that an upper surface of the terminal is exposed, and an electrode is formed on the lower substrate to contact the exposed terminal unit. An upper substrate is formed on the lower substrate and the electrode.
依據某些實施示範例，提供一種形成供一靜電夾頭用之一端子單元之方法。利用端子貫穿靜電夾頭之一本體並電連接至一外部電源之這樣的方式來準備一端子。此端子係被***至一絕緣體，以使端子之一末端部分露出。一緩衝層係形成於端子之露出表面上，緩衝層吸收由外界環境所施加之熱應力。According to certain embodiments, a method of forming a terminal unit for an electrostatic chuck is provided. A terminal is prepared in such a manner that the terminal penetrates one of the bodies of the electrostatic chuck and is electrically connected to an external power source. This terminal is inserted into an insulator to expose one end portion of the terminal. A buffer layer is formed on the exposed surface of the terminal, and the buffer layer absorbs thermal stress applied by the external environment.
於一實施示範例中，緩衝層之形成方式如下：將絕緣體移離端子，藉以露出端子之末端部分；以及將緩衝層塗佈於露出之端子上。緩衝層可能藉由大氣所導致的電漿噴灑塗佈製程而塗佈於端子上。在形成緩衝層之後，可更進一步在緩衝層上執行倒角製程，藉以將緩衝層之一邊緣部分形成為圓形。In an exemplary embodiment, the buffer layer is formed by moving the insulator away from the terminal to expose the end portion of the terminal; and applying a buffer layer to the exposed terminal. The buffer layer may be applied to the terminals by a plasma spray coating process caused by the atmosphere. After the buffer layer is formed, a chamfering process may be further performed on the buffer layer, whereby one edge portion of the buffer layer is formed into a circular shape.
依據某些實施示範例，ESC之熱應力可能被吸收至ESC中之緩衝層，從而可能充分減少由熱應力所導致的龜裂，藉以增加ESC之耐久性壽命。According to certain embodiments, the thermal stress of the ESC may be absorbed into the buffer layer in the ESC, thereby possibly reducing the crack caused by the thermal stress, thereby increasing the durability life of the ESC.
為讓本發明之上述內容能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:
以下將參考附圖更完全地說明各種實施示範例，於附圖中顯示本發明之數個實施示範例。然而，本發明可能以許多不同的形式被具體化，且不應被解釋成受限於於此所提出之實施示範例。反之，這些實施示範例之提供是為了能使這個揭露書呈現徹底且完整的，且將完全傳達本發明之範疇給熟習本項技藝者。在附圖中，為清楚起見，可能誇大數個層與數個區域之尺寸與相對尺寸。Various embodiments of the invention will be described more fully hereinafter with reference to the accompanying drawings in which FIG. However, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments disclosed herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. In the accompanying figures, the dimensions and relative dimensions of several
吾人將理解到當一元件或層被稱為係「在…之上」、「連接至」或「耦接至」另一個元件或層時，其可以是直接在其之上、連接或耦接至另一個元件或層，或者中介元件或層可能存在。相較之下，當一元件被稱為係「直接在…之上」、「直接連接至」或「直接耦接至」另一個元件或層時，則沒有中介元件或層存在。遍及全文，相同的參考數字表示相同的元件。如於此所使用的，專門用語「及/或」包含一個或多個相關的列出項目之任何與所有組合。It will be understood that when an element or layer is referred to as "above", "connected" or "coupled" to another element or layer, it may be directly above, connected or coupled. To another element or layer, or an intervening element or layer may be present. In contrast, when an element is referred to as being "directly on", "directly connected to" or "directly coupled" to another element or layer, no intervening element or layer exists. Throughout the text, the same reference numerals indicate the same elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
吾人將理解到雖然專門用語第一、第二、第三等可能於此被使用以說明各種元件、組件、區域、層及/或部，但這些元件、組件、區域、層及/或部不應受限於這些專門用語。這些專門用語只用以區別一個元件、組件、區域、層或部與另一個區域、層或部。因此，在不背離本發明之教導之下，以下所討論之一第一元件、組件、區域、層或部可稱為一第二元件、組件、區域、層或部。It will be understood that the terms, components, regions, layers, and/or sections may These special terms should be limited. These specific terms are only used to distinguish one element, component, region, layer or portion from another region or layer. Thus, a first element, component, region, layer or section may be referred to as a second element, component, region, layer or section.
於此可能使用空間相對的專門用語，例如「在底下」、「在下方」、「低於」、「在上方」、「高於」等等，以便簡化說明顯示於圖中之一個元件或特徵部與另一元件或特徵部之間的關係。吾人將理解到空間相對的專門用語係意圖包含使用中或操作中之除了描繪於圖中之方位以外的不同方位之裝置。舉例而言，如果翻轉圖中之裝置，「位在其他元件或特徵部以下或底下」之元件之方位會被改變成「位在其他元件或特徵部以上」。因此，例示的專門用語「以下」可包含上方或下方之方位。此裝置可能會被重新定方位(旋轉90度或位於其他方位)，且使用於此之空間相對的敘述元因此得到解釋。It is possible to use spatially specific terms such as "below", "below", "below", "above", "above", etc., in order to simplify the description of a component or feature shown in the figure. The relationship between a part and another component or feature. It will be understood that the space-specific terminology is intended to encompass a device that is in a different orientation than the orientation depicted in the drawings. For example, if the device in the figure is flipped, the orientation of the component "below or underneath other elements or features" will be changed to "beyond other components or features". Therefore, the exemplified term "below" may include the orientation above or below. The device may be repositioned (rotated 90 degrees or at other orientations) and the spatially relative narration used herein is thus explained.
於此所使用之專門用語係只用以說明特定實施示範例，而並非意圖成為本發明之限制。如於此所使用的，除非上下文清楚地表示，否則單數形式係意圖也包含複數形式。吾人將更進一步理解到專門用語「包含」及/或「含有」，當於本說明書中所使用時，指定出規定特徵、整數、步驟、運作、元件，及/或組件之存在，但並未阻止一個或多個其他特徵、整數、步驟、運作、元件、組件及/或其群組之存在或添加。The specific language used herein is for the purpose of illustration and description and description As used herein, the singular forms " " We will further understand the terms "including" and / or "including" as used in this specification to specify the existence of specified features, integers, steps, operations, components, and/or components, but not The existence or addition of one or more other features, integers, steps, operations, components, components, and/or groups thereof is prevented.
於此參考剖面圖例(其係為理想化實施示範例(與中間構造)之示意圖)來說明實施示範例。如此，從譬如由製造技術及/或公差之結果所造成之圖例之形狀之變化是可預期的。因此，實施示範例不應被解釋成受限於於此所顯示之區域之特定形狀，但係用以包含譬如由製造引起的形狀之偏差。舉例而言，顯示為矩形之植入區，一般是具有圓形或曲線特徵及/或於其邊緣處之植入濃度梯度而非從植入區到非植入區之二元改變(binary change)。同樣地，藉由植入而形成之埋入區可能導致在埋入區以及經由其發生植入之表面之間的區域中之某些植入。因此，顯示於圖中之區域本質上係為概要的，而它們的形狀並非意圖顯示裝置之區域之實際形狀，且並非意圖限制本發明之範疇。Embodiments are described herein with reference to cross-sectional illustrations, which are schematic representations of idealized implementation examples (and intermediate configurations). Thus, variations from the shapes of the illustrations as a result of manufacturing techniques and/or tolerances are contemplated. Thus, the examples are not to be construed as limited to the particular shapes of For example, an implanted area that is shown as a rectangle, typically having a circular or curved feature and/or an implant concentration gradient at its edges rather than a binary change from the implanted to the non-implanted region (binary change) ). Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which implantation occurs. Therefore, the regions shown in the figures are in the nature and are not intended to limit the scope of the invention.
除非另有定義，否則於此所使用之所有專門用語(包含技術與科學用語)具有與本發明所屬之其中一個熟習本項技藝者所通常理解相同的意思。吾人將更進一步理解到例如定義在常用字典中之那些專門用語應被解釋成具有下述意思，其係與相關技術之上下文中的它們的意思相符且將不會以一種理想化或過度形式的意識被解釋，除非於此特別如此定義。Unless otherwise defined, all of the specific terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood by us that, for example, those specific terms defined in commonly used dictionaries should be interpreted as having the following meanings consistent with their meaning in the context of the related art and will not be in an idealized or excessive form. Consciousness is explained unless it is specifically defined as such.
以下，將參考附圖而詳細說明實施示範例。Hereinafter, the embodiment will be described in detail with reference to the drawings.
第2圖係為顯示依據本發明的概念之實施示範例之靜電夾頭之剖面圖。Figure 2 is a cross-sectional view showing an electrostatic chuck according to an exemplary embodiment of the concept of the present invention.
參見第2圖，依據本發明的概念之實施示範例之靜電夾頭(ESC)200可包含：一本體201；一基底平板202，安裝於本體201上並包含一電極203於其中；一端子單元，包含一端子204與一絕緣構件205，端子204用以從一外部電源(未顯示)施加一高電壓至電極203，而絕緣構件205包圍端子204；以及一緩衝層206，用以吸收本體201之熱應力。於處理腔室中可將待被處理之基板(未顯示)固定地安置於基底平板202上，並可將緩衝層206安置於本體201與基底平板202之邊界區域之至少一部分。Referring to FIG. 2, an electrostatic chuck (ESC) 200 according to an exemplary embodiment of the present invention may include: a body 201; a substrate plate 202 mounted on the body 201 and including an electrode 203 therein; and a terminal unit The terminal 204 includes a terminal 204 for applying a high voltage from an external power source (not shown) to the electrode 203, and the insulating member 205 surrounding the terminal 204; and a buffer layer 206 for absorbing the body 201. Thermal stress. A substrate (not shown) to be processed may be fixedly disposed on the substrate plate 202 in the processing chamber, and the buffer layer 206 may be disposed on at least a portion of a boundary region between the body 201 and the substrate plate 202.
於一實施示範例中，本體201可包含例如鋁之導電材料，並發揮ESC 200之基礎支撐之功能。可於本體201之中央部分製備一穿孔207，並可將具有端子204與絕緣構件205之端子單元***至穿孔207，從而可貫通本體201。In an exemplary embodiment, the body 201 may comprise a conductive material such as aluminum and function as a base support for the ESC 200. A through hole 207 may be formed in a central portion of the body 201, and a terminal unit having the terminal 204 and the insulating member 205 may be inserted into the through hole 207 so as to be penetrated through the body 201.
於一實施示範例中，基底平板202可包含一介電材料，並可能藉由大氣所致的電漿噴灑(APS)塗佈製程而塗佈於本體201上。基底平板202可包含具有介電材料之陶瓷材料。陶瓷材料之例子可包含氧化鋁(Al2O3)、氧化釔(Y2O3)、氧化鋁(Al2O3)與氧化釔(Y2O3)之複合物、二氧化鋯(ZrO2)、碳化鋁(AlC)、氮化鈦(錫)、氮化鋁(AlN)、碳化鈦(TiC)、氧化鎂(MgO)、氧化鈣(CaO)、氧化鈰(CeO2)、氧化鈦(TiO2)、碳化硼(BxCy)、氮化硼(BN)、二氧化矽(SiO2)，碳化矽(SiC)、釔鋁石榴石(YAG，Y3Al5O12)、富鋁紅柱石(鋁矽酸鹽，3Al2O3‧2SiO3)、氟化鋁(AlF3)等。這些可被單獨使用或組合使用。In an exemplary embodiment, the substrate plate 202 may comprise a dielectric material and may be applied to the body 201 by an atmospheric plasma spray (APS) coating process. The substrate plate 202 can comprise a ceramic material having a dielectric material. Examples of the ceramic material may include alumina (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), a composite of alumina (Al 2 O 3 ) and yttrium oxide (Y 2 O 3 ), zirconium dioxide (ZrO 2 ), aluminum carbide (AlC), titanium nitride ( Tin), aluminum nitride (AlN), titanium carbide (TiC), magnesium oxide (MgO), calcium oxide (CaO), cerium oxide (CeO2), titanium oxide (TiO2), boron carbide (BxCy), boron nitride ( BN), cerium oxide (SiO2), lanthanum carbide (SiC), yttrium aluminum garnet (YAG, Y3Al5O12), mullite (aluminum silicate, 3Al2O3‧2SiO3), aluminum fluoride (AlF3), and the like. These can be used alone or in combination.
藉由靜電力，可將基板固定至基底平板202，並固定地定位基板，而靜電力可能藉由被施加至裝設於基底平板202之內部中之電極203之電力而產生。基底平板202之上表面可能是平的，從而使基板可能水平地安置於基底平板202上。於本實施示範例中，可將電極203裝設成實質上平行於基底平板202之上表面。By electrostatic force, the substrate can be fixed to the substrate plate 202 and the substrate can be fixedly positioned, and electrostatic force can be generated by the electric power applied to the electrode 203 installed in the interior of the substrate plate 202. The upper surface of the substrate plate 202 may be flat so that the substrate may be placed horizontally on the substrate plate 202. In the present embodiment, the electrode 203 may be disposed substantially parallel to the upper surface of the substrate plate 202.
可將一***部208設置於基底平板202之一中央部分，並可將與端子204***至***部208。端子204可經由基底平板202之***部208而與電極203接觸。因此，可經由穿孔207而將端子204***至本體201，並可經由基底平板202之***部208而將端子204延伸至電極203。亦即，可經由本體201之穿孔207與基底平板202之***部208而將端子204連接至電極203。An insertion portion 208 may be disposed at a central portion of the base plate 202, and the terminal 204 may be inserted into the insertion portion 208. The terminal 204 can be in contact with the electrode 203 via the insertion portion 208 of the base plate 202. Accordingly, the terminal 204 can be inserted into the body 201 via the through hole 207 and the terminal 204 can be extended to the electrode 203 via the insertion portion 208 of the base plate 202. That is, the terminal 204 can be connected to the electrode 203 via the through hole 207 of the body 201 and the insertion portion 208 of the base plate 202.
如上所述，可將電極203裝設於基底平板202中，並可經由端子204而將高電壓施加至電極203。因此，可將靜電力施加至基底平板202上之基板，並可將基板固定至基底平板202。亦即，可藉由靜電力而將基板固定地定位於基底平板202上。As described above, the electrode 203 can be mounted in the base plate 202, and a high voltage can be applied to the electrode 203 via the terminal 204. Therefore, an electrostatic force can be applied to the substrate on the substrate plate 202, and the substrate can be fixed to the substrate plate 202. That is, the substrate can be fixedly positioned on the substrate plate 202 by electrostatic force.
舉例而言，電極203可包含例如鎳(Ni)之導電材料。For example, the electrode 203 may comprise a conductive material such as nickel (Ni).
在本實施示範例中，藉由連續的大氣所致的電漿噴灑(APS)製程，可將電極203形成於基底平板202中。首先，可藉由一第一APS塗佈製程而將一下基底平板202a形成於本體201上，並可藉由一APS塗佈製程或一網印製程來將一電極層(未顯示)形成於下基底平板202a上。藉由圖案化製程，電極層可能於下基底平板202a上被製作成電極203。然後，可藉由一第二APS塗佈製程而在下基底平板202a上形成一上基底平板202b達到足夠厚度以覆蓋電極203。In the present embodiment, the electrode 203 can be formed in the substrate plate 202 by a continuous atmospheric plasma spray (APS) process. First, a lower substrate plate 202a can be formed on the body 201 by a first APS coating process, and an electrode layer (not shown) can be formed under the APS coating process or a screen printing process. On the substrate plate 202a. The electrode layer may be formed as an electrode 203 on the lower substrate plate 202a by a patterning process. Then, an upper substrate plate 202b is formed on the lower substrate plate 202a to a sufficient thickness to cover the electrode 203 by a second APS coating process.
舉例而言，可使下基底平板202a形成達到大約400μm至大約600μm之厚度，而電極203可具有大約5μm至大約65μm之厚度。又，上基底平板202b可能形成達到大約400μm至大約750μm之厚度。For example, the lower substrate plate 202a may be formed to a thickness of about 400 μm to about 600 μm, and the electrode 203 may have a thickness of about 5 μm to about 65 μm. Also, the upper substrate plate 202b may be formed to a thickness of about 400 μm to about 750 μm.
端子204可經由穿孔207與***部208而連接至電極203，並可從一外部電源(未顯示)經由端子204而將高電壓施加至電極203。端子204可包含例如鎢(W)、鉬(Mo)與鈦(Ti)之導電金屬材料。The terminal 204 can be connected to the electrode 203 via the via 207 and the insertion portion 208, and can apply a high voltage to the electrode 203 via an external power source (not shown) via the terminal 204. The terminal 204 may comprise a conductive metal material such as tungsten (W), molybdenum (Mo), and titanium (Ti).
於一實施示範例中，絕緣構件205可能介設於本體201與端子204之間，從而使本體201與端子204可彼此電氣絕緣。舉例而言，絕緣構件205可包含一種燒結之陶瓷材料，因為燒結之陶瓷材料中具有非常少的孔隙率，從而使在本體201與端子204之間之電氣絕緣得以最大化。In an exemplary embodiment, the insulating member 205 may be interposed between the body 201 and the terminal 204 such that the body 201 and the terminal 204 are electrically insulated from each other. For example, the insulating member 205 can comprise a sintered ceramic material because of the very low porosity in the sintered ceramic material, thereby maximizing electrical insulation between the body 201 and the terminal 204.
舉例而言，絕緣構件205可具有大約2,000μm之厚度，並具有大約0.1μm至大約2μm之表面粗糙度，俾能使表面電阻最小化，並避免電弧。於本例子中，絕緣構件205可具有大約1μm或更少之表面粗糙度。For example, the insulating member 205 may have a thickness of about 2,000 μm and have a surface roughness of about 0.1 μm to about 2 μm, which minimizes surface resistance and avoids arcing. In the present example, the insulating member 205 may have a surface roughness of about 1 μm or less.
於一實施示範例中，可將緩衝層206安置於本體201與絕緣構件205之一第一邊界區域之一部分，於基底平板202與絕緣構件205之一第二邊界區域，以及於基底平板202與端子204之一第三邊界區域。舉例而言，緩衝層206可包含一陶瓷材料。陶瓷材料之例子可包含氧化鋁(Al2O3)、氧化釔(Y2O3)、氧化鋁(Al2O3)與氧化釔(Y2O3)之複合物、二氧化鋯(ZrO2)、碳化鋁(AlC)、氮化鈦(錫)、氮化鋁(AlN)、碳化鈦(TiC)、氧化鎂(MgO)、氧化鈣(CaO)、氧化鈰(CeO2)、氧化鈦(TiO2)、碳化硼(BxCy)、氮化硼(BN)、氧化矽(SiO2)、碳化矽(SiC)、釔鋁石榴石(YAG，Y3Al5O12)、富鋁紅柱石(鋁矽酸鹽，3Al2O3‧2SiO3)、氟化鋁(AlF3)等。這些可被單獨使用或組合使用。緩衝層206可能藉由APS塗佈製程而形成於第一、第二及第三邊界區域。In an exemplary embodiment, the buffer layer 206 may be disposed on a portion of the first boundary region of the body 201 and the insulating member 205, in a second boundary region between the substrate plate 202 and the insulating member 205, and the substrate plate 202 One of the third boundary regions of the terminal 204. For example, buffer layer 206 can comprise a ceramic material. Examples of the ceramic material may include alumina (Al 2 O 3 ), yttrium oxide (Y 2 O 3 ), a composite of alumina (Al 2 O 3 ) and yttrium oxide (Y 2 O 3 ), zirconium dioxide (ZrO 2 ), aluminum carbide (AlC), titanium nitride ( Tin), aluminum nitride (AlN), titanium carbide (TiC), magnesium oxide (MgO), calcium oxide (CaO), cerium oxide (CeO2), titanium oxide (TiO2), boron carbide (BxCy), boron nitride ( BN), cerium oxide (SiO2), lanthanum carbide (SiC), yttrium aluminum garnet (YAG, Y3Al5O12), mullite (aluminum silicate, 3Al2O3‧2SiO3), aluminum fluoride (AlF3), and the like. These can be used alone or in combination. The buffer layer 206 may be formed in the first, second, and third boundary regions by an APS coating process.
舉例而言，緩衝層206可具有大約100μm至大約250μm之厚度，更好是大約150μm至大約200μm之厚度。當緩衝層206可具有大於大約250μm之厚度時，孔隙很可能良好地產生於緩衝層206中，其將導致在緩衝層206中之龜裂，雖然其小於大約100μm，但是緩衝層206將傾向於如此薄，以致於緩衝層206可能難以吸收本體201之熱應力。For example, the buffer layer 206 may have a thickness of about 100 μm to about 250 μm, more preferably about 150 μm to about 200 μm. When the buffer layer 206 can have a thickness greater than about 250 [mu]m, the voids are likely to be well produced in the buffer layer 206, which will cause cracking in the buffer layer 206, although it is less than about 100 [mu]m, the buffer layer 206 will tend to It is so thin that the buffer layer 206 may be difficult to absorb the thermal stress of the body 201.
此外，類似於絕緣構件205，緩衝層206可具有大約0.1μm至大約2μm之表面粗糙度，俾能使表面電阻最小化並避免電弧。於本例中，緩衝層206可具有大約1μm或更少之表面粗糙度。Further, similar to the insulating member 205, the buffer layer 206 may have a surface roughness of about 0.1 μm to about 2 μm, which minimizes surface resistance and avoids arcing. In this example, the buffer layer 206 may have a surface roughness of about 1 μm or less.
緩衝層206可吸收靜電夾頭200之熱應力，其可能由在一電漿沈積製程或一電漿蝕刻製程期間之溫升所導致。雖然習知之ESC鋁本體可能由於習知ESC在電漿製程中之高溫而熱膨脹，且各種熱應力可能被施加至習知之ESC，但是在同一電漿製程中之本發明之ESC之本體之熱膨脹可能會被吸收進入緩衝層206中。因此，無法將ESC之本體之熱應力施加至絕緣構件。更明確而言，可藉由緩衝層206來充分避免到達ESC之一邊緣點(對應至第1圖之部分A)之應力濃度，從而避免在ESC之本體201與絕緣構件205之間之邊界區域之龜裂，藉以增加ESC之耐久性壽命。The buffer layer 206 can absorb the thermal stress of the electrostatic chuck 200, which may be caused by a temperature rise during a plasma deposition process or a plasma etching process. Although the conventional ESC aluminum body may thermally expand due to the high temperature of the conventional ESC in the plasma process, and various thermal stresses may be applied to the conventional ESC, the thermal expansion of the body of the ESC of the present invention in the same plasma process may be Will be absorbed into the buffer layer 206. Therefore, the thermal stress of the body of the ESC cannot be applied to the insulating member. More specifically, the stress concentration of one of the edge points of the ESC (corresponding to the portion A of FIG. 1) can be sufficiently avoided by the buffer layer 206, thereby avoiding the boundary region between the body 201 of the ESC and the insulating member 205. The crack is cracked to increase the durability life of the ESC.
於本實施示範例中，緩衝層206之孔隙率可能等於或高於基底平板202之孔隙率，藉以使熱應力之吸收最大化，並使ESC之龜裂最小化。亦即，緩衝層206之孔隙率可能等於或高於下基底平板202a或上基底平板202b之孔隙率。舉例而言，緩衝層206可具有大約2%至大約10%之孔隙率，更好是大約2%至大約7%之孔隙率。當緩衝層206之孔隙率可能超過大約10%時，在緩衝層中之孔隙率傾向於過度，這會減少緩衝層206之強度，且最後會使緩衝層206與絕緣構件205和基底平板202分離。當孔隙率低於大約2%時，容易與急速地產生龜裂，以致於可能使緩衝層206難以吸收熱應力。In the present embodiment, the porosity of the buffer layer 206 may be equal to or higher than the porosity of the substrate plate 202, thereby maximizing the absorption of thermal stress and minimizing the cracking of the ESC. That is, the porosity of the buffer layer 206 may be equal to or higher than the porosity of the lower substrate plate 202a or the upper substrate plate 202b. For example, buffer layer 206 can have a porosity of from about 2% to about 10%, more preferably from about 2% to about 7%. When the porosity of the buffer layer 206 may exceed about 10%, the porosity in the buffer layer tends to be excessive, which reduces the strength of the buffer layer 206, and finally separates the buffer layer 206 from the insulating member 205 and the substrate plate 202. When the porosity is less than about 2%, cracks are easily and rapidly generated, so that it is possible to make the buffer layer 206 difficult to absorb thermal stress.
又，緩衝層206之邊緣部分可能被形成為圓形或被倒角，從而將尖銳部分移離緩衝層206。當緩衝層包含尖銳邊緣部分時，熱應力可能集中於尖銳部分，而龜裂可能從緩衝層206之尖銳邊緣部分急速成長。Also, the edge portion of the buffer layer 206 may be formed to be circular or chamfered to move the sharp portion away from the buffer layer 206. When the buffer layer contains a sharp edge portion, thermal stress may concentrate on the sharp portion, and the crack may rapidly grow from the sharp edge portion of the buffer layer 206.
再請參照第2圖，由於在ESC 200之中央部分之本體201之傾斜部S，使得下基底平板202a之中央厚度A可能大於下基底平板202a之周邊厚度B。因此，下基底平板202a在ESC 200之中央部分之密度可能小於在ESC 200之周邊部分之密度。然而，由於下基底平板202a之較大厚度，可充分減少經由位於ESC 200之中央部分之下基底平板202a之孔隙之電流洩漏，藉以避免在本體201與電極203之間形成弧狀(arcing)。Referring again to FIG. 2, the central thickness A of the lower base plate 202a may be greater than the peripheral thickness B of the lower base plate 202a due to the inclined portion S of the body 201 at the central portion of the ESC 200. Therefore, the density of the lower substrate plate 202a at the central portion of the ESC 200 may be less than the density at the peripheral portion of the ESC 200. However, due to the large thickness of the lower substrate plate 202a, current leakage through the apertures of the substrate plate 202a below the central portion of the ESC 200 can be substantially reduced to avoid arcing between the body 201 and the electrode 203.
此外，因為下基底平板202a於ESC 200之中央部分可具有較大厚度，所以可充分避免龜裂產生於本體201與絕緣構件205之第一邊界區域，藉以避免在本體201與電極203之間形成弧狀(arcing)。In addition, since the lower base plate 202a can have a large thickness in the central portion of the ESC 200, cracks can be sufficiently prevented from being generated in the first boundary region between the body 201 and the insulating member 205 to avoid formation between the body 201 and the electrode 203. Arcing.
一黏著層(未顯示)可能介設於本體201與下基底平板202a之間，藉以堅穩地固定本體201與下基底平板202a至彼此。黏著層之熱係數可能在本體之熱係數與下基底平板202a之熱係數之間改變，從而使本體201之熱應力可能被吸收至黏著層，且無法整體被施加至下基底平板202a。黏著層可包含例如鎳-鋁合金之金屬合金。An adhesive layer (not shown) may be interposed between the body 201 and the lower substrate plate 202a, thereby firmly fixing the body 201 and the lower substrate plate 202a to each other. The thermal coefficient of the adhesive layer may vary between the thermal coefficient of the body and the thermal coefficient of the lower substrate plate 202a, so that the thermal stress of the body 201 may be absorbed to the adhesive layer and cannot be applied to the lower substrate plate 202a as a whole. The adhesive layer may comprise a metal alloy such as a nickel-aluminum alloy.
請再參見第2圖，下基底平板202a可能以下述配置而形成於本體201、端子204與絕緣構件205上：下基底平板202a之一上表面可能高於位在ESC 200之周邊部分之端子204之上表面。因此，上基底平板202b在ESC之中央部分之中央厚度C可能大於在ESC 200之周邊部分之一周邊厚度D。因此，當可能經由端子204而將高電壓施加至電極203時，可充分避免在電極203與安置於上基底平板202b上之基板之間之電弧。Referring to FIG. 2 again, the lower substrate plate 202a may be formed on the body 201, the terminal 204 and the insulating member 205 in a configuration in which the upper surface of one of the lower substrate plates 202a may be higher than the terminal 204 located at the peripheral portion of the ESC 200. Above the surface. Therefore, the central thickness C of the upper base plate 202b at the central portion of the ESC may be greater than the peripheral thickness D of one of the peripheral portions of the ESC 200. Therefore, when a high voltage is likely to be applied to the electrode 203 via the terminal 204, an arc between the electrode 203 and the substrate disposed on the upper substrate plate 202b can be sufficiently avoided.
以下，可詳細說明顯示於第2圖之ESC 200之製造方法。Hereinafter, the manufacturing method of the ESC 200 shown in Fig. 2 can be described in detail.
首先，可將端子單元裝設至本體201。端子單元可包含端子204、絕緣構件205與緩衝層206。在操作ESC 200時，端子204可電連接至一外部電源。絕緣構件205可包圍端子204，從而可使本體201與端子204達到彼此電氣絕緣。緩衝層206可能形成於絕緣構件205之一部分上，並可吸收在ESC 200中之熱應力，藉以減少由於熱應力所導致之ESC 200之龜裂。First, the terminal unit can be mounted to the body 201. The terminal unit may include a terminal 204, an insulating member 205, and a buffer layer 206. When operating the ESC 200, the terminal 204 can be electrically connected to an external power source. The insulating member 205 can surround the terminal 204 such that the body 201 and the terminal 204 can be electrically insulated from each other. The buffer layer 206 may be formed on a portion of the insulating member 205 and may absorb thermal stress in the ESC 200 to reduce cracking of the ESC 200 due to thermal stress.
具有一預先決定的尺寸與形狀之一絕緣體(未顯示)可被處理，且端子204可個別被製備。然後，可將端子204***至並穿過被處理之絕緣體，從而使端子204與絕緣體之組合可利用端子可能局部地被絕緣體封閉之這樣的配置而設置。包圍端子204之絕緣體可發揮絕緣構件205之功能。然後，可將緩衝層206形成於端子204之一部分上。舉例而言，可將絕緣體移離端子204之末端部分，藉以於端子204形成緩衝區域。於端子204之末端部分，可將緩衝層206形成於緩衝區域上。An insulator (not shown) having a predetermined size and shape can be processed, and the terminals 204 can be separately prepared. Terminal 204 can then be inserted into and through the insulator being processed such that the combination of terminal 204 and insulator can be provided in such a configuration that the terminal may be partially enclosed by an insulator. The insulator surrounding the terminal 204 can function as the insulating member 205. The buffer layer 206 can then be formed on a portion of the terminal 204. For example, the insulator can be moved away from the end portion of the terminal 204, whereby the terminal 204 forms a buffer region. At the end portion of the terminal 204, a buffer layer 206 may be formed on the buffer region.
此外，端子204與絕緣構件205之邊緣部分可能形成為圓形或被倒角。然後，可藉由一平坦化製程而將緩衝層206平坦化，藉以縮小表面粗糙度。包含端子204、絕緣構件205與緩衝層206之端子單元可能貫穿本體201之穿孔207，藉以結合端子單元與本體201。Further, the terminal portion 204 and the edge portion of the insulating member 205 may be formed in a circular shape or chamfered. Then, the buffer layer 206 can be planarized by a planarization process to reduce the surface roughness. The terminal unit including the terminal 204, the insulating member 205 and the buffer layer 206 may penetrate through the through hole 207 of the body 201, thereby combining the terminal unit and the body 201.
然後，基底平板202可能依據以下配置而形成於本體201上：使電極203可能裝設於基底平板202之內部中。亦即，下基底平板202a係首先形成於本體201上，而電極層(未顯示)可能形成於下基底平板202a上。電極層可能被圖案化成為於下基底平板202a上之電極203。然後，上基底平板202b形成在下基底平板202a上，以達到足夠的厚度來覆蓋電極203。Then, the substrate plate 202 may be formed on the body 201 according to the following configuration: the electrode 203 may be installed in the interior of the substrate plate 202. That is, the lower substrate plate 202a is first formed on the body 201, and an electrode layer (not shown) may be formed on the lower substrate plate 202a. The electrode layer may be patterned into the electrode 203 on the lower substrate plate 202a. Then, the upper substrate plate 202b is formed on the lower substrate plate 202a to a sufficient thickness to cover the electrode 203.
更明確而言，可分別於下基底平板202a之表面上，於電極層之表面上，以及於上基底平板202b之表面上執行平坦化製程，藉以充分縮小表面粗糙度及增加表面平滑度。More specifically, a planarization process can be performed on the surface of the lower substrate plate 202a, on the surface of the electrode layer, and on the surface of the upper substrate plate 202b, thereby sufficiently reducing the surface roughness and increasing the surface smoothness.
於本實施示範例中，下基底平板202a可能依據以下配置而形成於本體201上：使貫穿本體201之端子204之一上表面無法被下基底平板202a覆蓋。舉例而言，在形成下基底平板202a之前，可提早形成一遮罩層(未顯示)於端子204之上表面上，並可在形成下基底平板202a以後，將遮罩層移離端子204。否則，一預備下基底平板(未顯示)可能形成於本體201上，且預備下基底平板之一中央部分可能局部被移離本體201，藉以形成一開口(未顯示)，使端子204之上表面經由此開口露出。In the present embodiment, the lower substrate plate 202a may be formed on the body 201 according to the following configuration: the upper surface of one of the terminals 204 penetrating the body 201 cannot be covered by the lower substrate plate 202a. For example, a mask layer (not shown) may be formed on the upper surface of the terminal 204 before the lower substrate plate 202a is formed, and the mask layer may be removed from the terminal 204 after the lower substrate plate 202a is formed. Otherwise, a preparatory lower substrate plate (not shown) may be formed on the body 201, and a central portion of the preliminary lower substrate plate may be partially removed from the body 201, thereby forming an opening (not shown) for the upper surface of the terminal 204. It is exposed through this opening.
依據某些實施示範例，ESC之熱應力可能被吸收至ESC中之緩衝層，從而可能充分減少由熱應力所導致的龜裂，藉以增加ESC之耐久性壽命。According to certain embodiments, the thermal stress of the ESC may be absorbed into the buffer layer in the ESC, thereby possibly reducing the crack caused by the thermal stress, thereby increasing the durability life of the ESC.
上述內容係用以說明實施示範例，且並非被解釋成對其作出特別限制。雖然已說明一些實施示範例，但是熟習本項技藝者將輕易地明白到，在實質上不背離本發明之嶄新教導與優點的情況下，仍可能對實施示範例作出各種變形例。因此，所有的這些變形例係意圖被涵蓋在在申請專利範圍中所界定的本發明之範疇之內。在申請專利範圍中，手段加功能子句意圖涵蓋說明於此之構造，如執行引用之功能，以及不但是構造的等效設計，而且是等效構造。因此，吾人應理解到上述內容係用以說明各種實施示範例，但並非被解釋成受限於所揭露之特定實施示範例，且對於所揭露之實施示範例所作之變形例以及其他實施示範例係意圖被涵蓋在以下的申請專利範圍之範疇之內。The above is intended to be illustrative of the embodiments and is not to be construed as limiting. While a few embodiments have been described, it will be apparent to those skilled in the art that various modifications of the embodiments may be made without departing from the scope of the invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the scope of the claims. In the scope of the patent application, the means plus function clauses are intended to cover the constructions described herein, such as the function of performing the reference, and the equivalent design of the construction, and the equivalent construction. Therefore, the above description is to be understood as illustrative of the various embodiments of the invention, but is not to be construed as limited It is intended to be included within the scope of the following patent application.
A．．．上端部/上部/中央厚度A. . . Upper end / upper / central thickness
B．．．周邊厚度B. . . Peripheral thickness
C．．．中央厚度C. . . Central thickness
D．．．周邊厚度D. . . Peripheral thickness
S．．．傾斜部S. . . Inclined portion
100．．．靜電夾頭100. . . Electrostatic chuck
101．．．本體101. . . Ontology
102．．．基底平板102. . . Base plate
103．．．電極103. . . electrode
104．．．端子104. . . Terminal
105．．．絕緣構件105. . . Insulating member
200．．．靜電夾頭200. . . Electrostatic chuck
201．．．本體201. . . Ontology
202．．．基底平板202. . . Base plate
202a．．．下基底平板202a. . . Lower base plate
202b．．．上基底平板202b. . . Upper substrate
203．．．電極203. . . electrode
204．．．端子204. . . Terminal
205．．．絕緣構件205. . . Insulating member
206．．．緩衝層206. . . The buffer layer
207．．．穿孔207. . . perforation
208．．．***部208. . . Insertion
第1圖係為顯示在處理腔室中之習知之靜電夾頭之剖面圖。Figure 1 is a cross-sectional view of a conventional electrostatic chuck shown in a processing chamber.
第2圖係為顯示依據本發明的概念之實施示範例之靜電夾頭之剖面圖。Figure 2 is a cross-sectional view showing an electrostatic chuck according to an exemplary embodiment of the concept of the present invention.
A．．．中央厚度A. . . Central thickness
B．．．周邊厚度B. . . Peripheral thickness
C．．．中央厚度C. . . Central thickness
D．．．周邊厚度D. . . Peripheral thickness
S．．．傾斜部S. . . Inclined portion
200．．．靜電夾頭200. . . Electrostatic chuck
201．．．本體201. . . Ontology
202．．．基底平板202. . . Base plate
202a．．．下基底平板202a. . . Lower base plate
202b．．．上基底平板202b. . . Upper substrate
203．．．電極203. . . electrode
204．．．端子204. . . Terminal
205．．．絕緣構件205. . . Insulating member
206．．．緩衝層206. . . The buffer layer
207．．．穿孔207. . . perforation
208．．．***部208. . . Insertion
Claims (14)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080088972A KR100995250B1 (en) | 2008-09-09 | 2008-09-09 | Electrostatic chuck containing buffer layer for reducing thermal stress |
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| Publication Number | Publication Date |
|---|---|
| TW201021154A TW201021154A (en) | 2010-06-01 |
| TWI401768B true TWI401768B (en) | 2013-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW098130090A TWI401768B (en) | 2008-09-09 | 2009-09-07 | Electrostatic chuck containing buffer layer for reducing thermal stress |
Country Status (4)
| Country | Link |
|---|---|
| KR (1) | KR100995250B1 (en) |
| CN (2) | CN103227138A (en) |
| TW (1) | TWI401768B (en) |
| WO (1) | WO2010030102A2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI785282B (en) * | 2018-11-09 | 2022-12-01 | 日商科理克股份有限公司 | thermostat |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102610476B (en) * | 2012-03-12 | 2015-05-27 | 中微半导体设备(上海)有限公司 | Electrostatic chuck |
| KR101974386B1 (en) * | 2012-03-21 | 2019-05-03 | 주식회사 미코 | Electrode static chuck |
| KR102119867B1 (en) * | 2013-10-21 | 2020-06-09 | 주식회사 미코세라믹스 | Electrostatic chuck |
| US11420278B2 (en) * | 2018-06-28 | 2022-08-23 | Spirit Aerosystems, Inc. | System and method employing active thermal buffer element for improved joule heating |
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| JPH11111827A (en) * | 1997-10-08 | 1999-04-23 | Tokyo Electron Ltd | Holding device and processing device mounting the same |
| JP2001287130A (en) * | 2000-04-07 | 2001-10-16 | Taiheiyo Cement Corp | Electrostatic chuck device and its manufacturing method |
| JP2001313331A (en) * | 2000-04-28 | 2001-11-09 | Sumitomo Osaka Cement Co Ltd | Electrostatic attraction device |
| TW517326B (en) * | 2000-08-16 | 2003-01-11 | Creative Tech Corp | Electrostatic chucking device and manufacturing method thereof |
| TW526672B (en) * | 1999-09-29 | 2003-04-01 | Tokyo Electron Ltd | Heater for heating a substrate in a processing gas within a processing reactor, multi-zone heater for heating a substrate in a processing gas within a processing reactor, and method of measuring clamping of a substrate to an electrostatic chuck |
| KR20030044499A (en) * | 2001-11-30 | 2003-06-09 | 삼성전자주식회사 | Electro static chuck and Method of Manufacturing Thereof |
| EP0899986B1 (en) * | 1996-05-05 | 2004-11-24 | Tateho Chemical Industries Co., Ltd. | Electric heating element and electrostatic chuck using the same |
| KR20070093583A (en) * | 2006-03-14 | 2007-09-19 | 주식회사 에이디피엔지니어링 | Esc, support table, chamber and the manufacture methods thereof |
| TW200746341A (en) * | 2005-10-06 | 2007-12-16 | Lam Res Corp | Electrostatic chuck having radial temperature control capability |
| US20080174930A1 (en) * | 2006-09-13 | 2008-07-24 | Ngk Insulators, Ltd. | Electrostatic chuck with heater and manufacturing method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3771722B2 (en) * | 1998-07-31 | 2006-04-26 | 京セラ株式会社 | Wafer support member |
| JP3859914B2 (en) * | 1999-10-08 | 2006-12-20 | 東芝セラミックス株式会社 | Ceramic-metal composite part having metal terminal and method for manufacturing the same |
| JP4510745B2 (en) * | 2005-10-28 | 2010-07-28 | 日本碍子株式会社 | Bonding structure of ceramic substrate and power supply connector |
| EP2065926B1 (en) * | 2006-09-19 | 2011-11-16 | Creative Technology Corporation | Feeding structure of electrostatic chuck, method for producing the same, and method for regenerating feeding structure of electrostatic chuck |
-
2008
- 2008-09-09 KR KR1020080088972A patent/KR100995250B1/en active IP Right Grant
-
2009
- 2009-09-07 TW TW098130090A patent/TWI401768B/en active
- 2009-09-08 CN CN2013101207103A patent/CN103227138A/en active Pending
- 2009-09-08 CN CN200980135897.6A patent/CN102150233B/en active Active
- 2009-09-08 WO PCT/KR2009/005070 patent/WO2010030102A2/en active Application Filing
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0899986B1 (en) * | 1996-05-05 | 2004-11-24 | Tateho Chemical Industries Co., Ltd. | Electric heating element and electrostatic chuck using the same |
| JPH11111827A (en) * | 1997-10-08 | 1999-04-23 | Tokyo Electron Ltd | Holding device and processing device mounting the same |
| TW526672B (en) * | 1999-09-29 | 2003-04-01 | Tokyo Electron Ltd | Heater for heating a substrate in a processing gas within a processing reactor, multi-zone heater for heating a substrate in a processing gas within a processing reactor, and method of measuring clamping of a substrate to an electrostatic chuck |
| JP2001287130A (en) * | 2000-04-07 | 2001-10-16 | Taiheiyo Cement Corp | Electrostatic chuck device and its manufacturing method |
| JP2001313331A (en) * | 2000-04-28 | 2001-11-09 | Sumitomo Osaka Cement Co Ltd | Electrostatic attraction device |
| TW517326B (en) * | 2000-08-16 | 2003-01-11 | Creative Tech Corp | Electrostatic chucking device and manufacturing method thereof |
| KR20030044499A (en) * | 2001-11-30 | 2003-06-09 | 삼성전자주식회사 | Electro static chuck and Method of Manufacturing Thereof |
| TW200746341A (en) * | 2005-10-06 | 2007-12-16 | Lam Res Corp | Electrostatic chuck having radial temperature control capability |
| KR20070093583A (en) * | 2006-03-14 | 2007-09-19 | 주식회사 에이디피엔지니어링 | Esc, support table, chamber and the manufacture methods thereof |
| US20080174930A1 (en) * | 2006-09-13 | 2008-07-24 | Ngk Insulators, Ltd. | Electrostatic chuck with heater and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI785282B (en) * | 2018-11-09 | 2022-12-01 | 日商科理克股份有限公司 | thermostat |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010030102A2 (en) | 2010-03-18 |
| CN102150233B (en) | 2014-10-15 |
| CN102150233A (en) | 2011-08-10 |
| KR20100030168A (en) | 2010-03-18 |
| KR100995250B1 (en) | 2010-11-18 |
| CN103227138A (en) | 2013-07-31 |
| WO2010030102A3 (en) | 2010-07-01 |
| TW201021154A (en) | 2010-06-01 |
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