TWI400807B - Thin film transistor - Google Patents
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- TWI400807B TWI400807B TW98129472A TW98129472A TWI400807B TW I400807 B TWI400807 B TW I400807B TW 98129472 A TW98129472 A TW 98129472A TW 98129472 A TW98129472 A TW 98129472A TW I400807 B TWI400807 B TW I400807B
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本發明涉及一薄膜電晶體，尤其涉及一種基於奈米碳管的薄膜電晶體。 The present invention relates to a thin film transistor, and more particularly to a thin film transistor based on a carbon nanotube.
薄膜電晶體(Thin Film Transistor,TFT)係現代微電子技術中的一種關鍵性電子元件，目前已經被廣泛的應用於平板顯示器等領域。薄膜電晶體主要包括閘極、絕緣層、半導體層、源極及汲極。其中，源極及汲極間隔設置並與半導體層電連接，閘極通過絕緣層與半導體層、源極及汲極間隔絕緣設置。所述半導體層位於所述源極及汲極之間的區域形成一通道區域。薄膜電晶體中的閘極、源極、汲極均由導電材料構成，該導電材料一般為金屬或合金。當在閘極上施加一電壓時，與閘極通過絕緣層間隔設置的半導體層中的通道區域會積累載流子，當載流子積累到一定程度，與半導體層電連接的源極、汲極之間將導通，從而有電流從源極流向汲極。 Thin Film Transistor (TFT) is a key electronic component in modern microelectronics technology and has been widely used in flat panel displays and other fields. The thin film transistor mainly includes a gate, an insulating layer, a semiconductor layer, a source, and a drain. The source and the drain are spaced apart from each other and electrically connected to the semiconductor layer, and the gate is insulated from the semiconductor layer, the source and the drain by an insulating layer. The semiconductor layer is located in a region between the source and the drain to form a channel region. The gate, the source and the drain of the thin film transistor are each composed of a conductive material, which is generally a metal or an alloy. When a voltage is applied to the gate, the channel region in the semiconductor layer spaced apart from the gate through the insulating layer accumulates carriers, and when the carrier accumulates to a certain extent, the source and the drain are electrically connected to the semiconductor layer. It will be turned on so that current flows from the source to the drain.
先前技術中的薄膜電晶體半導體層的材料為非晶矽、多晶矽或有機半導體聚合物等，絕緣層的材料為氮化矽等絕緣材料，源極、汲極及閘極為導電金屬層(R.E.I.Schropp,B. Stannowski,J.K.Rath,New challenges in thin film transistor research,Journal of Non-Crystalline Solids,299-302,1304-1310(2002))。然而採用金屬層形成的源極、汲極及閘極具有機械性能不好等缺點，並且當用於柔性薄膜電晶體時，金屬層在多次使用後由於基板的彎折易脫落及損壞，從而容易導致薄膜電晶體的耐用性差，壽命較短。另外，採用金屬層形成的源極、汲極及閘極耐高溫性能不好，在較高的溫度下金屬會融化導致薄膜電晶體結構破壞。 The material of the thin film transistor semiconductor layer in the prior art is an amorphous germanium, a polycrystalline germanium or an organic semiconductor polymer. The insulating layer is made of an insulating material such as tantalum nitride, and the source, the drain and the gate are extremely conductive metal layers (REISchropp). , B. Stannowski, J. K. Rath, New challenges in thin film transistor research, Journal of Non-Crystalline Solids, 299-302, 1304-1310 (2002)). However, the source, the drain and the gate formed by the metal layer have disadvantages such as poor mechanical properties, and when used in a flexible thin film transistor, the metal layer is easily peeled off and damaged due to bending of the substrate after repeated use. It is easy to cause poor durability of the thin film transistor and short life. In addition, the source, the drain and the gate formed by the metal layer have poor high temperature resistance, and the metal melts at a relatively high temperature to cause destruction of the thin film transistor structure.
有鑒於此，實為必要提供具有較好的柔韌性及耐高溫性能的薄膜電晶體。 In view of this, it is necessary to provide a thin film transistor having better flexibility and high temperature resistance.
一種薄膜電晶體，包括一源極、一汲極、一半導體層及一閘極。該汲極與該源極間隔設置。該半導體層與該源極及汲極電連接。該閘極通過一絕緣層與該半導體層、源極及汲極絕緣設置。該源極、汲極及/或閘極分別包括一奈米碳管金屬複合層，該奈米碳管金屬複合層包括一奈米碳管層及包覆於該奈米碳管層表面的金屬層，所述奈米碳管層包括複數奈米碳管通過凡德瓦爾力相互連接組成一自支撐結構。 A thin film transistor includes a source, a drain, a semiconductor layer and a gate. The drain is spaced from the source. The semiconductor layer is electrically connected to the source and the drain. The gate is insulated from the semiconductor layer, the source and the drain by an insulating layer. The source, the drain and/or the gate respectively comprise a carbon nanotube metal composite layer, the carbon nanotube metal composite layer comprising a carbon nanotube layer and a metal coated on the surface of the carbon nanotube layer The layer, the carbon nanotube layer comprises a plurality of carbon nanotubes interconnected by a van der Waals force to form a self-supporting structure.
與現有技術相比較，本發明實施例提供的採用奈米碳管金屬複合層作為源極、汲極及/或閘極的薄膜電晶體具有以下優點：其一，奈米碳管的優異的力學特性使得奈米碳管金屬複合層具有很好的韌性及機械強度，故，採用奈米碳管金屬複 合層代替先前的金屬層作源極、汲極及閘極，可以相應的提高薄膜電晶體的耐用性，尤其適用於柔性薄膜電晶體；其二，由於奈米碳管金屬複合層中的奈米碳管的結構在高溫下不會受到影響，故採用奈米碳管金屬複合層的源極、汲極及閘極在高溫下能夠正常工作，使薄膜電晶體具有很好的耐高溫性能。 Compared with the prior art, the thin film transistor using the carbon nanotube metal composite layer as the source, the drain and/or the gate provided by the embodiment of the invention has the following advantages: First, the excellent mechanics of the carbon nanotube The characteristics make the carbon nanotube metal composite layer have good toughness and mechanical strength. Therefore, the carbon nanotube metal complex is used. Replacing the previous metal layer as the source, drain and gate can improve the durability of the thin film transistor, especially for flexible thin film transistors; second, due to the nano tube in the carbon nanotube metal composite layer The structure of the carbon nanotubes is not affected at high temperatures, so the source, the drain and the gate of the carbon nanotube metal composite layer can work normally at high temperatures, so that the thin film transistor has good high temperature resistance.
10‧‧‧薄膜電晶體 10‧‧‧film transistor
20‧‧‧奈米碳管金屬復合層 20‧‧‧Nano carbon tube metal composite layer
21‧‧‧奈米碳管 21‧‧‧Nano Carbon Tube
22‧‧‧潤濕層 22‧‧‧ Wetting layer
23‧‧‧過渡層 23‧‧‧Transition layer
24‧‧‧導電層 24‧‧‧ Conductive layer
25‧‧‧抗氧化層 25‧‧‧Antioxidant layer
26‧‧‧強化層 26‧‧‧ Strengthening layer
28‧‧‧薄膜電晶體 28‧‧‧film transistor
100‧‧‧薄膜電晶體面板 100‧‧‧film transistor panel
110‧‧‧絕緣基板 110‧‧‧Insert substrate
120‧‧‧閘極 120‧‧‧ gate
130‧‧‧絕緣層 130‧‧‧Insulation
140‧‧‧半導體層 140‧‧‧Semiconductor layer
142‧‧‧半導體層的第一表面 142‧‧‧The first surface of the semiconductor layer
144‧‧‧半導體層的第二表面 144‧‧‧Second surface of the semiconductor layer
151‧‧‧源極 151‧‧‧ source
152‧‧‧汲極 152‧‧‧汲polar
156‧‧‧通道 156‧‧‧ channel
200‧‧‧薄膜電晶體面板 200‧‧‧film transistor panel
210‧‧‧絕緣基板 210‧‧‧Insert substrate
220‧‧‧閘極 220‧‧‧ gate
230‧‧‧絕緣層 230‧‧‧Insulation
240‧‧‧半導體層 240‧‧‧Semiconductor layer
251‧‧‧源極 251‧‧‧ source
252‧‧‧汲極 252‧‧‧汲polar
256‧‧‧通道 256‧‧‧ channel
圖1係本發明第一實施例薄膜電晶體的剖視結構示意圖。 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional structural view showing a thin film transistor of a first embodiment of the present invention.
圖2係本發明第一實施例薄膜電晶體中的奈米碳管金屬複合層的結構示意圖。 2 is a schematic view showing the structure of a carbon nanotube metal composite layer in a thin film transistor according to a first embodiment of the present invention.
圖3係本發明第一實施例薄膜電晶體中的奈米碳管金屬複合層中單根奈米碳管的結構示意圖。 3 is a schematic view showing the structure of a single carbon nanotube in a carbon nanotube metal composite layer in a thin film transistor according to a first embodiment of the present invention.
圖4係本發明第一實施例薄膜電晶體的工作狀態圖。 Fig. 4 is a view showing the operation state of the thin film transistor of the first embodiment of the present invention.
圖5係本發明第二實施例薄膜電晶體的剖視結構示意圖。 Fig. 5 is a cross-sectional structural view showing a thin film transistor of a second embodiment of the present invention.
以下將結合附圖詳細說明本發明實施例提供的薄膜電晶體。 Hereinafter, a thin film transistor according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
請參閱圖1，本發明第一實施例提供一種薄膜電晶體面板100，該薄膜電晶體面板100包括一絕緣基板110及複數形成於該絕緣基板110表面的薄膜電晶體10(圖中僅以一個為例)。 Referring to FIG. 1 , a first embodiment of the present invention provides a thin film transistor panel 100 including an insulating substrate 110 and a plurality of thin film transistors 10 formed on the surface of the insulating substrate 110 (only one in the figure) For example).
所述絕緣基板110起支撐作用，其材料可選擇為玻璃、石英、陶瓷、金剛石、矽片等硬性材料或塑膠、樹脂等柔性材料。本實施例中，所述絕緣基板110的材料為玻璃。所述絕緣 基板110用於對薄膜電晶體10提供支撐。所述絕緣基板110也可選用大型積體電路中的基板，且多個薄膜電晶體10可按照預定規律或圖形集成於同一絕緣基板110上，形成薄膜電晶體面板或其他薄膜電晶體半導體器件。 The insulating substrate 110 serves as a supporting material, and the material thereof may be selected from a hard material such as glass, quartz, ceramic, diamond, cymbal or the like, or a flexible material such as plastic or resin. In this embodiment, the material of the insulating substrate 110 is glass. The insulation The substrate 110 is used to provide support for the thin film transistor 10. The insulating substrate 110 can also be selected from a substrate in a large integrated circuit, and the plurality of thin film transistors 10 can be integrated on the same insulating substrate 110 according to a predetermined pattern or pattern to form a thin film transistor panel or other thin film transistor semiconductor device.
該薄膜電晶體10可以為頂柵型，其包括一半導體層140、一源極151、一汲極152、一絕緣層130及一閘極120。所述半導體層140具有相對的第一表面142及第二表面144。所述半導體層140設置於所述絕緣基板110的表面，且所述半導體層140通過其第一表面142與絕緣基板110的表面相連接。所述源極151及汲極152間隔設置於所述半導體層140的第二表面144上。所述絕緣層130設置於所述半導體層140的第二表面144。所述閘極120設置於所述絕緣層130表面。所述閘極120通過該絕緣層130與該半導體層140及源極151及汲極152絕緣設置。所述半導體層140位於所述源極151及汲極152之間的區域形成一通道156。所述源極151及汲極152的設置位置不限，只要確保所述源極151及汲極152間隔設置，並與所述半導體層140電接觸即可。具體地，所述源極151及汲極152可以間隔設置於所述半導體層140的第二表面144並位於所述絕緣層130與半導體層140之間。此時，源極151、汲極152與閘極120設置於半導體層140的同一側，形成一共面型薄膜電晶體10。可以理解的是，所述源極151及汲極152還可以間隔設置於所述半導體層140的第一表面142，此時，源極151、汲極152與閘極120設置於半導體層140的不同側，位於所述絕 緣基板110與半導體層140之間，形成一交錯型薄膜電晶體10。 The thin film transistor 10 can be a top gate type including a semiconductor layer 140, a source 151, a drain 152, an insulating layer 130, and a gate 120. The semiconductor layer 140 has opposing first and second surfaces 142, 144. The semiconductor layer 140 is disposed on a surface of the insulating substrate 110, and the semiconductor layer 140 is connected to a surface of the insulating substrate 110 through a first surface 142 thereof. The source 151 and the drain 152 are spaced apart from the second surface 144 of the semiconductor layer 140. The insulating layer 130 is disposed on the second surface 144 of the semiconductor layer 140. The gate 120 is disposed on a surface of the insulating layer 130. The gate 120 is insulated from the semiconductor layer 140 and the source 151 and the drain 152 by the insulating layer 130. The semiconductor layer 140 is located at a region between the source 151 and the drain 152 to form a channel 156. The installation positions of the source electrode 151 and the drain electrode 152 are not limited, as long as the source electrode 151 and the drain electrode 152 are spaced apart from each other and electrically contacted with the semiconductor layer 140. Specifically, the source 151 and the drain 152 may be disposed at intervals on the second surface 144 of the semiconductor layer 140 and between the insulating layer 130 and the semiconductor layer 140. At this time, the source 151, the drain 152 and the gate 120 are disposed on the same side of the semiconductor layer 140 to form a coplanar thin film transistor 10. It can be understood that the source 151 and the drain 152 may be disposed on the first surface 142 of the semiconductor layer 140. The source 151, the drain 152 and the gate 120 are disposed on the semiconductor layer 140. Different sides, located in the above A staggered thin film transistor 10 is formed between the edge substrate 110 and the semiconductor layer 140.
所述半導體層140的材料為非晶矽、多晶矽、有機半導體聚合物或半導體性奈米碳管等。優選地，所述半導體層140為一半導體性奈米碳管層。該半導體性奈米碳管層包括複數單壁或雙壁奈米碳管。所述單壁奈米碳管的直徑為0.5奈米~50奈米；所述雙壁奈米碳管的直徑為1.0奈米~50奈米。優選地，所述奈米碳管的直徑小於10奈米。具體地，所述奈米碳管層中可進一步僅包括一個半導體性奈米碳管薄膜，或包括複數重疊設置的半導體性奈米碳管薄膜，該半導體性奈米碳管薄膜為無序或者有序的半導體性奈米碳管薄膜。無序的半導體性奈米碳管薄膜中，半導體性奈米碳管為無序或各向同性排列。該無序排列的半導體性奈米碳管相互纏繞，該各向同性排列的半導體性奈米碳管平行於半導體性奈米碳管薄膜的表面。有序的半導體性奈米碳管薄膜中，半導體性奈米碳管為沿同一方向擇優取向排列或沿不同方向擇優取向排列。當半導體性奈米碳管層包括多層有序半導體性奈米碳管薄膜時，該多層半導體性奈米碳管薄膜可以沿任意方向重疊設置，因此，在該半導體性奈米碳管層中，半導體性奈米碳管為沿相同或不同方向擇優取向排列。本技術領域的技術人員應該明白，所述半導體性奈米碳管層可包括複數半導體性奈米碳管長線結構，所述半導體性奈米碳管長線結構包括複數首尾相連的半導體性奈米碳管束組成的束狀結構或由複數首尾相 連的半導體性奈米碳管束組成的絞線結構。本發明實施例中的半導體性奈米碳管層中包括兩個重疊的半導體性奈米碳管薄膜，相鄰的半導體性奈米碳管薄膜之間通過凡德瓦爾力緊密結合。每一半導體性奈米碳管薄膜包括複數擇優取向排列且通過凡德瓦爾力首尾相連的半導體性奈米碳管。相鄰的兩層半導體性奈米碳管薄膜中的半導體性奈米碳管形成一夾角α，且0°≦α≦90°。所述半導體層140採用半導體性奈米碳管層可以與源極151及汲極152中的奈米碳管金屬複合層更好的結合，有利於減少半導體層140與源極151及汲極152之間的接觸電阻。 The material of the semiconductor layer 140 is an amorphous germanium, a polycrystalline germanium, an organic semiconductor polymer, or a semiconducting carbon nanotube. Preferably, the semiconductor layer 140 is a semiconducting carbon nanotube layer. The semiconducting carbon nanotube layer comprises a plurality of single-wall or double-walled carbon nanotubes. The single-walled carbon nanotube has a diameter of 0.5 nm to 50 nm; and the double-walled carbon nanotube has a diameter of 1.0 nm to 50 nm. Preferably, the carbon nanotubes have a diameter of less than 10 nanometers. Specifically, the carbon nanotube layer may further include only one semiconducting carbon nanotube film, or include a plurality of stacked semiconducting carbon nanotube films, the semiconductor carbon nanotube film being disordered or Ordered semiconducting carbon nanotube film. In the disordered semiconductor carbon nanotube film, the semiconducting carbon nanotubes are disordered or isotropic. The disordered array of semiconducting carbon nanotubes are intertwined, and the isotropically arranged semiconducting carbon nanotubes are parallel to the surface of the semiconducting carbon nanotube film. In the ordered semiconducting carbon nanotube film, the semiconducting carbon nanotubes are arranged in a preferred orientation along the same direction or in a preferred orientation in different directions. When the semiconducting semiconducting carbon nanotube film comprises a plurality of ordered semiconducting carbon nanotube films, the multilayer semiconducting carbon nanotube film may be disposed in an overlapping manner in any direction, and therefore, in the semiconducting carbon nanotube layer, The semiconducting carbon nanotubes are arranged in a preferred orientation along the same or different directions. It should be understood by those skilled in the art that the semiconducting carbon nanotube layer may include a plurality of semiconducting carbon nanotube long-line structures including a plurality of semiconductor nanocarbons connected end to end. Bundle structure composed of bundles A twisted wire structure composed of a bundle of semiconducting carbon nanotubes. The semiconducting carbon nanotube layer in the embodiment of the invention comprises two overlapping semiconducting carbon nanotube films, and the adjacent semiconducting carbon nanotube films are tightly bonded by van der Waals force. Each of the semiconducting carbon nanotube films comprises a plurality of semiconducting carbon nanotubes arranged in a preferred orientation and connected end to end by van der Waals force. The semiconducting carbon nanotubes in the adjacent two layers of the semiconducting carbon nanotube film form an angle α of 0°≦α≦90°. The semiconductor layer 140 can be better combined with the carbon nanotube metal composite layer in the source 151 and the drain 152 by using the semiconducting carbon nanotube layer, which is advantageous for reducing the semiconductor layer 140 and the source 151 and the drain 152. Contact resistance between.
所述半導體層140的長度為1微米~100微米，寬度為1微米~1毫米，厚度為0.5奈米~100微米。所述通道156的長度為1微米~100微米，寬度為1微米~1毫米。本發明實施例中，所述半導體層140的長度為50微米，寬度為300微米，厚度為1微米。所述通道156的長度為40微米，寬度為300微米。 The semiconductor layer 140 has a length of 1 micrometer to 100 micrometers, a width of 1 micrometer to 1 millimeter, and a thickness of 0.5 nm to 100 micrometers. The channel 156 has a length of 1 micrometer to 100 micrometers and a width of 1 micrometer to 1 millimeter. In the embodiment of the present invention, the semiconductor layer 140 has a length of 50 micrometers, a width of 300 micrometers, and a thickness of 1 micrometer. The channel 156 has a length of 40 microns and a width of 300 microns.
所述絕緣層130材料為氮化矽、氧化矽等硬性材料或苯並環丁烯(BCB)、聚酯或丙烯酸樹脂等柔性材料。該絕緣層130的厚度為5奈米~100微米。本實施例中，所述絕緣層130的材料為氮化矽。可以理解，根據具體的形成工藝不同，所述絕緣層130不必完全覆蓋所述源極151、汲極152及半導體層140，只要能保證半導體層140、源極151及汲極152與其相對設置的閘極120絕緣即可。 The material of the insulating layer 130 is a hard material such as tantalum nitride or yttrium oxide or a flexible material such as benzocyclobutene (BCB), polyester or acrylic resin. The insulating layer 130 has a thickness of 5 nm to 100 μm. In this embodiment, the material of the insulating layer 130 is tantalum nitride. It can be understood that, according to a specific formation process, the insulating layer 130 does not have to completely cover the source 151, the drain 152, and the semiconductor layer 140, as long as the semiconductor layer 140, the source 151, and the drain 152 are disposed opposite thereto. The gate 120 can be insulated.
所述源極151、汲極152及/或閘極120為一奈米碳管金屬複合 層20，該奈米碳管金屬複合層20包括一奈米碳管層及包覆於該奈米碳管層表面的金屬層。所述金屬層包覆於所述奈米碳管層中每個奈米碳管的表面。優選地，所述源極151、汲極152及閘極120均為一奈米碳管金屬複合層。具體地，所述奈米碳管金屬複合層20中可僅包括一個奈米碳管金屬複合層，還可以為複數重疊設置的奈米碳管金屬複合層20。該奈米碳管金屬複合層20具有均勻的厚度。所述奈米碳管金屬複合層20的厚度為1.5奈米~1毫米。所述奈米碳管金屬複合層20的光透過率為70%-95%。 The source 151, the drain 152 and/or the gate 120 are a carbon nanotube metal composite The layer 20, the carbon nanotube metal composite layer 20 comprises a carbon nanotube layer and a metal layer coated on the surface of the carbon nanotube layer. The metal layer is coated on the surface of each of the carbon nanotubes in the carbon nanotube layer. Preferably, the source 151, the drain 152 and the gate 120 are each a carbon nanotube metal composite layer. Specifically, the carbon nanotube metal composite layer 20 may include only one carbon nanotube metal composite layer, and may also be a plurality of stacked carbon nanotube metal composite layers 20. The carbon nanotube metal composite layer 20 has a uniform thickness. The carbon nanotube metal composite layer 20 has a thickness of 1.5 nm to 1 mm. The carbon nanotube metal composite layer 20 has a light transmittance of 70% to 95%.
請參閱圖2，所述奈米碳管金屬複合層20包括一奈米碳管層及包覆於該奈米碳管層表面的一金屬層。具體地，所述奈米碳管層包括複數奈米碳管21通過凡德瓦爾力相互作用組成一自支撐結構，所述金屬層包覆於所述奈米碳管層中的每個奈米碳管21的表面。所述奈米碳管層包括一層奈米碳管膜或多層奈米碳管膜，且該多層奈米碳管膜並排設置或層疊設置。所述奈米碳管膜包括複數奈米碳管基本相互平行且平行於該奈米碳管膜的表面，該複數奈米碳管通過凡德瓦爾力首尾相連且基本沿同一方向擇優取向排列。所謂“自支撐”即該奈米碳管膜無需通過一支撐體支撐，也能保持自身特定的形狀。該自支撐的奈米碳管膜包括複數奈米碳管，該複數奈米碳管通過凡德瓦爾力相互吸引並首尾相連，從而使奈米碳管膜具有特定的形狀。該自支撐奈米碳管膜的厚度為0.5奈米~100微米。在該奈米碳管金屬複合層20中，奈米碳管21沿同 一個方向擇優取向排列。具體地，在該奈米碳管金屬複合層20中，每個奈米碳管21具有大致相等的長度，且通過凡德瓦爾力首尾相連。 Referring to FIG. 2, the carbon nanotube metal composite layer 20 includes a carbon nanotube layer and a metal layer coated on the surface of the carbon nanotube layer. Specifically, the carbon nanotube layer includes a plurality of carbon nanotubes 21 to form a self-supporting structure by van der Waals interaction, the metal layer coating each nanometer in the carbon nanotube layer The surface of the carbon tube 21. The carbon nanotube layer comprises a layer of carbon nanotube film or a plurality of layers of carbon nanotube film, and the plurality of layers of carbon nanotube film are arranged side by side or stacked. The carbon nanotube film comprises a plurality of carbon nanotubes substantially parallel to each other and parallel to a surface of the carbon nanotube film, the plurality of carbon nanotubes being connected end to end by van der Waals force and arranged in a preferred orientation in substantially the same direction. The so-called "self-supporting" means that the carbon nanotube film can maintain its own specific shape without being supported by a support. The self-supporting carbon nanotube film comprises a plurality of carbon nanotubes which are attracted to each other by van der Waals forces and are connected end to end, so that the carbon nanotube film has a specific shape. The self-supporting carbon nanotube film has a thickness of from 0.5 nm to 100 μm. In the carbon nanotube metal composite layer 20, the carbon nanotubes 21 are along One direction is preferred. Specifically, in the carbon nanotube metal composite layer 20, each of the carbon nanotubes 21 has substantially the same length and is connected end to end by Van der Waals force.
可選擇地，所述奈米碳管金屬複合層20包括複數奈米碳管金屬複合線狀結構相互連接組成一網狀結構。所述奈米碳管金屬複合線狀結構包括至少一奈米碳管線及包覆於該至少一奈米碳管線表面的金屬層。當所述奈米碳管金屬複合線狀結構包括至少兩個奈米碳管線時，該至少兩個奈米碳管線並排設置或交叉設置，且至少一個奈米碳管線的表面包覆一金屬層。所述奈米碳管線包括複數奈米碳管，該複數奈米碳管通過凡德瓦爾力首尾相連且沿著該奈米碳管線的軸向擇優取向排列或螺旋排列。其中，所述奈米碳管線中的每個奈米碳管的表面包覆一金屬層。另外，所述奈米碳管金屬複合線狀結構也可以包括至少一金屬奈米線及複合於該至少一金屬奈米線內部的奈米碳管。當所述奈米碳管金屬複合線狀結構包括至少兩個金屬奈米線，該至少兩個金屬奈米線並排設置或交叉設置，且至少有一個金屬奈米線的內部複合有奈米碳管。 Optionally, the carbon nanotube metal composite layer 20 comprises a plurality of carbon nanotube metal composite linear structures interconnected to form a network structure. The carbon nanotube metal composite wire structure comprises at least one nano carbon line and a metal layer coated on the surface of the at least one nano carbon line. When the carbon nanotube metal composite linear structure comprises at least two nano carbon pipelines, the at least two nanocarbon pipelines are arranged side by side or crosswise, and at least one surface of the nanocarbon pipeline is coated with a metal layer . The nanocarbon pipeline includes a plurality of carbon nanotubes connected end to end by a van der Waals force and arranged in a preferred orientation along the axial direction of the nanocarbon pipeline or spirally arranged. Wherein, the surface of each of the carbon nanotubes in the nanocarbon pipeline is coated with a metal layer. In addition, the carbon nanotube metal composite linear structure may also include at least one metal nanowire and a carbon nanotube compounded inside the at least one metal nanowire. When the carbon nanotube metal composite linear structure comprises at least two metal nanowires, the at least two metal nanowires are arranged side by side or crosswise, and at least one of the metal nanowires is internally composited with nanocarbon tube.
請同時參見圖3，該奈米碳管金屬複合層20中每一根奈米碳管21表面均包覆金屬層。具體地，該金屬層可包括與奈米碳管21表面直接結合的潤濕層22、設置在潤濕層22外的過渡層23、設置在過渡層23外的導電層24及設置在導電層24外的抗氧化層25。 Referring to FIG. 3 at the same time, the surface of each of the carbon nanotubes 21 in the carbon nanotube metal composite layer 20 is coated with a metal layer. Specifically, the metal layer may include a wetting layer 22 directly bonded to the surface of the carbon nanotube 21, a transition layer 23 disposed outside the wetting layer 22, a conductive layer 24 disposed outside the transition layer 23, and a conductive layer disposed thereon. Antioxidant layer 25 outside of 24.
由於奈米碳管21與大多數金屬之間的潤濕性不好，因此，所 述潤濕層22的作用為使導電層24與奈米碳管21更好的結合。形成該潤濕層22的導電材料可以為鐵、鈷、鎳、鈀或鈦等與奈米碳管21潤濕性好的金屬或它們的合金，該潤濕層22的厚度可以為1~10奈米(nm)。本實施例中，該潤濕層22的材料為鎳，厚度約為2奈米。可以理解，該潤濕層22為可選擇結構。 Due to the poor wettability between the carbon nanotubes 21 and most metals, The function of the wetting layer 22 is to better bond the conductive layer 24 to the carbon nanotubes 21. The conductive material forming the wetting layer 22 may be a metal such as iron, cobalt, nickel, palladium or titanium which is wettable with the carbon nanotubes 21 or an alloy thereof. The thickness of the wetting layer 22 may be 1 to 10. Nano (nm). In this embodiment, the wetting layer 22 is made of nickel and has a thickness of about 2 nm. It will be appreciated that the wetting layer 22 is of an alternative construction.
所述過渡層23的作用為使潤濕層22與導電層24更好的結合。形成該過渡層23的材料可以為與潤濕層22材料及導電層24材料均能較好結合的材料，該過渡層23的厚度為1奈米~10奈米。本實施例中，該過渡層23的材料為銅，厚度為2奈米。可以理解，該過渡層23為可選擇結構。 The transition layer 23 functions to better bond the wetting layer 22 to the conductive layer 24. The material forming the transition layer 23 may be a material which can be better combined with the material of the wetting layer 22 and the material of the conductive layer 24. The thickness of the transition layer 23 is from 1 nm to 10 nm. In this embodiment, the transition layer 23 is made of copper and has a thickness of 2 nm. It will be appreciated that the transition layer 23 is an optional structure.
所述導電層24的作用為使奈米碳管金屬複合層20具有較好的導電性能。形成該導電層24的材料可以為銅、銀或金等導電性好的金屬或其合金，該導電層24的厚度為1奈米~20奈米。本實施例中，該導電層24的材料為銀，厚度約為10奈米。 The conductive layer 24 functions to make the carbon nanotube metal composite layer 20 have better electrical conductivity. The material for forming the conductive layer 24 may be a conductive metal such as copper, silver or gold or an alloy thereof, and the conductive layer 24 has a thickness of 1 nm to 20 nm. In this embodiment, the conductive layer 24 is made of silver and has a thickness of about 10 nm.
所述抗氧化層25的作用為防止在奈米碳管金屬複合層20的製造過程中導電層24在空氣中被氧化，從而使奈米碳管金屬複合層20的導電性能下降。形成該抗氧化層25的材料可以為金或鉑等在空氣中不易氧化的穩定金屬或它們的合金。該抗氧化層25的厚度為1奈米~10奈米。本實施例中，該抗氧化層25的材料為鉑，其厚度為2奈米。可以理解，該抗氧化層25為可選擇結構。 The function of the oxidation resistant layer 25 is to prevent the conductive layer 24 from being oxidized in the air during the manufacturing process of the carbon nanotube metal composite layer 20, thereby degrading the electrical conductivity of the carbon nanotube metal composite layer 20. The material forming the oxidation resistant layer 25 may be a stable metal such as gold or platinum which is not easily oxidized in air or an alloy thereof. The thickness of the oxidation resistant layer 25 is from 1 nm to 10 nm. In this embodiment, the material of the oxidation resistant layer 25 is platinum and has a thickness of 2 nm. It will be appreciated that the oxidation resistant layer 25 is of an alternative construction.
進一步地，為提高奈米碳管金屬複合層20的強度，可在所述金屬層外進一步設置一強化層26。形成該強化層26的材料可以為聚乙烯醇(PVA)、聚苯撐苯並二惡唑(PBO)、聚乙烯(PE)或聚氯乙烯(PVC)等強度較高的聚合物，該強化層26的厚度為0.1微米~1微米。可以理解，該強化層26為可選擇結構。本實施例中，該強化層26的材料為聚乙烯醇(PVA)，厚度為0.5微米。 Further, in order to increase the strength of the carbon nanotube metal composite layer 20, a strengthening layer 26 may be further disposed outside the metal layer. The material forming the strengthening layer 26 may be a high strength polymer such as polyvinyl alcohol (PVA), polyphenylene benzobisoxazole (PBO), polyethylene (PE) or polyvinyl chloride (PVC). Layer 26 has a thickness of from 0.1 micron to 1 micron. It will be appreciated that the reinforcement layer 26 is an optional structure. In this embodiment, the reinforcing layer 26 is made of polyvinyl alcohol (PVA) and has a thickness of 0.5 μm.
本發明實施例中奈米碳管金屬複合層20的製備方法主要包括以下步驟： The preparation method of the carbon nanotube metal composite layer 20 in the embodiment of the invention mainly comprises the following steps:
步驟一：提供一奈米碳管膜。 Step 1: Provide a carbon nanotube film.
所述奈米碳管膜包括複數奈米碳管，相鄰的奈米碳管之間有間隙，且該奈米碳管平行於所述奈米碳管膜的表面。所述相鄰的奈米碳管之間的距離可大於奈米碳管的直徑。所述奈米碳管膜可具有自支撐結構。 The carbon nanotube membrane comprises a plurality of carbon nanotubes with a gap between adjacent carbon nanotubes, and the carbon nanotubes are parallel to the surface of the carbon nanotube membrane. The distance between the adjacent carbon nanotubes may be greater than the diameter of the carbon nanotubes. The carbon nanotube film may have a self-supporting structure.
步驟二：形成金屬層附著於所述奈米碳管膜表面。 Step 2: forming a metal layer attached to the surface of the carbon nanotube film.
所述形成金屬層附著於所述奈米碳管膜表面的方法可採用物理方法，如物理氣相沉積法(PVD)包括真空濺鍍或離子濺射等，也可採用化學方法，如電鍍或化學鍍等。優選地，本實施例採用物理方法中的真空濺鍍法形成所述金屬層附著於所述奈米碳管膜表面。 The method of forming a metal layer attached to the surface of the carbon nanotube film may be performed by a physical method such as physical vapor deposition (PVD) including vacuum sputtering or ion sputtering, or a chemical method such as electroplating or Electroless plating, etc. Preferably, the present embodiment forms the metal layer attached to the surface of the carbon nanotube film by vacuum sputtering in a physical method.
請參見圖4，使用時，所述源極151接地，在所述汲極152上施加一電壓Vds，在所述閘極120上施一電壓Vg，閘極120電 壓Vg在半導體層140中的通道156區域中產生電場，並在通道156區域靠近閘極120的表面處產生感應載流子。隨著閘極120電壓Vg的增加，所述通道156靠近閘極120的表面處逐漸轉變為載流子積累層，當載流子積累到一定程度時，就會在源極151及汲極152之間產生電流。該源極151與汲極152與應用該薄膜電晶體10的電子設備的相應控制部件相連接，閘極120用於在通道156區域中形成一電場，使半導體層140中積累載流子。因此，源極151、汲極152及閘極120應具有良好的導電性。由於所述奈米碳管金屬複合層具有較好的導電性，故由所述奈米碳管金屬複合層作為閘極120，可以為所述薄膜電晶體10提供穩定的閘極120電壓，進而提高薄膜電晶體10的回應速度，由所述奈米碳管金屬複合層作為源極151及汲極152，可以使所述薄膜電晶體10具有較好的輸入輸出性能。另外，當半導體層140為半導體性奈米碳管層時，由於半導體性奈米碳管具有較好的半導體性，故由所述半導體性奈米碳管組成的半導體性奈米碳管薄膜作為半導體層140，可以使所述薄膜電晶體10具有較大的載流子移動率，進而提高薄膜電晶體10的回應速度。本發明實施例中，所述薄膜電晶體10的載流子移動率高於10cm2/V-1s-1。開關電流比為1.0×102~1.0×106。 Referring to FIG. 4, in use, the source 151 is grounded, a voltage Vds is applied to the gate 152, a voltage Vg is applied to the gate 120, and the gate voltage Vg is in the semiconductor layer 140. An electric field is generated in the region of the channel 156, and induced carriers are generated at the surface of the channel 156 near the gate 120. As the gate voltage Vg increases, the channel 156 gradually changes to a carrier accumulation layer near the surface of the gate 120, and when the carrier accumulates to a certain extent, it is at the source 151 and the drain 152. A current is generated between them. The source 151 and the drain 152 are connected to respective control components of an electronic device to which the thin film transistor 10 is applied, and the gate 120 serves to form an electric field in the region of the channel 156 to accumulate carriers in the semiconductor layer 140. Therefore, the source 151, the drain 152, and the gate 120 should have good electrical conductivity. Since the carbon nanotube metal composite layer has good conductivity, the silicon carbide metal composite layer can serve as the gate 120, and the film transistor 10 can be provided with a stable gate 120 voltage. The response speed of the thin film transistor 10 is improved. The carbon nanotube metal composite layer is used as the source 151 and the drain 152, so that the thin film transistor 10 can have better input and output performance. In addition, when the semiconductor layer 140 is a semiconducting carbon nanotube layer, since the semiconducting carbon nanotube has good semiconductivity, the semiconducting carbon nanotube film composed of the semiconducting carbon nanotube is used as The semiconductor layer 140 can cause the thin film transistor 10 to have a large carrier mobility, thereby increasing the response speed of the thin film transistor 10. In the embodiment of the invention, the carrier mobility of the thin film transistor 10 is higher than 10 cm 2 /V -1 s -1 . The switching current ratio is 1.0 × 10 2 ~ 1.0 × 10 6 .
請參閱圖5，本發明第二實施例提供一種薄膜電晶體面板200，該薄膜電晶體面板200包括一絕緣基板210及複數薄膜電晶體28(圖中僅以一個為例)。該複數薄膜電晶體28形成於該 絕緣基板210表面。該薄膜電晶體28為背柵型，其包括一閘極220、一絕緣層230、一半導體層240、一源極251及一汲極252。該薄膜電晶體28設置在一絕緣基板210上。 Referring to FIG. 5, a second embodiment of the present invention provides a thin film transistor panel 200. The thin film transistor panel 200 includes an insulating substrate 210 and a plurality of thin film transistors 28 (only one of which is taken as an example). The plurality of thin film transistors 28 are formed in the The surface of the insulating substrate 210. The thin film transistor 28 is of a back gate type and includes a gate 220, an insulating layer 230, a semiconductor layer 240, a source 251, and a drain 252. The thin film transistor 28 is disposed on an insulating substrate 210.
本發明第二實施例薄膜電晶體28的結構與第一實施例中的薄膜電晶體10的結構基本相同，其區別在於：所述閘極220設置於所述絕緣基板210表面；所述絕緣層230設置於該閘極220表面；所述閘極220位於絕緣基板210及絕緣層230之間。所述半導體層240設置於該絕緣層230表面，所述絕緣層230位於所述半導體層240與所述閘極220之間，通過絕緣層230與閘極220絕緣設置；所述源極251及汲極252間隔設置並與所述半導體層240電接觸，該源極251、汲極252及半導體層240通過絕緣層230與所述閘極220電絕緣。所述半導體層240位於所述源極251及汲極252之間的區域形成一通道256。 The structure of the thin film transistor 28 of the second embodiment of the present invention is substantially the same as that of the thin film transistor 10 of the first embodiment, except that the gate 220 is disposed on the surface of the insulating substrate 210; the insulating layer 230 is disposed on the surface of the gate 220; the gate 220 is located between the insulating substrate 210 and the insulating layer 230. The semiconductor layer 240 is disposed on the surface of the insulating layer 230. The insulating layer 230 is disposed between the semiconductor layer 240 and the gate 220, and is insulated from the gate 220 by the insulating layer 230. The source 251 and The drain electrodes 252 are spaced apart from each other and in electrical contact with the semiconductor layer 240. The source electrode 251, the drain 252, and the semiconductor layer 240 are electrically insulated from the gate 220 by an insulating layer 230. The semiconductor layer 240 is located at a region between the source 251 and the drain 252 to form a channel 256.
所述源極251及汲極252可以間隔設置於該半導體層240的上表面，此時，源極251、汲極252與閘極220設置於半導體層140的不同面，形成一逆交錯型薄膜電晶體28。或者，所述源極251及汲極252可以間隔設置於該半導體層240的下表面，位於絕緣層230與半導體層240之間，此時，源極251、汲極252與閘極220設置於半導體層240的同一面，形成一逆共面型薄膜電晶體28。 The source 251 and the drain 252 may be disposed on the upper surface of the semiconductor layer 240. The source 251, the drain 252 and the gate 220 are disposed on different sides of the semiconductor layer 140 to form an inverted staggered film. Transistor 28. Alternatively, the source 251 and the drain 252 may be disposed on the lower surface of the semiconductor layer 240 between the insulating layer 230 and the semiconductor layer 240. At this time, the source 251, the drain 252 and the gate 220 are disposed on On the same side of the semiconductor layer 240, an inverse coplanar thin film transistor 28 is formed.
本發明實施例提供的採用奈米碳管金屬複合層的源極、汲極及/或閘極的薄膜電晶體具有以下優點：其一，奈米碳管的優異的力學特性使得奈米碳管金屬複合層具有很好的韌性及 機械強度，故，採用奈米碳管金屬複合層代替現有的金屬層作源極、汲極及閘極，可以相應的提高薄膜電晶體的耐用性，尤其適用於柔性薄膜電晶體；其二，由於奈米碳管金屬複合層中的奈米碳管的結構在高溫下不會受到影響，故採用奈米碳管金屬複合層的源極、汲極及閘極在高溫下能夠正常工作，使薄膜電晶體具有很好的耐高溫性能；其三，由於奈米碳管金屬複合層具有良好的導電性能，故，採用所述的奈米碳管金屬複合層作源極、汲極及閘極，可使得源極、汲極及閘極具有較好的導電性能；其四，由於奈米碳管具有較高的導熱係數，可以有效地將薄膜電晶體工作時所產生的熱量導出，從而有利於解決薄膜電晶體集成於大型積體電路中的散熱問題；其五，奈米碳管具有良好的透光性，因此，採用奈米碳管金屬複合層作源極、汲極及閘極可提高薄膜電晶體的透光性。 The thin film transistor using the source, the drain and/or the gate of the carbon nanotube metal composite layer provided by the embodiment of the invention has the following advantages: First, the excellent mechanical properties of the carbon nanotube make the carbon nanotube Metal composite layer has good toughness and Mechanical strength, therefore, the use of a carbon nanotube metal composite layer instead of the existing metal layer as the source, drain and gate, can correspondingly improve the durability of the thin film transistor, especially suitable for flexible thin film transistors; Since the structure of the carbon nanotubes in the carbon nanotube metal composite layer is not affected at high temperatures, the source, the drain and the gate of the carbon nanotube metal composite layer can work normally at high temperatures, so that The thin film transistor has good high temperature resistance; thirdly, since the carbon nanotube metal composite layer has good electrical conductivity, the carbon nanotube metal composite layer is used as the source, the drain and the gate. The source, the drain and the gate have better conductivity; and the fourth, because the carbon nanotube has a high thermal conductivity, the heat generated by the operation of the thin film transistor can be effectively derived, thereby facilitating The invention solves the problem of heat dissipation of the thin film transistor integrated in the large integrated circuit; fifthly, the carbon nanotube has good light transmittance, therefore, the carbon nanotube metal composite layer is used as the source, the drain and the gate. Improve thin A light-transmitting transistor.
綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.
10‧‧‧薄膜電晶體 10‧‧‧film transistor
100‧‧‧薄膜電晶體面板 100‧‧‧film transistor panel
110‧‧‧絕緣基板 110‧‧‧Insert substrate
120‧‧‧閘極 120‧‧‧ gate
130‧‧‧絕緣層 130‧‧‧Insulation
140‧‧‧半導體層 140‧‧‧Semiconductor layer
142‧‧‧半導體層的第一表面 142‧‧‧The first surface of the semiconductor layer
144‧‧‧半導體層的第二表面 144‧‧‧Second surface of the semiconductor layer
151‧‧‧源極 151‧‧‧ source
152‧‧‧汲極 152‧‧‧汲polar
156‧‧‧通道 156‧‧‧ channel
Claims (22)
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| TW98129472A TWI400807B (en) | 2009-09-01 | 2009-09-01 | Thin film transistor |
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| TWI400807B true TWI400807B (en) | 2013-07-01 |
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| CN104867980B (en) * | 2014-02-24 | 2018-04-24 | 清华大学 | Thin film transistor (TFT) and its array |
| CN104867876B (en) | 2014-02-24 | 2017-11-14 | 清华大学 | The preparation method of thin film transistor (TFT) array |
| CN105810748B (en) * | 2014-12-31 | 2018-12-21 | 清华大学 | N-type TFT |
| CN105810788B (en) * | 2014-12-31 | 2018-05-22 | 清华大学 | Light emitting diode |
| CN105810792B (en) * | 2014-12-31 | 2018-05-22 | 清华大学 | Light emitting diode |
| CN105810749B (en) * | 2014-12-31 | 2018-12-21 | 清华大学 | N-type TFT |
| CN105810785B (en) * | 2014-12-31 | 2018-05-22 | 清华大学 | Light emitting diode |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI222742B (en) * | 2003-05-05 | 2004-10-21 | Ind Tech Res Inst | Fabrication and structure of carbon nanotube-gate transistor |
| TW200710031A (en) * | 2005-05-20 | 2007-03-16 | Univ Central Florida | Carbon nanotube reinforced metal composites |
| TW200920689A (en) * | 2007-11-09 | 2009-05-16 | Hon Hai Prec Ind Co Ltd | Apparatus and method for synthesizing films of carbon nanotubes |
| TW200934725A (en) * | 2008-02-01 | 2009-08-16 | Hon Hai Prec Ind Co Ltd | Carbon nanotube composite and method for making the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI222742B (en) * | 2003-05-05 | 2004-10-21 | Ind Tech Res Inst | Fabrication and structure of carbon nanotube-gate transistor |
| TW200710031A (en) * | 2005-05-20 | 2007-03-16 | Univ Central Florida | Carbon nanotube reinforced metal composites |
| TW200920689A (en) * | 2007-11-09 | 2009-05-16 | Hon Hai Prec Ind Co Ltd | Apparatus and method for synthesizing films of carbon nanotubes |
| TW200934725A (en) * | 2008-02-01 | 2009-08-16 | Hon Hai Prec Ind Co Ltd | Carbon nanotube composite and method for making the same |
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