TWI400805B - Array substrate, liquid crystal display panel having the same and liquid crystal display device having the same - Google Patents

Array substrate, liquid crystal display panel having the same and liquid crystal display device having the same Download PDF

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TWI400805B
TWI400805B TW095101744A TW95101744A TWI400805B TW I400805 B TWI400805 B TW I400805B TW 095101744 A TW095101744 A TW 095101744A TW 95101744 A TW95101744 A TW 95101744A TW I400805 B TWI400805 B TW I400805B
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electrode
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electrically connected
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TW200642085A (en
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Sahng-Ik Jun
Dong-Gyu Kim
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Samsung Display Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/42—Arrangements for providing conduction through an insulating substrate

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Liquid Crystal (AREA)
  • Power Engineering (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

基板，具其之液晶顯示面板及具其之液晶顯示裝置Substrate, liquid crystal display panel therewith and liquid crystal display device therewith

本發明係關於一種陣列基板、具有該陣列基板之液晶顯示(LCD)面板及具有該陣列基板之LCD裝置。具體而言，本發明係關於一種能夠改良影像顯示品質之陣列基板、具有該陣列基板之液晶顯示(LCD)面板及具有該陣列基板之LCD裝置。The present invention relates to an array substrate, a liquid crystal display (LCD) panel having the array substrate, and an LCD device having the array substrate. Specifically, the present invention relates to an array substrate capable of improving image display quality, a liquid crystal display (LCD) panel having the array substrate, and an LCD device having the array substrate.

一般而言，一LCD裝置可包括一陣列基板、一彩色濾光基板及一液晶層。該陣列基板可包括複數個薄膜電晶體(TFT)，該複數個薄膜電晶體(TFT)係控制像素。該彩色濾光基板具有一共同電極。該液晶層被***在該陣列基板與該彩色濾光基板之間。該液晶層的透光度係回應一施加至該液晶層的電場而變更，藉此顯示一影像。In general, an LCD device can include an array substrate, a color filter substrate, and a liquid crystal layer. The array substrate can include a plurality of thin film transistors (TFTs) that control the pixels. The color filter substrate has a common electrode. The liquid crystal layer is interposed between the array substrate and the color filter substrate. The transmittance of the liquid crystal layer is changed in response to an electric field applied to the liquid crystal layer, thereby displaying an image.

該透光度之變化被限制在一預先決定範圍中，並且結果，該LCD裝置具有一相對窄之視角。為了增加該LCD裝置之視角，該LCD裝置實施一垂直對位(vertical alignment；VA)模式。The change in transmittance is limited to a predetermined range, and as a result, the LCD device has a relatively narrow viewing angle. In order to increase the viewing angle of the LCD device, the LCD device implements a vertical alignment (VA) mode.

經組態成實施該VA模式之該LCD裝置可包括兩個基板及一液晶層，該液晶層併入一種含展現負異向性(negative anisotropy)之介電常數的液晶材料。該液晶層中的液晶具有一垂直對位(homeotropic alignment)模式。The LCD device configured to implement the VA mode may include two substrates and a liquid crystal layer incorporating a liquid crystal material containing a dielectric constant exhibiting negative anisotropy. The liquid crystal in the liquid crystal layer has a homeotropic alignment mode.

在運作中，當未施加一電壓至該等基板時，該等液晶係往一垂直方向排列，以顯示黑色。當一至少等於V0 之電壓被施加至該等基板時(例如，用以控制該陣列基板的控制電極及該彩色濾光基板的相關聯之共同電極)，該等液晶係往一水平方向排列，以顯示白色。當一小於V0 之電壓被施加至該等基板時，該等液晶係相對於該水平方向傾斜，以顯示灰色，其中灰階取決於該液晶材料之分子的平均定向。In operation, when a voltage is not applied to the substrates, the liquid crystals are aligned in a vertical direction to display black. When a voltage at least equal to V 0 is applied to the substrates (eg, to control the control electrode of the array substrate and the associated common electrode of the color filter substrate), the liquid crystals are arranged in a horizontal direction To display white. When a voltage less than V 0 is applied to the substrates, the liquid crystals are tilted relative to the horizontal direction to exhibit gray, wherein the gray scale depends on the average orientation of the molecules of the liquid crystal material.

在小螢幕LCD裝置中，該LCD裝置被組態成實施一圖案化垂直對位(patterned vertical alignment；PVA)模式，以增加該視角且減少一灰階反轉(gray－scale inversion)。PVA模式之LCD裝置具有一圖案化共同電極及一圖案化像素電極。In a small screen LCD device, the LCD device is configured to implement a patterned vertical alignment (PVA) mode to increase the viewing angle and reduce a gray-scale inversion. The PVA mode LCD device has a patterned common electrode and a patterned pixel electrode.

在一些可用的LCD裝置中，一施加至每個像素的電壓不穩定，使得像素閃爍，導致影像顯示品質惡化。In some available LCD devices, a voltage applied to each pixel is unstable, causing the pixels to flicker, resulting in deterioration of image display quality.

本發明提供一種能夠改良影像顯示品質之陣列基板。The present invention provides an array substrate capable of improving image display quality.

本發明還提供一種具有上文所述之陣列基板的液晶顯示(LCD)面板。The present invention also provides a liquid crystal display (LCD) panel having the array substrate described above.

本發明還提供一種具有上文所述之陣列基板的LCD裝置。The present invention also provides an LCD device having the array substrate described above.

一種根據本發明一態樣之陣列基板可包括一絕緣基板、一開關元件(例如，一諸如電晶體之開關，其可能係一TFT)、一主像素部分、一耦合電容器及一子像素部分。該開關元件係在該絕緣基板上由互相鄰接之閘極線與資料線所界定之一像素區域中。舉例而言，該像素區域可能係由一第一閘極線與一鄰接之第一資料線所界定，並且進一步係由連貫於該第一閘極線的一第二閘極線與連貫於該第一資料線的一第二資料線所界定。該等閘極線與資料線係在該絕緣基板上。該主像素部分係在該像素區域之一第一(例如，中心)部分上。該耦合電容器被電連接到該開關元件。該耦合電容器係在該絕緣基板上。該子像素部分被電連接到該耦合電容器。該子像素部分係在該像素區域之一第二(例如，周邊)部分上。An array substrate according to an aspect of the present invention may include an insulating substrate, a switching element (for example, a switch such as a transistor, which may be a TFT), a main pixel portion, a coupling capacitor, and a sub-pixel portion. The switching element is disposed on the insulating substrate in a pixel region defined by mutually adjacent gate lines and data lines. For example, the pixel region may be defined by a first gate line and an adjacent first data line, and further connected by a second gate line connected to the first gate line A second data line of the first data line is defined. The gate lines and the data lines are on the insulating substrate. The main pixel portion is on a first (e.g., center) portion of one of the pixel regions. The coupling capacitor is electrically connected to the switching element. The coupling capacitor is attached to the insulating substrate. The sub-pixel portion is electrically connected to the coupling capacitor. The sub-pixel portion is on a second (e.g., peripheral) portion of one of the pixel regions.

一種根據本發明另一態樣之陣列基板可包括一絕緣基板、一主閘極線、一主開關、一主像素部分、一子閘極線、一子開關及一子像素部分。該絕緣基板具有一像素區域。該主閘極線係在該像素區域上。該主開關係在該絕緣基板上。該主開關被電連接到該主閘極線。該主像素部分係在該像素區域之一中心部分上。該主像素部分被電連接到該主開關。該子閘極線係在該像素區域上。該子開關係在該絕緣基板上。該子開關被電連接到該子閘極線。該子像素部分係在該像素區域之一周邊部分上。An array substrate according to another aspect of the present invention may include an insulating substrate, a main gate line, a main switch, a main pixel portion, a sub-gate line, a sub-switch, and a sub-pixel portion. The insulating substrate has a pixel area. The main gate line is on the pixel area. The main opening relationship is on the insulating substrate. The main switch is electrically connected to the main gate line. The main pixel portion is on a central portion of the pixel region. The main pixel portion is electrically connected to the main switch. The sub-gate line is on the pixel area. The sub-opening relationship is on the insulating substrate. The sub-switch is electrically connected to the sub-gate line. The sub-pixel portion is attached to a peripheral portion of the pixel region.

一種根據本發明之一示例性具體實施例的LCD面板可包括一上部基板、一下部基板及一液晶層。該上部基板具有一透明基板及一位於該透明基板上的共同電極。該下部基板可包括一絕緣基板、一主像素、一耦合電容器及一子像素部分。該絕緣基板具有一由互相鄰接之閘極線與資料線所界定之像素區域。該等閘極線與資料線係在該絕緣基板上。該主像素部分係在一第一(例如，中心)部分上。該耦合電容器被電連接到該絕緣基板上的一開關元件。該子像素部分被電連接到該耦合電容器。該子像素部分係在該像素區域之一周邊部分上。該液晶層被***在該上部基板與該下部基板之間。An LCD panel according to an exemplary embodiment of the present invention may include an upper substrate, a lower substrate, and a liquid crystal layer. The upper substrate has a transparent substrate and a common electrode on the transparent substrate. The lower substrate may include an insulating substrate, a main pixel, a coupling capacitor, and a sub-pixel portion. The insulating substrate has a pixel area defined by mutually adjacent gate lines and data lines. The gate lines and the data lines are on the insulating substrate. The main pixel portion is on a first (e.g., center) portion. The coupling capacitor is electrically connected to a switching element on the insulating substrate. The sub-pixel portion is electrically connected to the coupling capacitor. The sub-pixel portion is attached to a peripheral portion of the pixel region. The liquid crystal layer is interposed between the upper substrate and the lower substrate.

一種根據本發明之一示例性具體實施例的LCD裝置可包括一上部基板、一下部基板及一液晶層。該上部基板具有一透明基板及一位於該透明基板上的共同電極。該下部基板可包括一絕緣基板、一閘極線、一資料線、一開關元件、一主像素、一第一耦合電容器、一第一子像素部分、一第二耦合電容器及一第二子像素部分。該閘極線係在該絕緣基板上，用以傳輸一閘極訊號。該資料線係在該絕緣基板上，用以傳輸一資料訊號。該開關元件被電連接到該閘極線及該資料線。該開關元件係在該絕緣基板上。該主像素部分被電連接到該開關元件。該主像素部分係在該絕緣基板上。該第一耦合電容器具有一電連接到該開關元件之第一末端。該第一子像素部分係透過該第一耦合電容器而電連接到該開關元件。該第一子像素部分係在該絕緣基板上。該第二耦合電容器具有一電連接到該開關元件之末端。該第二子像素部分係透過該第二耦合電容器而電連接到該開關元件。該第二子像素部分係在該絕緣基板上。該液晶層被***在該上部基板與該下部基板之間。An LCD device according to an exemplary embodiment of the present invention may include an upper substrate, a lower substrate, and a liquid crystal layer. The upper substrate has a transparent substrate and a common electrode on the transparent substrate. The lower substrate may include an insulating substrate, a gate line, a data line, a switching element, a main pixel, a first coupling capacitor, a first sub-pixel portion, a second coupling capacitor, and a second sub-pixel. section. The gate line is on the insulating substrate for transmitting a gate signal. The data line is on the insulating substrate for transmitting a data signal. The switching element is electrically connected to the gate line and the data line. The switching element is attached to the insulating substrate. The main pixel portion is electrically connected to the switching element. The main pixel portion is attached to the insulating substrate. The first coupling capacitor has a first end electrically connected to the switching element. The first sub-pixel portion is electrically connected to the switching element through the first coupling capacitor. The first sub-pixel portion is attached to the insulating substrate. The second coupling capacitor has an end electrically connected to the switching element. The second sub-pixel portion is electrically connected to the switching element through the second coupling capacitor. The second sub-pixel portion is attached to the insulating substrate. The liquid crystal layer is interposed between the upper substrate and the lower substrate.

根據本發明之一些具體實施例，一總閘極－源極電容被劃分成一閘極－源極電容器的一閘極－源極電容及一額外閘極－源極電容器的一額外閘極－源極電容。該閘極－源極電容器及該額外閘極－源極電容器分別對應於主電極及子電極。結果，減小該主電極的一回掃脈衝(kickback)電壓，並且改良該LCD裝置的影像顯示品質。According to some embodiments of the invention, a total gate-source capacitance is divided into a gate-source capacitance of a gate-source capacitor and an additional gate-source of an additional gate-source capacitor Extreme capacitance. The gate-source capacitor and the additional gate-source capacitor correspond to the main electrode and the sub-electrode, respectively. As a result, a kickback voltage of the main electrode is reduced, and the image display quality of the LCD device is improved.

下文將參考用以呈現本發明具體實施例的附圖來詳細說明本發明之具體實施例。然而，本發明可運用許多不同形式具體化，並且不應視為限於本文中提出的具體實施例。而是，提供這些具體實施例以徹底且完整地揭示本發明，並且對熟悉此項技術者完整描述本發明。在圖式中，為了清楚明晰而誇大層及區域的大小及相對大小。Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, the invention may be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein. Rather, these specific embodiments are provided to fully and completely disclose the invention, and the invention is fully described by those skilled in the art. In the drawings, the size and relative sizes of layers and regions are exaggerated for clarity.

應明白，當將一元件或層聲稱係"在另一元件或層上"、"連接至"或"耦合至"另一元件或層時，可能為直接在其他元件或層上，或連接至或耦合至其他元件或層，或可能有中間元件或層。反之，當將一元件聲稱係"直接位於另一元件上或層上"、"直接連接至"或"直接耦合至"另一元件或層時，則沒有中間元件或層。整份說明書中相似的數字代表相似的元件。在本文中，用詞"及/或"包括一或多項相關聯之所列出項目的任何或所有組合。It will be understood that when an element or layer is "on" or "coupled" or "coupled" to another element or layer, it may be directly on the other element or layer, or Or coupled to other elements or layers, or there may be intermediate elements or layers. In contrast, when an element is claimed to be "directly on" or "directly" or "directly connected to" or "directly connected to" another element or layer, there is no intermediate element or layer. Like numbers in the entire specification represent similar elements. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

應明白，雖然本文中使用用詞"第一"、"第二"、"第三"等等來描述各種元件、組件、區域、層及/或區段，但是彼等元件、組件、區域、層及/或區段不應受限於彼等用詞。彼等用詞僅用來區別一元件、組件、區域、層或區段與另一元件、組件、區域、層或區段。因此，下文所論述的一第一元件、組件、區域、層或區段可被稱為一第二元件、組件、區域、層或區段，而不會脫離本發明之講授。引用一"第一"元件等等未意謂著需要"第二"或額外元件。It will be understood that the terms "first", "second", "third", etc., are used to describe various elements, components, regions, layers and/or sections, but the elements, components, regions, Layers and/or sections should not be limited by their terms. They are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, a first element, component, region, layer or section discussed below may be referred to as a second element, component, region, layer or section without departing from the teachings of the invention. Reference to a "first" element or the like does not mean that a "second" or additional element is required.

為了容易說明，來描述如圖所示之一元件或特徵相對於其他元件或特徵的關係，本文中會使用空間相對用詞，諸如"下面"、"下方"、"下部"、"上方"、"上部"等等。For ease of description, the relationship of one element or feature to other elements or features as illustrated is described herein, and spatially relative terms such as "below", "below", "lower", "above", "Upper" and so on.

應明白，除了圖中所描繪之定向以外，彼等空間相對用詞還預定涵蓋使用中或運作中之裝置的不同定向。例如，如果圖式中的元件翻轉，則描述為在其他元件或特徵"下面"或"下方"的元件或特徵，於是被定向成在其他元件或特徵"上方"。因此，示例性用詞"下方"可涵蓋"上方"及"下方"兩種定向。可用其他方式來定向該裝置(旋轉90度或以其他定向)，並且據此解釋本文中使用的空間相對描述項。It will be understood that in addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or in operation. For example, an element or feature that is "under" or "beneath" or "an" or "an" Thus, the exemplary term "lower" can encompass both "upper" and "lower" orientations. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptions used herein are interpreted accordingly.

本文中使用的術語係僅用於描述特定具體實施例之用途，並且非預定限制本發明。在本文中，單數形式"一"及"該"預定也包括複數形式，除非內容以其他方式明確表明。應進一步明白，當本文中使用用詞"包括"、"包含"、"含有"及/或"具有"時，係用來明確說明所述特徵、實體、步驟、操作、元件及/或組件之存在，但不排除一或一個以上其他特徵、實體、步驟、操作、元件、組件及/或其群組之存在或附加。The terminology used herein is for the purpose of describing particular embodiments, and In the present specification, the singular forms "a", "the" It is to be understood that the terms "comprising", "comprising", "comprising", and" The existence or addition of one or more other features, entities, steps, operations, components, components and/or groups thereof are not excluded.

本文中參考本發明之理想化具體實施例(及中間結構)的概要圖解來描述本發明具體實施例。就其本身而論，由於(舉例而言)製造技術及/或容限，來自於圖解之形狀的變化係所預期。因此，本發明之具體實施例不應被視為限於本文中示例之特定區域形狀，而是包括(舉例而言)製造所致的形狀偏差。舉例而言，繪示為矩形的一植入之區域將典型具有圓形或曲線特徵及/或位於其邊緣之植入集中梯度，而非從植入之區域至非植入之區域的二進制變更。同樣地，藉由植入所形成的一埋入區域可導致在介於該埋入區域與發生該植入之表面之間的區域中之一些植入。因此，圖式中所繪示之區域本質上係概要形式，並且其形狀非預定用以繪示出一裝置之一區域的實質形狀，並且非預定用以限制本發明之範疇。Specific embodiments of the invention are described herein with reference to the <RTIgt; For its part, variations from the shapes of the illustrations are contemplated by, for example, manufacturing techniques and/or tolerances. Thus, the specific embodiments of the present invention should not be construed as limited to the particular s For example, an implanted region depicted as a rectangle will typically have a circular or curved feature and/or an implanted gradient at its edge, rather than a binary change from the implanted region to the non-implanted region. . Likewise, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface where the implantation occurs. Accordingly, the regions illustrated in the figures are in the form of a summary and are not intended to depict a substantial shape of a region of a device, and are not intended to limit the scope of the invention.

除非以其他方式定義，否則本文中使用的所有用詞(包括技術及科學用詞)具有相同於熟悉本發明所屬之技術的一般技術者所通常理解之意義。應進一步明白，用詞(諸如常用字典中所定義之用詞)應被解釋為具有與相關技術背景中之意義一致的意義，並且不應以理想化或過度形式意義予以解釋，惟本文中明確定義除外。Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It should be further understood that the use of words (such as those defined in commonly used dictionaries) should be interpreted as having meaning consistent with the meaning in the relevant technical context, and should not be interpreted in an idealized or excessively formal sense, but Except for definitions.

下文中，將參考附圖來詳細說明本發明之具體實施例。Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.

圖1繪示根據本發明示例性具體實施例之LCD面板的平面圖。圖2繪示以沿圖1所示之I－I'線為例的斷面圖。圖1及2之示例性具體實施例繪示一種透射型LCD面板。1 is a plan view of an LCD panel in accordance with an exemplary embodiment of the present invention. 2 is a cross-sectional view taken along the line II' shown in FIG. 1. An exemplary embodiment of Figures 1 and 2 illustrates a transmissive LCD panel.

請參考圖1及圖2，該LCD面板包括一陣列基板100、一液晶層180及一彩色濾光基板190。將該彩色濾光基板190與該陣列基板100結合在一起，使得該液晶層180被***在該陣列基板100與該彩色濾光基板190之間。Referring to FIG. 1 and FIG. 2 , the LCD panel includes an array substrate 100 , a liquid crystal layer 180 , and a color filter substrate 190 . The color filter substrate 190 is bonded to the array substrate 100 such that the liquid crystal layer 180 is interposed between the array substrate 100 and the color filter substrate 190.

該陣列基板100可包括：一閘極線110，其往一水平方向延伸；一閘電極112，其被電連接至該閘極線110；第一與第二下部儲存圖案STL1與STL2，其在一像素區域中與該閘極線110相間隔，並且實質上平行於該閘極線110；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。該陣列基板100可包括複數個閘極線110、複數個閘電極112、複數個像素區域及複數個第一耦合圖案CPL。The array substrate 100 can include: a gate line 110 extending in a horizontal direction; a gate electrode 112 electrically connected to the gate line 110; and first and second lower storage patterns STL1 and STL2, a pixel region is spaced apart from the gate line 110 and substantially parallel to the gate line 110; and a first coupling pattern CPL that divides the pixel region into two regions. The array substrate 100 can include a plurality of gate lines 110, a plurality of gate electrodes 112, a plurality of pixel regions, and a plurality of first coupling patterns CPL.

該陣列基板100可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板105。該陣列基板100可進一步包括一閘極絕緣層113及一作用層114。該閘極絕緣層113係在具有該閘極線110及該閘電極112的該絕緣基板105上。該作用層114係在該閘極絕緣層113上一相對應於該閘電極112之位置處。該作用層114包括一半導體層(諸如非晶系矽、多晶矽及/或其他適合之材料)及一已植入雜質之半導體層(N＋非晶系矽、N＋多晶矽及/或其他適合之材料)。The array substrate 100 can include an insulating substrate 105 comprising tantalum nitride, hafnium oxide, and/or other insulating material. The array substrate 100 can further include a gate insulating layer 113 and an active layer 114. The gate insulating layer 113 is on the insulating substrate 105 having the gate line 110 and the gate electrode 112. The active layer 114 is on the gate insulating layer 113 at a position corresponding to the gate electrode 112. The active layer 114 includes a semiconductor layer (such as an amorphous germanium, polysilicon, and/or other suitable material) and a semiconductor layer (N+ amorphous germanium, N+ polysilicon, and/or other suitable materials) that have been implanted with impurities. .

該陣列基板100可包括：一源極線120，其往一縱向方向延伸；一源電極122，其被電連接至該源極線120；以及一汲電極123，其與該源電極122相間隔。該陣列基板100可包括複數個源極線120、複數個源電極122及複數個汲電極123。閘電極112、作用層114(包括半導體層及已植入雜質之半導體層)、源電極122及汲電極123形成一或多個薄膜電晶體(TFT)。The array substrate 100 may include: a source line 120 extending in a longitudinal direction; a source electrode 122 electrically connected to the source line 120; and a drain electrode 123 spaced apart from the source electrode 122 . The array substrate 100 can include a plurality of source lines 120, a plurality of source electrodes 122, and a plurality of germanium electrodes 123. The gate electrode 112, the active layer 114 (including the semiconductor layer and the semiconductor layer on which the impurity has been implanted), the source electrode 122, and the germanium electrode 123 form one or more thin film transistors (TFTs).

該陣列基板100可進一步包括：一第一上部儲存圖案124，其被電連接至該汲電極123；一第一延伸圖案125，其在該像素區域之一左側上電連接至該汲電極123；一第二耦合圖案126，其被電連接至該第一延伸圖案125；一第二延伸圖案127，其在該像素區域之該左側上電連接至該第一延伸圖案125；以及一第二上部儲存圖案128，其被電連接至該第二延伸圖案127。The array substrate 100 may further include: a first upper storage pattern 124 electrically connected to the germanium electrode 123; a first extension pattern 125, electrically connected to the germanium electrode 123 on one of the left side of the pixel region; a second coupling pattern 126 electrically connected to the first extension pattern 125; a second extension pattern 127 electrically connected to the first extension pattern 125 on the left side of the pixel region; and a second upper portion A pattern 128 is stored that is electrically connected to the second extension pattern 127.

該閘極線110可具有一種單層式結構或一種多層式結構。當該閘極線110具有一種單層式結構時，該閘極線110可包括鋁、鋁釹合金等等。當該閘極線110具有一種多層式結構時，該閘極線110可包括一下層部位(其具有鉻、鉬、鉬合金及/或其他適合之材料)及一上層部位(其具有鋁、鋁合金及/或其他適合之材料)。The gate line 110 can have a single layer structure or a multilayer structure. When the gate line 110 has a single layer structure, the gate line 110 may include aluminum, an aluminum-bismuth alloy, or the like. When the gate line 110 has a multi-layer structure, the gate line 110 may include a lower layer portion (having chromium, molybdenum, molybdenum alloy, and/or other suitable materials) and an upper portion (having aluminum, aluminum) Alloy and / or other suitable materials).

該陣列基板100可進一步包括一鈍化層130及一有機絕緣層132。該鈍化層130覆蓋該TFT。該鈍化層130及該有機絕緣層132具有一接觸通孔，透過該接觸通孔而局部曝露該汲電極123。該鈍化層130及該有機絕緣層132保護介於該源電極122與該汲電極123之間的該作用層114。藉由該鈍化層130及該有機絕緣層132，使該TFT電絕緣於一像素電極構件140。該作用層114可包括一半導體層及一已摻雜(例如，已植入雜質)之半導體層。The array substrate 100 may further include a passivation layer 130 and an organic insulating layer 132. The passivation layer 130 covers the TFT. The passivation layer 130 and the organic insulating layer 132 have a contact via through which the germanium electrode 123 is partially exposed. The passivation layer 130 and the organic insulating layer 132 protect the active layer 114 between the source electrode 122 and the germanium electrode 123. The TFT is electrically insulated from the pixel electrode member 140 by the passivation layer 130 and the organic insulating layer 132. The active layer 114 can include a semiconductor layer and a semiconductor layer that has been doped (eg, implanted with impurities).

該有機絕緣層132的一高度受到控制，使得該液晶層180的一厚度受到控制。在一些具體實施例中，可省略該鈍化層130。A height of the organic insulating layer 132 is controlled such that a thickness of the liquid crystal layer 180 is controlled. In some embodiments, the passivation layer 130 can be omitted.

該陣列基板100可進一步包括透過該接觸通孔而電連接至該TFT之該汲電極123的該像素電極構件140。該像素電極構件140具有開口圖樣。The array substrate 100 may further include the pixel electrode member 140 electrically connected to the germanium electrode 123 of the TFT through the contact via. The pixel electrode member 140 has an opening pattern.

具體而言，該像素電極構件140可包括一主電極144、一第一子電極142及一第二子電極146。該主電極144被電連接至該第二耦合圖案126。該第一子電極142被電連接至該第一下部儲存圖案STL1。該第二子電極146與該第一子電極142相間隔，並且被電連接至該第二下部儲存圖案STL2。Specifically, the pixel electrode member 140 can include a main electrode 144, a first sub-electrode 142, and a second sub-electrode 146. The main electrode 144 is electrically connected to the second coupling pattern 126. The first sub-electrode 142 is electrically connected to the first lower storage pattern STL1. The second sub-electrode 146 is spaced apart from the first sub-electrode 142 and is electrically connected to the second lower storage pattern STL2.

該主電極144具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°的兩個鄰接桿。該第一子電極142具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一。該第二子電極146具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之另一桿。該第一子電極142之該等線形開口圖樣係相對於該中心線而對稱於該第二子電極146之該等線形開口圖樣。在運作中，在該液晶層180中，形成鄰接於該像素電極構件140的該等開口圖樣的複數個域。The main electrode 144 has two Y-shaped opening patterns which are symmetrical with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting about 90°. The first sub-electrode 142 has two linear opening patterns that are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The second sub-electrode 146 has two linear opening patterns substantially parallel to the other of the two adjacent rods of the respective Y-shaped opening patterns. The linear opening patterns of the first sub-electrode 142 are symmetric with respect to the center line and the linear opening patterns of the second sub-electrode 146. In operation, in the liquid crystal layer 180, a plurality of domains adjacent to the opening pattern of the pixel electrode member 140 are formed.

該主電極144、該第一子電極142及該第二子電極146可包括一透明導電材料，諸如氧化銦錫(indium tin oxide；ITO)、非晶系氧化銦錫(amorphous indium tin oxide；a－ITO)、氧化銦鋅(indium zinc oxide；IZO)、氧化鋅(zinc oxide；ZO)及/或其他透明導電材料。The main electrode 144, the first sub-electrode 142 and the second sub-electrode 146 may comprise a transparent conductive material, such as indium tin oxide (ITO), amorphous indium tin oxide (a). -ITO), indium zinc oxide (IZO), zinc oxide (ZO) and/or other transparent conductive materials.

該彩色濾光基板190可包括：一透明基板192；一彩色濾光層194，其在該透明基板192上；以及一共同電極196，其在該彩色濾光層194上。該共同電極196覆蓋該像素電極構件140的該等開口圖樣，並且被局部展開。該彩色濾光基板190被附接至該陣列基板100，以密封該液晶層180。在此示例性具體實施例中，該液晶層180具有一垂直對位(VA)模式。The color filter substrate 190 can include a transparent substrate 192, a color filter layer 194 on the transparent substrate 192, and a common electrode 196 on the color filter layer 194. The common electrode 196 covers the opening patterns of the pixel electrode member 140 and is partially expanded. The color filter substrate 190 is attached to the array substrate 100 to seal the liquid crystal layer 180. In this exemplary embodiment, the liquid crystal layer 180 has a vertical alignment (VA) mode.

該等域係由該主電極144與該第一子電極142和該第二子電極146所形成，使得可以省略該陣列基板100及/或該彩色濾光基板190的一配向製程(rubbing process)。此外，也可以省略對位層(圖中未顯示)。The domains are formed by the main electrode 144 and the first sub-electrode 142 and the second sub-electrode 146, so that an alignment process of the array substrate 100 and/or the color filter substrate 190 can be omitted. . In addition, the alignment layer (not shown) may be omitted.

圖3繪示圖2所示之陣列基板的電路圖。3 is a circuit diagram of the array substrate shown in FIG. 2.

請參考圖3，該LCD裝置可包括一閘極線GL、一資料線DL、一薄膜電晶體TFT、一主像素部分MP、一第一耦合電容器Ccp1、一第一子像素部分SP1、一第二耦合電容器Ccp2及一第二子像素部分SP2。Referring to FIG. 3, the LCD device may include a gate line GL, a data line DL, a thin film transistor TFT, a main pixel portion MP, a first coupling capacitor Ccp1, a first sub-pixel portion SP1, and a first The second coupling capacitor Ccp2 and a second sub-pixel portion SP2.

透過該閘極線GL，將一閘極訊號施加至該薄膜電晶體TFT。透過該資料線DL，將一資料訊號施加至該薄膜電晶體TFT。A gate signal is applied to the thin film transistor TFT through the gate line GL. A data signal is applied to the thin film transistor TFT through the data line DL.

該主像素部分MP可包括一主液晶電容器ClcM及一主儲存電容器CstM。該主液晶電容器ClcM之一末端被電連接至該薄膜電晶體TFT，以及一共同電壓Vcom被施加至該主液晶電容器ClcM之另一末端。該主儲存電容器CstM之一末端被電連接至該薄膜電晶體TFT，以及一儲存電壓Vst被施加至該主儲存電容器CstM之另一末端。The main pixel portion MP may include a main liquid crystal capacitor ClcM and a main storage capacitor CstM. One end of the main liquid crystal capacitor ClcM is electrically connected to the thin film transistor TFT, and a common voltage Vcom is applied to the other end of the main liquid crystal capacitor ClcM. One end of the main storage capacitor CstM is electrically connected to the thin film transistor TFT, and a storage voltage Vst is applied to the other end of the main storage capacitor CstM.

該第一耦合電容器Ccp1之一末端被電連接至該薄膜電晶體TFT，並且該第一耦合電容器Ccp1之另一末端被電連接至該第一子像素部分SP1。One end of the first coupling capacitor Ccp1 is electrically connected to the thin film transistor TFT, and the other end of the first coupling capacitor Ccp1 is electrically connected to the first sub-pixel portion SP1.

該第一子像素部分SP1可包括一第一液晶電容器Clcs1及一第一儲存電容器Csts1。該第一液晶電容器Clcs1之一末端被電連接至該第一耦合電容器Ccp1，以及該共同電壓被施加至該第一液晶電容器Clcs1之另一末端。該第一儲存電容器Csts1之一末端被電連接至該第一耦合電容器Ccp1，以及該儲存電壓Vst被施加至該第一儲存電容器Csts1之另一末端。The first sub-pixel portion SP1 may include a first liquid crystal capacitor Clcs1 and a first storage capacitor Csts1. One end of the first liquid crystal capacitor Clcs1 is electrically connected to the first coupling capacitor Ccp1, and the common voltage is applied to the other end of the first liquid crystal capacitor Clcs1. One end of the first storage capacitor Csts1 is electrically connected to the first coupling capacitor Ccp1, and the storage voltage Vst is applied to the other end of the first storage capacitor Csts1.

該第二耦合電容器Ccp2之一末端被電連接至該薄膜電晶體TFT，並且該第二耦合電容器Ccp2之另一末端被電連接至該第二子像素部分SP2。One end of the second coupling capacitor Ccp2 is electrically connected to the thin film transistor TFT, and the other end of the second coupling capacitor Ccp2 is electrically connected to the second sub-pixel portion SP2.

該第二子像素部分SP2可包括一第二液晶電容器Clcs2及一第二儲存電容器Csts2。該第二液晶電容器Clcs2之一末端被電連接至該第二耦合電容器Ccp2，以及該共同電壓Vcom被施加至該第二液晶電容器Clcs2之另一末端。該第二儲存電容器Csts2之一末端被電連接至該第二耦合電容器Ccp2，以及該儲存電壓Vst被施加至該第二儲存電容器Csts2之另一末端。The second sub-pixel portion SP2 may include a second liquid crystal capacitor Clcs2 and a second storage capacitor Csts2. One end of the second liquid crystal capacitor Clcs2 is electrically connected to the second coupling capacitor Ccp2, and the common voltage Vcom is applied to the other end of the second liquid crystal capacitor Clcs2. One end of the second storage capacitor Csts2 is electrically connected to the second coupling capacitor Ccp2, and the storage voltage Vst is applied to the other end of the second storage capacitor Csts2.

圖4到8繪示一種製造圖3所示之陣列基板之方法的平面圖。該陣列基板具有接觸通孔，該等接觸通孔分別與鄰接於該TFT的汲極線及相隔於該TFT的汲極線鄰接。具體而言，圖4繪示該閘極線的平面圖。圖5繪示該作用層的平面圖。圖6繪示該源極－汲極線的平面圖。圖7繪示該有機絕緣層的平面圖。圖8繪示該像素電極構件的平面圖。4 to 8 are plan views showing a method of manufacturing the array substrate shown in Fig. 3. The array substrate has contact vias respectively adjacent to a drain line adjacent to the TFT and a drain line spaced apart from the TFT. Specifically, FIG. 4 is a plan view of the gate line. Figure 5 is a plan view of the active layer. Figure 6 is a plan view of the source-drain line. Figure 7 is a plan view of the organic insulating layer. Fig. 8 is a plan view showing the pixel electrode member.

請參考圖2及圖4，一或多種金屬材料(諸如鉭(Ta)、鈦(Ti)、鉬(Mo)、鋁(Al)、鉻(Cr)、銅(Cu)、鎢(W)及/或其他金屬材料)被沉積一含一透明絕緣材料(諸如玻璃、陶瓷等等)的該絕緣基板105上，藉此形成一金屬層。Please refer to FIG. 2 and FIG. 4 , one or more metal materials (such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), tungsten (W) and / or other metallic material) is deposited on the insulating substrate 105 containing a transparent insulating material such as glass, ceramics, etc., thereby forming a metal layer.

該沉積之金屬層被圖案化，以形成：該等閘極線110，其往該水平方向延伸且往縱向方向予以排列；該等閘電極112，其被電連接至該等閘極線110；該等第一與第二下部儲存圖案STL1與STL2，其在該像素區域中實質上平行於該等閘極線110；以及該第一耦合圖案CPL，其將該像素區域劃分成兩個區域。The deposited metal layer is patterned to form: the gate lines 110 extending in the horizontal direction and arranged in the longitudinal direction; the gate electrodes 112 are electrically connected to the gate lines 110; The first and second lower storage patterns STL1 and STL2 are substantially parallel to the gate lines 110 in the pixel region; and the first coupling pattern CPL divides the pixel region into two regions.

在具有該等閘極線110、該等閘電極112、該等第一與第二下部儲存圖案STL1與STL2及該第一耦合圖案CPL的該絕緣基板105上沉積氮化矽，以形成該閘極絕緣層113。在此示例性具體實施例中，透過一化學沉積製程，在該絕緣基板105上沉積氮化矽，並且在整個該絕緣基板105沉積上該閘極絕緣層113。替代做法為，該閘極絕緣層113被圖案化，使得該圖案化之閘極絕緣層僅在該等閘極線110、該等閘電極112、該等第一與第二下部儲存圖案STL1與STL2及該第一耦合圖案CPL上。Depositing tantalum nitride on the insulating substrate 105 having the gate lines 110, the gate electrodes 112, the first and second lower memory patterns STL1 and STL2, and the first coupling pattern CPL to form the gate A pole insulating layer 113. In this exemplary embodiment, tantalum nitride is deposited on the insulating substrate 105 through a chemical deposition process, and the gate insulating layer 113 is deposited over the insulating substrate 105. Alternatively, the gate insulating layer 113 is patterned such that the patterned gate insulating layer is only at the gate lines 110, the gate electrodes 112, the first and second lower memory patterns STL1 and STL2 and the first coupling pattern CPL.

請參考圖5，在該閘極絕緣層113上形成一非晶系矽層及一N＋非晶系矽層。該非晶系矽層及一N＋非晶系矽層被圖案化，以在該閘電極112上形成該作用層114。Referring to FIG. 5, an amorphous germanium layer and an N+ amorphous germanium layer are formed on the gate insulating layer 113. The amorphous germanium layer and an N+ amorphous germanium layer are patterned to form the active layer 114 on the gate electrode 112.

一或多種金屬料(諸如鉭(Ta)、鈦(Ti)、鉬(Mo)、鋁(Al)、鉻(Cr)、銅(Cu)、鎢(W)及/或其他金屬材料)被沉積一具有該作用層114的該閘極絕緣層113上，藉此形成一金屬層。One or more metal materials such as tantalum (Ta), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), copper (Cu), tungsten (W), and/or other metallic materials are deposited A gate insulating layer 113 having the active layer 114 is formed thereby forming a metal layer.

請參考圖6，該沉積之金屬層被圖案化，以形成：該等資料線120；該等源電極122，其被電連接至該等資料線120；以及該等汲電極123，其分別與該等源電極122相間隔；該等第一上部儲存圖案124，其分別電連接至該等汲電極123；該等第一延伸圖案125，其分別電連接至該等汲電極123；該等第二耦合圖案126，其分別電連接至該等第一延伸圖案125；該等第二延伸圖案127，其分別電連接至該等第一延伸圖案125；以及該等第二上部儲存圖案128，其分別電連接至該等第二延伸圖案127。Referring to FIG. 6, the deposited metal layer is patterned to form: the data lines 120; the source electrodes 122 are electrically connected to the data lines 120; and the germanium electrodes 123 are respectively associated with The first upper storage patterns 124 are respectively electrically connected to the second electrodes 123; the first extension patterns 125 are electrically connected to the second electrodes 123, respectively; Two coupling patterns 126 electrically connected to the first extension patterns 125, respectively; the second extension patterns 127 are electrically connected to the first extension patterns 125, respectively; and the second upper storage patterns 128, They are electrically connected to the second extension patterns 127, respectively.

在該等第一上部儲存圖案124之每一第一上部儲存圖案上各形成一第一接觸通孔CNTST1。該等第二耦合圖案126之每一第二耦合圖案各覆蓋該等第一耦合圖案CPL之每一第一耦合圖案且將該像素區域劃分成兩個區域。在該等第二上部儲存圖案128之每一第二上部儲存圖案上各形成一第二接觸通孔CNTST2。A first contact via CNTST1 is formed on each of the first upper storage patterns of the first upper storage patterns 124. Each of the second coupling patterns 126 each covers a first coupling pattern of the first coupling patterns CPL and divides the pixel region into two regions. A second contact via CNTST2 is formed on each of the second upper storage patterns of the second upper storage patterns 128.

請參考圖2及圖7，在具有該作用層114、該等資料線120、該等源電極122、該等汲電極123、該等第一上部儲存圖案124、該等第一延伸圖案125、該等第二耦合圖案126、該等第二延伸圖案127及該等第二上部儲存圖案128的該閘極絕緣層113上，形成該鈍化層130及該有機絕緣層132。在此示例性具體實施例中，該汲極線包括該等第一上部儲存圖案124、該等第一延伸圖案125、該等第二耦合圖案126、該等第二延伸圖案127及該等第二上部儲存圖案128。Referring to FIG. 2 and FIG. 7 , the active layer 114 , the data lines 120 , the source electrodes 122 , the germanium electrodes 123 , the first upper memory patterns 124 , the first extension patterns 125 , The passivation layer 130 and the organic insulating layer 132 are formed on the second coupling pattern 126, the second extension patterns 127, and the gate insulating layer 113 of the second upper memory patterns 128. In this exemplary embodiment, the drain line includes the first upper storage patterns 124, the first extension patterns 125, the second coupling patterns 126, the second extension patterns 127, and the like The upper portion stores the pattern 128.

在該像素區域中的該鈍化層130之一部分及該有機絕緣層132被局部移除，以形成一相對應於該第一接觸通孔CNTST1的第三接觸通孔CNTST3、一相對應於該第二接觸通孔CNTST2的第四接觸通孔CNTST4以及一相對應於該第二耦合圖案126的第五接觸通孔CNTCP。該陣列基板的像素區域被界定為由連貫之閘極線110與資料線120所限界的區域。A portion of the passivation layer 130 and the organic insulating layer 132 are partially removed in the pixel region to form a third contact via CNTST3 corresponding to the first contact via CNTST1, corresponding to the first The fourth contact via CNTST4 of the second contact via CNTST2 and a fifth contact via CNTCP corresponding to the second coupling pattern 126. The pixel area of the array substrate is defined as the area bounded by the continuous gate line 110 and the data line 120.

請參考圖2及圖8，該像素電極構件140被形成在該有機絕緣層132上。該像素電極構件140係透過該第一接觸通孔CNTST1和該第三接觸通孔CNTST3而電連接至每個該等第一下部儲存圖案STL1，並且係透過該第二接觸通孔CNTST2和該第四接觸通孔CNTST4而電連接至每個該等第二下部儲存圖案STL2。此外，該像素電極構件140係透過該第五接觸通孔CNTCP而電連接至該第二耦合圖案126。Referring to FIGS. 2 and 8, the pixel electrode member 140 is formed on the organic insulating layer 132. The pixel electrode member 140 is electrically connected to each of the first lower storage patterns STL1 through the first contact via CNTST1 and the third contact via CNTST3, and is passed through the second contact via CNTST2 and the The fourth contact via CNTST4 is electrically connected to each of the second lower storage patterns STL2. In addition, the pixel electrode member 140 is electrically connected to the second coupling pattern 126 through the fifth contact via CNTCP.

具體而言，該像素電極構件140可包括：該主電極144，其被電連接至該第二耦合圖案126；該第一子電極142，其被電連接至該第一下部儲存圖案STL1；以及該第二子電極146，其被電連接至該第二下部儲存圖案STL2且相間隔於該第一下部儲存圖案STL1。Specifically, the pixel electrode member 140 may include: the main electrode 144 is electrically connected to the second coupling pattern 126; the first sub-electrode 142 is electrically connected to the first lower storage pattern STL1; And the second sub-electrode 146 is electrically connected to the second lower storage pattern STL2 and spaced apart from the first lower storage pattern STL1.

該主電極144具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。該第一子電極142具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一。該第二子電極146具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之另一桿。該第一子電極l42之該等線形開口圖樣係相對於該中心線而對稱於該第二子電極146之該等線形開口圖樣。在運作中，在介於該陣列基板與該彩色濾光基板之間的該液晶層180中，形成鄰接於該陣列基板之該像素電極構件140的該等開口圖樣的複數個域。The main electrode 144 has two Y-shaped opening patterns which are symmetrical with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°. The first sub-electrode 142 has two linear opening patterns that are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The second sub-electrode 146 has two linear opening patterns substantially parallel to the other of the two adjacent rods of the respective Y-shaped opening patterns. The linear opening patterns of the first sub-electrode l42 are symmetric with respect to the center line and the linear opening patterns of the second sub-electrode 146. In operation, a plurality of domains of the opening pattern adjacent to the pixel electrode member 140 of the array substrate are formed in the liquid crystal layer 180 between the array substrate and the color filter substrate.

該主電極144、該第一子電極142及該第二子電極146包括一或多種透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。該透明導電材料可被塗佈在該有機絕緣層132上，並且可被圖案以形成該主電極144、該第一子電極142及該第二子電極146。替代做法為，可透過互相不同的製程來形成該主電極144、該第一子電極142及該第二子電極146。The main electrode 144, the first sub-electrode 142 and the second sub-electrode 146 comprise one or more transparent conductive materials, such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide ( IZO), zinc oxide (ZO) and/or other transparent conductive materials. The transparent conductive material may be coated on the organic insulating layer 132 and may be patterned to form the main electrode 144, the first sub-electrode 142, and the second sub-electrode 146. Alternatively, the main electrode 144, the first sub-electrode 142, and the second sub-electrode 146 may be formed by mutually different processes.

在此示例性具體實施例中，該主電極144、該第一子電極142及該第二子電極146互相間隔。替代做法為，該主電極144可局部重疊於該第一子電極142及該第二子電極146。In this exemplary embodiment, the main electrode 144, the first sub-electrode 142, and the second sub-electrode 146 are spaced apart from each other. Alternatively, the main electrode 144 may partially overlap the first sub-electrode 142 and the second sub-electrode 146.

根據此示例性具體實施例，該主像素部分係在該像素區域之一中心部分上；以及該子像素部分係在該像素區域之一周邊部分上。該子像素部分係透過該耦合電容器而電連接到該薄膜電晶體。因此，減小該主像素部分的一回掃脈衝電壓。According to this exemplary embodiment, the main pixel portion is on a central portion of the pixel region; and the sub-pixel portion is on a peripheral portion of the pixel region. The sub-pixel portion is electrically connected to the thin film transistor through the coupling capacitor. Therefore, a retrace pulse voltage of the main pixel portion is reduced.

圖9繪示根據本發明示例性具體實施例之閘極－源極電容器的平面圖。9 is a plan view of a gate-source capacitor in accordance with an exemplary embodiment of the present invention.

請參考圖9，一閘極－源極電容器Cgs1係藉由一作用層上的一閘極線110與一汲極線120的重疊部分予以界定。在此示例性具體實施例中，一額外閘極－源極電容器Cgs2係藉由該閘極線110與一像素電極142的重疊部分予以界定。Referring to FIG. 9, a gate-source capacitor Cgs1 is defined by an overlap of a gate line 110 and a drain line 120 on an active layer. In this exemplary embodiment, an additional gate-source capacitor Cgs2 is defined by the overlap of the gate line 110 and a pixel electrode 142.

一總閘極－源極電容被劃分成該閘極－源極電容器Cgs1的一閘極－源極電容及該額外閘極－源極電容器Cgs2的一額外閘極－源極電容。該額外閘極－源極電容器Cgs2的該額外閘極－源極電容對應於該子像素部分，使得按照下列等式1，減小該主像素部分的一回掃脈衝電壓。在此示例性具體實施例中，該閘極－源極電容器Cgs1與該額外閘極－源極電容器Cgs2的面積比係約60：40。A total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor Cgs1 and an additional gate-source capacitance of the additional gate-source capacitor Cgs2. The additional gate-source capacitance of the additional gate-source capacitor Cgs2 corresponds to the sub-pixel portion such that a retrace pulse voltage of the main pixel portion is reduced according to Equation 1 below. In this exemplary embodiment, the area ratio of the gate-source capacitor Cgs1 to the additional gate-source capacitor Cgs2 is about 60:40.

下列等式1表示該回掃脈衝電壓Vk。The following equation 1 represents the retrace pulse voltage Vk.

等式1 Vk＝Cgs．(Von－Voff)/(Cgs＋Cst＋Clc)Equation 1 Vk=Cgs. (Von-Voff)/(Cgs+Cst+Clc)

Cgs、Cst、Clc、Von及Voff分別表示該閘極－源極電容、一儲存電容、一液晶電容、一閘極開通電壓及一閘極關斷電壓。Cgs, Cst, Clc, Von, and Voff represent the gate-source capacitance, a storage capacitor, a liquid crystal capacitor, a gate turn-on voltage, and a gate turn-off voltage, respectively.

藉由減小該回掃脈衝電壓，得以減少或排除一些顯示缺陷。舉例而言，減少一像素電壓的根均方(root－meansquare；RMS)所造成的一故障，例如，一閃爍。By reducing the retrace pulse voltage, some display defects are reduced or eliminated. For example, reducing a failure caused by a root-mean square (RMS) of a pixel voltage, for example, a flicker.

此外，該子電極部分顯示介於一零灰階與一中間灰階之間的黑色，藉此減少一低灰階的一殘像。In addition, the sub-electrode portion displays black between a zero gray scale and an intermediate gray scale, thereby reducing an afterimage of a low gray scale.

圖10繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖11繪示圖10所示之陣列基板的平面圖。該陣列基板具有一在一層上的接觸通孔，在該層上形成一鄰接於一薄膜電晶體(TFT)的汲電極。FIG. 10 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. 11 is a plan view of the array substrate shown in FIG. The array substrate has a contact via on a layer on which a germanium electrode adjacent to a thin film transistor (TFT) is formed.

請參考圖2、圖10及圖11，該陣列基板200可包括：一閘極線210，其往一水平方向延伸；一閘電極212，其被電連接至該閘極線210；第一與第二下部儲存圖案STL1與STL2，其在一像素區域中與該閘極線210相間隔，並且實質上平行於該閘極線210；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。在一些具體實施例中，該陣列基板200可包括複數個閘極線210、複數個閘電極212、複數個像素區域及複數個第一耦合圖案CPL，其中像素區域係由連貫之閘極線210與資料線220予以界定。Referring to FIG. 2, FIG. 10 and FIG. 11, the array substrate 200 may include: a gate line 210 extending in a horizontal direction; and a gate electrode 212 electrically connected to the gate line 210; a second lower storage pattern STL1 and STL2 spaced apart from the gate line 210 in a pixel region and substantially parallel to the gate line 210; and a first coupling pattern CPL that divides the pixel region into Two areas. In some embodiments, the array substrate 200 can include a plurality of gate lines 210, a plurality of gate electrodes 212, a plurality of pixel regions, and a plurality of first coupling patterns CPL, wherein the pixel regions are formed by consecutive gate lines 210. It is defined with data line 220.

該陣列基板200可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板200可進一步包括一閘極絕緣層(圖中未繪示)及一作用層214。該閘極絕緣層(圖中未繪示)係在具有該閘極線210及該閘電極212的該絕緣基板(圖中未繪示)上。該作用層214係在該閘極絕緣層(圖中未繪示)上而相對應於該閘電極212。該作用層214包括一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其包含N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 200 may include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 200 can further include a gate insulating layer (not shown) and an active layer 214. The gate insulating layer (not shown) is on the insulating substrate (not shown) having the gate line 210 and the gate electrode 212. The active layer 214 is corresponding to the gate electrode 212 on the gate insulating layer (not shown). The active layer 214 includes a semiconductor layer (having an amorphous germanium, polycrystalline germanium, and/or other suitable material) and a semiconductor layer that has been doped (eg, implanted) of impurities (which includes an N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板200可包括：一源極線220，其往一縱向方向延伸；一源電極222，其被電連接至該源極線220；以及一汲電極223，其與該源電極222相間隔。在一些具體實施例中，該陣列基板200可包括複數個源極線220、複數個源電極222及複數個汲電極223。每個該等閘電極212、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等源電極222及每個該等汲電極223各形成一相關聯之薄膜電晶體(TFT)。The array substrate 200 can include: a source line 220 extending in a longitudinal direction; a source electrode 222 electrically connected to the source line 220; and a drain electrode 223 spaced apart from the source electrode 222 . In some embodiments, the array substrate 200 can include a plurality of source lines 220, a plurality of source electrodes 222, and a plurality of germanium electrodes 223. Each of the gate electrodes 212, each of the semiconductor layers, each of the semiconductor layers having implanted impurities, each of the source electrodes 222, and each of the germanium electrodes 223 each form an associated thin film current Crystal (TFT).

該陣列基板200可進一步包括：一第一上部儲存圖案224，其被電連接至該汲電極223；一第一延伸圖案225，其在該像素區域之一左側上電連接至該汲電極223；一第二耦合圖案226，其被電連接至該第一延伸圖案225；一第二延伸圖案227，其在該像素區域之該左側上電連接至該第一延伸圖案225；以及一第二上部儲存圖案228，其被電連接至該第二延伸圖案227。在此示例性具體實施例中，該等第一上部儲存圖案224、該等第一延伸圖案225、該等第二耦合圖案226、該等第二延伸圖案227及該等第二上部儲存圖案228形成一汲極線。The array substrate 200 may further include: a first upper storage pattern 224 electrically connected to the germanium electrode 223; a first extension pattern 225, electrically connected to the germanium electrode 223 on one of the left side of the pixel region; a second coupling pattern 226 electrically connected to the first extension pattern 225; a second extension pattern 227 electrically connected to the first extension pattern 225 on the left side of the pixel region; and a second upper portion A pattern 228 is stored that is electrically connected to the second extension pattern 227. In this exemplary embodiment, the first upper storage patterns 224, the first extension patterns 225, the second coupling patterns 226, the second extension patterns 227, and the second upper storage patterns 228 Form a bungee line.

該陣列基板200可進一步包括一鈍化層230及一有機絕緣層232。該鈍化層230覆蓋該TFT。該鈍化層230及該有機絕緣層232具有一接觸通孔，透過該接觸通孔而局部曝露該汲電極223。該鈍化層230及該有機絕緣層232保護介於該源電極222與該汲電極223之間的該作用層214。藉由該鈍化層230及該有機絕緣層232，使該TFT電絕緣於一像素電極構件。該作用層214可包括該半導體層及該已植入雜質之半導體層。The array substrate 200 can further include a passivation layer 230 and an organic insulating layer 232. The passivation layer 230 covers the TFT. The passivation layer 230 and the organic insulating layer 232 have a contact via through which the germanium electrode 223 is partially exposed. The passivation layer 230 and the organic insulating layer 232 protect the active layer 214 between the source electrode 222 and the germanium electrode 223. The TFT is electrically insulated from the pixel electrode member by the passivation layer 230 and the organic insulating layer 232. The active layer 214 can include the semiconductor layer and the semiconductor layer to which the impurity has been implanted.

該有機絕緣層232的一高度可受到控制，使得該液晶層200的一厚度受到控制。在一些具體實施例中，可省略該鈍化層230。A height of the organic insulating layer 232 can be controlled such that a thickness of the liquid crystal layer 200 is controlled. In some embodiments, the passivation layer 230 can be omitted.

該陣列基板200可進一步包括透過該接觸通孔CNTST1而電連接至該第一上部儲存圖案224的該像素電極構件。該像素電極構件具有開口圖樣。The array substrate 200 may further include the pixel electrode member electrically connected to the first upper storage pattern 224 through the contact via CNTST1. The pixel electrode member has an opening pattern.

具體而言，該像素電極構件可包括一主電極244及一子電極242。該主電極244具有一朝向該像素區域之一右側突出的楔形形狀。該子電極242係在該像素區域之未形成該主電極244的一其餘部分上。Specifically, the pixel electrode member may include a main electrode 244 and a sub-electrode 242. The main electrode 244 has a wedge shape that protrudes toward the right side of one of the pixel regions. The sub-electrode 242 is on a remaining portion of the pixel region where the main electrode 244 is not formed.

在此圖解具體實施例中，該主電極244具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。該子電極242被劃分成複數個部分。在此圖解具體實施例中，該子電極242的每個部分各具有一實質上固定寬度。In the illustrated embodiment, the main electrode 244 has two Y-shaped opening patterns that are symmetric with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°. The sub-electrode 242 is divided into a plurality of portions. In the illustrated embodiment, each portion of the sub-electrode 242 has a substantially fixed width.

該子電極242具有四個線性開口圖樣。其中兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一上部桿。其餘兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一下部桿。實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該上部桿的該等兩個線形開口圖樣，係相對於該中心線而對稱於實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該下部桿的該等其餘兩個線形開口圖樣。The sub-electrode 242 has four linear opening patterns. Two of the linear opening patterns are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The remaining two linear opening patterns are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The two linear opening patterns of the upper rods of the two adjacent rods substantially parallel to the respective Y-shaped opening patterns are symmetrical with respect to the center line substantially parallel to the Y-shaped opening patterns The remaining two linear opening patterns of the lower bars of the respective two adjacent rods.

在一包括陣列基板200之LCD裝置運作中，在置放於陣列基板200與一彩色濾光基板之間的該液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。In an LCD device operation including the array substrate 200, a plurality of domains adjacent to the opening pattern of the pixel electrode member are formed in the liquid crystal layer disposed between the array substrate 200 and a color filter substrate.

該主電極244及該子電極242包括一或多種透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 244 and the sub-electrode 242 include one or more transparent conductive materials, such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide (IZO), zinc oxide (ZO), and / or other transparent conductive materials.

根據此示例性具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該子電極242，使得減小該主像素部分的一回掃脈衝電壓。因此，改良該LCD裝置的影像顯示品質。According to this exemplary embodiment, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor Extreme capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the sub-electrode 242 such that a retrace pulse voltage of the main pixel portion is reduced. Therefore, the image display quality of the LCD device is improved.

此外，在一有機絕緣層上之該等接觸通孔的數量係僅有兩個，這可改良該LCD裝置的可靠度，如下文所述。Furthermore, the number of such contact vias on an organic insulating layer is only two, which improves the reliability of the LCD device, as described below.

在本文所論述之示例性具體實施例中，一接觸通孔被形成在一形成該閘極線210的層與一形成該源極線220的層之間；以及另一接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線220的層之間。其他LCD裝置組態具有三個接觸通孔：一接觸通孔被形成在一形成一閘極線的層與一形成一源極線的層之間；以及另兩個接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線的層之間。由於每個接觸通孔增加可能形成一短路的機率，所以此圖解具體實施例降低介於該形成該閘極線210的層與該形成該源極線220的層之間的一短路之機率。介於該形成該閘極線210的層與該形成該源極線220的層之間的一短路可造成該LCD裝置之一故障。In an exemplary embodiment discussed herein, a contact via is formed between a layer forming the gate line 210 and a layer forming the source line 220; and another contact via is formed in A layer forming the pixel electrode member is interposed between the layer forming the source line 220. Other LCD device configurations have three contact vias: a contact via is formed between a layer forming a gate line and a layer forming a source line; and the other two contact vias are formed in a A layer forming the pixel electrode member and the layer forming the source line. Since each contact via increases the probability that a short circuit may be formed, the illustrated embodiment reduces the probability of a short circuit between the layer forming the gate line 210 and the layer forming the source line 220. A short circuit between the layer forming the gate line 210 and the layer forming the source line 220 may cause one of the LCD devices to malfunction.

此外，在此圖解具體實施例中，在每個像素區域中僅形成一個子電極。即，減少子電極之數量，使得可以容易測試該陣列基板200。這可縮短該LCD裝置的製造時間。Moreover, in this illustrative embodiment, only one sub-electrode is formed in each pixel region. That is, the number of sub-electrodes is reduced, so that the array substrate 200 can be easily tested. This can shorten the manufacturing time of the LCD device.

圖12繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖13繪示圖12所示之陣列基板的平面圖。多個接觸通孔被形成在鄰接於一TFT的一儲存線上及相隔於該TFT的該儲存線上。該儲存線之一中心部分的寬度大於該儲存線之一其餘部分的寬度。FIG. 12 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. FIG. 13 is a plan view showing the array substrate shown in FIG. A plurality of contact vias are formed on a storage line adjacent to a TFT and on the storage line spaced apart from the TFT. The width of one of the central portions of the storage line is greater than the width of the remainder of one of the storage lines.

請參考圖12及圖13，該陣列基板300可包括：一閘極線310，其往一水平方向延伸；一閘電極312，其被電連接至該閘極線310；第一與第二下部儲存圖案STL1與STL2，其在一像素區域中與該閘極線310相間隔，並且實質上平行於該閘極線310；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。在一些具體實施例中，該陣列基板300可包括複數個閘極線310、複數個閘電極312、複數個像素區域及複數個第一耦合圖案CPL，其中像素區域係由連貫之閘極線310與資料線320予以界定。Referring to FIG. 12 and FIG. 13 , the array substrate 300 may include: a gate line 310 extending in a horizontal direction; a gate electrode 312 electrically connected to the gate line 310; first and second lower portions Storing patterns STL1 and STL2 spaced apart from the gate line 310 in a pixel region and substantially parallel to the gate line 310; and a first coupling pattern CPL dividing the pixel region into two regions . In some embodiments, the array substrate 300 can include a plurality of gate lines 310, a plurality of gate electrodes 312, a plurality of pixel regions, and a plurality of first coupling patterns CPL, wherein the pixel regions are connected by a continuous gate line 310. It is defined with data line 320.

該陣列基板300可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板300可進一步包括一閘極絕緣層(圖中未繪示)及一作用層314。該閘極絕緣層(圖中未繪示)係在具有該閘極線310及該閘電極312的該絕緣基板(圖中未繪示)上。該作用層314係在該閘極絕緣層(圖中未繪示)上而相對應於該閘電極312。該作用層314具有一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其包含N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 300 can include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 300 can further include a gate insulating layer (not shown) and an active layer 314. The gate insulating layer (not shown) is on the insulating substrate (not shown) having the gate line 310 and the gate electrode 312. The active layer 314 is on the gate insulating layer (not shown) and corresponds to the gate electrode 312. The active layer 314 has a semiconductor layer (having an amorphous germanium, a polysilicon, and/or other suitable material) and a semiconductor layer (which includes an implanted) impurity (which includes an N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板300可包括：一源極線320，其往一縱向方向延伸；一源電極322，其被電連接至該源極線320；以及一汲電極323，其與該源電極322相間隔。在一些具體實施例中，該陣列基板300可包括複數個源極線320、複數個源電極322及複數個汲電極323。每個該等閘電極312、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等源電極322及每個該等汲電極323各形成一相關聯之薄膜電晶體(TFT)。The array substrate 300 can include: a source line 320 extending in a longitudinal direction; a source electrode 322 electrically connected to the source line 320; and a drain electrode 323 spaced apart from the source electrode 322 . In some embodiments, the array substrate 300 can include a plurality of source lines 320, a plurality of source electrodes 322, and a plurality of germanium electrodes 323. Each of the gate electrodes 312, each of the semiconductor layers, each of the semiconductor layers implanted with impurities, each of the source electrodes 322, and each of the germanium electrodes 323 each form an associated thin film Crystal (TFT).

該陣列基板300可進一步包括：一第一上部儲存圖案324，其被電連接至該汲電極323，並且具有一開口，透過該開口而局部曝露出該第一下部儲存圖案STL1；一第一延伸圖案325，其在該像素區域之一左側上電連接至該第一上部儲存圖案324；一第二耦合圖案326，其被電連接至該第一延伸圖案325；一第二延伸圖案327，其在該像素區域之該左側上電連接至該第一延伸圖案325；以及一第二上部儲存圖案328，其被電連接至該第二延伸圖案327，並且具有一開口，透過該開口而局部曝露出該第二下部儲存圖案STL2。在此示例性具體實施例中，該等第一上部儲存圖案324、該等第一延伸圖案325、該等第二耦合圖案326、該等第二延伸圖案327及該等第二上部儲存圖案328形成一汲極線。The array substrate 300 may further include: a first upper storage pattern 324 electrically connected to the germanium electrode 323, and having an opening through which the first lower storage pattern STL1 is partially exposed; An extension pattern 325 electrically connected to the first upper storage pattern 324 on one side of the pixel area; a second coupling pattern 326 electrically connected to the first extension pattern 325; a second extension pattern 327, It is electrically connected to the first extension pattern 325 on the left side of the pixel region; and a second upper storage pattern 328 electrically connected to the second extension pattern 327 and having an opening through which the portion is partially The second lower storage pattern STL2 is exposed. In this exemplary embodiment, the first upper storage patterns 324, the first extension patterns 325, the second coupling patterns 326, the second extension patterns 327, and the second upper storage patterns 328 Form a bungee line.

該陣列基板300可進一步包括一鈍化層(圖中未繪示)及一閘極絕緣層(圖中未繪示)。該鈍化層(圖中未繪示)覆蓋該TFT。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)具有一接觸通孔，透過該接觸通孔而局部曝露該汲電極323。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)保護介於該源電極322與該汲電極323之間的該作用層314。藉由該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)，使該TFT電絕緣於一像素電極構件。該作用層314可包括該半導體層及該已植入雜質之半導體層。The array substrate 300 may further include a passivation layer (not shown) and a gate insulating layer (not shown). The passivation layer (not shown) covers the TFT. The passivation layer (not shown) and the organic insulating layer (not shown) have a contact via through which the germanium electrode 323 is partially exposed. The passivation layer (not shown) and the organic insulating layer (not shown) protect the active layer 314 between the source electrode 322 and the drain electrode 323. The TFT is electrically insulated from the pixel electrode member by the passivation layer (not shown) and the organic insulating layer (not shown). The active layer 314 can include the semiconductor layer and the semiconductor layer to which the impurity has been implanted.

該陣列基板300可進一步包括透過一接觸通孔CNTCP而電連接至該第二耦合圖案326的該像素電極構件。The array substrate 300 may further include the pixel electrode member electrically connected to the second coupling pattern 326 through a contact via CNTCP.

具體而言，該像素電極構件可包括一主電極344、一第一子電極342及一第二子電極346。該主電極344係透過該接觸通孔CNTCP而電連接至該第二耦合圖案326。該第一子電極342被電連接至該第一下部儲存圖案STL1。該第二子電極346被電連接至該第二下部儲存圖案STL2，並且相間隔於該第一子電極342。Specifically, the pixel electrode member may include a main electrode 344, a first sub-electrode 342, and a second sub-electrode 346. The main electrode 344 is electrically connected to the second coupling pattern 326 through the contact via CNTCP. The first sub-electrode 342 is electrically connected to the first lower storage pattern STL1. The second sub-electrode 346 is electrically connected to the second lower storage pattern STL2 and spaced apart from the first sub-electrode 342.

在此圖解具體實施例中，該主電極344具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。該第一子電極342具有兩個線形開口圖樣，該等個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一。該第二子電極346具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之另一桿。該第一子電極342之該等線形開口圖樣係相對於該中心線而對稱於該第二子電極346之該等線形開口圖樣。在一包括陣列基板300之LCD裝置運作中，在置放於陣列基板300與一彩色濾光基板之間的一液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。In the illustrated embodiment, the main electrode 344 has two Y-shaped opening patterns that are symmetric with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°. The first sub-electrode 342 has two linear opening patterns that are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The second sub-electrode 346 has two linear opening patterns that are substantially parallel to the other of the two adjacent rods of the respective Y-shaped opening patterns. The linear opening patterns of the first sub-electrodes 342 are symmetric with respect to the center line and the linear opening patterns of the second sub-electrodes 346. In an LCD device operation including the array substrate 300, a plurality of domains adjacent to the opening pattern of the pixel electrode member are formed in a liquid crystal layer disposed between the array substrate 300 and a color filter substrate.

該主電極344、該第一子電極342及該第二子電極346包括一或多種透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 344, the first sub-electrode 342 and the second sub-electrode 346 comprise one or more transparent conductive materials, such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide ( IZO), zinc oxide (ZO) and/or other transparent conductive materials.

該等域係由該主電極344與該第一子電極342和該第二子電極346所形成，使得可以省略該陣列基板及/或一彩色濾光基板的一配向製程。此外，也可以省略對位層(圖中未顯示)。The fields are formed by the main electrode 344 and the first sub-electrode 342 and the second sub-electrode 346, so that an alignment process of the array substrate and/or a color filter substrate can be omitted. In addition, the alignment layer (not shown) may be omitted.

根據此示例性具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該第一子電極342和該第二子電極346。結果，減小該主電極344的一回掃脈衝電壓，並且改良該LCD裝置的影像顯示品質。According to this exemplary embodiment, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor Extreme capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the first sub-electrode 342 and the second sub-electrode 346. As a result, a retrace pulse voltage of the main electrode 344 is reduced, and the image display quality of the LCD device is improved.

圖14繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖15繪示圖14所示之陣列基板的平面圖。在此圖解具體實施例中，多個接觸通孔被形成在鄰接於一TFT的一汲極線上、相隔於該TFT的該汲極線上以及一儲存線的一中心部分上。在其上形成該等接觸通孔的該汲極線之一部分的寬度大於該汲極線之其餘部分的寬度。該儲存線之該中心部分的寬度大於該儲存線之一其餘部分的寬度。FIG. 14 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. 15 is a plan view of the array substrate shown in FIG. 14. In the illustrated embodiment, a plurality of contact vias are formed on a drain line adjacent to a TFT, on the dipole line of the TFT, and on a central portion of a storage line. The width of a portion of the drain line on which the contact vias are formed is greater than the width of the remaining portion of the drain line. The width of the central portion of the storage line is greater than the width of the remainder of one of the storage lines.

請參考圖14及圖15，該陣列基板400可包括：一閘極線410，其往一水平方向延伸；一閘電極412，其被電連接至該閘極線410；第一與第二下部儲存圖案STL1與STL2，其在一像素區域中與該閘極線410相間隔，並且實質上平行於該閘極線410；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。在一些具體實施例中，該陣列基板400可包括複數個閘極線410、複數個閘電極412、複數個像素區域及複數個第一耦合圖案CPL，其中像素區域係由連貫之閘極線410與資料線420予以界定。Referring to FIG. 14 and FIG. 15, the array substrate 400 may include: a gate line 410 extending in a horizontal direction; a gate electrode 412 electrically connected to the gate line 410; first and second lower portions Storing patterns STL1 and STL2 spaced apart from the gate line 410 in a pixel region and substantially parallel to the gate line 410; and a first coupling pattern CPL dividing the pixel region into two regions . In some embodiments, the array substrate 400 can include a plurality of gate lines 410, a plurality of gate electrodes 412, a plurality of pixel regions, and a plurality of first coupling patterns CPL, wherein the pixel regions are formed by consecutive gate lines 410. It is defined with data line 420.

該陣列基板400可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板400可進一步包括一閘極絕緣層(圖中未繪示)及一作用層414。該閘極絕緣層(圖中未繪示)係在具有該閘極線410及該閘電極412的該絕緣基板(圖中未繪示)上。該作用層414係在該閘極絕緣層(圖中未繪示)上而相對應於該閘電極412。該作用層414包括一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其具有N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 400 can include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 400 can further include a gate insulating layer (not shown) and an active layer 414. The gate insulating layer (not shown) is on the insulating substrate (not shown) having the gate line 410 and the gate electrode 412. The active layer 414 is on the gate insulating layer (not shown) and corresponds to the gate electrode 412. The active layer 414 includes a semiconductor layer (having an amorphous germanium, polycrystalline germanium, and/or other suitable material) and a semiconductor layer that has been doped (eg, implanted) of impurities (having an N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板400可包括：一源極線420，其往一縱向方向延伸；一源電極422，其被電連接至該源極線420；以及一汲電極423，其與該源電極422相間隔。在一些具體實施例中，該陣列基板400可包括複數個源極線420、複數個源電極422及複數個汲電極423。每個該等閘電極412、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等源電極422及每個該等汲電極423各形成一相關聯之薄膜電晶體(TFT)。The array substrate 400 can include: a source line 420 extending in a longitudinal direction; a source electrode 422 electrically connected to the source line 420; and a drain electrode 423 spaced apart from the source electrode 422 . In some embodiments, the array substrate 400 can include a plurality of source lines 420, a plurality of source electrodes 422, and a plurality of germanium electrodes 423. Each of the gate electrodes 412, each of the semiconductor layers, each of the semiconductor layers having implanted impurities, each of the source electrodes 422, and each of the germanium electrodes 423 each form an associated thin film current Crystal (TFT).

該陣列基板400可進一步包括：一第一上部儲存圖案424、一第一延伸圖案425、一第二耦合圖案426、一第二延伸圖案427及一第二上部儲存圖案428。在此示例性具體實施例中，該等第一上部儲存圖案424、該等第一延伸圖案425、該等第二耦合圖案426、該等第二延伸圖案427及該等第二上部儲存圖案428形成一汲極線。在一些具體實施例中，該陣列基板400可進一步包括：複數個第一上部儲存圖案424、複數個第一延伸圖案425、複數個第二耦合圖案426、複數個第二延伸圖案427及複數個第二上部儲存圖案428。The array substrate 400 can further include a first upper storage pattern 424, a first extension pattern 425, a second coupling pattern 426, a second extension pattern 427, and a second upper storage pattern 428. In this exemplary embodiment, the first upper storage patterns 424, the first extension patterns 425, the second coupling patterns 426, the second extension patterns 427, and the second upper storage patterns 428 Form a bungee line. In some embodiments, the array substrate 400 may further include: a plurality of first upper storage patterns 424, a plurality of first extension patterns 425, a plurality of second coupling patterns 426, a plurality of second extension patterns 427, and a plurality of The second upper storage pattern 428.

該第一上部儲存圖案424被電連接至該汲電極423，並且該第一上部儲存圖案424係在該第一下部儲存圖案STL1上。該第一延伸圖案425係在該像素區域之一左側上電連接至該第一上部儲存圖案424。替代做法為，該第一延伸圖案425可能係置在該像素區域之一中心部分上。替代做法為，該第二耦合圖案426被電連接至該第一延伸圖案425，並且覆蓋該第一耦合圖案CPL。該第二延伸圖案427係在該像素區域之該左側上電連接至該第一延伸圖案425。替代做法為，該第二延伸圖案427可能係置在該像素區域之該中心部分上。該第二上部儲存圖案428被電連接至該第二延伸圖案427，並且該第二上部儲存圖案428係在該第二下部儲存圖案STL2上。The first upper storage pattern 424 is electrically connected to the germanium electrode 423, and the first upper storage pattern 424 is attached to the first lower storage pattern STL1. The first extension pattern 425 is electrically connected to the first upper storage pattern 424 on one of the left sides of the pixel region. Alternatively, the first extension pattern 425 may be attached to a central portion of the pixel area. Alternatively, the second coupling pattern 426 is electrically connected to the first extension pattern 425 and covers the first coupling pattern CPL. The second extension pattern 427 is electrically connected to the first extension pattern 425 on the left side of the pixel region. Alternatively, the second extension pattern 427 may be attached to the central portion of the pixel region. The second upper storage pattern 428 is electrically connected to the second extension pattern 427, and the second upper storage pattern 428 is attached to the second lower storage pattern STL2.

該陣列基板400可進一步包括一鈍化層(圖中未繪示)及一閘極絕緣層(圖中未繪示)。該鈍化層(圖中未繪示)覆蓋該TFT。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)具有一接觸通孔，透過該接觸通孔而局部曝露該汲電極423。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)保護介於該源電極422與該汲電極423之間的該作用層414。藉由該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)，使該TFT電絕緣於一像素電極構件。該作用層414可包括該半導體層及該已植入雜質之半導體層。The array substrate 400 can further include a passivation layer (not shown) and a gate insulating layer (not shown). The passivation layer (not shown) covers the TFT. The passivation layer (not shown) and the organic insulating layer (not shown) have a contact via through which the germanium electrode 423 is partially exposed. The passivation layer (not shown) and the organic insulating layer (not shown) protect the active layer 414 between the source electrode 422 and the germanium electrode 423. The TFT is electrically insulated from the pixel electrode member by the passivation layer (not shown) and the organic insulating layer (not shown). The active layer 414 can include the semiconductor layer and the semiconductor layer to which the impurity has been implanted.

該陣列基板400可進一步包括透過一接觸通孔CNTCP而電連接至該第二耦合圖案426的該像素電極構件。The array substrate 400 may further include the pixel electrode member electrically connected to the second coupling pattern 426 through a contact via CNTCP.

具體而言，該像素電極構件可包括一主電極444、一第一子電極442及一第二子電極446。該主電極444係透過該接觸通孔CNTCP而電連接至該第二耦合圖案426。該第一子電極442被電連接至該第一下部儲存圖案STL1。該第二子電極446被電連接至該第二下部儲存圖案STL2，並且相間隔於該第一子電極442。Specifically, the pixel electrode member can include a main electrode 444, a first sub-electrode 442, and a second sub-electrode 446. The main electrode 444 is electrically connected to the second coupling pattern 426 through the contact via CNTCP. The first sub-electrode 442 is electrically connected to the first lower storage pattern STL1. The second sub-electrode 446 is electrically connected to the second lower storage pattern STL2 and spaced apart from the first sub-electrode 442.

在此圖解具體實施例中，該主電極444具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。In the illustrated embodiment, the main electrode 444 has two Y-shaped opening patterns that are symmetric with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°.

該第一子電極442具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一。The first sub-electrode 442 has two linear opening patterns that are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns.

該第二子電極446具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之另一桿。該第一子電極442之該等線形開口圖樣係相對於該中心線而對稱於該第二子電極446之該等線形開口圖樣。在一包括陣列基板400之LCD裝置運作中，在置放於陣列基板400與一彩色濾光基板之間的一液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。The second sub-electrode 446 has two linear opening patterns that are substantially parallel to the other of the two adjacent rods of the respective Y-shaped opening patterns. The linear opening patterns of the first sub-electrodes 442 are symmetric with respect to the center line and the linear opening patterns of the second sub-electrodes 446. In an LCD device operation including the array substrate 400, a plurality of domains adjacent to the opening pattern of the pixel electrode member are formed in a liquid crystal layer disposed between the array substrate 400 and a color filter substrate.

該主電極444、該第一子電極442及該第二子電極446包括一或多種透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 444, the first sub-electrode 442 and the second sub-electrode 446 comprise one or more transparent conductive materials, such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide ( IZO), zinc oxide (ZO) and/or other transparent conductive materials.

該等域係由該主電極444與該第一子電極442和該第二子電極446所形成，使得可以省略該陣列基板及/或一彩色濾光基板的一配向製程。此外，也可以省略對位層(圖中未顯示)。The fields are formed by the main electrode 444 and the first sub-electrode 442 and the second sub-electrode 446, so that an alignment process of the array substrate and/or a color filter substrate can be omitted. In addition, the alignment layer (not shown) may be omitted.

根據此示例性具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該第一子電極442和該第二子電極446。結果，減小該主電極444的一回掃脈衝電壓，並且改良該LCD裝置的影像顯示品質。According to this exemplary embodiment, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor Extreme capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the first sub-electrode 442 and the second sub-electrode 446. As a result, a retrace pulse voltage of the main electrode 444 is reduced, and the image display quality of the LCD device is improved.

圖16繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖17繪示圖16所示之陣列基板的平面圖。在此圖解具體實施例中，一接觸通孔被形成在鄰接於一TFT的一汲極線上。一儲存線之一中心部分的寬度大於該儲存線之一其餘部分的寬度。16 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. 17 is a plan view showing the array substrate shown in FIG. 16. In the illustrated embodiment, a contact via is formed on a drain line adjacent to a TFT. The width of a central portion of one of the storage lines is greater than the width of the remainder of one of the storage lines.

請參考圖16及圖17，該陣列基板500可包括：一閘極線510，其往一水平方向延伸；一閘電極512，其被電連接至該閘極線510；一下部儲存圖案STL，其在一像素區域中與該閘極線510相間隔，並且實質上平行於該閘極線510；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。在一些具體實施例中，該陣列基板500可包括複數個閘極線510、複數個閘電極512、複數個像素區域、複數個下部儲存圖案STL及複數個第一耦合圖案CPL，其中像素區域係由連貫之閘極線510與資料線520予以界定。Referring to FIG. 16 and FIG. 17, the array substrate 500 may include: a gate line 510 extending in a horizontal direction; a gate electrode 512 electrically connected to the gate line 510; and a lower storage pattern STL. It is spaced apart from the gate line 510 in a pixel region and substantially parallel to the gate line 510; and a first coupling pattern CPL that divides the pixel region into two regions. In some embodiments, the array substrate 500 can include a plurality of gate lines 510, a plurality of gate electrodes 512, a plurality of pixel regions, a plurality of lower memory patterns STL, and a plurality of first coupling patterns CPL, wherein the pixel regions are It is defined by a coherent gate line 510 and a data line 520.

該陣列基板500可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板500可進一步包括一閘極絕緣層(圖中未繪示)及一作用層514。該閘極絕緣層(圖中未繪示)係在具有該閘極線510及該閘電極512的該絕緣基板(圖中未繪示)上。該作用層514係在該閘極絕緣層(圖中未繪示)上而相對應於該閘電極512。該作用層514包括一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其具有N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 500 can include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 500 can further include a gate insulating layer (not shown) and an active layer 514. The gate insulating layer (not shown) is on the insulating substrate (not shown) having the gate line 510 and the gate electrode 512. The active layer 514 is corresponding to the gate electrode 512 on the gate insulating layer (not shown). The active layer 514 includes a semiconductor layer (having an amorphous germanium, polysilicon and/or other suitable material) and a semiconductor layer (eg, implanted) of impurities (having an N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板500可包括：一源極線520，其往一縱向方向延伸；一源電極522，其被電連接至該源極線520；以及一汲電極523，其與該源電極522相間隔。在一些具體實施例中，該陣列基板500可包括複數個源極線520、複數個源電極522及複數個汲電極523。每個該等閘電極512、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等源電極522及每個該等汲電極523各形成一相關聯之薄膜電晶體(TFT)。The array substrate 500 can include: a source line 520 extending in a longitudinal direction; a source electrode 522 electrically connected to the source line 520; and a drain electrode 523 spaced apart from the source electrode 522 . In some embodiments, the array substrate 500 can include a plurality of source lines 520, a plurality of source electrodes 522, and a plurality of germanium electrodes 523. Each of the gate electrodes 512, each of the semiconductor layers, each of the semiconductor layers implanted with impurities, each of the source electrodes 522, and each of the germanium electrodes 523 form an associated thin film current Crystal (TFT).

該陣列基板500可進一步包括：一第一上部儲存圖案524，其被電連接至該汲電極523；一第一延伸圖案525，其在該像素區域之一左側上電連接至該第一上部儲存圖案524；以及一第二耦合圖案526，其被電連接至該第一延伸圖案525，以覆蓋一第一耦合圖案CPL。在一些具體實施例中，該陣列基板500可進一步包括複數個第一上部儲存圖案524、複數個第一延伸圖案525及複數個第二耦合圖案526。在此示例性具體實施例中，該等第一上部儲存圖案524、該等第一延伸圖案525及該等第二耦合圖案526形成一汲極線。The array substrate 500 can further include: a first upper storage pattern 524 electrically connected to the germanium electrode 523; a first extension pattern 525 electrically connected to the first upper portion on a left side of the pixel region a pattern 524; and a second coupling pattern 526 electrically connected to the first extension pattern 525 to cover a first coupling pattern CPL. In some embodiments, the array substrate 500 can further include a plurality of first upper storage patterns 524, a plurality of first extension patterns 525, and a plurality of second coupling patterns 526. In this exemplary embodiment, the first upper storage patterns 524, the first extension patterns 525, and the second coupling patterns 526 form a drain line.

該陣列基板500可進一步包括一鈍化層(圖中未繪示)及一閘極絕緣層(圖中未繪示)。該鈍化層(圖中未繪示)及一有機絕緣層(圖中未繪示)覆蓋該TFT。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)保護介於該源電極522與該汲電極523之間的該作用層514。藉由該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)，使該TFT電絕緣於一像素電極構件。該作用層514可包括該半導體層及該已植入雜質之半導體層。The array substrate 500 can further include a passivation layer (not shown) and a gate insulating layer (not shown). The passivation layer (not shown) and an organic insulating layer (not shown) cover the TFT. The passivation layer (not shown) and the organic insulating layer (not shown) protect the active layer 514 between the source electrode 522 and the germanium electrode 523. The TFT is electrically insulated from the pixel electrode member by the passivation layer (not shown) and the organic insulating layer (not shown). The active layer 514 can include the semiconductor layer and the semiconductor layer to which the impurity has been implanted.

該陣列基板500可進一步包括透過該接觸通孔CNTCP而電連接至該第二耦合圖案526的該像素電極構件。該像素電極構件具有開口圖樣。The array substrate 500 may further include the pixel electrode member electrically connected to the second coupling pattern 526 through the contact via CNTCP. The pixel electrode member has an opening pattern.

具體而言，該像素電極構件可包括一主電極544及一子電極542。該主電極544具有一朝向該像素區域之一右側突出的楔形形狀。該子像素542係在該像素區域之未形成該主電極544的一其餘部分上。Specifically, the pixel electrode member may include a main electrode 544 and a sub-electrode 542. The main electrode 544 has a wedge shape that protrudes toward the right side of one of the pixel regions. The sub-pixel 542 is on a remaining portion of the pixel region where the main electrode 544 is not formed.

在此圖解具體實施例中，該主電極544具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。該子像素542被劃分成複數個部分。該子像素542的每個部分各具有一實質上固定寬度。In the illustrated embodiment, the main electrode 544 has two Y-shaped opening patterns that are symmetric with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°. The sub-pixel 542 is divided into a plurality of sections. Each portion of the sub-pixel 542 has a substantially fixed width.

該子電極542具有四個線性開口圖樣。其中兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一上部桿。其餘兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該下部桿。實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該上部桿的該等兩個線形開口圖樣，係相對於該中心線而對稱於實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該下部桿的該等其餘兩個線形開口圖樣。The sub-electrode 542 has four linear opening patterns. Two of the linear opening patterns are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The remaining two linear opening patterns are substantially parallel to the lower bars of the two adjacent rods of the respective Y-shaped opening patterns. The two linear opening patterns of the upper rods of the two adjacent rods substantially parallel to the respective Y-shaped opening patterns are symmetrical with respect to the center line substantially parallel to the Y-shaped opening patterns The remaining two linear opening patterns of the lower bars of the respective two adjacent rods.

替代做法為，該子電極542可具有該楔形形狀及該等Y形開口圖樣，以及該主電極544可具有該等線形開口圖樣。Alternatively, the sub-electrode 542 can have the wedge shape and the Y-shaped opening patterns, and the main electrode 544 can have the linear opening patterns.

在一包括陣列基板500之LCD裝置運作中，在置放於陣列基板500與一彩色濾光基板之間的該液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。In an LCD device operation including the array substrate 500, a plurality of domains adjacent to the opening pattern of the pixel electrode member are formed in the liquid crystal layer disposed between the array substrate 500 and a color filter substrate.

該主電極544及該子電極542包括一或多種透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 544 and the sub-electrode 542 include one or more transparent conductive materials, such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide (IZO), zinc oxide (ZO), and / or other transparent conductive materials.

該等域係由該主電極544與該子電極542所形成，使得可以省略該陣列基板500及/或該彩色濾光基板的一配向製程。此外，也可以省略對位層(圖中未顯示)。The domains are formed by the main electrode 544 and the sub-electrode 542, so that an alignment process of the array substrate 500 and/or the color filter substrate can be omitted. In addition, the alignment layer (not shown) may be omitted.

根據此示例性具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該子電極542。結果，減小該主電極544的一回掃脈衝電壓，並且改良該LCD裝置的影像顯示品質。According to this exemplary embodiment, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor Extreme capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the sub-electrode 542. As a result, a retrace pulse voltage of the main electrode 544 is reduced, and the image display quality of the LCD device is improved.

此外，在一有機絕緣層上之該等接觸通孔的數量係僅有兩個，這可改良該LCD裝置的可靠度，如下文所述。Furthermore, the number of such contact vias on an organic insulating layer is only two, which improves the reliability of the LCD device, as described below.

在本文所論述之示例性具體實施例中，一接觸通孔被形成在一形成該閘極線510的層與一形成該源極線520的層之間；以及另一接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線520的層之間。其他LCD裝置組態具有三個接觸通孔：一接觸通孔被形成在一形成一閘極線的層與一形成一源極線的層之間；以及另兩個接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線的層之間。由於每個接觸通孔增加可能形成一短路的機率，所以此圖解具體實施例降低介於該形成該閘極線510的層與該形成該源極線520的層之間的一短路之機率。介於該形成該閘極線510的層與該形成該源極線520的層之間的一短路可造成該LCD裝置之一故障。In an exemplary embodiment discussed herein, a contact via is formed between a layer forming the gate line 510 and a layer forming the source line 520; and another contact via is formed in A layer forming the pixel electrode member and the layer forming the source line 520. Other LCD device configurations have three contact vias: a contact via is formed between a layer forming a gate line and a layer forming a source line; and the other two contact vias are formed in a A layer forming the pixel electrode member and the layer forming the source line. Since each contact via increases the probability that a short circuit may be formed, the illustrated embodiment reduces the probability of a short circuit between the layer forming the gate line 510 and the layer forming the source line 520. A short circuit between the layer forming the gate line 510 and the layer forming the source line 520 may cause one of the LCD devices to malfunction.

此外，在此圖解具體實施例中，在每個像素區域中僅形成一個子電極。即，減少子電極之數量，使得可以容易測試該陣列基板500。這可縮短該LCD裝置的製造時間。Moreover, in this illustrative embodiment, only one sub-electrode is formed in each pixel region. That is, the number of sub-electrodes is reduced, so that the array substrate 500 can be easily tested. This can shorten the manufacturing time of the LCD device.

圖18繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖19繪示圖18所示之陣列基板的平面圖。在此圖解具體實施例中，多個接觸通孔被形成在鄰接於一TFT的一汲極線上、相隔於該TFT的該汲極線上以及一儲存線上。第一延伸圖案及第二延伸圖案係往該像素區域之該縱向方向而沿著該像素區域之一中心線。18 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. Figure 19 is a plan view showing the array substrate shown in Figure 18. In the illustrated embodiment, a plurality of contact vias are formed on a drain line adjacent to a TFT, on the drain line of the TFT, and on a storage line. The first extension pattern and the second extension pattern are in the longitudinal direction of the pixel region along a centerline of the pixel region.

請參考圖18及圖19，該陣列基板600可包括：一閘極線610，其往一水平方向延伸；一閘電極612，其被電連接至該閘極線610；第一與第二下－部儲存圖案STL1與STL2，其在一像素區域中與該閘極線610相間隔，並且實質上平行於該閘極線610；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。在一些具體實施例中，該陣列基板600可包括複數個閘極線610、複數個閘電極612、複數個像素區域及複數個第一耦合圖案CPL。Referring to FIG. 18 and FIG. 19, the array substrate 600 may include: a gate line 610 extending in a horizontal direction; a gate electrode 612 electrically connected to the gate line 610; first and second a portion storing patterns STL1 and STL2 spaced apart from the gate line 610 in a pixel region and substantially parallel to the gate line 610; and a first coupling pattern CPL dividing the pixel region into two Areas. In some embodiments, the array substrate 600 can include a plurality of gate lines 610, a plurality of gate electrodes 612, a plurality of pixel regions, and a plurality of first coupling patterns CPL.

該陣列基板600可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板600可進一步包括一閘極絕緣層(圖中未繪示)及一作用層614。該閘極絕緣層(圖中未繪示)係在具有該閘極線610及該閘電極612的該絕緣基板(圖中未繪示)上。該作用層614係在該閘極絕緣層(圖中未繪示)上而相對應於該閘電極612。該作用層614包括一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其具有N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 600 can include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 600 can further include a gate insulating layer (not shown) and an active layer 614. The gate insulating layer (not shown) is on the insulating substrate (not shown) having the gate line 610 and the gate electrode 612. The active layer 614 is on the gate insulating layer (not shown) and corresponds to the gate electrode 612. The active layer 614 includes a semiconductor layer (having an amorphous germanium, a polysilicon, and/or other suitable material) and a semiconductor layer that has been doped (eg, implanted) with impurities (having an N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板600可包括：一源極線620，其往一縱向方向延伸；一源電極622，其被電連接至該源極線620；以及一汲電極623，其與該源電極622相間隔。在一些具體實施例中，該陣列基板600可包括複數個源極線620、複數個源電極622及複數個汲電極623。每個該等閘電極612、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等源電極622及每個該等汲電極623各形成一相關聯之薄膜電晶體(TFT)。The array substrate 600 can include a source line 620 extending in a longitudinal direction, a source electrode 622 electrically connected to the source line 620, and a drain electrode 623 spaced apart from the source electrode 622. . In some embodiments, the array substrate 600 can include a plurality of source lines 620, a plurality of source electrodes 622, and a plurality of germanium electrodes 623. Each of the gate electrodes 612, each of the semiconductor layers, each of the semiconductor layers implanted with impurities, each of the source electrodes 622, and each of the germanium electrodes 623 form an associated thin film current Crystal (TFT).

該陣列基板600可進一步包括：一第一上部儲存圖案624、一第一延伸圖案625、一第二耦合圖案626、一第二延伸圖案627及一第二上部儲存圖案628。在一些具體實施例中，該陣列基板600可進一步包括：複數個第一上部儲存圖案624、複數個第一延伸圖案625、複數個第二耦合圖案626、複數個第二延伸圖案627及複數個第二上部儲存圖案628。在此示例性具體實施例中，該等第一上部儲存圖案624、該等第一延伸圖案625、該等第二耦合圖案626、該等第二延伸圖案627及該等第二上部儲存圖案628形成一汲極線。The array substrate 600 can further include a first upper storage pattern 624, a first extension pattern 625, a second coupling pattern 626, a second extension pattern 627, and a second upper storage pattern 628. In some embodiments, the array substrate 600 can further include: a plurality of first upper storage patterns 624, a plurality of first extension patterns 625, a plurality of second coupling patterns 626, a plurality of second extension patterns 627, and a plurality of The second upper storage pattern 628. In this exemplary embodiment, the first upper storage pattern 624, the first extension patterns 625, the second coupling patterns 626, the second extension patterns 627, and the second upper storage patterns 628 Form a bungee line.

具體而言，該第一上部儲存圖案624被電連接至該汲電極623，並且該第一上部儲存圖案624係在該第一下部儲存圖案STL1上。該第一延伸圖案625係往該像素區域之該縱向方向而在該像素區域之一中心線上電連接至該第一上部儲存圖案624。該第二耦合圖案626被電連接至該第一延伸圖案625，並且覆蓋該第一耦合圖案CPL。該第二延伸圖案627係往該縱向方向而在該像素區域之該中心線上電連接至該第一延伸圖案625。該第二上部儲存圖案628被電連接至該第二延伸圖案627，並且該第二上部儲存圖案628係在該第二下部儲存圖案STL2上。Specifically, the first upper storage pattern 624 is electrically connected to the 汲 electrode 623, and the first upper storage pattern 624 is attached to the first lower storage pattern STL1. The first extension pattern 625 is electrically connected to the first upper memory pattern 624 to the longitudinal direction of the pixel region and to a center line of the pixel region. The second coupling pattern 626 is electrically connected to the first extension pattern 625 and covers the first coupling pattern CPL. The second extension pattern 627 is electrically connected to the first extension pattern 625 on the center line of the pixel region in the longitudinal direction. The second upper storage pattern 628 is electrically connected to the second extension pattern 627, and the second upper storage pattern 628 is attached to the second lower storage pattern STL2.

該陣列基板600可進一步包括一鈍化層(圖中未繪示)及一閘極絕緣層(圖中未繪示)。該鈍化層(圖中未繪示)覆蓋該TFT。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)具有一接觸通孔，透過該接觸通孔而局部曝露該汲電極623。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)保護介於該源電極622與該汲電極623之間的該作用層614。藉由該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)，使該TFT電絕緣於一像素電極構件。該作用層614可包括該半導體層及該已植入雜質之半導體層。The array substrate 600 can further include a passivation layer (not shown) and a gate insulating layer (not shown). The passivation layer (not shown) covers the TFT. The passivation layer (not shown) and the organic insulating layer (not shown) have a contact via through which the germanium electrode 623 is partially exposed. The passivation layer (not shown) and the organic insulating layer (not shown) protect the active layer 614 between the source electrode 622 and the drain electrode 623. The TFT is electrically insulated from the pixel electrode member by the passivation layer (not shown) and the organic insulating layer (not shown). The active layer 614 can include the semiconductor layer and the semiconductor layer to which the impurity has been implanted.

該陣列基板600可進一步包括透過一接觸通孔CNTCP而電連接至該第二耦合圖案626的一像素電極構件。The array substrate 600 may further include a pixel electrode member electrically connected to the second coupling pattern 626 through a contact via CNTCP.

具體而言，該像素電極構件可包括一主電極644、一第一子電極642及一第二子電極646。該主電極644係透過該接觸通孔CNTCP而電連接至該第二耦合圖案626。該第一子電極642被電連接至該第一下部儲存圖案STL1。該第二子電極646被電連接至該第二下部儲存圖案STL2，並且相間隔於該第一子電極642。Specifically, the pixel electrode member may include a main electrode 644, a first sub-electrode 642 and a second sub-electrode 646. The main electrode 644 is electrically connected to the second coupling pattern 626 through the contact via CNTCP. The first sub-electrode 642 is electrically connected to the first lower storage pattern STL1. The second sub-electrode 646 is electrically connected to the second lower storage pattern STL2 and spaced apart from the first sub-electrode 642.

在此圖解具體實施例中，該主電極644具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。In the illustrated embodiment, the main electrode 644 has two Y-shaped opening patterns that are symmetric with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°.

該第一子電極642具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一。The first sub-electrode 642 has two linear opening patterns that are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns.

該第二子電極646具有兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之另一桿。該第一子電極642之該等線形開口圖樣係相對於該中心線而對稱於該第二子電極646之該等線形開口圖樣。在一包括陣列基板600之LCD裝置運作中，在置放於陣列基板600與一彩色濾光基板之間的一液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。The second sub-electrode 646 has two linear opening patterns that are substantially parallel to the other of the two adjacent rods of the respective Y-shaped opening patterns. The linear opening patterns of the first sub-electrode 642 are symmetric with respect to the center line and the linear opening patterns of the second sub-electrode 646. In an LCD device operation including the array substrate 600, a plurality of domains adjacent to the opening pattern of the pixel electrode member are formed in a liquid crystal layer disposed between the array substrate 600 and a color filter substrate.

該主電極644、該第一子電極642及該第二子電極646包括一透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 644, the first sub-electrode 642, and the second sub-electrode 646 comprise a transparent conductive material such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide (IZO). , zinc oxide (ZO) and / or other transparent conductive materials.

該等域係由該主電極644與該第一子電極642和該第二子電極646所形成，使得可以省略該陣列基板及/或一彩色濾光基板的一配向製程。此外，也可以省略對位層(圖中未顯示)。The fields are formed by the main electrode 644 and the first sub-electrode 642 and the second sub-electrode 646, so that an alignment process of the array substrate and/or a color filter substrate can be omitted. In addition, the alignment layer (not shown) may be omitted.

根據此示例性具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該第一子電極642和該第二子電極646。結果，減小該主電極644的一回掃脈衝電壓，並且得以改良該LCD裝置的影像顯示品質。According to this exemplary embodiment, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor Extreme capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the first sub-electrode 642 and the second sub-electrode 646. As a result, a retrace pulse voltage of the main electrode 644 is reduced, and the image display quality of the LCD device is improved.

此外，該第一延伸圖案625及該第二延伸圖案627係在該像素區域之該中心線上，以防止介於一形成該源極線620的層與一形成該閘極線610的層之間形成一短路。In addition, the first extension pattern 625 and the second extension pattern 627 are on the center line of the pixel region to prevent between a layer forming the source line 620 and a layer forming the gate line 610. A short circuit is formed.

圖20繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖21繪示圖20所示之陣列基板的平面圖。在此圖解具體實施例中，多個接觸通孔被形成在相間隔於該TFT的一汲極線上。第一延伸圖案及第二延伸圖案係往該像素區域之該縱向方向而沿著該像素區域之一中心線。20 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. 21 is a plan view showing the array substrate shown in FIG. 20. In the illustrated embodiment, a plurality of contact vias are formed on a drain line spaced apart from the TFT. The first extension pattern and the second extension pattern are in the longitudinal direction of the pixel region along a centerline of the pixel region.

請參考圖20及圖21，該陣列基板700可包括：一閘極線710，其往一水平方向延伸；一閘電極712，其被電連接至該閘極線710；第一與第二下部儲存圖案STL1與STL2，其在一像素區域中與該閘極線710相間隔，並且實質上平行於該閘極線710；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。在一些具體實施例中，該陣列基板700可包括複數個閘極線710、複數個閘電極712、複數個像素區域及複數個第一耦合圖案CPL，其中像素區域係由連貫之閘極線710與資料線720予以界定。Referring to FIG. 20 and FIG. 21, the array substrate 700 may include: a gate line 710 extending in a horizontal direction; a gate electrode 712 electrically connected to the gate line 710; first and second lower portions Storing patterns STL1 and STL2 spaced apart from the gate line 710 in a pixel region and substantially parallel to the gate line 710; and a first coupling pattern CPL dividing the pixel region into two regions . In some embodiments, the array substrate 700 can include a plurality of gate lines 710, a plurality of gate electrodes 712, a plurality of pixel regions, and a plurality of first coupling patterns CPL, wherein the pixel regions are connected by a continuous gate line 710. It is defined with data line 720.

該陣列基板700可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板700可進一步包括一閘極絕緣層(圖中未繪示)及一作用層714。該閘極絕緣層(圖中未繪示)係在具有該閘極線710及該閘電極712的該絕緣基板(圖中未繪示)上。該作用層714係在該閘極絕緣層(圖中未繪示)上而相對應於該閘電極712。該作用層714包括一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其具有N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 700 can include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 700 can further include a gate insulating layer (not shown) and an active layer 714. The gate insulating layer (not shown) is on the insulating substrate (not shown) having the gate line 710 and the gate electrode 712. The active layer 714 is on the gate insulating layer (not shown) and corresponds to the gate electrode 712. The active layer 714 includes a semiconductor layer (having an amorphous germanium, a polysilicon and/or other suitable material) and a semiconductor layer (eg, implanted) of impurities (having an N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板700可包括：一源極線720，其往一縱向方向延伸；一源電極722，其被電連接至該源極線720；以及一汲電極723，其與該源電極722相間隔。在一些具體實施例中，該陣列基板700可包括複數個源極線720、複數個源電極722及複數個汲電極723。每個該等閘電極712、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等源電極722及每個該等汲電極723各形成一相關聯之薄膜電晶體(TFT)。The array substrate 700 can include a source line 720 extending in a longitudinal direction, a source electrode 722 electrically connected to the source line 720, and a drain electrode 723 spaced apart from the source electrode 722. . In some embodiments, the array substrate 700 can include a plurality of source lines 720, a plurality of source electrodes 722, and a plurality of germanium electrodes 723. Each of the gate electrodes 712, each of the semiconductor layers, each of the semiconductor layers implanted with impurities, each of the source electrodes 722, and each of the germanium electrodes 723 form an associated thin film current Crystal (TFT).

該陣列基板700可進一步包括：一第一上部儲存圖案724、一第一延伸圖案725、一第二耦合圖案726、一第二延伸圖案727及一第二上部儲存圖案728。在一些具體實施例中，該陣列基板700可進一步包括：複數個第一上部儲存圖案724、複數個第一延伸圖案725、複數個第二耦合圖案726、複數個第二延伸圖案727及複數個第二上部儲存圖案728。在此示例性具體實施例中，該等第一上部儲存圖案724、該等第一延伸圖案725、該等第二耦合圖案726、該等第二延伸圖案727及該等第二上部儲存圖案728形成一汲極線。The array substrate 700 can further include a first upper storage pattern 724, a first extension pattern 725, a second coupling pattern 726, a second extension pattern 727, and a second upper storage pattern 728. In some embodiments, the array substrate 700 can further include: a plurality of first upper storage patterns 724, a plurality of first extension patterns 725, a plurality of second coupling patterns 726, a plurality of second extension patterns 727, and a plurality of The second upper storage pattern 728. In this exemplary embodiment, the first upper storage patterns 724, the first extension patterns 725, the second coupling patterns 726, the second extension patterns 727, and the second upper storage patterns 728 Form a bungee line.

具體而言，該第一上部儲存圖案724被電連接至該汲電極723，並且該第一上部儲存圖案724係在該第一下部儲存圖案STL1上。該第一延伸圖案725係往該像素區域之該縱向方向而在該像素區域之一中心線上電連接至該第一上部儲存圖案724。該第二耦合圖案726被電連接至該第一延伸圖案725，並且覆蓋該第一耦合圖案CPL。該第二延伸圖案727係往該縱向方向而在該像素區域之該中心線上電連接至該第一延伸圖案725。該第二上部儲存圖案728被電連接至該第二延伸圖案727，並且該第二上部儲存圖案728係在該第二下部儲存圖案STL2上。Specifically, the first upper storage pattern 724 is electrically connected to the 汲 electrode 723, and the first upper storage pattern 724 is attached to the first lower storage pattern STL1. The first extension pattern 725 is electrically connected to the first upper storage pattern 724 to the longitudinal direction of the pixel region and to a center line of the pixel region. The second coupling pattern 726 is electrically connected to the first extension pattern 725 and covers the first coupling pattern CPL. The second extension pattern 727 is electrically connected to the first extension pattern 725 on the center line of the pixel region in the longitudinal direction. The second upper storage pattern 728 is electrically connected to the second extension pattern 727, and the second upper storage pattern 728 is attached to the second lower storage pattern STL2.

該陣列基板700可進一步包括一鈍化層(圖中未繪示)及一閘極絕緣層(圖中未繪示)。該鈍化層(圖中未繪示)覆蓋該TFT。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)具有一接觸通孔，透過該接觸通孔而局部曝露該汲電極723。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)保護介於該源電極722與該汲電極723之間的該作用層714。藉由該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)，使該TFT電絕緣於一像素電極構件。該作用層714可包括該半導體層及該已植入雜質之半導體層。The array substrate 700 can further include a passivation layer (not shown) and a gate insulating layer (not shown). The passivation layer (not shown) covers the TFT. The passivation layer (not shown) and the organic insulating layer (not shown) have a contact via through which the germanium electrode 723 is partially exposed. The passivation layer (not shown) and the organic insulating layer (not shown) protect the active layer 714 between the source electrode 722 and the germanium electrode 723. The TFT is electrically insulated from the pixel electrode member by the passivation layer (not shown) and the organic insulating layer (not shown). The active layer 714 can include the semiconductor layer and the semiconductor layer to which the impurity has been implanted.

該陣列基板700可進一步包括透過一接觸通孔CNTCP而電連接至該第二耦合圖案726的一像素電極構件。The array substrate 700 may further include a pixel electrode member electrically connected to the second coupling pattern 726 through a contact via CNTCP.

具體而言，該像素電極構件可包括一主電極742及一子電極744。該子電極744具有一朝向該像素區域之一右側突出的楔形形狀。該主電極742係在該像素區域之未形成該子電極744的一其餘部分上。Specifically, the pixel electrode member may include a main electrode 742 and a sub-electrode 744. The sub-electrode 744 has a wedge shape that protrudes toward the right side of one of the pixel regions. The main electrode 742 is on a remaining portion of the pixel region where the sub-electrode 744 is not formed.

在此圖解具體實施例中，該子電極744具有兩個Y形開口圖樣，該等Y形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等Y形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。藉由該等Y形開口圖樣，將該子像素744劃分成複數個部分。該子電極744的每個部分各具有一實質上固定寬度。In the illustrated embodiment, the sub-electrode 744 has two Y-shaped opening patterns that are symmetric with respect to a center line of the pixel region of the pixel region in the horizontal direction. Each of the central portions of the Y-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°. The sub-pixel 744 is divided into a plurality of portions by the Y-shaped opening patterns. Each portion of the sub-electrode 744 has a substantially fixed width.

該主電極742具有四個線性開口圖樣。其中兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一上部桿。其餘兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一下部桿。實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該上部桿的該等兩個線形開口圖樣，係相對於該中心線而對稱於實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該下部桿的該等其餘兩個線形開口圖樣。The main electrode 742 has four linear opening patterns. Two of the linear opening patterns are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The remaining two linear opening patterns are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The two linear opening patterns of the upper rods of the two adjacent rods substantially parallel to the respective Y-shaped opening patterns are symmetrical with respect to the center line substantially parallel to the Y-shaped opening patterns The remaining two linear opening patterns of the lower bars of the respective two adjacent rods.

在一包括陣列基板700之LCD裝置運作中，在置放於陣列基板700與一彩色濾光基板之間的該液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。In an LCD device operation including the array substrate 700, a plurality of domains adjacent to the opening pattern of the pixel electrode member are formed in the liquid crystal layer disposed between the array substrate 700 and a color filter substrate.

該主電極742及該子電極744包括一透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 742 and the sub-electrode 744 comprise a transparent conductive material such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide (IZO), zinc oxide (ZO) and/or Other transparent conductive materials.

根據此示例性具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該子電極742。結果，減小該主電極744的一回掃脈衝電壓，並且改良該LCD裝置的影像顯示品質。According to this exemplary embodiment, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor Extreme capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the sub-electrode 742. As a result, a retrace pulse voltage of the main electrode 744 is reduced, and the image display quality of the LCD device is improved.

此外，在一有機絕緣層上之該等接觸通孔的數量係僅有兩個，這可改良該LCD裝置的可靠度，如下文所述。Furthermore, the number of such contact vias on an organic insulating layer is only two, which improves the reliability of the LCD device, as described below.

在本文所論述之示例性具體實施例中，一接觸通孔被形成在一形成該閘極線710的層與一形成該源極線720的層之間；以及另一接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線720的層之間。其他LCD裝置組態具有三個接觸通孔：一接觸通孔被形成在一形成一閘極線的層與一形成一源極線的層之間；以及另兩個接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線的層之間。由於每個接觸通孔增加可能形成一短路的機率，所以此圖解具體實施例降低介於該形成該閘極線710的層與該形成該源極線720的層之間的一短路之機率。介於該形成該閘極線710的層與該形成該源極線720的層之間的一短路可造成該LCD裝置之一故障。In an exemplary embodiment discussed herein, a contact via is formed between a layer forming the gate line 710 and a layer forming the source line 720; and another contact via is formed in A layer forming the pixel electrode member is interposed between the layer forming the source line 720. Other LCD device configurations have three contact vias: a contact via is formed between a layer forming a gate line and a layer forming a source line; and the other two contact vias are formed in a A layer forming the pixel electrode member and the layer forming the source line. Since each contact via increases the probability that a short circuit may be formed, the illustrated embodiment reduces the probability of a short circuit between the layer forming the gate line 710 and the layer forming the source line 720. A short circuit between the layer forming the gate line 710 and the layer forming the source line 720 can cause one of the LCD devices to malfunction.

此外，在此圖解具體實施例中，在每個像素區域中僅形成一個子電極。即，減少子電極之數量，使得可以容易測試該陣列基板700。這可縮短該LCD裝置的製造時間。Moreover, in this illustrative embodiment, only one sub-electrode is formed in each pixel region. That is, the number of sub-electrodes is reduced, so that the array substrate 700 can be easily tested. This can shorten the manufacturing time of the LCD device.

另外，該第一延伸圖案725及該第二延伸圖案727係在該像素區域之該中心線上，以防止介於一形成該源極線720的層與一形成該閘極線710的層之間形成一短路。In addition, the first extension pattern 725 and the second extension pattern 727 are on the center line of the pixel region to prevent between a layer forming the source line 720 and a layer forming the gate line 710. A short circuit is formed.

在此示例性具體實施例中，一TFT被形成在每個像素區域中。在一些具體實施例中，複數個TFT可被形成在每個像素區域中。In this exemplary embodiment, a TFT is formed in each of the pixel regions. In some embodiments, a plurality of TFTs can be formed in each pixel region.

圖22繪示根據本發明另一示例性具體實施例之LCD面板的平面圖。圖23繪示圖22所示之陣列基板的平面圖。在此圖解具體實施例中，兩個TFT被形成在每個像素區域上。一主像素係在該像素區域之一中心部分上；以及一子像素係在該像素區域之一周邊部分上。22 is a plan view of an LCD panel in accordance with another exemplary embodiment of the present invention. 23 is a plan view showing the array substrate shown in FIG. 22. In the illustrated embodiment, two TFTs are formed on each of the pixel regions. A primary pixel is on a central portion of the pixel region; and a sub-pixel is on a peripheral portion of the pixel region.

請參考圖22及圖23，該陣列基板800可包括：第一閘極線810M和第二閘極線810S，其往一水平方向延伸；第一閘電極812M和第二閘電極812S，其分別電連接至該第一閘極線810M和該第二閘極線810S；一第一下部儲存圖案STL，其在一像素區域中相間隔於該第一閘極線810M和該第二閘極線810S，並且實質上垂直於該第一閘極線810M；以及一第一耦合圖案CPL，其將該像素區域劃分成兩個區域。該第一耦合圖案CPL係鄰接於該像素區域之一右側而電連接至該第一下部儲存圖案STL。在一些具體實施例中，該陣列基板800可包括複數個第一下部儲存圖案STL及複數個第一耦合圖案CPL。Referring to FIG. 22 and FIG. 23, the array substrate 800 may include: a first gate line 810M and a second gate line 810S extending in a horizontal direction; a first gate electrode 812M and a second gate electrode 812S, respectively Electrically connected to the first gate line 810M and the second gate line 810S; a first lower storage pattern STL spaced apart from the first gate line 810M and the second gate in a pixel region Line 810S, and substantially perpendicular to the first gate line 810M; and a first coupling pattern CPL that divides the pixel area into two regions. The first coupling pattern CPL is electrically connected to the first lower storage pattern STL adjacent to one of the right sides of the pixel region. In some embodiments, the array substrate 800 can include a plurality of first lower storage patterns STL and a plurality of first coupling patterns CPL.

該陣列基板800可包括一包含氮化矽、氧化矽及/或其他絕緣材料之絕緣基板(圖中未繪示)。該陣列基板800可進一步包括一閘極絕緣層(圖中未繪示)及第一作用層814M和第二作用層814S。該閘極絕緣層(圖中未繪示)係在具有該第一閘極線810M、該第二閘極線810S、該第一閘電極812M及該第二閘電極812S的該絕緣基板(圖中未繪示)上。該第一作用層814M及該第二作用層814S係在該閘極絕緣層(圖中未繪示)上而分別相對應於該第一閘電極812M及該第二閘電極812S。該第一作用層814M及該第二作用層814S各包括一半導體層(其具有非晶系矽、多晶矽及/或其他適合之材料)及一已摻雜(例如，已植入)雜質之半導體層(其具有N＋非晶系矽、N＋多晶矽及/或其他已摻雜之材料)。The array substrate 800 can include an insulating substrate (not shown) including tantalum nitride, hafnium oxide, and/or other insulating materials. The array substrate 800 can further include a gate insulating layer (not shown) and a first active layer 814M and a second active layer 814S. The gate insulating layer (not shown) is disposed on the insulating substrate having the first gate line 810M, the second gate line 810S, the first gate electrode 812M, and the second gate electrode 812S (FIG. Not shown in the middle). The first active layer 814M and the second active layer 814S are respectively on the gate insulating layer (not shown) and correspond to the first gate electrode 812M and the second gate electrode 812S, respectively. The first active layer 814M and the second active layer 814S each comprise a semiconductor layer (having an amorphous germanium, polysilicon and/or other suitable material) and a semiconductor doped (eg, implanted) impurity A layer (having N+ amorphous germanium, N+ polysilicon and/or other doped materials).

該陣列基板800可包括：一源極線820，其往一縱向方向延伸；第一源電極822M和第二源電極822S，其被電連接至該源極線820；以及第一汲電極823M和第二汲電極823S，其與該第一源電極822M和該第二源電極822S相間隔。在一些具體實施例中，該陣列基板800可包括複數個源極線820。每個該等第一閘電極812M、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等第一源電極822M及每個該等第一汲電極823M各形成一相關聯之主TFT。每個該等第二閘電極812S、每個該等半導體層、每個該等已植入雜質之半導體層、每個該等第二源電極822S及每個該等第二汲電極823S各形成一相關聯之子TFT。The array substrate 800 can include: a source line 820 extending in a longitudinal direction; a first source electrode 822M and a second source electrode 822S electrically connected to the source line 820; and a first drain electrode 823M and The second drain electrode 823S is spaced apart from the first source electrode 822M and the second source electrode 822S. In some embodiments, the array substrate 800 can include a plurality of source lines 820. Each of the first gate electrodes 812M, each of the semiconductor layers, each of the semiconductor layers implanted with impurities, each of the first source electrodes 822M, and each of the first germanium electrodes 823M are formed An associated main TFT. Each of the second gate electrodes 812S, each of the semiconductor layers, each of the semiconductor layers implanted with impurities, each of the second source electrodes 822S, and each of the second germanium electrodes 823S are formed An associated sub-TFT.

該陣列基板800可進一步包括：一第一延伸圖案825M，其被電連接至第一汲電極823M且鄰接於該像素區域之一左側；一第一上部儲存圖案824M，其被電連接至該第一延伸圖案825M且在該第一耦合圖案CPL上；一第二上部儲存圖案824S，其被電連接至該第二汲電極823S且在該第一下部儲存圖案STL上；以及一第二延伸圖案825S，其被電連接至該第二上部儲存圖案824S且鄰接於該像素區域之一右側。在一些具體實施例中，該陣列基板800可進一步包括複數個第一延伸圖案825M、複數個第一上部儲存圖案824M、複數個第二上部儲存圖案824S及複數個第二延伸圖案825S。在此示例性具體實施例中，該等第一上部儲存圖案824M及該等第一延伸圖案825M形成一第一汲極線；該等第二上部儲存圖案824S及該等第二延伸圖案825S形成一第二汲極線。The array substrate 800 can further include: a first extension pattern 825M electrically connected to the first germanium electrode 823M and adjacent to one of the left side of the pixel region; a first upper memory pattern 824M electrically connected to the first An extension pattern 825M and on the first coupling pattern CPL; a second upper storage pattern 824S electrically connected to the second germanium electrode 823S and on the first lower storage pattern STL; and a second extension A pattern 825S is electrically connected to the second upper storage pattern 824S and adjacent to one of the right of the pixel region. In some embodiments, the array substrate 800 can further include a plurality of first extension patterns 825M, a plurality of first upper storage patterns 824M, a plurality of second upper storage patterns 824S, and a plurality of second extension patterns 825S. In this exemplary embodiment, the first upper storage patterns 824M and the first extension patterns 825M form a first drain line; the second upper storage patterns 824S and the second extension patterns 825S are formed. A second bungee line.

該陣列基板800可進一步包括一第二耦合圖案826，該第二耦合圖案826電連接至該第一汲電極823M且覆蓋該第一耦合圖案CPL。在一些具體實施例中，該陣列基板800可進一步包括複數個第二耦合圖案826。The array substrate 800 can further include a second coupling pattern 826 electrically connected to the first germanium electrode 823M and covering the first coupling pattern CPL. In some embodiments, the array substrate 800 can further include a plurality of second coupling patterns 826.

該陣列基板800可進一步包括一鈍化層(圖中未繪示)及一閘極絕緣層(圖中未繪示)。該鈍化層(圖中未繪示)覆蓋該主TFT及該子TFT。該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)具有多個接觸通孔，透過該等接觸通孔而局部曝露該第二上部儲存圖案824S及該第二耦合圖案826。The array substrate 800 can further include a passivation layer (not shown) and a gate insulating layer (not shown). The passivation layer (not shown) covers the main TFT and the sub-TFT. The passivation layer (not shown) and the organic insulating layer (not shown) have a plurality of contact vias through which the second upper memory pattern 824S and the second coupling are partially exposed. Pattern 826.

該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)保護介於該第一源電極822M與該第一汲電極823M之間的該第一作用層814M，以及介於該第二源電極822S與該第二汲電極823S之間的該第二作用層814S。藉由該鈍化層(圖中未繪示)及該有機絕緣層(圖中未繪示)，使該主TFT及該子TFT電絕緣於一像素電極構件。該第一作用層814M及該第二作用層814S各可包括該半導體層及該已植入雜質之半導體層。The passivation layer (not shown) and the organic insulating layer (not shown) protect the first active layer 814M between the first source electrode 822M and the first germanium electrode 823M, and The second active layer 814S is between the second source electrode 822S and the second drain electrode 823S. The main TFT and the sub-TFT are electrically insulated from the pixel electrode member by the passivation layer (not shown) and the organic insulating layer (not shown). The first active layer 814M and the second active layer 814S may each include the semiconductor layer and the semiconductor layer implanted with impurities.

該陣列基板800可進一步包括一主電極844及一子電極842。該主電極844係透過一接觸通孔CNTCP而電連接至該第二耦合圖案826。該子電極842係透過一第一接觸通孔CNTST1而電連接至該第二上部儲存圖案824S。The array substrate 800 can further include a main electrode 844 and a sub-electrode 842. The main electrode 844 is electrically connected to the second coupling pattern 826 through a contact via CNTCP. The sub-electrode 842 is electrically connected to the second upper storage pattern 824S through a first contact via CNTST1.

該主電極844具有一朝向該像素區域之一右側突出的楔形形狀。該子電極842係在該像素區域之未形成該主電極844的一其餘部分上。The main electrode 844 has a wedge shape that protrudes toward the right side of one of the pixel regions. The sub-electrode 842 is on a remaining portion of the pixel region where the main electrode 844 is not formed.

該主電極844具有兩個V形開口圖樣，該等V形開口圖樣係相對於該像素區域之該水平方向的該像素區域之一中心線呈對稱。該等V形開口圖樣中之該較小V形開口圖樣的未端部分被展開，並且該等V形開口圖樣中之該較小V形開口圖樣的一中心部分被封閉。該等V形開口圖樣中之該較大V形開口圖樣的一中心部分被展開。該等V形開口圖樣各自的一中心部分具有構成約90°內角的兩個鄰接桿。藉由該等V形開口圖樣，將該子電極844劃分成複數個部分。該主電極844之該等劃分部分係互相電連接。該主電極844的每個部分各具有一實質上固定寬度。The main electrode 844 has two V-shaped opening patterns which are symmetrical with respect to a center line of the pixel region of the pixel region in the horizontal direction. The end portions of the smaller V-shaped opening pattern in the V-shaped opening patterns are unfolded, and a central portion of the smaller V-shaped opening pattern in the V-shaped opening patterns is closed. A central portion of the larger V-shaped opening pattern in the V-shaped opening pattern is unfolded. Each of the central portions of the V-shaped opening patterns has two adjacent rods constituting an internal angle of about 90°. The sub-electrodes 844 are divided into a plurality of portions by the V-shaped opening patterns. The divided portions of the main electrode 844 are electrically connected to each other. Each portion of the main electrode 844 has a substantially fixed width.

該子電極842具有四個線性開口圖樣。其中兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之一上部桿。其餘兩個線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該下部桿。實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該上部桿的該等兩個線形開口圖樣，係相對於該中心線而對稱於實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之該下部桿的該等其餘兩個線形開口圖樣。The sub-electrode 842 has four linear opening patterns. Two of the linear opening patterns are substantially parallel to one of the two adjacent rods of the respective Y-shaped opening patterns. The remaining two linear opening patterns are substantially parallel to the lower bars of the two adjacent rods of the respective Y-shaped opening patterns. The two linear opening patterns of the upper rods of the two adjacent rods substantially parallel to the respective Y-shaped opening patterns are symmetrical with respect to the center line substantially parallel to the Y-shaped opening patterns The remaining two linear opening patterns of the lower bars of the respective two adjacent rods.

在一包括陣列基板800之LCD裝置運作中，在該液晶層中，形成鄰接於該像素電極構件的該等開口圖樣的複數個域。In an LCD device operation including the array substrate 800, a plurality of domains of the opening patterns adjacent to the pixel electrode members are formed in the liquid crystal layer.

該主電極844及該子電極842包括一透明導電材料，諸如氧化銦錫(ITO)、非晶系氧化銦錫(a－ITO)、氧化銦鋅(IZO)、氧化鋅(ZO)及/或其他透明導電材料。The main electrode 844 and the sub-electrode 842 comprise a transparent conductive material such as indium tin oxide (ITO), amorphous indium tin oxide (a-ITO), indium zinc oxide (IZO), zinc oxide (ZO) and/or Other transparent conductive materials.

該等域係由該主電極844與該子電極842所形成，使得可以省略該陣列基板及/或該一色濾光基板的一配向製程。此外，也可以省略對位層(圖中未顯示)。The fields are formed by the main electrode 844 and the sub-electrode 842, so that an alignment process of the array substrate and/or the color filter substrate can be omitted. In addition, the alignment layer (not shown) may be omitted.

根據本發明具體實施例，一總閘極－源極電容被劃分成該閘極－源極電容器的一閘極－源極電容及該額外閘極－源極電容器的一額外閘極－源極電容。該額外閘極－源極電容器的該額外閘極－源極電容對應於該子電極。結果，減小該主電極的一回掃脈衝電壓，並且得以改良該LCD裝置的影像顯示品質。According to an embodiment of the invention, a total gate-source capacitance is divided into a gate-source capacitance of the gate-source capacitor and an additional gate-source of the additional gate-source capacitor capacitance. The additional gate-source capacitance of the additional gate-source capacitor corresponds to the sub-electrode. As a result, a retrace pulse voltage of the main electrode is reduced, and the image display quality of the LCD device is improved.

此外，該子電極部分顯示介於一零灰階與一中間灰階之間的黑色，藉此減少一低灰階的一殘像。另外，減少在一有機絕緣層上之該等接觸通孔的數量，這可改良該LCD裝置的可靠度。In addition, the sub-electrode portion displays black between a zero gray scale and an intermediate gray scale, thereby reducing an afterimage of a low gray scale. In addition, the number of such contact vias on an organic insulating layer is reduced, which improves the reliability of the LCD device.

在本文所論述之具體實施例中，一接觸通孔被形成在一形成該閘極線的層與一形成該源極線的層之間；以及另一接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線的層之間。其他LCD裝置組態具有三個接觸通孔：一接觸通孔被形成在一形成一閘極線的層與一形成一源極線的層之間；以及另兩個接觸通孔被形成在一形成該像素電極構件的層與該形成該源極線的層之間。由於每個接觸通孔增加可能形成一短路的機率，所以此圖解具體實施例降低介於該形成該閘極線的層與該形成該源極線的層之間的一短路之機率。In a specific embodiment discussed herein, a contact via is formed between a layer forming the gate line and a layer forming the source line; and another contact via is formed in the forming the pixel A layer between the electrode member and the layer forming the source line. Other LCD device configurations have three contact vias: a contact via is formed between a layer forming a gate line and a layer forming a source line; and the other two contact vias are formed in a A layer forming the pixel electrode member and the layer forming the source line. Since each contact via increases the probability that a short circuit may be formed, this illustrated embodiment reduces the probability of a short circuit between the layer forming the gate line and the layer forming the source line.

此外，僅一TFT被形成在每個像素區域中。即，減少子電極之數量，使得可以容易測試該陣列基板，並且可以縮短該LCD裝置的製造時間。Further, only one TFT is formed in each pixel region. That is, the number of sub-electrodes is reduced, so that the array substrate can be easily tested, and the manufacturing time of the LCD device can be shortened.

另外，該汲極線之一部分係在該像素區域之一中心部分上，這可降低介於該源極線與該汲極線之間的一短路之機率。Additionally, one portion of the drain line is on a central portion of the pixel region, which reduces the probability of a short circuit between the source line and the drain line.

已參考彼等示例性具體實施例來說明本發明。但是，顯而易見，熟悉此項技術者應明白可根據前文說明內容進行許多替代修改及變化。據此，本發明包含屬於隨附申請專利範圍之精神與範疇內的所有此類替代修改及變化。The invention has been described with reference to the exemplary embodiments thereof. However, it will be apparent to those skilled in the art that many alternative modifications and variations are possible in light of the foregoing description. Accordingly, the present invention includes all such alternative modifications and variations that come within the spirit and scope of the appended claims.

100．．．陣列基板100. . . Array substrate

105．．．絕緣基板105. . . Insulating substrate

110．．．閘極線110. . . Gate line

112．．．閘電極112. . . Gate electrode

113．．．閘極絕緣層113. . . Gate insulation

114．．．作用層114. . . Working layer

120．．．源極線(圖1)120. . . Source line (Figure 1)

120．．．資料線(圖6)120. . . Data line (Figure 6)

120．．．汲極線(圖9)120. . . Bungee line (Figure 9)

122．．．源電極122. . . Source electrode

123．．．汲電極123. . . Helium electrode

124．．．第一上部儲存圖案124. . . First upper storage pattern

125．．．第一延伸圖案125. . . First extension pattern

126．．．第二耦合圖案126. . . Second coupling pattern

127．．．第二延伸圖案127. . . Second extension pattern

128．．．第二上部儲存圖案128. . . Second upper storage pattern

130．．．鈍化層130. . . Passivation layer

132．．．有機絕緣層132. . . Organic insulation

140．．．像素電極構件140. . . Pixel electrode member

142．．．第一子電極142. . . First subelectrode

142．．．像素電極(圖9)142. . . Pixel electrode (Figure 9)

144．．．主電極144. . . Main electrode

146．．．第二子電極146. . . Second subelectrode

180．．．液晶層180. . . Liquid crystal layer

190．．．彩色濾光基板190. . . Color filter substrate

192．．．透明基板192. . . Transparent substrate

194．．．彩色濾光層194. . . Color filter layer

196．．．共同電極196. . . Common electrode

200．．．陣列基板200. . . Array substrate

210．．．閘極線210. . . Gate line

212．．．閘電極212. . . Gate electrode

214．．．作用層214. . . Working layer

220．．．資料線(源極線)220. . . Data line (source line)

222．．．源電極222. . . Source electrode

223．．．汲電極223. . . Helium electrode

224．．．第一上部儲存圖案224. . . First upper storage pattern

225．．．第一延伸圖案225. . . First extension pattern

226．．．第二耦合圖案226. . . Second coupling pattern

227．．．第二延伸圖案227. . . Second extension pattern

228．．．第二上部儲存圖案228. . . Second upper storage pattern

230．．．鈍化層230. . . Passivation layer

232．．．有機絕緣層232. . . Organic insulation

242．．．子電極242. . . Subelectrode

244．．．主電極244. . . Main electrode

300．．．陣列基板300. . . Array substrate

310．．．閘極線310. . . Gate line

312．．．閘電極312. . . Gate electrode

314．．．作用層314. . . Working layer

320．．．資料線(源極線)320. . . Data line (source line)

322．．．源電極322. . . Source electrode

323．．．汲電極323. . . Helium electrode

324．．．第一上部儲存圖案324. . . First upper storage pattern

325．．．第一延伸圖案325. . . First extension pattern

326．．．第二耦合圖案326. . . Second coupling pattern

327．．．第二延伸圖案327. . . Second extension pattern

328．．．第二上部儲存圖案328. . . Second upper storage pattern

342．．．第一子電極342. . . First subelectrode

344．．．主電極344. . . Main electrode

346．．．第二子電極346. . . Second subelectrode

400．．．陣列基板400. . . Array substrate

410．．．閘極線410. . . Gate line

412．．．閘電極412. . . Gate electrode

414．．．作用層414. . . Working layer

420．．．資料線(源極線)420. . . Data line (source line)

422．．．源電極422. . . Source electrode

423．．．汲電極423. . . Helium electrode

424．．．第一上部儲存圖案424. . . First upper storage pattern

425．．．第一延伸圖案425. . . First extension pattern

427．．．第二延伸圖案427. . . Second extension pattern

428．．．第二上部儲存圖案428. . . Second upper storage pattern

442．．．第一子電極442. . . First subelectrode

444．．．主電極444. . . Main electrode

446．．．第二子電極446. . . Second subelectrode

500．．．陣列基板500. . . Array substrate

510．．．閘極線510. . . Gate line

512．．．閘電極512. . . Gate electrode

514．．．作用層514. . . Working layer

520．．．資料線(源極線)520. . . Data line (source line)

522．．．源電極522. . . Source electrode

523．．．汲電極523. . . Helium electrode

524．．．第一上部儲存圖案524. . . First upper storage pattern

525．．．第一延伸圖案525. . . First extension pattern

526．．．第二耦合圖案526. . . Second coupling pattern

542．．．子電極542. . . Subelectrode

544．．．主電極544. . . Main electrode

600．．．陣列基板600. . . Array substrate

610．．．閘極線610. . . Gate line

612．．．閘電極612. . . Gate electrode

614．．．作用層614. . . Working layer

620．．．源極線620. . . Source line

622．．．源電極622. . . Source electrode

623．．．汲電極623. . . Helium electrode

624．．．第一上部儲存圖案624. . . First upper storage pattern

625．．．第一延伸圖案625. . . First extension pattern

626．．．第二耦合圖案626. . . Second coupling pattern

627．．．第二延伸圖案627. . . Second extension pattern

628．．．第二上部儲存圖案628. . . Second upper storage pattern

642．．．第一子電極642. . . First subelectrode

644．．．主電極644. . . Main electrode

646．．．第二子電極646. . . Second subelectrode

700．．．陣列基板700. . . Array substrate

710．．．閘極線710. . . Gate line

712．．．閘電極712. . . Gate electrode

714．．．作用層714. . . Working layer

720．．．資料線(源極線)720. . . Data line (source line)

722．．．源電極722. . . Source electrode

723．．．汲電極723. . . Helium electrode

724．．．第一上部儲存圖案724. . . First upper storage pattern

725．．．第一延伸圖案725. . . First extension pattern

726．．．第二耦合圖案726. . . Second coupling pattern

727．．．第二延伸圖案727. . . Second extension pattern

728．．．第二上部儲存圖案728. . . Second upper storage pattern

742．．．主電極742. . . Main electrode

744．．．子電極744. . . Subelectrode

800．．．陣列基板800. . . Array substrate

810M．．．第一閘極線810M. . . First gate line

810S．．．第二閘極線810S. . . Second gate line

812M．．．第一閘電極812M. . . First gate electrode

812S．．．第二閘電極812S. . . Second gate electrode

814M．．．第一作用層814M. . . First active layer

814S．．．第二作用層814S. . . Second active layer

820．．．源極線820. . . Source line

822M．．．第一源電極822M. . . First source electrode

822S．．．第二源電極822S. . . Second source electrode

823M．．．第一汲電極823M. . . First electrode

823S．．．第二汲電極823S. . . Second electrode

824M．．．第一上部儲存圖案824M. . . First upper storage pattern

824S．．．第二上部儲存圖案824S. . . Second upper storage pattern

825M．．．第一延伸圖案825M. . . First extension pattern

825S．．．第二延伸圖案825S. . . Second extension pattern

826．．．第二耦合圖案826. . . Second coupling pattern

842．．．子電極842. . . Subelectrode

844．．．主電極844. . . Main electrode

CNTST1．．．第一接觸通孔CNTST1. . . First contact through hole

CNTST2．．．第二接觸通孔CNTST2. . . Second contact through hole

CNTST3．．．第三接觸通孔CNTST3. . . Third contact through hole

CNTST4．．．第四接觸通孔CNTST4. . . Fourth contact through hole

CNTCP．．．第五接觸通孔(圖2，圖7)CNTCP. . . Fifth contact through hole (Figure 2, Figure 7)

CNTCP．．．接觸通孔(圖12，圖13)CNTCP. . . Contact through hole (Figure 12, Figure 13)

Cgs1．．．閘極－源極電容器Cgs1. . . Gate-source capacitor

Cgs2．．．額外閘極－源極電容器Cgs2. . . Additional gate-source capacitor

ClcM．．．主液晶電容器ClcM. . . Main liquid crystal capacitor

CstM．．．主儲存電容器CstM. . . Main storage capacitor

Ccp1．．．第一耦合電容器Ccp1. . . First coupling capacitor

Ccp2．．．第二耦合電容器Ccp2. . . Second coupling capacitor

Clcs1．．．第一液晶電容器Clcs1. . . First liquid crystal capacitor

Csts1．．．第一儲存電容器Csts1. . . First storage capacitor

Clcs2．．．第二液晶電容器Clcs2. . . Second liquid crystal capacitor

Clcs2．．．第二液晶電容器Clcs2. . . Second liquid crystal capacitor

Cgs．．．閘極－源極電容Cgs. . . Gate-source capacitance

Cst．．．儲存電容Cst. . . Storage capacitor

Clc．．．液晶電容Clc. . . Liquid crystal capacitor

CPL．．．第一耦合圖案CPL. . . First coupling pattern

STL．．．下部儲存圖案STL. . . Lower storage pattern

STL1．．．第一下部儲存圖案STL1. . . First lower storage pattern

STL2．．．第二下部儲存圖案STL2. . . Second lower storage pattern

GL．．．閘極線GL. . . Gate line

DL．．．資料線DL. . . Data line

TFT．．．薄膜電晶體TFT. . . Thin film transistor

MP．．．主像素部分MP. . . Main pixel portion

SP1．．．第一子像素部分SP1. . . First sub-pixel portion

SP2．．．第二子像素部分SP2. . . Second sub-pixel portion

Vcom．．．共同電壓Vcom. . . Common voltage

Vst．．．儲存電壓Vst. . . Storage voltage

Vk．．．回掃脈衝電壓Vk. . . Sweep pulse voltage

Von．．．閘極開通電壓Von. . . Gate turn-on voltage

Voff．．．閘極關斷電壓Voff. . . Gate turn-off voltage

藉由詳讀【實施方式】中參考附圖所說明的示例性具體實施例，將可明白本發明的前述及其他態樣，圖式中：圖1繪示根據本發明示例性具體實施例之LCD面板的平面圖；圖2繪示以沿圖1所示之I－I'線為例的斷面圖；圖3繪示圖2所示之陣列基板的電路圖；圖4到8繪示一種製造圖3所示之陣列基板之方法的平面圖；圖9繪示根據本發明示例性具體實施例之閘極－源極電容器的平面圖；圖10繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；圖11繪示圖10所示之陣列基板的平面圖；圖12繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；圖13繪示圖12所示之陣列基板的平面圖；圖14繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；圖15繪示圖14所示之陣列基板的平面圖；圖16繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；圖17繪示圖16所示之陣列基板的平面圖；圖18繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；圖19繪示圖18所示之陣列基板的平面圖；圖20繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；圖21繪示圖20所示之陣列基板的平面圖；圖22繪示根據本發明另一示例性具體實施例之LCD面板的平面圖；以及圖23繪示圖22所示之陣列基板的平面圖。The foregoing and other aspects of the present invention will be understood by the following detailed description of the exemplary embodiments FIG. 2 is a cross-sectional view taken along line I-I' shown in FIG. 1; FIG. 3 is a circuit diagram of the array substrate shown in FIG. 2; and FIGS. 4 to 8 are diagrams showing a manufacturing process. 3 is a plan view of a method of the array substrate shown in FIG. 3; FIG. 9 is a plan view of a gate-source capacitor according to an exemplary embodiment of the present invention; and FIG. 10 illustrates an LCD according to another exemplary embodiment of the present invention. FIG. 11 is a plan view of the array substrate shown in FIG. 10; FIG. 12 is a plan view of the LCD panel according to another exemplary embodiment of the present invention; FIG. 14 is a plan view of an LCD panel according to another exemplary embodiment of the present invention; FIG. 15 is a plan view of the array substrate shown in FIG. 14; FIG. 16 is a view showing another exemplary embodiment of the present invention. a plan view of the LCD panel; FIG. 17 shows FIG. Figure 18 is a plan view of an LCD panel according to another exemplary embodiment of the present invention; Figure 19 is a plan view of the array substrate shown in Figure 18; Figure 20 is another plan view of the array substrate shown in Figure 18; A plan view of an LCD panel of an exemplary embodiment; FIG. 21 is a plan view of the array substrate shown in FIG. 20; FIG. 22 is a plan view of an LCD panel according to another exemplary embodiment of the present invention; A plan view of the array substrate shown in FIG.

100．．．陣列基板100. . . Array substrate

105．．．絕緣基板105. . . Insulating substrate

110．．．閘極線110. . . Gate line

112．．．閘電極112. . . Gate electrode

113．．．閘極絕緣層113. . . Gate insulation

114．．．作用層114. . . Working layer

122．．．源電極122. . . Source electrode

123．．．汲電極123. . . Helium electrode

124．．．第一上部儲存圖案124. . . First upper storage pattern

125．．．第一延伸圖案125. . . First extension pattern

126．．．第二耦合圖案126. . . Second coupling pattern

127．．．第二延伸圖案127. . . Second extension pattern

128．．．第二上部儲存圖案128. . . Second upper storage pattern

130．．．鈍化層130. . . Passivation layer

132．．．有機絕緣層132. . . Organic insulation

140．．．像素電極構件140. . . Pixel electrode member

142．．．第一子電極142. . . First subelectrode

144．．．主電極144. . . Main electrode

146．．．第二子電極146. . . Second subelectrode

180．．．液晶層180. . . Liquid crystal layer

190．．．彩色濾光基板190. . . Color filter substrate

192．．．透明基板192. . . Transparent substrate

194．．．彩色濾光層194. . . Color filter layer

196．．．共同電極196. . . Common electrode

CNTST1．．．第一接觸通孔CNTST1. . . First contact through hole

CNTST2．．．第二接觸通孔CNTST2. . . Second contact through hole

CNTST3．．．第三接觸通孔CNTST3. . . Third contact through hole

CNTST4．．．第四接觸通孔CNTST4. . . Fourth contact through hole

CNTCP．．．第五接觸通孔CNTCP. . . Fifth contact through hole

CPL．．．第一耦合圖案CPL. . . First coupling pattern

STL1．．．第一下部儲存圖案STL1. . . First lower storage pattern

STL2．．．第二下部儲存圖案STL2. . . Second lower storage pattern

Claims (23)

一種陣列基板，包括：一絕緣基板；一開關，其在該絕緣基板上之一像素區域中，該像素區域係由一第一閘極線與一鄰接之第一資料線所界定，該第一閘極線及該第一資料線係在該絕緣基板上；一主像素部分，其在該像素區域上，該主像素部分包含一主電容；一耦合電容器，該耦合電容器具有一電連接到該開關之第一末端；一子像素部分，該子像素部分包含電連接到該耦合電容器之一第二末端的至少一電容；以及其中該第一閘極線重疊該子像素部分之一部份但不重疊該主像素部分。 An array substrate includes: an insulating substrate; a switch in a pixel region on the insulating substrate, the pixel region is defined by a first gate line and an adjacent first data line, the first The gate line and the first data line are on the insulating substrate; a main pixel portion on the pixel region, the main pixel portion includes a main capacitor; a coupling capacitor having an electrical connection to the a first end of the switch; a sub-pixel portion including at least one capacitor electrically connected to a second end of the coupling capacitor; and wherein the first gate line overlaps a portion of the sub-pixel portion but The main pixel portion is not overlapped. 如請求項1之陣列基板，其中複數個開口圖樣被形成在該主像素部分上。 The array substrate of claim 1, wherein a plurality of opening patterns are formed on the main pixel portion. 如請求項1之陣列基板，其中複數個開口圖樣被形成在該子像素部分上。 The array substrate of claim 1, wherein a plurality of opening patterns are formed on the sub-pixel portion. 如請求項1之陣列基板，其中該主像素部分沿該第一閘極線而將該像素區域劃分成兩個區域。 The array substrate of claim 1, wherein the main pixel portion divides the pixel region into two regions along the first gate line. 如請求項1之陣列基板，其中該主像素部分被電連接到該開關，並且其中該開關包括一電晶體。 The array substrate of claim 1, wherein the main pixel portion is electrically connected to the switch, and wherein the switch comprises a transistor. 如請求項1之陣列基板，其中該主像素部分包括：一第二耦合圖案，其在該絕緣基板上；以及 一主電極，其在該第二耦合圖案上，該主電極被電連接至該第二耦合圖案。 The array substrate of claim 1, wherein the main pixel portion comprises: a second coupling pattern on the insulating substrate; a main electrode on the second coupling pattern, the main electrode being electrically connected to the second coupling pattern. 如請求項6之陣列基板，其中該子像素部分包括：一第一下部儲存圖案，其在該絕緣基板上；一第一子電極，其在該第一下部儲存圖案上，該第一子電極被電連接至該第一下部儲存圖案；一第二下部儲存圖案，其在該絕緣基板上；以及一第二子電極，其在該第二下部儲存圖案上而相間隔於該第一子電極，該第二子電極被電連接至該第二下部儲存圖案。 The array substrate of claim 6, wherein the sub-pixel portion comprises: a first lower storage pattern on the insulating substrate; a first sub-electrode on the first lower storage pattern, the first a sub-electrode is electrically connected to the first lower storage pattern; a second lower storage pattern on the insulating substrate; and a second sub-electrode on the second lower storage pattern spaced apart from the first a sub-electrode, the second sub-electrode being electrically connected to the second lower storage pattern. 如請求項7之陣列基板，其中兩個Y形開口圖樣被形成在該主電極上，並且其中該等Y形開口圖樣之每一Y形開口圖樣係相對於該像素區域之一水平方向的該像素區域之一中心線呈對稱。 The array substrate of claim 7, wherein two Y-shaped opening patterns are formed on the main electrode, and wherein each of the Y-shaped opening patterns of the Y-shaped opening pattern is horizontal with respect to one of the pixel regions The center line of one of the pixel areas is symmetrical. 如請求項8之陣列基板，其中在該第一子電極上形成兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的兩個鄰接桿之一。 The array substrate of claim 8, wherein two linear opening patterns are formed on the first sub-electrode, the linear opening patterns being substantially parallel to one of two adjacent rods of the respective Y-shaped opening patterns. 如請求項9之陣列基板，其中在該第二子電極上形成兩個線形開口圖樣，該等線形開口圖樣實質上平行於該等Y形開口圖樣各自的該等兩個鄰接桿之另一桿；以及其中形成在該第一子電極上的該等兩個線形開口圖樣係相對於該像素區域之該水平方向的該像素區域之該中心線而對稱於形成在該第二子電極上的該等兩個線形開口圖樣。 The array substrate of claim 9, wherein two linear opening patterns are formed on the second sub-electrode, the linear opening patterns being substantially parallel to the other one of the two adjacent rods of the respective Y-shaped opening patterns And the two linear opening patterns formed on the first sub-electrode are symmetric with respect to the center line of the pixel region of the horizontal direction of the pixel region and formed on the second sub-electrode Wait for two linear openings. 如請求項1之陣列基板，其中該主電容包括一主液晶電容。 The array substrate of claim 1, wherein the main capacitor comprises a main liquid crystal capacitor. 如請求項11之陣列基板，其中該主電容進一步包括一主儲存電容。 The array substrate of claim 11, wherein the main capacitor further comprises a main storage capacitor. 如請求項1之陣列基板，其中該至少一電容包括該子像素部分的一液晶電容。 The array substrate of claim 1, wherein the at least one capacitor comprises a liquid crystal capacitor of the sub-pixel portion. 如請求項13之陣列基板，其中該至少一電容進一步包括該子像素部分的一儲存電容。 The array substrate of claim 13, wherein the at least one capacitor further comprises a storage capacitor of the sub-pixel portion. 如請求項1之陣列基板，其中該像素區域進一步係由連貫於該絕緣基板上之該第一閘極線的一第二閘極線與連貫於該絕緣基板上之該第一資料線的一第二資料線所界定。 The array substrate of claim 1, wherein the pixel region is further formed by a second gate line of the first gate line connected to the insulating substrate and the first data line connected to the insulating substrate The second data line is defined. 一種陣列基板，包括：一絕緣基板，其具有一像素區域；一主閘極線，其在該像素區域上；一主開關，其在該絕緣基板上，該主開關被電連接到該主閘極線；一主像素部分，其被置於該像素區域之一中心部分上，主像素部分被連接至該主開關；一子閘極線，其在該像素區域上；一子開關，其在該絕緣基板上，該子開關被電連接到該子閘極線；一子像素部分，其係在該像素區域之一周邊部分上；以及 其中該主閘極線重疊該子像素部分之一部份但不重疊該主像素部分。 An array substrate comprising: an insulating substrate having a pixel region; a main gate line on the pixel region; a main switch on the insulating substrate, the main switch being electrically connected to the main gate a main pixel portion disposed on a central portion of the pixel region, the main pixel portion being coupled to the main switch; a sub-gate line on the pixel region; a sub-switch, The sub-switch is electrically connected to the sub-gate line on the insulating substrate; a sub-pixel portion is attached to a peripheral portion of the pixel region; Wherein the main gate line overlaps a portion of the sub-pixel portion but does not overlap the main pixel portion. 如請求項16之陣列基板，進一步包括：一第一下部儲存圖案，其在該絕緣基板上且實質上垂直於該閘極線；以及一第一耦合圖案，其沿該像素區域之一水平方向而將該像素區域劃分成兩個區域，該第一耦合圖案係鄰接於該像素區域之一右側而電連接至該第一下部儲存圖案。 The array substrate of claim 16, further comprising: a first lower storage pattern on the insulating substrate and substantially perpendicular to the gate line; and a first coupling pattern along a level of the pixel region The pixel region is divided into two regions, and the first coupling pattern is electrically connected to the first lower storage pattern adjacent to one of the right sides of the pixel region. 一種液晶顯示裝置，包括：一上部基板，其具有一透明基板及一位於該透明基板上的共同電極；一下部基板，包含：一絕緣基板，其具有一像素區域，該像素區域係由一第一閘極線與一鄰接之第一資料線所界定，該第一閘極線及該第一資料線係在該絕緣基板上；一主像素部分，其在該一中心部分上，該主像素部分包含一主電容；一耦合電容器，該耦合電容器具有一電連接到該絕緣基板上之一開關之第一末端；以及一子像素部分，該子像素部分包含電連接到該耦合電容器之一第二末端的至少一電容，該子像素部分係在該像素區域之一周邊部分上；其中該第一閘極線重疊該子像素部分之一部份但不重疊該主像素部分；以及 一液晶層，其被***在該上部基板與該下部基板之間。 A liquid crystal display device comprising: an upper substrate having a transparent substrate and a common electrode on the transparent substrate; and a lower substrate comprising: an insulating substrate having a pixel region, the pixel region being a gate line is defined by an adjacent first data line, the first gate line and the first data line are on the insulating substrate; a main pixel portion is on the central portion, the main pixel The portion includes a main capacitor; a coupling capacitor having a first end electrically connected to a switch on the insulating substrate; and a sub-pixel portion including an electrical connection to the one of the coupling capacitor At least one capacitor at the two ends, the sub-pixel portion being on a peripheral portion of the pixel region; wherein the first gate line overlaps a portion of the sub-pixel portion but does not overlap the main pixel portion; A liquid crystal layer interposed between the upper substrate and the lower substrate. 如請求項18之液晶顯示裝置，其中複數個開口圖樣被形成在該主像素部分及該子像素部分上，以及複數個開口圖樣被形成在共同電極上，使得在該液晶顯示裝置運作中，複數個域被形成在該液晶層中。 The liquid crystal display device of claim 18, wherein a plurality of opening patterns are formed on the main pixel portion and the sub-pixel portion, and a plurality of opening patterns are formed on the common electrode, so that in the operation of the liquid crystal display device, A domain is formed in the liquid crystal layer. 一種液晶顯示裝置，包括：一上部基板，其具有一透明基板及一位於該透明基板上的共同電極；一下部基板，包含：一絕緣基板；一閘極線，其在該絕緣基板上，用以傳輸一閘極訊號；一資料線，其在該絕緣基板上，用以傳輸一資料訊號；一開關，其電連接到該閘極線及該資料線，該開關係在該絕緣基板上；一主像素部分，其電連接到該開關，該主像素部分係在該絕緣基板上；一第一耦合電容器，其具有一電連接到該開關之第一末端；一第一子像素部分，其透過該第一耦合電容器而電連接到該開關，該第一子像素部分係在該絕緣基板上； 一第二耦合電容器，其具有一電連接到該開關之末端；以及一第二子像素部分，其透過該第二耦合電容器而電連接到該開關，該第二子像素部分係在該絕緣基板上；以及一液晶層，其被***在該上部基板與該下部基板之間。 A liquid crystal display device comprising: an upper substrate having a transparent substrate and a common electrode on the transparent substrate; a lower substrate comprising: an insulating substrate; and a gate line on the insulating substrate To transmit a gate signal; a data line on the insulating substrate for transmitting a data signal; a switch electrically connected to the gate line and the data line, the open relationship on the insulating substrate; a main pixel portion electrically connected to the switch, the main pixel portion being attached to the insulating substrate; a first coupling capacitor having a first end electrically connected to the switch; a first sub-pixel portion Electrically connected to the switch through the first coupling capacitor, the first sub-pixel portion is attached to the insulating substrate; a second coupling capacitor having an end electrically connected to the switch; and a second sub-pixel portion electrically connected to the switch through the second coupling capacitor, the second sub-pixel portion being attached to the insulating substrate And a liquid crystal layer interposed between the upper substrate and the lower substrate. 如請求項20之液晶顯示裝置，其中該主像素部分包括：一主液晶電容器，其具有一電連接到該開關之末端及接收一共同電壓之另一末端；以及一主儲存電容器，其具有一電連接到該開關之末端及接收一儲存電壓之另一末端。 The liquid crystal display device of claim 20, wherein the main pixel portion comprises: a main liquid crystal capacitor having an end electrically connected to the end of the switch and receiving a common voltage; and a main storage capacitor having a Electrically connected to the end of the switch and receiving the other end of a stored voltage. 如請求項20之液晶顯示裝置，其中該第一子像素部分包括：一第一液晶電容器，其具有一電連接到該第一耦合電容器之末端及接收一共同電壓之另一末端；以及一第一儲存電容器，其具有一電連接到該第一耦合電容器之末端及接收一儲存電壓之另一末端。 The liquid crystal display device of claim 20, wherein the first sub-pixel portion comprises: a first liquid crystal capacitor having an end electrically connected to the end of the first coupling capacitor and receiving a common voltage; and a first A storage capacitor having an end electrically coupled to the end of the first coupling capacitor and receiving a stored voltage. 如請求項20之液晶顯示裝置，其中該第二子像素部分包括：一第二液晶電容器，其具有一電連接到該第二耦合電容器之末端及接收一共同電壓之另一末端；以及一第二儲存電容器，其具有一電連接到該第二耦合電容器之末端及接收一儲存電壓之另一末端。The liquid crystal display device of claim 20, wherein the second sub-pixel portion comprises: a second liquid crystal capacitor having an end electrically connected to the end of the second coupling capacitor and receiving a common voltage; and a first A storage capacitor having an end electrically coupled to the end of the second coupling capacitor and receiving a stored voltage.
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