TWI397164B - 矽穿孔連通延伸之晶片封裝構造 - Google Patents

矽穿孔連通延伸之晶片封裝構造 Download PDF

Info

Publication number
TWI397164B
TWI397164B TW097141868A TW97141868A TWI397164B TW I397164 B TWI397164 B TW I397164B TW 097141868 A TW097141868 A TW 097141868A TW 97141868 A TW97141868 A TW 97141868A TW I397164 B TWI397164 B TW I397164B
Authority
TW
Taiwan
Prior art keywords
substrate
wafer
holes
package structure
conductive
Prior art date
Application number
TW097141868A
Other languages
English (en)
Other versions
TW201017855A (en
Inventor
Chi Hung Chiou
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW097141868A priority Critical patent/TWI397164B/zh
Publication of TW201017855A publication Critical patent/TW201017855A/zh
Application granted granted Critical
Publication of TWI397164B publication Critical patent/TWI397164B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29011—Shape comprising apertures or cavities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Description

矽穿孔連通延伸之晶片封裝構造
本發明係有關於半導體裝置，特別係有關於一種矽穿孔連通延伸之晶片封裝構造。
在電子產品的微小化要求下，用以保護半導體晶片並提供外部電路連接的晶片封裝構造需要符合輕薄短小的發展趨勢。在晶片封裝構造中，晶片與基板之間的電性連接方式通常係採用打線方式，晶片封裝構造則係藉由銲球作為對外接合之媒介。然而，銲線具有一定的打線弧高而使得密封銲線之封膠體需具有較厚的厚度，而難以降低整體的封裝厚度與封裝尺寸。
請參閱第1圖所示，一種習知打線連接之晶片封裝構造100，主要包含一基板110、一晶片120、一封膠體140、複數個銲線170以及複數個銲球180。該基板110係具有一上表面111、一下表面112、複數個鍍通孔113、複數個內接指114以及複數個外接墊115。該些內接指114係形成於該上表面111之周邊，該些外接墊115係形成於該下表面112，其中該些內接指114係藉由該些鍍通孔113電性連接至該些外接墊115。該些鍍通孔113係為在孔壁形成金屬層之貫通孔，並在封裝過程之前便以填充物填滿以不突出於該上表面111與該下表面112。在一黏晶步驟中，該晶片120係設置於該基板110之該上表面111並且不可覆蓋該些 內接指114。通常該晶片120係利用一黏晶層150之黏貼使其背面黏設於該基板110之該上表面111。在一打線步驟中，該些銲線170係電性連接該晶片120之複數個銲墊121至該基板110之該些內接指114，以達到該晶片120與該基板110之間的電性互連。在一模封步驟中，該封膠體140係形成於該基板110之該上表面111，並密封該晶片120與該些銲線170。在一植球步驟中，利用迴焊方式使該些銲球180係設置於該基板110之該些外接墊115，以作為該晶片封裝構造100之對外端子。
在上述習知的晶片封裝構造100中，該晶片120與該基板110係藉由該些銲線170進行電性連接。然而，該些銲線170必須具有一定的打線弧高，使得該封膠體140需具有相當的厚度才可避免銲線170外露之問題，因而造成該晶片封裝構造100具有較厚的厚度。由於該些銲線170係連接該些銲墊121至該些內接指114，故必須具有一定的長度與間距，以避免在模封的過程中產生沖線的問題。並且該些內接指114位於該基板110之晶片覆蓋區之外，以供該些銲線170連接，所以該基板110之尺寸需較大於該晶片120之尺寸，以供預留該些內接指114之形成位置，故無法縮小該基板110之尺寸，因而導致該晶片封裝構造100之封裝尺寸難以縮小。此外，當該些銲球180對外接合時，會因為應力的產生而導致掉球，造成產品的可靠度低 落。
另，有人提出一種先進的晶片封裝構造，具有矽穿孔(Through Silicon Via, TSV)之晶片設置於基板上，矽穿孔貫穿晶片，主要是運用在晶片的立體堆疊。在晶片與基板之結合界面中，最低層晶片的矽穿孔是利用焊料接合到基板的內接墊，由於晶片為半導體材質，而基板為有機材質，兩者材質不同導致存在有熱膨脹係數的差異，故應力會集中在晶片與基板之結合界面，導致焊料接合點的斷裂。在另一種晶片與基板之結合方式中，先在基板上設置插針，當晶片放置於基板上時，插針穿過晶片的矽穿孔達到電性連觸，當其中一插針不為直立或有彎斜現象時，會有孔對不準的問題，故製程良率甚低。並且，電性接觸不佳會有阻抗增加與訊號中斷的問題。
為了解決上述之問題，本發明之主要目的係在於提供一種矽穿孔連通延伸之晶片封裝構造，以液態填充方式形成之導電填充材能同時取代習知在打線步驟形成之銲線與在植球步驟形成之銲球，也不會有習知矽穿孔在晶片與基板之結合界面中焊料接合點斷裂的問題以及習知以插針穿過晶片的矽穿孔造成孔對不準的低製程良率。此外，並能降低晶片封裝構造之整體高度與縮小封裝尺寸。
本發明的目的及解決其技術問題是採用以下技術 方案來實現的。本發明揭示一種矽穿孔連通延伸之晶片封裝構造，主要包含一基板、一晶片、複數個導電填充材以及一封膠體。該基板係具有一上表面、一下表面以及複數個基板通孔。該晶片係設置於該基板之該上表面，該晶片係具有複數個矽穿孔，該些矽穿孔與該些基板通孔係為縱向對應連通。該些導電填充材係以液態填充方式形成於該些矽穿孔與該些基板通孔中，該些導電填充材更突出於該基板之該下表面，以形成為複數個孔對孔一體連接之外接凸塊。該封膠體係形成於該基板之該上表面，以密封該晶片。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述晶片封裝構造中，該些導電填充材係可為內含金屬粒子的熱固性樹脂。
在前述晶片封裝構造中，該些導電填充材係可由金屬膏燒結成形。
在前述晶片封裝構造中，該封膠體係可更覆蓋該些導電填充材外露在該晶片之複數個端部。
在前述晶片封裝構造中，該些導電填充材之該些端部係可形成為複數個大於該些矽穿孔之凸塊部。
在前述晶片封裝構造中，該些導電填充材之液態填充方式係可包含模封(transfer molding)。
在前述晶片封裝構造中，可另包含一黏晶層，係形成於該晶片與該基板之間，並且該基板係設有複數個 位在該上表面之擋環，其係環繞該些基板通孔在該上表面之開口，用以阻擋該黏晶層流入該些基板通孔。
在前述晶片封裝構造中，該基板係可設有複數個位在該下表面之凸塊承座，其係環繞該些基板通孔在該下表面之開口，該些導電填充材之該些外接凸塊係結合於該些凸塊承座。
在前述晶片封裝構造中，可另包含一異方性導電膠膜，係形成於該基板之該下表面並覆蓋該些外接凸塊。
在前述晶片封裝構造中，該異方性導電膠膜係可包含複數個等球徑的導電顆粒，其中至少一導電顆粒係電性接觸該些外接凸塊至一外部印刷電路板，其中所述電性接觸之導電顆粒係局部嵌陷於該些導電填充材之對應外接凸塊內。
在前述晶片封裝構造中，該基板之該上表面係可具有一接近該晶片之表面覆蓋區之面積。
由以上技術方案可以看出，本發明之矽穿孔連通延伸之晶片封裝構造，具有以下優點與功效：一、以液態填充方式形成之導電填充材與封裝構造內部元件具有特定的連接關係能同時取代習知之銲線與銲球，故可省略打線步驟與植球步驟，以簡化製程。
二、利用導電填充材同時貫穿基板與晶片並形成孔對孔一體連接之外接凸塊，故封膠體不需要保留超過晶片的打線弧高，並且基板之上表面周邊不需 要預設內指指的區域，故可降低晶片封裝構造之整體高度以及縮小封裝尺寸。
三、由導電填充材的一端形成之外接凸塊可取代習知銲球，以供在表面接合(SMT)時使用異方性導電膠，使得異方性導電膠內的導電粒子可局部嵌埋在外接凸塊。
四、利用導電填充材的材料特性，例如銀膠，產生高流動性並具有韌性，以防止外接凸塊或孔內斷裂。
五、藉由導電填充材在晶片表面之端部形成為大於矽穿孔之凸塊部，可防止該些導電填充材的鬆脫。
六、藉由導電填充材以模封方式形成，能使導電填充材之外接凸塊具有一致且整齊的形狀。
七、藉由凸塊承座環繞基板通孔在基板下表面之開口，能控制外接凸塊在基板下表面之覆蓋面積並可增進外接凸塊的結合力。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能 更為複雜。
依據本發明之一具體實施例，一種矽穿孔連通延伸之晶片封裝構造舉例說明於第2圖之截面示意圖。該晶片封裝構造200主要包含一基板210、一晶片220、複數個導電填充材230以及一封膠體240。該基板210舉例說明於第3圖之基板上表面示意圖以及第4圖之基板下表面示意圖。該基板210係具有一上表面211、一下表面212以及複數個基板通孔213。該些基板通孔213係由該上表面211貫穿至該下表面212，該些基板通孔213係可為無電性連接功能的貫穿孔，即該些基板通孔213內可以無電鍍金屬層。在本實施例中，該些基板通孔213係可以電射鑽孔或機械穿孔等方式形成。該些基板通孔213係可為陣列排列、周邊排列或是單/多排中心線排列。較佳地，該基板210之該上表面211係可具有一接近該晶片220之表面覆蓋區之面積，以達成晶片尺寸封裝，而不需要預留在習知基板上表面周圍的內接指。
請參閱第2圖所示，該晶片220係設置於該基板210之該上表面211，該晶片220係具有複數個矽穿孔221，該些矽穿孔221與該些基板通孔213係為縱向對應連通。該些矽穿孔221係貫穿該晶片220，該些矽穿孔221內可具有金屬層或其中一開口更貫穿該晶片220之銲墊，以作為該晶片220之內部端子。並利用該些導電填充材230作為連接該晶片220之該些矽穿 孔221之電氣訊號之傳遞通路。請再參閱第2圖所示，該晶片220係以該些矽穿孔221對準於該些基板通孔213之方式設置於該基板210上，以達到縱向對應連通。該些矽穿孔221之形成可利用既有的矽穿孔製造技術，例如由IBM公司開發的TSV (Through Silicon Via)晶片連接技術。
在本實施例中，該晶片封裝構造200可另包含一黏晶層250，其係黏接該晶片220與該基板210。請參閱第2圖所示，該黏晶層250係形成於該晶片220與該基板210之間。並且較佳地，該基板210係設有複數個位在該上表面211之擋環214(如第3圖所示)，其係環繞該些基板通孔213在該上表面211之開口，用以阻擋該黏晶層250流入該些基板通孔213。關於該黏晶層250之形成方法，可先將該黏晶層250形成於該基板210上，再使該晶片220壓合於該黏晶層250。在另一實施例中，該黏晶層250的形成係採用底部填充(under filling)的方式，即先設置該晶片220在該基板210上，再點塗液態黏著膠，以形成填滿在該晶片220與該基板210之間的黏晶層250，使得該晶片220與該基板210為緊密接合。當該黏晶層250係以底部填充形成時，該黏晶層250在未固化時具有高流動性，故該些擋環214壓觸至該晶片220為一較佳的技術手段，以有效阻擋該黏晶層250流入該些基板通孔213。較佳地，該些擋環214的厚度係可略高於該基板 210在該上表面211之防焊層的厚度，以發揮阻擋該黏晶層250之作用。在不同實施例中，該基板210係可不具有防焊層，以進一步提升該些擋環214的擋膠效果並可加強該晶片220與該基板210之間之黏著力。此外，該些擋環214之材質可為金屬，如銅。該些擋環214係可為該基板210表面突出之金屬環，並位於該基板210用以設置該晶片220的區域內。
請參閱第2圖所示，該些導電填充材230係以液態填充方式形成於該些矽穿孔221與該些基板通孔213中，該些導電填充材230更突出於該基板210之該下表面212，以形成為複數個孔對孔一體連接之外接凸塊231。在此所述的「孔對孔一體連接」係指每一導電填充材230在一體連接對應外接凸塊231的部位是更連接填充入縱向對應的該些矽穿孔221與該些基板通孔213。換言之，該些外接凸塊231係為該些導電填充材230之突出部位，其一體連接之根部更可嵌埋貫穿該基板210與該晶片220，形成為不可動搖或脫落的外接端子，為習知焊接在基板表面的銲球所不可預期的作用。
較佳地，該些導電填充材230係可為內含金屬粒子的熱固性樹脂，例如銀膠，產生高流動性並具有韌性，以防止該些外接凸塊231或孔內斷裂。在另一實施例中，該些導電填充材230係可由金屬膏燒結成形，例如銅膏或錫膏。
該些導電填充材230之液態填充方式係可包含模封、液態點注或為毛細現象的孔填充，其中以模封方式為較佳。請參閱第5D圖所示，在模封過程中可利用一下模具10以使該些導電填充材230之外接凸塊231具有一致且整齊的形狀。該些外接凸塊231在該基板210之該下表面212的覆蓋面積係可大於該導電填充材230在該些基板通孔213內的截面積，以增加該些外接凸塊231對外電性連接的接觸面積。
由於該些導電填充材230係用以電性連接該晶片220與該基板210並提供作為該晶片封裝構造200之對外接合，故能同時取代習知之銲線與銲球，可省略習知打線步驟與植球步驟，以簡化製程。
請參閱第2圖所示，較佳地，該基板210係可設有複數個位在該下表面212之凸塊承座215，其係環繞該些基板通孔213在該下表面212之開口，該些導電填充材230之該些外接凸塊231係結合於該些凸塊承座215，該些凸塊承座215具有控制該些導電填充材230之該些外接凸塊231在該基板210之該下表面212之覆蓋面積並可增進該些外接凸塊231的結合力。其中該些外接凸塊231係可完全覆蓋該些凸塊承座215。更具體而言，該些凸塊承座215之尺寸係稍大於該些擋環214之尺寸。請參閱第4圖所示，在本實施例中，該些凸塊承座215之形狀係可為具有開孔之矩形。此外，該基板210更具有複數個虛置墊216，係 設置於該基板210之該下表面212並顯露於該下表面212，以增加散熱效果，但可不具有訊號傳遞的作用。具體而言，該些虛置墊216係排列於該基板210之兩相對側邊或周邊。
請參閱第2圖所示，該封膠體240係形成於該基板210之該上表面211，以密封該晶片220。該封膠體240係提供適當的封裝保護，以防止電性短路與塵埃污染。請再參閱第2圖所示，該封膠體240係可更覆蓋該些導電填充材230外露在該晶片220之複數個端部232，以形成單晶片封裝之結構。較佳地，該些導電填充材230之該些端部232係可形成為複數個大於該些矽穿孔221之凸塊部，可防止該些導電填充材230的鬆脫。請參閱第2圖所示，在本實施例中，每一導電填充材230係形成為一如「工」字形之截面形狀，以防止脫落或位移。
由上述可知，利用該些導電填充材230填入縱向對應且連通之該些矽穿孔221與該些基板通孔213的結構，使該晶片220之電氣訊號能傳遞至突出於該基板210之該些外接凸塊231，能同時取代習知在打線步驟形成之銲線與在植球步驟形成之銲球，也不會有習知矽穿孔在晶片與基板之結合界面中焊料接合點斷裂的問題以及習知以插針穿過晶片的矽穿孔造成孔對不準的低製程良率。此外，利用該些導電填充材230同時貫穿該基板210與該晶片220並形成孔對孔一體連接 之該些外接凸塊231，故該封膠體240不需要保留超過晶片的打線弧高，並且基板之上表面周邊不需要預設內指指的區域，故可降低該晶片封裝構造200之整體高度以及縮小封裝尺寸。
在本實施例中，如第5H圖所示，該晶片封裝構造200可另包含一異方性導電膠膜260，係形成於該基板210之該下表面212並覆蓋該些外接凸塊231。該些外接凸塊231係突出於該基板210之該下表面212，有助於該異方性導電膠膜260接觸。該異方性導電膠膜260係可包含複數個等球徑的導電顆粒261，其中至少一導電顆粒261A係電性接觸該些外接凸塊231至一外部印刷電路板20之複數個連接墊21，其中所述電性接觸之導電顆粒261A係局部嵌陷於該些導電填充材230之對應外接凸塊231內，使得電性接觸更為確實。當該晶片封裝構造200與該外部印刷電路板20接合時，該晶片封裝構造200會下壓至該異方性導電膠膜260，而該些導電填充材230之該些外接凸塊231會壓到至少一導電顆粒261A，因而使該晶片封裝構造200與該外部印刷電路板20電性導通，其餘的該些導電顆粒261會由非導電性的膠體區隔開來，不會導致電性短路。由該些導電填充材230的一端形成之該些外接凸塊231可取代習知銲球，以供在表面接合(SMT)時使用該異方性導電膠260，使得該異方性導電膠260內的導電粒子261A可局部嵌埋在該些外接凸塊231，並 使該晶片封裝構造200與該外部印刷電路板20結合，此方式亦可運用在手機、記憶卡以及記憶體模組。
本發明進一步說明該晶片封裝構造200之製造方法，以彰顯本案的功效。請參閱第5A至5E圖之元件截面示意圖。
首先，請參閱第5A圖所示，提供該晶片220。該晶片220係具有複數個矽穿孔221，該些矽穿孔221的形成可採用離子反應蝕刻或是雷射鑽孔等技術。接著，請參閱第5B圖所示，提供該基板210，用以承載該晶片220，該基板210係具有複數個貫穿該上表面211至該下表面212之基板通孔213。該晶片220係以該些矽穿孔221對準於該些基板通孔213之方式黏貼於該基板210之該上表面211。請再參閱第5B圖所示，一黏晶層250係局部塗佈在該基板210之該上表面211且不覆蓋該些基板通孔213。在本實施例中，該基板210更設有複數個擋環214以及複數個凸塊承座215，該些擋環214係位在該上表面211並環繞該些基板通孔213在該上表面211之開口，該些凸塊承座215係位在該下表面212並環繞該些基板通孔213在該下表面212之開口。接著，請參閱第5C圖所示，在黏晶時，該些矽穿孔221可縱向對應連通至該些基板通孔213，並可藉由該些擋環214阻擋該黏晶層250流入該些基板通孔213，以避免該黏晶層250溢膠之問題。較佳地，該些擋環214的厚度係略高於該基板 210之防焊層的厚度，以發揮擋膠之作用。
之後，請參閱第5D圖所示，提供一下模具10並將已承載有該晶片220之基板210置放於該下模具10，其中該基板210之該下表面212係朝向該下模具10。該下模具10係具有一定位槽11及複數個形成於該定位槽11內之凹穴12，其中該些凹穴12的深度係大於該定位槽11的深度。該定位槽11係用以容置該基板210，且該定位槽11之尺寸係概等於該基板210之尺寸，以避免該基板210位移。該些凹穴12係對準該些基板通孔213，且該些凹穴12之尺寸係大於該些基板通孔213的截面積，用以形成該些外接凸塊231。接著，請參閱第5E圖所示，可利用模封方式填入該些導電填充材230於該些矽穿孔221與該些基板通孔213，同時利用該下模具10之該些凹穴12承接該些由上而下的導電填充材230，以形成複數個具有一致且整齊形狀的外接凸塊231。在形成該些外接凸塊231之後，烘烤固化該些導電填充材230，使得該晶片220與該基板210上下導通結合。在本實施例中，該些導電填充材230更具有複數個外露在該晶片220且大於該些矽穿孔221之端部232。因此，藉由該些外接凸塊231與該些端部232可防止該些導電填充材230的鬆脫。
請參閱第5F圖所示，形成該封膠體240於該基板210之該上表面211，並密封該晶片220與該些導電填充材230之該些端部232，以形成單晶片封裝之結構。 接著，請參閱第5G圖所示，將一異方性導電膠膜260貼覆在一外部印刷電路板20上，並覆蓋該外部印刷電路板20之複數個連接墊21。該異方性導電膠膜260係包含複數個等球徑的導電顆粒261。最後，請參閱第5H圖所示，壓合該晶片封裝構造200至該外部印刷電路板20，並藉由該異方性導電膠膜260之至少一導電顆粒261A電性接觸該些外接凸塊231至該些連接墊21，以達到該晶片封裝構造200與該外部印刷電路板20之電性互連。
因此，由以上的製造方法可知，可以省略習知之打線步驟與植球步驟，在模封步驟之後再進行標記步驟與切割步驟即可完成整個晶片封裝製程。本發明能以一膠填孔之步驟取代習知打線步驟與植球步驟，亦不會有習知沖線的問題。
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。
10‧‧‧下模具
11‧‧‧定位槽
12‧‧‧凹穴
20‧‧‧外部印刷電路板
21‧‧‧連接墊
100‧‧‧晶片封裝構造
110‧‧‧基板
111‧‧‧上表面
112‧‧‧下表面
113‧‧‧鍍通孔
114‧‧‧內接指
115‧‧‧外接墊
120‧‧‧晶片
121‧‧‧銲墊
140‧‧‧封膠體
150‧‧‧黏晶層
170‧‧‧銲線
180‧‧‧銲球
200‧‧‧矽穿孔連通延伸之晶片封裝構造
210‧‧‧基板
211‧‧‧上表面
212‧‧‧下表面
213‧‧‧基板通孔
214‧‧‧擋環
215‧‧‧凸塊承座
216‧‧‧虛置墊
220‧‧‧晶片
221‧‧‧矽穿孔
230‧‧‧導電填充材
231‧‧‧外接凸塊
232‧‧‧端部
240‧‧‧封膠體
250‧‧‧黏晶層
260‧‧‧異方性導電膠膜
261‧‧‧導電顆粒
261A‧‧‧導電顆粒
第1圖：習知晶片封裝構造之截面示意圖。
第2圖：依據本發明一具體實施例的一種矽穿孔連通延伸之晶片封裝構造之截面示意圖。
第3圖：依據本發明之一具體實施例的晶片封裝構造的基板上表面示意圖。
第4圖：依據本發明之一具體實施例的晶片封裝構造的基板下表面示意圖。
第5A與5H圖：依據本發明之一具體實施例的晶片封裝構造在製程中元件的截面示意圖以及該晶片封裝構造接合至外部印刷電路板之截面示意圖。
200‧‧‧矽穿孔連通延伸之晶片封裝構造
210‧‧‧基板
211‧‧‧上表面
212‧‧‧下表面
213‧‧‧基板通孔
214‧‧‧擋環
215‧‧‧凸塊承座
216‧‧‧虛置墊
220‧‧‧晶片
221‧‧‧矽穿孔
230‧‧‧導電填充材
231‧‧‧外接凸塊
232‧‧‧端部
240‧‧‧封膠體
250‧‧‧黏晶層

Claims (14)

  1. 一種矽穿孔連通延伸之晶片封裝構造，包含：一基板，係具有一上表面、一下表面以及複數個基板通孔；一晶片，係設置於該基板之該上表面，該晶片係具有複數個矽穿孔，該些矽穿孔與該些基板通孔係為縱向對應連通；複數個導電填充材，係以液態填充方式形成於該些矽穿孔與該些基板通孔中，該些導電填充材更突出於該基板之該下表面，以形成為複數個孔對孔一體連接之外接凸塊，其中該些導電填充材係為內含金屬粒子的熱固性樹脂；以及一封膠體，係形成於該基板之該上表面，以密封該晶片。
  2. 如申請專利範圍第1項所述之晶片封裝構造，其中該封膠體係更覆蓋該些導電填充材外露在該晶片之複數個端部。
  3. 如申請專利範圍第2項所述之晶片封裝構造，其中該些導電填充材之該些端部係形成為複數個大於該些矽穿孔之凸塊部。
  4. 如申請專利範圍第1項所述之晶片封裝構造，其中該些導電填充材之液態填充方式係包含模封。
  5. 如申請專利範圍第1項所述之晶片封裝構造，另包含一黏晶層，係形成於該晶片與該基板之間，並 且該基板係設有複數個位在該上表面之擋環，其係環繞該些基板通孔在該上表面之開口，用以阻擋該黏晶層流入該些基板通孔。
  6. 如申請專利範圍第1項所述之晶片封裝構造，其中該基板係設有複數個位在該下表面之凸塊承座，其係環繞該些基板通孔在該下表面之開口，該些導電填充材之該些外接凸塊係結合於該些凸塊承座。
  7. 如申請專利範圍第1項所述之晶片封裝構造，另包含一異方性導電膠膜，係形成於該基板之該下表面並覆蓋該些外接凸塊。
  8. 如申請專利範圍第7項所述之晶片封裝構造，其中該異方性導電膠膜係包含複數個等球徑的導電顆粒，其中至少一導電顆粒係電性接觸該些外接凸塊至一外部印刷電路板，其中所述電性接觸之導電顆粒係局部嵌陷於該些導電填充材之對應外接凸塊內。
  9. 如申請專利範圍第1項所述之晶片封裝構造，其中該基板之該上表面係具有一接近該晶片之表面覆蓋區之面積。
  10. 一種矽穿孔連通延伸之晶片封裝構造，主要包含一基板、一設於該基板上之晶片以及複數個突出於該基板下之外接凸塊，其特徵在於，該些外接凸塊係由導電填充材所形成並貫穿該基板與該晶片，以 形成複數個外露在該晶片之端部，該晶片封裝構造係另包含一黏晶層，係形成於該晶片與該基板之間，並且該基板係設有複數個位在該上表面之擋環，其係環繞該些基板通孔在該上表面之開口，用以阻擋該黏晶層流入該些基板通孔。
  11. 如申請專利範圍第10項所述之晶片封裝構造，另包含有一封膠體，係形成於該基板設有該晶片之一表面，以密封該晶片並覆蓋該些端部。
  12. 一種矽穿孔連通延伸之晶片封裝構造，包含：一基板，係具有一上表面、一下表面以及複數個基板通孔；一晶片，係設置於該基板之該上表面，該晶片係具有複數個矽穿孔，該些矽穿孔與該些基板通孔係為縱向對應連通；複數個導電填充材，係以液態填充方式形成於該些矽穿孔與該些基板通孔中，該些導電填充材更突出於該基板之該下表面，以形成為複數個孔對孔一體連接之外接凸塊；以及一封膠體，係形成於該基板之該上表面，以密封該晶片；其中該基板係設有複數個位在該下表面之凸塊承座，其係環繞該些基板通孔在該下表面之開口，該些導電填充材之該些外接凸塊係結合於該些凸塊承座。
  13. 如申請專利範圍第11項所述之晶片封裝構造，另包含一異方性導電膠膜，係形成於該基板之該下表面並覆蓋該些外接凸塊。
  14. 如申請專利範圍第13項所述之晶片封裝構造，其中該異方性導電膠膜係包含複數個等球徑的導電顆粒，其中至少一導電顆粒係電性接觸該些外接凸塊至一外部印刷電路板，其中所述電性接觸之導電顆粒係局部嵌陷於該些導電填充材之對應外接凸塊內。
TW097141868A 2008-10-30 2008-10-30 矽穿孔連通延伸之晶片封裝構造 TWI397164B (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW097141868A TWI397164B (zh) 2008-10-30 2008-10-30 矽穿孔連通延伸之晶片封裝構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW097141868A TWI397164B (zh) 2008-10-30 2008-10-30 矽穿孔連通延伸之晶片封裝構造

Publications (2)

Publication Number Publication Date
TW201017855A TW201017855A (en) 2010-05-01
TWI397164B true TWI397164B (zh) 2013-05-21

Family

ID=44830992

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097141868A TWI397164B (zh) 2008-10-30 2008-10-30 矽穿孔連通延伸之晶片封裝構造

Country Status (1)

Country Link
TW (1) TWI397164B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8582373B2 (en) 2010-08-31 2013-11-12 Micron Technology, Inc. Buffer die in stacks of memory dies and methods
TWI482240B (zh) * 2011-12-19 2015-04-21 Nat Univ Tsing Hua 半導體之貫孔內連接線的製造方法
TWI453420B (zh) * 2013-01-11 2014-09-21 Mpi Corp 孔板
US9470715B2 (en) 2013-01-11 2016-10-18 Mpi Corporation Probe head
US11183443B2 (en) * 2019-06-13 2021-11-23 Nanya Technology Corporation Semiconductor structure and method for manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006124597A2 (en) * 2005-05-12 2006-11-23 Foster Ron B Infinitely stackable interconnect device and method
US7446420B1 (en) * 2007-06-20 2008-11-04 Hynix Semiconductor Inc. Through silicon via chip stack package capable of facilitating chip selection during device operation
TW200915451A (en) * 2007-06-07 2009-04-01 United Test & Assembly Ct Lt Through silicon via dies and packages

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006124597A2 (en) * 2005-05-12 2006-11-23 Foster Ron B Infinitely stackable interconnect device and method
TW200915451A (en) * 2007-06-07 2009-04-01 United Test & Assembly Ct Lt Through silicon via dies and packages
US7446420B1 (en) * 2007-06-20 2008-11-04 Hynix Semiconductor Inc. Through silicon via chip stack package capable of facilitating chip selection during device operation

Also Published As

Publication number Publication date
TW201017855A (en) 2010-05-01

Similar Documents

Publication Publication Date Title
US7772687B2 (en) Multiple electronic component containing substrate
JP6408986B2 (ja) Ｂｖａインタポーザ
US7816183B2 (en) Method of making a multi-layered semiconductor device
TWI495082B (zh) 多層半導體封裝
US7656031B2 (en) Stackable semiconductor package having metal pin within through hole of package
US20030164541A1 (en) Method and apparatus for dielectric filling of flip chip on interposer assembly
US20100258933A1 (en) Semiconductor device, method of forming the same, and electronic device
US9520374B2 (en) Semiconductor device, substrate and semiconductor device manufacturing method
US20120273941A1 (en) Package structure having embedded electronic component and fabrication method thereof
CN101194360A (zh) 接插件及半导体装置
US11869829B2 (en) Semiconductor device with through-mold via
US20120146242A1 (en) Semiconductor device and method of fabricating the same
KR100240748B1 (ko) 기판을 갖는 반도체 칩 패키지와 그 제조 방법 및 그를 이용한적층 패키지
CN112310063A (zh) 半导体装置封装及其制造方法
TW200531188A (en) Land grid array packaged device and method of forming same
KR101208028B1 (ko) 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지
TWI397164B (zh) 矽穿孔連通延伸之晶片封裝構造
US8030768B2 (en) Semiconductor package with under bump metallization aligned with open vias
TW201719828A (zh) 半導體裝置
JP5547703B2 (ja) 半導体装置の製造方法
KR102050011B1 (ko) 반도체 패키지용 상호 연결 구조체 및 상호 연결 구조체의 제조 방법
US20120049359A1 (en) Ball grid array package
TWI435429B (zh) 孔對孔貫穿之半導體封裝構造
TW201507097A (zh) 半導體晶片及具有半導體晶片之半導體裝置
KR20080065871A (ko) 배선 기판 내에 홈을 구비하는 멀티 칩 스택 패키지 및그의 제조 방법