TWI397089B - 電容器、包含該電容器之電路板及積體電路承載基板 - Google Patents

電容器、包含該電容器之電路板及積體電路承載基板 Download PDF

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TWI397089B
TWI397089B TW097111632A TW97111632A TWI397089B TW I397089 B TWI397089 B TW I397089B TW 097111632 A TW097111632 A TW 097111632A TW 97111632 A TW97111632 A TW 97111632A TW I397089 B TWI397089 B TW I397089B
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communication hole
conductive layer
electrically connected
ground
capacitor
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TW200839812A (en
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Chien Min Hsu
Shih Hsien Wu
Min Lin Lee
Shinn Juh Lai
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Ind Tech Res Inst
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Description

電容器、包含該電容器之電路板及積體電路承載基板
本發明一般係關於電容器，更特定言之，本發明係關於電容器之線路結構。
多層印刷電路板(PCB)目前已被廣泛使用於積體電路(IC)、晶片等電子電路系統及電子元件之內部電子訊號傳遞與連接。近年來，被大量使用於降低印刷電路板(Printed Circuit Board)或IC載板(substrate)上之電源雜訊的方法是在電源接腳(power/ground pin)附近放置去耦合電容(decoupling capacitor)或是旁路電容(bypass capacitor)，主要功能是將額定的電能儲存在電容器中，在電能不足時可以適時補給電能，以達到吸收突波(glitch)、降低RF雜訊及穩定電源的效果。一般而言，印刷電路板中常見的去耦合電容元件可分為黏著於電路板表面的分散式電容(如SMD電容器(Surface Mounted Device Capacitor)或叉指式電容器(Inter－Digitated Capacitor,IDC)等以及內埋於電路板內的內埋式電容(如平板電容)。然而，電源傳輸系統主要是藉著電容器的低阻抗特性，提供一個低阻抗路徑將雜訊濾除，但是當操作頻率高於電容器本身的諧振頻率點之後，其阻抗特性由電容性轉變為電感性，因此，隨著頻率上升而增加的寄生電感，將會導致原本提供低阻抗路徑的去耦合電容逐漸失去濾除高頻雜訊的作用。
隨著電子系統中訊號傳輸速度不斷地提升，線路密度不 斷地增加，訊號之間衍生的相互干擾問題也相對嚴重且不可忽視。目前普遍解決前述問題的方法是在印刷電路板表面黏著去耦合電容，因其形成之電流傳輸路徑無法縮短而使得寄生電感值太大，進而使得此方法無法有效抑制電源傳輸系統所產生同步切換干擾。然而，若將去耦合電容內埋至印刷電路板或IC載板中，必定比焊接在表面的表面黏著型式電容更靠近電子元件的電源或接地接腳，因此高頻時內埋式去耦合電容的電源傳輸路徑所產生的寄生電感值將會比SMD電容低。此外，內埋電容技術降低電路板焊接的被動元件數量，不但可以降低成本，還可以達到縮小電子元件構裝體積的市場需求。
一般在電源傳輸系統設計時會考量電源的傳輸阻抗，也就是目標阻抗(target impedance)，其指的是電源在符合低雜訊規格的前提下，電源傳輸系統在特定的頻帶範圍內所能容許的最大等效阻抗值。圖1所示為電容值為1 μ F且黏著於電路板表面的分散式電容器在頻率範圍從0.01 MHz到1000MHz之阻抗特性曲線，其中包括0612及1206電容器及低電感叉指式電容器。參考圖1，當操作頻率達數百MHz，該叉指式電容器之阻抗仍然可以低於系統需求之目標阻抗(約0.5歐姆)。但是，未來積體電路載板設計需求之目標阻抗將會低於0.1歐姆或更小，換言之，當在高頻操作時，表面黏著型式的分散式電容器將無法提供電源傳輸系統足夠低之阻抗以抑制不可預期的雜訊產生。簡言之，內埋電容技術是未來最有可能被實現以降低電容之基板寄 生電感值以及增加去耦合電容之低阻抗頻寬的方法，但是內嵌式平板電容和一般電容器一樣，當操作頻率高於其自振頻率點之後，依然會由電容性轉變為電感性，進而失去濾除高頻雜訊的作用。因此，本發明揭露一種降低內嵌式平板電容的線路結構，藉著減少平板電容的電流迴路長度以降低其寄生電感值，使得電子系統即使操作在高頻區段時，內埋式平板電容仍能發揮去耦合電容的功效，提供一個低阻抗路徑以濾除電源系統產生的雜訊。
Howard等人之美國專利號5,161,086描述了如圖2所示在印刷電路板多層薄片電容器之結構剖面圖。參照圖2，該積體電路14’分別藉由第一金屬連通孔34’及第二金屬連通孔36’與一電容器之電極28’及30’互相電性連接。而且該第一金屬連通孔34’藉由絕緣環穿過電極30’而未與電極30’電性連接。同樣地，該第二金屬連通孔36’藉由絕緣孔穿過電極28’而未與電極30’電性連接。
Naito等人之美國專利號6,678,145提出可降低電容器之寄生電感值的線路連接結構。圖3(a)是電容器41之內部一個電極結構的俯視圖。圖3(b)顯示從圖3(a)沿著線III－III之橫截面圖。參照圖3(a)，複數個第一金屬連通孔46及第二金屬連通孔47分別連接至該電容器之第一內部電極44及第二內部電極45。參照圖3(b)，每一個第一金屬連通孔46皆與第二金屬連通孔47相鄰擺置，此結構可以減少電流迴路面積，以達到降低寄生電感值之目的。
根據本發明之一實例提供一電容器，該電容器包括複數個電極，該電極包含一頂部電極及一底部電極，一第一連通孔沿該電容器之厚度方向從頂部電極延伸至底部電極，一第二連通孔沿該電容器之厚度方向從頂部電極延伸至底部電極。該電極包含一組第一電極及一組第二電極。該第一連通孔電性連接至第一電極，此外，該第二連通孔電性連接至第二電極。該電容器尚包括了一額外連通孔，該額外連通孔介於該第一連通孔及該第二連通孔之間。而且，該額外連通孔長度較該第一連通孔及該第二連通孔之長度短。此外，該額外連通孔與該第一電極及該第二電極其中之一電性連接。
根據本發明之另一個實例提供一內埋於電路板內之電容器，該電容器包括：複數個電極、一第一連通孔沿該電容器之該厚度方向從該頂部電極延伸至該底部電極、及一第二連通孔沿該電容器之該厚度方向從該頂部電極延伸至該底部電極。該電極包括一組第一電極及一組第二電極。該第一連通孔與該第一電極電性連接且該第二連通孔與該第二電極電性連接。該電容器尚包括一額外連通孔，該額外連通孔介於該第一連通孔及該第二連通孔之間。而且，該額外連通孔長度較該第一連通孔及該第二連通孔之長度短。此外，該額外連通孔與該第一電極及該第二電極其中之一電性連接。該電容器還包括了複數個絕緣層，該絕緣層位於該第一電極和該第二金屬極板之間。該電容器可被使用於各種印刷電路應用中，例如，可內藏至硬式及/或可 撓式電路板、印刷電路板或其他微電子元件(如封裝晶片等)之中。
在根據本發明之另一個實例中，一積體電路承載基板，其電性連接至一積體電路元件，包括：一線路板，該線路板包含一電源層及一接地層；一電容器，該電容器電性連接至該電源層及該接地層。該電容器包括：複數個電極，其包括了一頂部電極及一底部電極，一第一連通孔沿該電容器之厚度方向從該頂部電極延伸至該底部電極；以及一第二連通孔沿該電容器之厚度方向從該頂部電極延伸至該底部電極。該電極包括一組第一電極及一組第二電極。該第一連通孔與該第一電極電性連接，且該第二連通孔與該第二電極電性連接。該電容器也包括一額外連通孔，該額外連通孔介於該第一連通孔與該第二連通孔之間。該額外連通孔長度較該第一連通孔及該第二連通孔之長度短。此外，該額外連通孔與該第一電極及該第二電極其中之一相互電性連接。該電容器還包括了複數個絕緣層，該絕緣層位於該第一電極和該第二金屬極板之間。
本發明提供在電路板中一電容器之線路結構，該電路板之一額外連通孔配置於第二連通孔及第一連通孔之間。該額外連通孔之長度較該第二連通孔或該第一連通孔之長度短。特別在高頻時，在電容元件中藉由該額外連通孔縮短該第二連通孔與該第一連通孔所形成的電流迴路面積，因此可以減少寄生電感效應(即電容器之ESL)。
圖4是根據本發明實例中具有一線路連接結構之電容器之橫截面圖示。參照圖4，一電容器400可包括至少一第一電極410及至少一第二電極420，其中該第一電極410與該第二電極420的極性相反。各對第一電極410及第二電極420間具有一絕緣層430，以在電容器400中形成一電容性元件。圖4之實例中提供該二對第一電極410及第二電極420，其包含最靠近電容器400頂層表面之頂部電極420－1以及最靠近電容器400底層表面之底部電極410－1。在另一實施例中，電容器亦可包含多對第一電極及第二電極，其配置方式可相似於圖4所示之第一電極410及第二電極420。該第一電極410及第二電極420的材料可為任何具有導電性物質所形成。在一實例中，第一電極410及第二420由銅製成。該絕緣層430的材料為不具導電性或低導電性的介電材料所形成，如一實例中之陶瓷介電材料。
在電容器400中，至少一第一連通孔440及至少一第二連通孔450朝著絕緣層430之厚度方向延伸並穿過一特定之絕緣層430。至少有一該第一連通孔440及至少有一該第二連通孔450自電容器400之頂層表面朝向電容器400底層表面的方向延伸。該第一連通孔440及該第二連通孔450可藉由如雷射鑽孔製程、蝕刻製程、孔柱電鍍、增層法等製程，將具有導電性的材料填滿該第一連通孔440及該第二連通孔450，或在其孔壁上塗上一具有導電性的材料，使得連通孔具有導電性。在一個實施例中，該第一連 通孔440及第二連通孔450的內壁被鍍上銅。由於銅具有導電性，第一連通孔440可電性連接至該第一電極410並藉由絕緣環與該第二電極420電性絕緣。相對地，第二連通孔450電性連接至第二電極420並與該第一電極410電性絕緣。因此，藉由第一連通孔440及第二連通孔450以並聯方式連接複數個第一電極410及第二電極420，可產生複數個電容性元件。
再度參考圖4，該電容器400也包含至少一個額外連通孔460，該額外連通孔460配置於任何一對該第一連通孔440及該第二連通孔450之間。該額外連通孔460在長度上短於第一連通孔440之長度，而且該額外連通孔460長度也短於第二連通孔450之長度。如同該第一連通孔440及第二連通孔450，額外連通孔460可藉由如雷射鑽孔製程、增層法、蝕刻、鑽孔及電鍍等製程形成。然而，該第一連通孔、第二連通孔及額外連通孔之形狀可為圓柱狀或其他任何形狀之通道及其組合。該額外連通孔460被填滿或塗上一導電材料以形成導體。在一個實例中，該額外連通孔460的內壁被鍍上銅。如圖4所示，當該額外連通孔460被配置相對接近於一第二連通孔450時，該額外連通孔460電性連接至第一電極410，且與第一連通孔440電性導通。相反地，當額外連通孔460配置於相對接近一第一連通孔440時，該額外連通孔460電性連接至第二電極420，且與第二連通孔450電性導通。該額外連通孔460配置的目的是減少由第一連通孔440及第二連通孔450流入 電容元件的電流迴路面積，以降低寄生電感效應。
圖5所示為根據本發明之一實例之電容器。參照圖5，該電容器500類似於圖4之電容器400，除了在電容器500之絕緣層430a、430b及430c係分別由具有不同介電常數之絕緣材料所形成。
圖6所示為根據本發明之一實例中之一電容器。參照圖6，該電容器600類似於圖4之電容器400，除了該電容器600可包含兩個額外連通孔460a及460b，每個額外連通孔配置於一對該第一連通孔440及該第二連通孔450之間。
圖7所示為根據本發明之電容器線路結構的實例，應用於一電子電路系統，當作去耦合電容器之功效。該電子電路系統700可包含一積體電路710，其藉由錫鉛凸塊760及焊墊770電性連接至電路板720。該電路板720包含一電容器730及線路層740。該電容器730乃根據本發明之一結構，該電容器730之第一電極732a及第二電極732b分別電性連接至一第一連通孔734a及一第二連通孔734b。一額外連通孔736在該第一連通孔734a及該第二連通孔734b之間，在本實例中，該額外連通孔736相對接近該第二連通孔734b，該額外連通孔736電性連接至第一電極732a並與第一連通孔734a電性導通。該電容器730有複數個絕緣層738，其中每個絕緣層被夾在毗鄰的兩個金屬電極之間。參照圖7，該第二連通孔734b電性連接至接地層750b，其中接地層750b位於線路層740之中，然而，該額外連通孔736電性連接至電源層750a，其中電源層 750a位於線路層740之中。該第一連通孔734a和第二連通孔734b透過錫鉛凸塊760及焊墊770電性連接至積體電路710，以作為該積體電路710的電源系統去耦合之用。依據前述線路結構，當該電路操作在一高頻中，電流會流經額外連通孔736並經由第二連通孔734b流回積體電路710，進而縮小電流迴路面積。該電容器可使用在多種印刷電路之應用。例如，電容器可被電性耦接或內埋於硬式及/或可撓性電子電路、印刷電路板或其它微電子器件，如晶片封裝等。
熟習此技藝之人士應瞭解，在不脫離本發明之廣泛發明概念之情況下可對上述實施例進行更改。因此應瞭解，本發明不限於所揭示之特定實施例，而是意欲涵蓋在隨附申請專利範圍所界定之本發明之精神及範疇內的所做之修改。
14’‧‧‧積體電路
28’‧‧‧導電金屬層
30’‧‧‧導電金屬層
34’‧‧‧第一金屬連通孔
36’‧‧‧第二金屬連通孔
41‧‧‧電容器
44‧‧‧第一內部電極
45‧‧‧第二內部電極
46‧‧‧第一金屬連通孔
47‧‧‧第二金屬連通孔
400‧‧‧電容器
410‧‧‧第一電極
420‧‧‧第二電極
430‧‧‧絕緣層
430a‧‧‧絕緣層
430b‧‧‧絕緣層
430c‧‧‧絕緣層
440‧‧‧第一連通孔
450‧‧‧第二連通孔
460‧‧‧額外連通孔
460a‧‧‧額外連通孔
460b‧‧‧額外連通孔
500‧‧‧電容器
600‧‧‧電容器
700‧‧‧電子電路系統
710‧‧‧積體電路
720‧‧‧電路板
730‧‧‧電容器
732a‧‧‧第一電極
732b‧‧‧第二電極
734a‧‧‧第一連通孔
734b‧‧‧第二連通孔
736‧‧‧額外連通孔
738‧‧‧絕緣層
740‧‧‧線路層
750a‧‧‧電源層
750b‧‧‧接地層
760‧‧‧錫鉛凸塊
770‧‧‧焊墊
結合隨附例示性圖式進行閱讀將更好地瞭解前文所述之本發明的【發明內容】及以下【實施方式】。然而應瞭解，本發明不限於所示之精確配置及手段。
圖示中： 圖1所示為習知表面黏著電容器示例性阻抗曲線圖；圖2所示為習知多層電路板上之傳統電容器；圖3(a)所示為習知傳統電容器之內部結構之平面圖；圖3(b)所示為圖3(a)結構之橫截面圖示；圖4所示為根據本發明之實例中，一電路板之電容器之 橫截面圖示；圖5所示為根據本發明之實例中，一電路板之電容器之橫截面圖示；圖6所示為根據本發明之實例中，一電路板之電容器之橫截面圖示；以及圖7所示為根據本發明之實例中，具有電容器之電路板之橫截面圖示；
400‧‧‧電容器
410‧‧‧第一電極
420‧‧‧第二電極
430‧‧‧絕緣層
440‧‧‧第一連通孔
450‧‧‧第二連通孔
460‧‧‧額外連通孔

Claims (19)

  1. 一種層疊電容器，該層疊電容器包括：複數個導電層，該導電層包含一頂部導電層及一底部導電層，該等導電層包含一組第一導電層及一組第二導電層；一電源連通孔，該電源連通孔沿該層疊電容器之厚度方向從該頂部導電層延伸至該底部導電層，該電源連通孔電性連接至第一導電層；一接地連通孔，該接地連通孔沿該層疊電容器之厚度方向從該頂部導電層延伸至該底部導電層，該接地連通孔電性連接至第二導電層；以及一輔助連通孔，該輔助連通孔的位置介於該電源連通孔及該接地連通孔之間，該輔助連通孔長度較該電源連通孔及該接地連通孔之長度短，而且該輔助連通孔與該第一導電層及該第二導電層其中之一電性連接。
  2. 如申請專利範圍第1項所述之層疊電容器，其中該電源連通孔、該接地連通孔及該輔助連通孔之形狀係為圓柱狀或其它任何形狀及其組合。
  3. 如申請專利範圍第1項所述之層疊電容器，其中該輔助連通孔電性連接至該第一導電層及該第二導電層之一係取決於電源連通孔及接地連通孔何者之配置位置相對較靠近該輔助連通孔。
  4. 如申請專利範圍第1項所述之層疊電容器，其中當該輔助連通孔配置於相對靠近於該接地連通孔，該輔助連通孔電性連接至該第一導電層。
  5. 如申請專利範圍第1項所述之層疊電容器，其中當該輔助連通孔配置於相對靠近於該電源連通孔時，該輔助連通孔電性連接至該第二導電層。
  6. 一種內埋於一電路板之層疊電容器，該層疊電容器包括：複數個導電層，其包括了一頂部導電層及一底部導電層，該導電層包括一組第一導電層及一組第二導電層；一電源連通孔，該電源連通孔沿該層疊電容器之厚度方向從該頂部導電層延伸至該底部導電層，該電源連通孔電性連接至該第一導電層；一接地連通孔，該接地連通孔沿該層疊電容器之厚度方向從該頂部導電層延伸至該底部導電層，該接地連通孔電性連接至該第二導電層；一輔助連通孔，該輔助連通孔的位置介於該電源連通孔及該接地連通孔之間，該輔助連通孔長度較該電源連通孔及該接地連通孔之長度短，該輔助連通孔與該第一導電層及該第二導電層其中之一電性連接；以及複數個絕緣層，各絕緣層被配置在兩個相鄰之導電層之間。
  7. 如申請專利範圍第6項所述之層疊電容器，其中該絕緣層係由相同或不同介電常數之絕緣材料所形成。
  8. 如申請專利範圍第6項所述之層疊電容器，其中該電源連通孔、該接地連通孔及該輔助連通孔之形狀係為圓柱狀或其它任何形狀及其組合。
  9. 如申請專利範圍第6項所述之層疊電容器，其中該輔助連通孔電性連接至該第一導電層及該第二電極導電層之一係取決於電源連通孔及接地連通孔何者之配置位置相對較靠近該輔助連通孔。
  10. 如申請專利範圍第6項所述之層疊電容器，其中當該輔助連通孔配置於相對靠近該電源連通孔時，該輔助連通孔電性連接至該第二導電層。
  11. 如申請專利範圍第6項所述之層疊電容器，其中當該輔助連通孔配置於相對靠近該接地連通孔時，該輔助連通孔電性連接至該第一導電層。
  12. 一種積體電路承載基板，其電性連接至一積體電路晶片，該積體電路承載基板包括：一包含一電源層及一接地層之線路層；以及一層疊電容器，該層疊電容器電性連接至該電源層及該接地層，其中該層疊電容器包括：複數個導電層，其包括了一頂部導電層及一底部導電層，該導電層包括一組第一導電層及一組第二導電層；一電源連通孔，該電源連通孔沿該層疊電容器之厚度方向從該頂部導電層延伸至該底部導電層，該電源連通孔電性連接至該第一導電層；一接地連通孔，該接地連通孔沿該層疊電容器之厚度方向從該頂部導電層延伸至該底部導電層，該接地連通孔電性連接至該第二導電層；一輔助連通孔，該輔助連通孔的位置介於該電源連通孔 及該接地連通孔之間，該輔助連通孔長度較該電源連通孔及該接地連通孔之長度短，該輔助連通孔與該第一導電層及該第二導電層其中之一電性連接；以及複數個絕緣層，各絕緣層被配置在兩個相鄰之導電層之間。
  13. 如申請專利範圍第12項所述之積體電路承載基板，其中該接地連通孔電性連接至該接地層，該輔助連通孔及接地連通孔皆電性連接至該電源層。
  14. 如申請專利範圍第12項所述之積體電路承載基板，其中該電源連通孔電性連接至該接地層，該輔助連通孔及接地連通孔皆電性連接至該電源層。
  15. 如申請專利範圍第12項所述之積體電路承載基板，其中該絕緣層係由相同或不同介電常數之絕緣材料所形成。
  16. 如申請專利範圍第12項所述之積體電路承載基板，其中該電源連通孔、該接地連通孔及該輔助連通孔之形狀係為圓柱狀或其它任何形狀及其組合。
  17. 如申請專利範圍第12項所述之積體電路承載基板，其中該輔助連通孔電性連接至該第一導電層及該第二導電層之一係取決於電源連通孔及接地連通孔何者的配置位置相對較靠近該輔助連通孔。
  18. 如申請專利範圍第12項所述之積體電路承載基板，其中當該輔助連通孔配置於相對靠近該電源連通孔時，該輔助連通孔電性連接至該第二導電層。
  19. 如申請專利範圍第12項所述之積體電路承載基 板，其中當該輔助連通孔配置於相對靠近該接地連通孔時，該輔助連通孔電性連接至該第一導電層。
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