TWI395529B - Carrier substrate amd method for making the same - Google Patents
Carrier substrate amd method for making the same Download PDFInfo
- Publication number
- TWI395529B TWI395529B TW099122816A TW99122816A TWI395529B TW I395529 B TWI395529 B TW I395529B TW 099122816 A TW099122816 A TW 099122816A TW 99122816 A TW99122816 A TW 99122816A TW I395529 B TWI395529 B TW I395529B
- Authority
- TW
- Taiwan
- Prior art keywords
- carrier
- printed circuit
- circuit board
- wafer
- elastic contact
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
Landscapes
- Wire Bonding (AREA)
- Measuring Leads Or Probes (AREA)
Description
本發明係有關於一種載板(carrier substrate)，特別是一種在印刷電路板接合端面(PCB side)上設有彈性接觸件的載板、使用該載板的晶片模組及其製作方法。The present invention relates to a carrier substrate, and more particularly to a carrier having an elastic contact member on a PCB side, a wafer module using the carrier, and a method of fabricating the same.
隨著積體電路晶片的訊號輸入/輸出計數(I/O pin count)與密度不斷提高，使得連結晶片模組至印刷電路板的過程變得極具挑戰性。在過去，晶片模組通常是直接焊接在印刷電路板上，但是日後若要更換焊接好的晶片模組，就必須將整個電路板送回供應商，才能移除、更換，再連結，造成成本的增加。As the signal input/output count (I/O pin count) and density of integrated circuit chips continue to increase, the process of connecting the chip modules to the printed circuit board becomes extremely challenging. In the past, wafer modules were usually soldered directly to the printed circuit board. However, if the soldered chip module is to be replaced in the future, the entire circuit board must be returned to the supplier for removal, replacement, and connection, resulting in cost. Increase.
為了避免上述問題，業界於是發展出一種在晶片模組的載板與印刷電路板之間另外置入一內插連接器(interposer)的技術，見第1圖，在一載板1與一印刷電路板2之間設有一內插連接器3，其中，內插連接器3包括一基板30、設在基板30的一晶片接合端面(chip side)3a上的複數個彈性接觸件32，以及設在基板30的一印刷電路板接合端面(PCB side)3b上的複數個錫球34。其中，彈性接觸件32與載板1的底面1a上的網格陣列(land grid array,LGA)接墊12構成電連接，而錫球34則與印刷電路板2構成電連接。In order to avoid the above problems, the industry has developed a technique for additionally inserting an interposer between the carrier of the wafer module and the printed circuit board. See Fig. 1 for printing on a carrier 1 and a carrier. An interposer connector 3 is disposed between the circuit board 2, wherein the interposer connector 3 includes a substrate 30, a plurality of elastic contact members 32 disposed on a chip side 3a of the substrate 30, and A plurality of solder balls 34 on a printed circuit board bonding end face (PCB side) 3b of the substrate 30. The elastic contact member 32 is electrically connected to the land grid array (LGA) pad 12 on the bottom surface 1a of the carrier board 1, and the solder ball 34 is electrically connected to the printed circuit board 2.
然而，上述先前技藝仍有諸多缺點需要進一步的改善與改進。例如，利用前述內插連接器技術需要加工兩次，組裝步驟較麻煩，而且成本較高。再者，晶片與印刷電路板之間在增加內插連接器之後，訊號傳遞的路徑變長，將造成元件的操作效能降低。此外，內插連接器會增加電路板組裝厚度，故不適合應用在組裝空間有限的特定場合。However, there are still many shortcomings in the above prior art that require further improvements and improvements. For example, the use of the aforementioned interposer connector technology requires two processing steps, the assembly step is cumbersome, and the cost is high. Moreover, after the interposer is added between the wafer and the printed circuit board, the path of the signal transmission becomes long, which will result in a decrease in the operational efficiency of the component. In addition, the interposer connector increases the board assembly thickness and is therefore not suitable for use in specific applications where assembly space is limited.
因此，本發明的主要目的在提供一種改良的載板以及應用該載板的晶片模組，以解決上述先前技藝的不足與缺點。Accordingly, it is a primary object of the present invention to provide an improved carrier board and a wafer module to which the carrier board is applied to address the deficiencies and shortcomings of the prior art described above.
根據本發明之較佳實施例，本發明提供一種載板，包含有一基板，其具有一晶片接合端面及一印刷電路板接合端面；複數個接合墊，設於晶片接合端面上，用來與一晶片接合；複數個網格陣列接墊，設於印刷電路板接合端面上；及複數個呈陣列排列的彈性接觸件，設於印刷電路板接合端面上，其中，彈性接觸件與網格陣列接墊電連接。According to a preferred embodiment of the present invention, there is provided a carrier board comprising a substrate having a wafer bonding end surface and a printed circuit board bonding end surface; a plurality of bonding pads disposed on the wafer bonding end surface for use with a carrier Wafer bonding; a plurality of grid array pads disposed on the bonding end surface of the printed circuit board; and a plurality of elastic contact members arranged in an array disposed on the bonding end surface of the printed circuit board, wherein the elastic contact members are connected to the grid array The pads are electrically connected.
根據本發明之另一較佳實施例，本發明提供一種晶片模組，包含有一載板，其包含有一基板，其具有一晶片接合端面以及一印刷電路板接合端面。晶片與在晶片接合端面上的接合墊接合在一起，而在相對於晶片接合端面的印刷電路板接合端面上則設有網格陣列接墊以及複數個呈陣列排列的彈性接觸件。其中，複數個彈性接觸件分別與網格陣列接墊電連接。In accordance with another preferred embodiment of the present invention, a wafer die assembly includes a carrier plate including a substrate having a die bond end face and a printed circuit board bond end face. The wafer is bonded to the bonding pad on the wafer bonding end face, and a grid array pad and a plurality of elastic contacts arranged in an array are disposed on the bonding surface of the printed circuit board opposite to the wafer bonding end face. Wherein, the plurality of elastic contacts are electrically connected to the grid array pads, respectively.
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention.
請參閱第2圖，其為依據本發明一較佳實施例所繪示的載板的剖面示意圖。如第2圖所示，依據本發明較佳實施例，載板100包含有一基板110，例如為一多層板或單層板，其具有一晶片接合端面110a以及一印刷電路板接合端面110b。在晶片接合端面110a上設有複數個用來與一晶片101接合的接合墊111，而在相對於晶片接合端面110a的印刷電路板接合端面110b上則設有網格陣列(land grid array,LGA)接墊112以及複數個呈陣列排列的彈性接觸件120。其中，複數個彈性接觸件120分別與網格陣列接墊112電連接。Please refer to FIG. 2, which is a cross-sectional view of a carrier board according to a preferred embodiment of the present invention. As shown in FIG. 2, in accordance with a preferred embodiment of the present invention, carrier board 100 includes a substrate 110, such as a multilayer board or a single layer board having a wafer bond end face 110a and a printed circuit board bond end face 110b. A plurality of bonding pads 111 for bonding to a wafer 101 are provided on the wafer bonding end surface 110a, and a land grid array (LGA) is provided on the bonding surface 110b of the printed circuit board with respect to the wafer bonding end surface 110a. The pad 112 and a plurality of elastic contacts 120 arranged in an array. The plurality of resilient contacts 120 are electrically connected to the grid array pads 112, respectively.
依據本發明較佳實施例，彈性接觸件120可以是一金屬懸凸臂(metal flange)，例如，銅或複合金屬，包括一基部120a、一具有曲度的中間延伸段120b，以及一接觸末端120c。彈性接觸件120係藉由基部120a固定在基板110的印刷電路板接合端面110b上，例如，可以利用一低流膠介電層(low-flow prepreg)130，將彈性接觸件120的基部120a壓合固著在基板110的印刷電路板接合端面110b上。在彈性接觸件120的表面另形成有一選擇性鍍金層140或其它不易氧化、耐磨的貴金屬材料。彈性接觸件120係透過一形成在低流膠介電層130中的一電鍍通孔150與網格陣列接墊112電連接。另外，在低流膠介電材130上可以覆蓋一保護層(coverlay)160。In accordance with a preferred embodiment of the present invention, the resilient contact member 120 can be a metal metal flange, such as copper or a composite metal, including a base 120a, a meandering section 120b having a curvature, and a contact end. 120c. The elastic contact 120 is fixed on the printed circuit board bonding end surface 110b of the substrate 110 by the base 120a. For example, the base 120a of the elastic contact 120 can be pressed by a low-flow prepreg 130. The printed circuit board bonding end surface 110b of the substrate 110 is bonded. A selective gold plating layer 140 or other precious metal material which is not easily oxidized and wear-resistant is formed on the surface of the elastic contact member 120. The resilient contact member 120 is electrically connected to the grid array pad 112 through a plated through hole 150 formed in the low flow adhesive dielectric layer 130. Additionally, a coverlay 160 may be overlaid on the low flow adhesive dielectric 130.
本發明的技術特徵在於透過設置在印刷電路板接合接端面110b上的彈性接觸件120，載板100可以直接與印刷電路板2接合連結，而晶片101係接合在載板100的晶片接合端面110a上，如此一來，即可以省略先前技藝中的內插連接器，其優點包括：(1)組裝步驟較簡單，而且省略內插連接器後，成本降低。(2)省略內插連接器後，晶片與印刷電路板之間的訊號傳遞路徑變短，提升元件的操作效能。(3)組裝後，電路板整體厚度降低。The technical feature of the present invention is that the carrier 100 can be directly bonded to the printed circuit board 2 through the elastic contact 120 disposed on the printed circuit board bonding end surface 110b, and the wafer 101 is bonded to the wafer bonding end surface 110a of the carrier 100. In this way, the interposer connector of the prior art can be omitted, and the advantages include: (1) the assembly step is relatively simple, and the cost is reduced after omitting the interposer connector. (2) After omitting the interposer connector, the signal transmission path between the wafer and the printed circuit board is shortened, and the operational performance of the component is improved. (3) After assembly, the overall thickness of the board is reduced.
依據本發明較佳實施例之載板100的製作方法，將於下做詳細說明。A method of fabricating the carrier 100 in accordance with a preferred embodiment of the present invention will be described in detail below.
請參閱第3圖至第8圖，載板100的製作方法包含有提供一基板110，其具有一晶片接合端面110a以及一印刷電路板接合端面110b。在晶片接合端面110a上設有複數個用來與一晶片(圖未示)接合的接合墊111，而在相對於晶片接合端面110a的印刷電路板接合端面110b上設有網格陣列接墊112(如第3圖)。接著，在印刷電路板接合端面110b以一金屬皮層200壓合低流膠介電層130。金屬皮層200上具有呈陣列排列的複數個彈性接觸件120，其中，彈性接觸件120可以是一金屬懸凸臂，例如，銅或複合金屬，包括一基部120a、一具有曲度的中間延伸段120b，以及一接觸末端120c。彈性接觸件120係藉由基部120a固定在基板110的印刷電路板接合端面110b上(如第4圖)。在金屬皮層200上的複數個彈性接觸件120可以利用沖壓、蝕刻或其它方式形成。Referring to FIGS. 3-8, the method of fabricating the carrier 100 includes providing a substrate 110 having a die bond end face 110a and a printed circuit board bond end face 110b. A plurality of bonding pads 111 for bonding to a wafer (not shown) are disposed on the wafer bonding end surface 110a, and a grid array pad 112 is disposed on the bonding surface 110b of the printed circuit board with respect to the die bonding end surface 110a. (as in Figure 3). Next, the low-flow adhesive dielectric layer 130 is laminated to the printed circuit board bonding end face 110b with a metal skin layer 200. The metal skin layer 200 has a plurality of elastic contact members 120 arranged in an array, wherein the elastic contact member 120 can be a metal cantilever arm, for example, copper or composite metal, including a base portion 120a and an intermediate portion having a curvature. 120b, and a contact end 120c. The elastic contact 120 is fixed to the printed circuit board bonding end face 110b of the substrate 110 by the base 120a (as shown in FIG. 4). The plurality of resilient contacts 120 on the metal skin 200 can be formed by stamping, etching, or other means.
接著，進行電鍍製程，在基板110的印刷電路板接合端面110b上電鍍銅及鎳金屬層132，同時在低流膠介電層130中形成電鍍通孔150，如此使電鍍通孔150電連接網格陣列接墊112及彈性接觸件120(如第5圖)。隨後，進行選擇性電鍍金製程，利用光阻(圖未示)將基板110的非鍍金表面區域蓋住，而在鍍金表面區域，例如，包括彈性接觸件120的表面以及部分的銅及鎳金屬層132表面，鍍上一層金屬金140(如第6圖)。然後，在去除光阻層之後，進行線路蝕刻步驟，去除部分的金屬皮層200、銅及鎳金屬層132，而曝露出部分的低流膠介電層130(如第7圖)。最後，在低流膠介電層130上覆蓋一保護層160，其中，保護層160可以利用一黏著層(圖未示)固著在載板100上，即完成載板100的製作(如第8圖)。Then, an electroplating process is performed to plate the copper and nickel metal layers 132 on the printed circuit board bonding end surface 110b of the substrate 110, and at the same time, the plated through holes 150 are formed in the low-flow adhesive dielectric layer 130, so that the plated through holes 150 are electrically connected to the net. Array pad 112 and resilient contact 120 (as shown in Figure 5). Subsequently, a selective gold plating process is performed to cover the non-gold-plated surface area of the substrate 110 with a photoresist (not shown), and in the gold-plated surface area, for example, the surface including the elastic contact 120 and a portion of copper and nickel metal. The surface of layer 132 is plated with a layer of metallic gold 140 (as shown in Figure 6). Then, after removing the photoresist layer, a line etching step is performed to remove portions of the metal skin layer 200, the copper and nickel metal layers 132, and expose portions of the low-flow plastic dielectric layer 130 (as shown in FIG. 7). Finally, the protective layer 160 is covered on the low-flow adhesive dielectric layer 130. The protective layer 160 can be fixed on the carrier 100 by using an adhesive layer (not shown), that is, the fabrication of the carrier 100 is completed. 8 picture).
另一方面，本發明亦提出一種使用載板100的晶片模組100’，見第9圖，晶片模組100’包含有一載板100，其結構同第8圖，同樣包含有一基板110，其具有一晶片接合端面110a以及一印刷電路板接合端面110b。晶片101與在晶片接合端面110a上的接合墊111接合在一起，而在相對於晶片接合端面110a的印刷電路板接合端面110b上則設有網格陣列接墊112以及複數個呈陣列排列的彈性接觸件120。其中，複數個彈性接觸件120分別與網格陣列接墊112電連接。彈性接觸件120可以是一金屬懸凸臂，例如，銅或複合金屬，包括一基部120a、一具有曲度的中間延伸段120b，以及一接觸末端120c。In another aspect, the present invention also provides a wafer module 100' using a carrier 100. See FIG. 9, the wafer module 100' includes a carrier 100 having the same structure as that of FIG. 8, and also includes a substrate 110. There is a wafer bonding end face 110a and a printed circuit board bonding end face 110b. The wafer 101 is bonded to the bonding pads 111 on the wafer bonding end face 110a, and the grid array pads 112 are provided on the printed circuit board bonding end faces 110b with respect to the wafer bonding end faces 110a, and a plurality of elastic arrays are arranged. Contact 120. The plurality of resilient contacts 120 are electrically connected to the grid array pads 112, respectively. The resilient contact member 120 can be a metal cantilevered arm, such as copper or a composite metal, including a base 120a, an intermediate extension 120b having a curvature, and a contact end 120c.
彈性接觸件120係藉由基部120a固定在基板110的印刷電路板接合端面110b上，例如，可以利用一低流膠介電層130，將彈性接觸件120壓合固著在基板110的印刷電路板接合端面110b上。在彈性接觸件120的表面另有選擇性鍍金140或其它不易氧化、耐磨的貴金屬材料。彈性接觸件120係透過一形成在低流膠介電層130中的電鍍通孔150與網格陣列接墊112電連接。另外，在低流膠介電材130上可以形成一保護層160。The elastic contact 120 is fixed on the printed circuit board bonding end surface 110b of the substrate 110 by the base 120a. For example, the low contact adhesive dielectric layer 130 can be used to press the elastic contact 120 to the printed circuit of the substrate 110. The plate is joined to the end face 110b. There is also a selective gold plating 140 or other precious metal material which is not easily oxidized and wear-resistant on the surface of the elastic contact member 120. The resilient contact member 120 is electrically connected to the grid array pad 112 through a plated through hole 150 formed in the low flow adhesive dielectric layer 130. In addition, a protective layer 160 may be formed on the low flow adhesive dielectric material 130.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
1．．．載板1. . . Carrier board
1a．．．底面1a. . . Bottom
2．．．印刷電路板2. . . A printed circuit board
3．．．內插連接器3. . . Interposer connector
3a．．．晶片接合端面3a. . . Wafer bonding end face
3b．．．印刷電路板接合端面3b. . . Printed circuit board joint end face
12．．．網格陣列接墊12. . . Grid array pad
30．．．基板30. . . Substrate
32．．．彈性接觸件32. . . Elastic contact
34‧‧‧錫球34‧‧‧ solder balls
100‧‧‧載板100‧‧‧ Carrier Board
100’‧‧‧晶片模組100'‧‧‧ wafer module
101‧‧‧晶片101‧‧‧ wafer
110‧‧‧基板110‧‧‧Substrate
110a‧‧‧晶片接合端面110a‧‧‧ wafer joint end face
110b‧‧‧印刷電路板接合端面110b‧‧‧ Printed circuit board joint end face
111‧‧‧接合墊111‧‧‧Material pads
112‧‧‧網格陣列接墊112‧‧‧Grid Array Pads
120‧‧‧彈性接觸件120‧‧‧Flexible contacts
120a‧‧‧基部120a‧‧‧ base
120b‧‧‧中間延伸段120b‧‧‧Intermediate extension
120c‧‧‧接觸末端120c‧‧‧Contact end
130‧‧‧低流膠介電材130‧‧‧Low-flow adhesive dielectric
132‧‧‧銅及鎳金屬層132‧‧‧ copper and nickel metal layers
140‧‧‧選擇性鍍金層(金層)140‧‧‧Selective gold plating layer (gold layer)
150‧‧‧電鍍通孔150‧‧‧ plated through hole
160‧‧‧保護層160‧‧‧Protective layer
200‧‧‧金屬皮層200‧‧‧metal cortex
第1圖為習知技術在晶片模組的載板與印刷電路板之間置入一內插連接器的示意圖。FIG. 1 is a schematic view showing a conventional insertion of an interposer between a carrier of a wafer module and a printed circuit board.
第2圖為依據本發明較佳實施例所繪示的載板的剖面示意圖。2 is a cross-sectional view of a carrier board according to a preferred embodiment of the present invention.
第3圖至第8圖例示本發明載板的製作方法，其中，第3圖例示基板的剖面結構，第4圖例示本發明載板在基板的印刷電路板接合端面壓合彈性接觸件之後的剖面結構，第5圖例示本發明載板在電鍍銅及鎳金屬層之後的剖面結構，第6圖例示本發明載板在進行選擇性電鍍金之後的剖面結構，第7圖例示本發明載板在進行線路蝕刻步驟之後的剖面結構，第8圖例示本發明載板在覆蓋保護層之後的剖面結構。3 to 8 illustrate a method of fabricating the carrier of the present invention, wherein FIG. 3 illustrates a cross-sectional structure of the substrate, and FIG. 4 illustrates the carrier of the present invention after the bonding surface of the printed circuit board of the substrate is pressed against the elastic contact. The cross-sectional structure, FIG. 5 illustrates a cross-sectional structure of the carrier of the present invention after electroplating of copper and nickel metal layers, FIG. 6 illustrates a cross-sectional structure of the carrier of the present invention after selective electroplating of gold, and FIG. 7 illustrates the carrier of the present invention. The cross-sectional structure after the line etching step is performed, and Fig. 8 illustrates the cross-sectional structure of the carrier of the present invention after covering the protective layer.
第9圖為依據本發明較佳實施例所繪示的晶片模組的剖面示意圖。FIG. 9 is a cross-sectional view of a wafer module in accordance with a preferred embodiment of the present invention.
2．．．印刷電路板2. . . A printed circuit board
100．．．載板100. . . Carrier board
101．．．晶片101. . . Wafer
110．．．基板110. . . Substrate
110a．．．晶片接合端面110a. . . Wafer bonding end face
110b．．．印刷電路板接合端面110b. . . Printed circuit board joint end face
111．．．接合墊111. . . Mat
112．．．網格陣列接墊112. . . Grid array pad
120．．．彈性接觸件120. . . Elastic contact
120a．．．基部120a. . . Base
120b．．．中間延伸段120b. . . Intermediate extension
120c．．．接觸末端120c. . . Contact end
130．．．低流膠介電材130. . . Low flow adhesive dielectric
140．．．選擇性鍍金層(金層)140. . . Selective gold plating layer (gold layer)
150．．．電鍍通孔150. . . Plating through hole
160．．．保護層160. . . The protective layer
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099122816A TWI395529B (en) | 2010-07-12 | 2010-07-12 | Carrier substrate amd method for making the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW099122816A TWI395529B (en) | 2010-07-12 | 2010-07-12 | Carrier substrate amd method for making the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201204205A TW201204205A (en) | 2012-01-16 |
| TWI395529B true TWI395529B (en) | 2013-05-01 |
Family
ID=46756527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW099122816A TWI395529B (en) | 2010-07-12 | 2010-07-12 | Carrier substrate amd method for making the same |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI395529B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080239683A1 (en) * | 2007-03-30 | 2008-10-02 | William Louis Brodsky | Method and Apparatus for Electrically Connecting Two Substrates Using a Land Grid Array Connector Provided with a Frame Structure Having Power Distribution Elements |
-
2010
- 2010-07-12 TW TW099122816A patent/TWI395529B/en active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080239683A1 (en) * | 2007-03-30 | 2008-10-02 | William Louis Brodsky | Method and Apparatus for Electrically Connecting Two Substrates Using a Land Grid Array Connector Provided with a Frame Structure Having Power Distribution Elements |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201204205A (en) | 2012-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5759047A (en) | Flexible circuitized interposer with apertured member and method for making same | |
| US7628617B2 (en) | Structure and process for a contact grid array formed in a circuitized substrate | |
| JP5500870B2 (en) | Substrate with connection terminal and socket for electronic parts | |
| JP4308608B2 (en) | Semiconductor device | |
| JP5663379B2 (en) | Connection terminal structure, socket and electronic component package | |
| JP5788166B2 (en) | Connection terminal structure, manufacturing method thereof, and socket | |
| JP2004343030A (en) | Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board | |
| JP4070470B2 (en) | Multilayer circuit board for semiconductor device, manufacturing method thereof, and semiconductor device | |
| JP2011049031A (en) | Flexible harness and electric connection component using it | |
| KR100891334B1 (en) | Circuit board, semiconductor package having the board, and methods of fabricating the circuit board and the semiconductor package | |
| US20130029500A1 (en) | Connector and fabrication method thereof | |
| US20110042828A1 (en) | Wiring board, semiconductor device and method for manufacturing semiconductor device | |
| TWI427860B (en) | Land grid array module with contact locating features | |
| TWI452659B (en) | Circuit board, fabricating method thereof and package structure | |
| JP4360240B2 (en) | Semiconductor device and multilayer substrate for semiconductor device | |
| TWI395529B (en) | Carrier substrate amd method for making the same | |
| US8274798B2 (en) | Carrier substrate and method for making the same | |
| JP5794833B2 (en) | Connection terminal, manufacturing method thereof, and socket | |
| TWI394250B (en) | Package structure and fabrication method thereof | |
| US6459592B1 (en) | Circuit assembly including VLSI package | |
| TWI519794B (en) | Interconnect structure, manufacturing method and application thereof | |
| TW201306403A (en) | Connector and fabrication method thereof | |
| CN108666293B (en) | Circuit carrier plate and manufacturing method thereof | |
| JP2006294825A (en) | Semiconductor integrated circuit device | |
| JP2001194417A (en) | Substrate with electrode, inspecting jig using the same, inspection apparatus and adapter apparatus |