TWI416698B - Semiconductor package structure - Google Patents

Semiconductor package structure Download PDF

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Publication number
TWI416698B
TWI416698B TW097128057A TW97128057A TWI416698B TW I416698 B TWI416698 B TW I416698B TW 097128057 A TW097128057 A TW 097128057A TW 97128057 A TW97128057 A TW 97128057A TW I416698 B TWI416698 B TW I416698B
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Taiwan
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substrate
wafer
adhesive layer
back surface
package structure
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TW097128057A
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Chinese (zh)
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TW201005914A (en
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Hung Tsun Lin
Cheng Ting Wu
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Priority to TW097128057A priority Critical patent/TWI416698B/en
Publication of TW201005914A publication Critical patent/TW201005914A/en
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Publication of TWI416698B publication Critical patent/TWI416698B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

A semiconductor package structure is provided, which includes a front side and a reverse side, and an opening penetrated the substrate; a first chip having an active surface and a reverse, in which the active surface of first chip is faced-up and attached on the reverse side of substrate by a first adhesive layer and covered the opening of substrate; a first conductive wire electrically connected the active surface of first chip and the front side of substrate; a second adhesive layer covered the first conductive wire and the pads of the active surface of first chip; a second chip having an active surface and a reverse side, and the reverse side of the second chip is attached on the front side of the substrate; a first encapsulated body encapsulated the first chip, the first adhesive layer, the first conductive wire and the portion reverse side of the substrate; the second encapsulated body encapsulated the second chip, second adhesive layer, second conductive wire, and the portion front side of substrate; and conductive component is disposed on the reverse side of the substrate.

Description

半導體封裝結構Semiconductor package structure

本發明係有關於一種封裝結構及其方法，特別是有關於一種具有開口之基板之封裝結構及其方法。The present invention relates to a package structure and method therefor, and more particularly to a package structure and method for an open substrate.

具有開口之基板之半導體封裝結構係為較先進之封裝技術，其特徵在於：在基板上形成至少一個貫孔(opening)，且允許晶片設置且覆蓋住基板之貫孔，並藉由穿過貫孔之打線接合之導線與基板電性連接。此種設置的方式可有效的縮短打線接合之導線之長度，藉此在基板及晶片之間形成電性連接。習知的具有開口之基板之封裝結構如第1圖所示，其中基板100具有一上表面及一下表面且具有一開口102貫穿基板100。接著，一晶片120以主動面(未在圖中表示)朝下的方式且其主動面上的焊墊122係曝露於基板100之開口102。緊接著，複數條導線130以打線接合(bonding wires)的方式經由基板100之開口102連接至曝露於開口102之晶片120之焊墊122，藉此電性連接基板100之下表面與晶片120之主動面。接著，一封裝體140藉由印刷的方式形成在基板100的下表面上用以包覆導線130以及將基板100之開口102密封住。The semiconductor package structure with the open substrate is a more advanced packaging technology, characterized in that at least one opening is formed on the substrate, and the wafer is allowed to be disposed and covers the through hole of the substrate, and The wire bonding wire of the hole is electrically connected to the substrate. This arrangement can effectively shorten the length of the wire bonding wire, thereby forming an electrical connection between the substrate and the wafer. The package structure of a conventional substrate having an opening is as shown in FIG. 1 , wherein the substrate 100 has an upper surface and a lower surface and has an opening 102 penetrating through the substrate 100 . Next, a wafer 120 is exposed to the opening 102 of the substrate 100 in such a manner that the active surface (not shown) faces downward and the pads 122 on the active surface thereof. Then, the plurality of wires 130 are connected to the pads 122 of the wafer 120 exposed to the openings 102 through the openings 102 of the substrate 100 in a bonding manner, thereby electrically connecting the lower surface of the substrate 100 and the wafer 120. Active face. Next, a package body 140 is formed on the lower surface of the substrate 100 by printing to cover the wires 130 and seal the openings 102 of the substrate 100.

然而，由於在封裝體140(尤其是藉由樹脂材料(resin materila)所形成之封裝體140)及與封裝體140接觸之晶片120之間的熱膨脹係數(CTE,coefficient of thermal expansion)之不匹配，在高溫的條件下，例如封裝體140之固化(curing)步驟或是後續的熱循環步驟，特別是在晶粒120的部份因為來自於封裝體140的熱應力(thermal stress)會產生晶粒崩裂(chip－crack)的問題，而相對於較長且較大尺寸的晶粒來說，其可靠度以及良率都會降低。此外，在封裝體140的形成過程中，其焊線接合之導線會與樹脂材料以模流的方式形成 封裝體時接觸，使得會有短路的問題。However, due to the mismatch between the coefficient of thermal expansion (CTE) between the package 140 (especially the package 140 formed by resin materila) and the wafer 120 in contact with the package 140 Under high temperature conditions, such as a curing step of the package 140 or a subsequent thermal cycle step, particularly in the portion of the die 120 due to thermal stress from the package 140, crystals are generated. The problem of chip-crack, and its reliability and yield are reduced relative to longer and larger sized grains. In addition, during the formation of the package body 140, the wires of the wire bonding are formed in a mold flow manner with the resin material. Contact when the package is in contact, causing a problem of short circuit.

鑒於以上的問題，本發明的主要目的在於提供一種具有窗口(window)之半導體封裝結構，藉此以縮短基板之導線長度增加晶粒之間的電性傳送以提昇半導體封裝結構之電性及效能。In view of the above problems, the main object of the present invention is to provide a semiconductor package structure having a window, thereby shortening the wire length of the substrate and increasing the electrical transfer between the crystal grains to improve the electrical and performance of the semiconductor package structure. .

根據以上之目的，本發明提供一種半導體封裝結構，包含：一基板，具有一正面及一背面，且具有一開口穿透過基板；一第一晶片，具有一主動面及一背面，其中第一晶片之主動面係朝上，且經由第一黏著層覆蓋在開口上，並藉由第一黏著層貼附在基板之背面上；複數條第一導線，經由開口電性連接第一晶片及基板之正面；第二黏著層，用以包覆複數條第一導線及覆蓋在第一晶片之主動面上之複數條焊墊；一第二晶片，具有一主動面及一背面，第二晶片之背面係相對於第一晶片朝下且將主動面朝上，藉由第二黏著層貼附在基板之正面上；複數條第二導線，用以電性連接第二晶片之主動面及基板之正面；第一封裝體，用以包覆第一晶片、第一黏著層、複數條第一導線及基板之部份背面；第二封裝體，用以包覆第二晶片、第二黏著層、複數條第二導線及基板之部份正面；及複數個導電元件，係設置在基板之背面上。According to the above objective, the present invention provides a semiconductor package structure comprising: a substrate having a front surface and a back surface and having an opening penetrating through the substrate; a first wafer having an active surface and a back surface, wherein the first wafer The active surface is facing upward, and is covered on the opening via the first adhesive layer, and is attached to the back surface of the substrate by the first adhesive layer; the plurality of first wires are electrically connected to the first wafer and the substrate via the opening a second adhesive layer for coating a plurality of first wires and a plurality of pads covering the active surface of the first wafer; a second wafer having an active surface and a back surface, the back surface of the second wafer The second adhesive layer is attached to the front surface of the substrate by the second adhesive layer, and the second conductive layer is electrically connected to the active surface of the second wafer and the front surface of the substrate. a first package body for covering the first wafer, the first adhesive layer, the plurality of first wires, and a portion of the back surface of the substrate; the second package body for covering the second wafer, the second adhesive layer, and the plurality Second wire The front portion of the substrate; and a plurality of conductive elements, based on a rear substrate disposed of.

本發明還揭露一種半導體封裝結構，包含：一基板，具有一正面及一背面，且具有一開口穿透過基板；第一晶片，具有一主動面及一背面，其中第一晶片之主動面係朝上且經由第一黏著層覆蓋在開口上並藉由第一黏著層貼附在基板之背面上；第二晶片，具有一主動面及一背面，其中第二晶片之背面係相對於第一晶片朝下經由第二黏著層覆蓋在開口上，並藉由第二黏著層貼附在基板之正面上；一第三晶片，具有一主動面及一背面，係以覆晶方式朝下藉由複數個第一導電元件連接基板之向外延伸之正面上；複數條第一導線，係用以電性連接第一晶片及基板之正面；複數條第二導 線，係用以電性連接第二晶片之主動面及基板之正面；第一封裝體，用以包覆第一晶片、第一黏著層、複數條第一導線及基板之部份背面；第二封裝體，用以包覆第二晶片、第二黏著層、複數條第二導線及基板之部份正面；及複數個第二導電元件，係設置在基板之背面上。The present invention also discloses a semiconductor package structure comprising: a substrate having a front surface and a back surface and having an opening penetrating through the substrate; the first wafer having an active surface and a back surface, wherein the active surface of the first wafer is oriented And overlying the opening via the first adhesive layer and attached to the back surface of the substrate by the first adhesive layer; the second wafer has an active surface and a back surface, wherein the back surface of the second wafer is opposite to the first wafer Covering the opening downward through the second adhesive layer, and attaching to the front surface of the substrate through the second adhesive layer; a third wafer having an active surface and a back surface, which are flipped down by a plurality of layers The first conductive elements are connected to the outwardly extending front surface of the substrate; the plurality of first conductive lines are electrically connected to the front surface of the first wafer and the substrate; and the plurality of second guides a wire for electrically connecting the active surface of the second wafer and the front surface of the substrate; the first package body for covering the first wafer, the first adhesive layer, the plurality of first wires, and a portion of the back surface of the substrate; a second package for covering the second wafer, the second adhesive layer, the plurality of second wires and a portion of the front surface of the substrate; and a plurality of second conductive members disposed on the back surface of the substrate.

本發明又揭露一種半導體封裝結構，包含：一基板，具有一正面及一背面，且具有一開口穿透過基板且於基板之一端設置有複數個導電端點；一第一晶片，具有一主動面及一背面，其中第一晶片之主動面係朝上，且經由第一黏著層覆蓋在開口上，並藉由第一黏著層貼附在基板之背面上；複數條第一導線，經由開口電性連接第一晶片及基板之正面；第二黏著層，用以包覆複數條第一導線及覆蓋在第一晶片之主動面上；一第二晶片，具有一主動面及一背面，第二晶片之背面係相對於第一晶片朝下且將主動面朝上，藉由第二黏著層貼附在基板之正面上；第三晶片，具有一主動面及一背面，係以覆晶方式朝下藉由複數個第一導電元件電性連接於基板之向外延伸之正面之複數個連接端點上；複數條第二導線，用以電性連接第二晶片之主動面及基板之正面；第一封裝體，用以包覆第一晶片、第一黏著層、複數條第一導線及基板之部份背面；第二封裝體，用以包覆第二晶片、第二黏著層、複數條第二導線及基板之部份正面；及複數個第二導電元件，設置在基板之背面上且部份第二導電元件係與基板上之複數個連接端點電性連接“The present invention further discloses a semiconductor package structure comprising: a substrate having a front surface and a back surface, and having an opening penetrating through the substrate and having a plurality of conductive terminals disposed at one end of the substrate; a first wafer having an active surface And a back surface, wherein the active surface of the first wafer is facing upward, and is covered on the opening via the first adhesive layer, and is attached to the back surface of the substrate by the first adhesive layer; the plurality of first wires are electrically connected via the opening The first adhesive layer is connected to the front surface of the first wafer and the substrate; the second adhesive layer is used to cover the plurality of first conductive lines and covers the active surface of the first wafer; and the second semiconductor has an active surface and a back surface, and second The back side of the wafer is directed downward with respect to the first wafer and faces upward, and is attached to the front surface of the substrate by a second adhesive layer; the third wafer has an active surface and a back surface, and is flipped The plurality of first conductive elements are electrically connected to the plurality of connection terminals of the outwardly extending front surface of the substrate; the plurality of second wires are electrically connected to the active surface of the second wafer and the front surface of the substrate; First a package body for covering a first wafer, a first adhesive layer, a plurality of first wires, and a portion of the back surface of the substrate; and a second package body for covering the second wafer, the second adhesive layer, and the plurality of second a portion of the front surface of the wire and the substrate; and a plurality of second conductive elements disposed on the back surface of the substrate and the second conductive element is electrically connected to the plurality of connection terminals on the substrate

有關本發明的特徵與實作，茲配合圖示作最佳實施例詳細說明如下。(為使對本發明的目的、構造、特徵、及其功能有進一步的瞭解，茲配合實施例詳細說明如下。)The features and implementations of the present invention are described in detail below with reference to the preferred embodiments. (In order to further understand the objects, structures, features, and functions of the present invention, the following detailed description will be given in conjunction with the embodiments.)

本發明在此所探討的方向為一種封裝結構及其封裝方法，係提供具有開口之基板，使得上、下晶片以覆晶方式朝向開口貼附在基板上，然後進 行封裝的方法。為了能徹底地瞭解本發明，將在下列的描述中提出詳盡的步驟及其組成。顯然地，本發明的施行並未限定晶片封裝的方式之技藝者所熟習的特殊細節。對於本發明的較佳實施例，則會詳細描述如下，然而除了這些詳細描述之外，本發明還可以廣泛地施行在其他的實施例中，且本發明的範圍不受限定，其以之後的專利範圍為準。The invention is directed to a package structure and a packaging method thereof, which provide a substrate having an opening such that the upper and lower wafers are attached to the substrate in a flip-chip manner toward the opening, and then into the substrate. The method of row encapsulation. In order to thoroughly understand the present invention, detailed steps and compositions thereof will be set forth in the following description. Obviously, the practice of the present invention does not define the specific details familiar to those skilled in the art of wafer packaging. The preferred embodiments of the present invention will be described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited, and The scope of the patent shall prevail.

請參考第2A圖至第2F圖係根據本發明所揭露之一種具有開口之基板之半導體封裝結構之各步驟示意圖。第2A圖係表示具有開口之基板之示意圖。在第2A圖中，其基板10具有正面及背面，且具有一開口12穿透過基板10之正面及背面，在此，基板10之材料可以是電路板或金屬薄板所組成之族群之中。另外，在本發明的實施例中，在基板10的正面及背面係以先設置不同的線路佈局(layout)(未在圖中表示)，以做為後續之電性連接各個元件使用，然而，在基板10之正面及背面之線路佈局並非為本發明之技術特徵，因此，在此不加以多加描述。Please refer to FIG. 2A to FIG. 2F for a schematic diagram of steps of a semiconductor package structure having an open substrate according to the present invention. Fig. 2A is a schematic view showing a substrate having an opening. In FIG. 2A, the substrate 10 has a front side and a back side, and has an opening 12 penetrating through the front and back sides of the substrate 10. Here, the material of the substrate 10 may be among the groups of circuit boards or metal sheets. In addition, in the embodiment of the present invention, different layouts (not shown) are disposed on the front and back sides of the substrate 10 for subsequent electrical connection of the respective components. The layout of the lines on the front and back sides of the substrate 10 is not a technical feature of the present invention, and therefore, it will not be described here.

接著，請參考第2B圖，係表示將第一晶片以覆晶方式形成在基板10之背面之示意圖。在第2B圖中，係提供一第一晶片30，且此第一晶片30A具有一主動面及背面，且於主動面的中心部份具有複數個焊墊31A。係將第一晶片30A的主動面朝上，且對準基板10之開口12，然後將第一晶片30A之主動面藉由第一黏著層20貼附在基板10之背面上並且覆蓋住開口12之一側。在此實施例中，第一黏著層20可以先形成在基板10之背面上，然後再將第一晶片30A之主動面朝向基板10之背面，並藉由第一黏著層20固著在基板10之背面。另外，在另一實施例中，第一黏著層20先形成在第一晶片30A之主動面上，同樣地，再將第一晶片30A之主動面朝上對準基板10之開口12處，然後將第一晶片30藉由第一黏著層20貼附並固著於基板10之背面上，且將第一晶片30A之焊墊31A曝露於基板10之開口12。在此，第一黏著層20之材料可以是二階段式熱固性膠材(B－stage)。Next, please refer to FIG. 2B, which is a schematic view showing the first wafer formed on the back surface of the substrate 10 in a flip chip manner. In FIG. 2B, a first wafer 30 is provided, and the first wafer 30A has an active surface and a back surface, and has a plurality of pads 31A at a central portion of the active surface. The active surface of the first wafer 30A is directed upward, and the opening 12 of the substrate 10 is aligned, and then the active surface of the first wafer 30A is attached to the back surface of the substrate 10 by the first adhesive layer 20 and covers the opening 12. One side. In this embodiment, the first adhesive layer 20 may be formed on the back surface of the substrate 10, and then the active surface of the first wafer 30A faces the back surface of the substrate 10, and is fixed on the substrate 10 by the first adhesive layer 20. The back. In addition, in another embodiment, the first adhesive layer 20 is first formed on the active surface of the first wafer 30A, and similarly, the active surface of the first wafer 30A is aligned upward with the opening 12 of the substrate 10, and then The first wafer 30 is attached and fixed on the back surface of the substrate 10 by the first adhesive layer 20, and the pad 31A of the first wafer 30A is exposed to the opening 12 of the substrate 10. Here, the material of the first adhesive layer 20 may be a two-stage thermosetting adhesive (B-stage).

接著，請參考第2C圖，係表示利用複數條導線電性連接第一晶片與基 板之示意圖。在第2C圖中，係利用逆打線接合(reverse wire bonding)的方式，將複數條第一導線40A分別形成在基板10之正面上所曝露出之複數個連接端點(未在圖中表示)及經由開口12形成在第一晶片30A之中心焊墊31A上，藉以電性連接基板10與第一晶片30A。Next, please refer to FIG. 2C, which shows that the first wafer and the base are electrically connected by using a plurality of wires. Schematic diagram of the board. In FIG. 2C, a plurality of first wires 40A are respectively formed on the front surface of the substrate 10 by reverse wire bonding (not shown in the figure). And formed on the center pad 31A of the first wafer 30A via the opening 12, thereby electrically connecting the substrate 10 and the first wafer 30A.

接著，請參考第2D圖係表示第二晶片形成在基板上之示意圖。在第2D圖中，係將FOW(film over wire)50形成以包覆住複數條第一導線40A，且同時將FOW 50密封住基板10之開口12、並覆蓋在第一晶片30A之主動面上及在基板10的部份正面上。緊接著，同樣參考第2D圖，係將第二晶片32A之主動面(未在圖中表示)朝上，藉由FOW 50固著在基板10上。接下來，係利用打線的方式(wiring bonding)將複數條第二導線40B的兩端分別形成在第二晶片30B的主動面之複數個焊墊31B上以及基板10之正面所曝露出之複數個連接端點(未在圖中表示)上，藉以電性連接第二晶片32及基板10。在此，第二晶片30B之焊墊31B係並非設置在第二晶片30B之中心位置，且第二晶片30B之功能及尺寸與第一晶片30A不同。Next, please refer to FIG. 2D for a schematic view showing that the second wafer is formed on the substrate. In FIG. 2D, FOW (film over wire) 50 is formed to cover a plurality of first wires 40A, and at the same time, FOW 50 is sealed to the opening 12 of the substrate 10 and covers the active surface of the first wafer 30A. It is on the front side of the substrate 10. Next, referring also to FIG. 2D, the active surface (not shown) of the second wafer 32A is directed upward, and is fixed to the substrate 10 by the FOW 50. Next, the two ends of the plurality of second wires 40B are respectively formed on the plurality of pads 31B of the active surface of the second wafer 30B and the plurality of exposed surfaces of the substrate 10 by means of wiring bonding. The terminal (not shown) is connected to electrically connect the second wafer 32 and the substrate 10. Here, the pad 31B of the second wafer 30B is not disposed at the center of the second wafer 30B, and the function and size of the second wafer 30B are different from those of the first wafer 30A.

接下來，請參考第2E圖，係表示形成封裝結構之示意圖。在第5圖中，係先將第一高分子材料(未在圖中表示)形成在第一晶片30A以及基板10之部份背面上，然後對第一高分子材料進行固化以形成第一封裝體60A以包覆住第一晶片30A及基板10之部份背面。同樣地，將第二高分子材料(未在圖中表示)形成在第二晶片30B、複數條第二導線40B以及基板10之部份正面上，然後對第二高分子材料進行固化以形成第二封裝體60B以包覆住第二晶片30B、複數條第二導線40B、部份FOW 50及基板10之部份正面。Next, please refer to FIG. 2E, which is a schematic view showing the formation of a package structure. In FIG. 5, a first polymer material (not shown) is formed on the first wafer 30A and a portion of the back surface of the substrate 10, and then the first polymer material is cured to form a first package. The body 60A covers the back surface of the first wafer 30A and the substrate 10. Similarly, a second polymer material (not shown) is formed on the front surface of the second wafer 30B, the plurality of second wires 40B, and the substrate 10, and then the second polymer material is cured to form a first The second package 60B covers the front surface of the second wafer 30B, the plurality of second wires 40B, the portion of the FOW 50, and the substrate 10.

接著，第2F圖係表示在基板之背面上形成複數個導電元件之示意圖。在第2F圖中，係將複數個導電元件70形成在基板10的背面上之複數個連接端點(未在圖中表示)，用以與其他外部之電子元件電性連接。在此，導電元件70可以是錫球(solder ball)。Next, FIG. 2F is a schematic view showing the formation of a plurality of conductive elements on the back surface of the substrate. In FIG. 2F, a plurality of conductive elements 70 are formed on a plurality of connection terminals (not shown) on the back surface of the substrate 10 for electrically connecting with other external electronic components. Here, the conductive element 70 may be a solder ball.

此外，第3A圖至第3B圖係為本發明所揭露之另一較佳實施例。在此， 第3A圖之形成步驟、材料及功能係與前述之第2A圖至第2E圖相同，在此不再多加描述。然而第3A圖與第2E圖之差異在於，在第3A圖中，基板10之至少向外延伸之一端之正面上係設置有一第三晶片30C，且以覆晶的方式並藉由複數個第二導電元件70B與基板10之正面上所曝露之複數個連接端點(未在圖中表示)電性連接。接著，請參考第3B圖，係將複數個第一導電元件70A形成在基板10之背面所曝露出之複數個連接端點(未在圖中表示)上，並與其電性連接。在此實施例中，可以先在基板10之背面形成複數個第一導電元件70A或者是先將第三晶片30C以覆晶方式並藉由第二複數個導電元件70B形成在基板10之正面上，因此，兩者形成在基板10上之先後順序並沒有加以限制。另外，值得一提的是，第三晶片30C之尺寸大小可以與第一晶片30A及第二晶片30B均不相同，亦或是與其中之一顆晶片(第一晶片30A或第二晶片30B)相同。In addition, FIGS. 3A to 3B are another preferred embodiment of the present invention. here, The formation steps, materials, and functions of Fig. 3A are the same as those of Figs. 2A to 2E described above, and will not be further described herein. However, the difference between FIG. 3A and FIG. 2E is that, in FIG. 3A, a third wafer 30C is disposed on the front surface of at least one of the outwardly extending ends of the substrate 10, and is in a flip chip manner and by a plurality of The two conductive elements 70B are electrically connected to a plurality of connection terminals (not shown) exposed on the front surface of the substrate 10. Next, referring to FIG. 3B, a plurality of first conductive elements 70A are formed on a plurality of connection terminals (not shown) exposed on the back surface of the substrate 10, and are electrically connected thereto. In this embodiment, a plurality of first conductive elements 70A may be formed on the back surface of the substrate 10 or the third wafer 30C may be flip-chip first and formed on the front surface of the substrate 10 by the second plurality of conductive elements 70B. Therefore, the order in which the two are formed on the substrate 10 is not limited. In addition, it is worth mentioning that the size of the third wafer 30C may be different from that of the first wafer 30A and the second wafer 30B, or may be one of the wafers (the first wafer 30A or the second wafer 30B). the same.

再者，第4A圖至第4B圖係為本發明所揭露之再一較佳實施例。在此，第4A圖之形成步驟、材料及功能係與前述之第2A圖至第2E圖相同，在此不再多加描述。然而第4A圖至第4B圖與先前之實施例之差異性在於，在第4A圖中，基板10之至少向外延伸之一端內設置有複數個連接端點80，此連接端點80可以是金手指(golden finger)結構，藉以電性連接其他電子元件。接著，係在基板10之向外延伸起設置有連接端點80之一端上設置一第三晶片30C，並且以覆晶的方式經由複數個第二導電元件70B與基板10之正面上所曝露之複數個連接端點80電性連接。接著，請參考第4B圖，係將複數個第一導電元件70A形成在基板10之背面所曝露出之複數個連接端點上，並與其電性連接。同樣的，在此實施例中，可以先在基板10之背面形成複數個第一導電元件70A或者是先將第三晶片30C以覆晶方式並藉由第二複數個導電元件70B形成在基板10之正面上，因此，兩者形成在基板10上之先後順序並沒有加以限制。另外，值得一提的是，第三晶片30C之尺寸大小可以與第一晶片30A及第二晶片30B均不相同，亦或是與其中 之一顆晶片(第一晶片30A或第二晶片30B)相同。在本實施例中，第一導電元件7０A及第二導電元件70B可以是錫球(solder ball)。Furthermore, FIGS. 4A to 4B are still further preferred embodiments of the present invention. Here, the forming steps, materials, and functions of FIG. 4A are the same as those of FIGS. 2A to 2E described above, and will not be further described herein. However, the difference between the 4A and 4B figures and the previous embodiment is that, in FIG. 4A, at least one of the connection ends 80 is provided in at least one of the outwardly extending ends of the substrate 10, and the connection end point 80 may be A golden finger structure that electrically connects other electronic components. Next, a third wafer 30C is disposed on one end of the substrate 10 extending outward from the connection terminal 80, and is exposed on the front surface of the substrate 10 via the plurality of second conductive elements 70B in a flip chip manner. A plurality of connection terminals 80 are electrically connected. Next, referring to FIG. 4B, a plurality of first conductive elements 70A are formed on a plurality of connection terminals exposed on the back surface of the substrate 10, and are electrically connected thereto. Similarly, in this embodiment, a plurality of first conductive elements 70A may be formed on the back surface of the substrate 10 or the third wafer 30C may be flip-chip first and formed on the substrate 10 by the second plurality of conductive elements 70B. On the front side, therefore, the order in which the two are formed on the substrate 10 is not limited. In addition, it is worth mentioning that the size of the third wafer 30C may be different from or different from the first wafer 30A and the second wafer 30B. One of the wafers (the first wafer 30A or the second wafer 30B) is the same. In this embodiment, the first conductive element 70A and the second conductive element 70B may be solder balls.

雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發明，任何熟習相像技藝者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，因此本發明之專利保護範圍須視本說明書所附之申請專利範圍所界定者為準。While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The patent protection scope of the invention is subject to the definition of the scope of the patent application attached to the specification.

10‧‧‧基板10‧‧‧Substrate

12‧‧‧開口12‧‧‧ openings

20‧‧‧第一黏著層20‧‧‧First adhesive layer

30A‧‧‧第一晶片30A‧‧‧First chip

31A‧‧‧焊墊31A‧‧‧ solder pads

30B‧‧‧第二晶片30B‧‧‧second chip

31B‧‧‧焊墊31B‧‧‧ solder pads

30C‧‧‧第三晶片30C‧‧‧ third chip

40A‧‧‧第一導線40A‧‧‧First wire

40B‧‧‧第二導線40B‧‧‧Second wire

50‧‧‧FOW(film over wire)50‧‧‧FOW(film over wire)

60A‧‧‧第一封裝體60A‧‧‧first package

60B‧‧‧第二封裝體60B‧‧‧Second package

70、70A、70B‧‧‧導電元件70, 70A, 70B‧‧‧ conductive elements

80‧‧‧連接端點80‧‧‧Connection endpoint

100‧‧‧基板100‧‧‧Substrate

102‧‧‧開口102‧‧‧ openings

120‧‧‧晶片120‧‧‧ wafer

122‧‧‧焊墊122‧‧‧ solder pads

130‧‧‧導線130‧‧‧Wire

140‧‧‧封裝體140‧‧‧Package

第1圖係根據習知之技術，表示具有開口之基板之封裝結構之示意圖；2A圖至第2F圖係根據本發明之技術，表示一種具有開口之基板之半導體封裝結構之各步驟示意圖；第3A圖至第3B圖係根據本發明之技術，表示另一具有開口之基板之半導體封裝結構之另一較佳實施例之各步驟示意圖；及第4A圖至第4B圖係根據本發明之技術，表示具有開口之基板之半導體封裝結構之再一較佳實施例之各步驟示意圖。1 is a schematic view showing a package structure of an open substrate according to a conventional technique; and FIGS. 2A to 2F are schematic views showing steps of a semiconductor package structure having an open substrate according to the technology of the present invention; FIG. 3B is a schematic diagram showing steps of another preferred embodiment of a semiconductor package structure having another substrate having an opening according to the technology of the present invention; and FIGS. 4A to 4B are diagrams according to the present invention. A schematic diagram showing the steps of a further preferred embodiment of a semiconductor package structure having an open substrate.

10‧‧‧基板10‧‧‧Substrate

20‧‧‧第一黏著層20‧‧‧First adhesive layer

30A‧‧‧第一晶片30A‧‧‧First chip

31A‧‧‧焊墊31A‧‧‧ solder pads

30B‧‧‧第二晶片30B‧‧‧second chip

31B‧‧‧焊墊31B‧‧‧ solder pads

40A‧‧‧第一導線40A‧‧‧First wire

40B‧‧‧第二導線40B‧‧‧Second wire

50‧‧‧FOW(film over wire)50‧‧‧FOW(film over wire)

60A‧‧‧第一封裝體60A‧‧‧first package

60B‧‧‧第二封裝體60B‧‧‧Second package

70‧‧‧導電元件70‧‧‧Conducting components

Claims (19)

一種半導體封裝結構，包含：一基板，具有一正面及一背面，且具有一開口穿透過該基板；一第一晶片，具有一主動面及一背面，且該主動面朝上且經由一第一黏著層覆蓋在該開口上並藉由該第一黏著層貼附在該基板之該背面上；複數條第一導線，經由開口電性連接該第一晶片及該基板之該正面；一第二黏著層，用以包覆該些第一導線及覆蓋在該第一晶片之該主動面上之該些焊墊且形成在該基板之部份正面上，其中該第二黏著層為FOW(film over wire)；一第二晶片，具有一主動面及一背面，該第二晶片之該背面係朝下藉由該第二黏著層貼附在該基板之該正面上；複數條第二導線，係用以電性連接該第二晶片之該主動面及該基板之該正面；一第一封裝體，係用以包覆該第一晶片、該第一黏著層、該些第一導線及部份該基板之該背面；一第二封裝體，係用以包覆該第二晶片、該第二黏著層、該些第二導線及部份該基板之該正面；及複數個導電元件，係設置在該基板之該背面上。 A semiconductor package structure comprising: a substrate having a front surface and a back surface and having an opening penetrating the substrate; a first wafer having an active surface and a back surface, wherein the active surface faces upward and passes through a first An adhesive layer covers the opening and is attached to the back surface of the substrate by the first adhesive layer; a plurality of first wires are electrically connected to the front surface of the first wafer and the substrate via the opening; An adhesive layer for covering the first wires and the pads covering the active surface of the first wafer and formed on a front surface of the substrate, wherein the second adhesive layer is FOW (film a second wafer having an active surface and a back surface, the back surface of the second wafer being attached downwardly on the front surface of the substrate by the second adhesive layer; a plurality of second wires, The first package is configured to electrically cover the active surface of the second wafer and the front surface of the substrate; the first package is configured to cover the first wafer, the first adhesive layer, the first wires and the portion The back side of the substrate; a second package is used The front surface of the second wafer, the second adhesive layer, the second conductive lines and a portion of the substrate are coated; and a plurality of conductive elements are disposed on the back surface of the substrate. 如申請專利範圍第1項所述之半導體封裝結構，其中該基板之材料係為電路板或金屬薄板。 The semiconductor package structure of claim 1, wherein the material of the substrate is a circuit board or a metal thin plate. 如申請專利範圍第1項所述之半導體封裝結構，其中該第一晶片及該第二晶片之尺寸大小不同。 The semiconductor package structure of claim 1, wherein the first wafer and the second wafer are different in size. 如申請專利範圍第1項所述之半導體封裝結構，其中該第一晶片之焊墊係為中心設置之焊墊。 The semiconductor package structure of claim 1, wherein the pads of the first wafer are centrally disposed pads. 如申請專利範圍第1項所述之半導體封裝結構，其中該第一黏著層為二階段熱固性膠(B-stage)。 The semiconductor package structure of claim 1, wherein the first adhesive layer is a two-stage thermosetting adhesive (B-stage). 如申請專利範圍第1項所述之半導體封裝結構，其中該些導電元件為錫球 (solder ball)。 The semiconductor package structure of claim 1, wherein the conductive elements are solder balls (solder ball). 一種半導體封裝結構，包含：一基板，具有一正面及一背面，且具有一開口穿透過該基板；一第一晶片，具有一主動面及一背面，其中該第一晶片之該主動面係朝上且經由一第一黏著層覆蓋在該開口上並藉由該第一黏著層貼附在該基板之該背面上；複數條第一導線，係用以電性連接該第一晶片及該基板之該正面；一第二黏著層，用以包覆該些第一導線及覆蓋在該第一晶片之該主動面上，其中該第二黏著層為FOW(tilm over wire)；一第二晶片，具有一主動面及一背面，該第二晶片之該背面係相對於該第一晶片朝下且將該主動面朝上，藉由該第二黏著層貼附在該基板之該正面上；複數條第二導線，係用以電性連接該第二晶片之該主動面及該基板之該正面；一第一封裝體，係用以包覆該第一晶片、該第一黏著層、該些第一導線及部份該基板之該背面；一第二封裝體，係用以包覆該第二晶片、該第二黏著層、該些第二導線及部份該基板之該正面；複數個第二導電元件，係設置在該基板之該背面上；及一第三晶片，具有一主動面及一背面，係以覆晶方式朝下藉由複數個第一導電元件連接該基板之向外延伸之該正面上。 A semiconductor package structure comprising: a substrate having a front surface and a back surface and having an opening penetrating the substrate; a first wafer having an active surface and a back surface, wherein the active surface of the first wafer is oriented And overlying the opening via a first adhesive layer and attached to the back surface of the substrate by the first adhesive layer; the plurality of first wires are electrically connected to the first wafer and the substrate a second adhesive layer for covering the first wires and covering the active surface of the first wafer, wherein the second adhesive layer is FOW (tilm over wire); a second wafer Having an active surface and a back surface, the back surface of the second wafer is downward with respect to the first wafer and the active surface is facing upward, and the second adhesive layer is attached to the front surface of the substrate; a plurality of second wires for electrically connecting the active surface of the second wafer and the front surface of the substrate; a first package for covering the first wafer, the first adhesive layer, the a first wire and a portion of the back surface of the substrate; a second seal The mounting body is configured to cover the second wafer, the second adhesive layer, the second conductive lines and a portion of the front surface of the substrate; a plurality of second conductive elements are disposed on the back surface of the substrate; And a third wafer having an active surface and a back surface, which are connected to the front surface of the substrate extending outward by a plurality of first conductive elements in a flip chip manner. 如申請專利範圍第7項所述之半導體封裝結構，其中該基板之材料係為電路板或金屬薄板。 The semiconductor package structure of claim 7, wherein the material of the substrate is a circuit board or a metal thin plate. 如申請專利範圍第7項所述之半導體封裝結構，其中該第一晶片、該第二晶片及該第三晶片之尺寸大小不同。 The semiconductor package structure of claim 7, wherein the first wafer, the second wafer, and the third wafer are different in size. 如申請專利範圍第7項所述之半導體封裝結構，其中該第一晶片之焊墊係為中心設置之焊墊。 The semiconductor package structure of claim 7, wherein the pad of the first wafer is a centrally disposed pad. 如申請專利範圍第7項所述之半導體封裝結構，其中該第一黏著層為二階段熱固性膠(B-stage)。 The semiconductor package structure of claim 7, wherein the first adhesive layer is a two-stage thermosetting adhesive (B-stage). 如申請專利範圍第7項所述之半導體封裝結構，其中該些第一導電元件及該些第二導電元件為錫球(solder ball)。 The semiconductor package structure of claim 7, wherein the first conductive elements and the second conductive elements are solder balls. 一種半導體封裝結構，包含：一基板，具有一正面及一背面，且具有一開口穿透過該基板且於該基板之一端設置有複數個連接端點；一第一晶片，具有一主動面及一背面，其中該第一晶片之該主動面係朝上且經由一第一黏著層覆蓋在該開口上並藉由該第一黏著層貼附在該基板之該背面上；複數條第一導線，係用以電性連接該第一晶片及該基板之該正面；一第二黏著層，用以包覆該些第一導線及覆蓋在該第一晶片之該主動面上，其中該第二黏著層為FOW(film over wire)：一第二晶片，具有一主動面及一背面，其中該第二晶片之該背面係相對於該第一晶片朝下經由該第二黏著層覆蓋在該開口上，並藉由該第二黏著層貼附在該基板之該正面上；複數條第二導線，係用以電性連接該第二晶片之該主動面及該基板之該正面；一第一封裝體，係用以包覆該第一晶片、該第一黏著層、該些第一導線及部份該基板之該背面；一第二封裝體，係用以包覆該第二晶片、該第二黏著層、該些第二導線及部份該基板之該正面；一第三晶片，具有一主動面及一背面，係以覆晶方式朝下藉由複數個第一導電元件電性連接於該基板之向外延伸之該正面之該些連接端點上；及複數個第二導電元件，係設置在該基板之該背面上且部份該些第二導電元件係與在該基板之該背面上之該些連接端點電性連接。 A semiconductor package structure comprising: a substrate having a front surface and a back surface, and having an opening penetrating the substrate and having a plurality of connection terminals disposed at one end of the substrate; a first wafer having an active surface and a substrate a back surface, wherein the active surface of the first wafer is facing upward and over the opening via a first adhesive layer and attached to the back surface of the substrate by the first adhesive layer; a plurality of first wires, The second adhesive layer is used to electrically connect the first wafer and the front surface of the substrate; a second adhesive layer is used to cover the first conductive lines and cover the active surface of the first wafer, wherein the second adhesive layer The layer is a FOW (film over wire): a second wafer having an active surface and a back surface, wherein the back surface of the second wafer is covered on the opening via the second adhesive layer with respect to the first wafer facing downward And attaching the second adhesive layer to the front surface of the substrate; the plurality of second wires are electrically connected to the active surface of the second wafer and the front surface of the substrate; a first package a body for coating the first wafer, The first adhesive layer, the first conductive lines and a portion of the back surface of the substrate; a second package for covering the second wafer, the second adhesive layer, the second conductive lines and portions a front surface of the substrate; a third wafer having an active surface and a back surface, wherein the front surface of the substrate is electrically connected to the front surface of the substrate by a plurality of first conductive elements And a plurality of second conductive elements disposed on the back surface of the substrate and a portion of the second conductive elements are electrically connected to the connection terminals on the back surface of the substrate. 如申請專利範圍第13項所述之半導體封裝結構，其中該基板之材料係為電路板或金屬薄板。 The semiconductor package structure of claim 13, wherein the material of the substrate is a circuit board or a metal thin plate. 如申請專利範圍第13項所述之半導體封裝結構，其中該基板之該些連接端點為金手指。 The semiconductor package structure of claim 13, wherein the connection terminals of the substrate are gold fingers. 如申請專利範圍第13項所述之半導體封裝結構，其中該第一晶片、該第二晶片及該第三晶片之尺寸大小不同。 The semiconductor package structure of claim 13, wherein the first wafer, the second wafer, and the third wafer are different in size. 如申請專利範圍第13項所述之半導體封裝結構，其中該第一晶片之焊墊係為中心設置之焊墊。 The semiconductor package structure of claim 13, wherein the pad of the first wafer is a centrally disposed pad. 如申請專利範圍第13項所述之半導體封裝結構，其中該第一黏著層為二階段熱固性膠(B-stage)。 The semiconductor package structure of claim 13, wherein the first adhesive layer is a two-stage thermosetting adhesive (B-stage). 如申請專利範圍第13項所述之半導體封裝結構，其中該些第一導電元件及該些第二導電元件為錫球(solder ball)。The semiconductor package structure of claim 13, wherein the first conductive elements and the second conductive elements are solder balls.
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW488045B (en) * 2001-04-12 2002-05-21 Siliconware Precision Industries Co Ltd Semiconductor package with dislocated multi-chips
TW554502B (en) * 2002-08-21 2003-09-21 Ultratera Corp Stacked integrated circuit die packaging
TW567601B (en) * 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TW200709378A (en) * 2005-08-31 2007-03-01 Chipmos Technologies Inc Chip package structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW488045B (en) * 2001-04-12 2002-05-21 Siliconware Precision Industries Co Ltd Semiconductor package with dislocated multi-chips
TW554502B (en) * 2002-08-21 2003-09-21 Ultratera Corp Stacked integrated circuit die packaging
TW567601B (en) * 2002-10-18 2003-12-21 Siliconware Precision Industries Co Ltd Module device of stacked semiconductor package and method for fabricating the same
TW200709378A (en) * 2005-08-31 2007-03-01 Chipmos Technologies Inc Chip package structure

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