TWI392093B - Mosfet device and method for making the same - Google Patents
Mosfet device and method for making the same Download PDFInfo
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本發明係關於一種半導體裝置及其製造方法，詳言之，係關於一種金屬氧化物半導體裝置及其製造方法。The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a metal oxide semiconductor device and a method of fabricating the same.
隨著目前元件尺寸的日益縮小，電晶體已進入奈米的世代(小於100奈米)，但是，隨著元件的微縮化，許多不良的因素也一一的浮現，因此對於在有限的晶圓空間內，如何達到更高的電晶體數目及單一快閃記憶體元件具有更多位元的電性表現，以及在微縮的尺寸下如何維持應有的電性特性，甚至獲得更好的特性，就成為了共同努力的方向。With the current shrinking component size, the transistor has entered the nano generation (less than 100 nm), but with the miniaturization of components, many undesirable factors have emerged one by one, so for a limited number of wafers How to achieve a higher number of transistors in a space and a single flash memory component with more bits of electrical performance, and how to maintain the electrical properties under the miniature size, and even get better characteristics, It has become the direction of joint efforts.
元件及晶片面積縮小是必然的趨勢，而傳統元件需要有夠淺的接面深度以防止貫穿效應(punch through effects)，及夠低的串接電阻以提高驅動電流。然而，縮小的元件所造成的短通道效應(short-channel effects，SCEs)也是需要克服的。Component and wafer area reductions are an inevitable trend, while conventional components need to have shallow junction depths to prevent punch through effects, and low enough series resistance to increase drive current. However, the short-channel effects (SCEs) caused by the reduced components also need to be overcome.
在文獻中有利用超薄本體(ultrathin body，UTB)的架構，其揭示因元件的微縮，短通道效應越來越嚴重，藉由UTB可以提升元件的性能及閘極控制空乏區的能力，同時也降低了漏電流。另外，UTB也可以克服浮體效應(Floating-Body Effects，FBEs)。In the literature, there is an architecture that utilizes an ultrathin body (UTB), which reveals that the short channel effect is becoming more and more serious due to the miniaturization of components. UTB can improve the performance of the component and the ability of the gate to control the depletion region. It also reduces leakage current. In addition, UTB can also overcome Floating-Body Effects (FBEs).
在文獻中亦有利用兩層邊襯(spacer)的架構，即閘極外面第一層是氮化層(nitride)邊襯，第二層是氧化層(oxide)邊襯，兩層邊襯的高度差會影響到元件的性能。其中，第二層的氧化層邊襯是用來降低離子佈植所造成的通道直通(Channeling)效應。習知技術亦有揭示增加邊襯的厚度，可以降低米勒電容效應，可是同時也增加了源汲極的寄生串接阻抗。There are also two layers of spacers in the literature, that is, the first layer on the outside of the gate is a nitride liner, the second layer is an oxide liner, and the two layers are lined. The height difference affects the performance of the component. Among them, the second layer of oxide layer lining is used to reduce the channeling effect caused by ion implantation. Conventional techniques have also revealed that increasing the thickness of the edge liner can reduce the Miller capacitance effect, but also increases the parasitic series impedance of the source drain.
因此，有必要提供一種創新且具進步性的金屬氧化物半導體裝置及其製造方法，以解決上述問題。Therefore, it is necessary to provide an innovative and progressive metal oxide semiconductor device and a method of manufacturing the same to solve the above problems.
本發明提供一種金屬氧化物半導體裝置，包括：一基板及一閘極單元。該基板具有一矽層及一第一氧化層，該矽層形成於該第一氧化層上，該矽層具有一主動區，該主動區包括一第一區域及一第二區域，該第一區域定義為一通道，該第二區域具有複數個延伸部，該等延伸部具有至少一源極及至少一汲極，該通道、該源極及該汲極可不沿同一直線排列。該閘極單元包括：一閘極氧化層及一閘極層。該閘極氧化層覆蓋該通道。該閘極層覆蓋該閘極氧化層。The invention provides a metal oxide semiconductor device comprising: a substrate and a gate unit. The substrate has a germanium layer and a first oxide layer. The germanium layer is formed on the first oxide layer. The germanium layer has an active region. The active region includes a first region and a second region. The area is defined as a channel, and the second area has a plurality of extensions having at least one source and at least one drain, and the channel, the source and the drain may not be aligned along the same line. The gate unit includes a gate oxide layer and a gate layer. The gate oxide layer covers the channel. The gate layer covers the gate oxide layer.
本發明另提供一種金屬氧化物半導體裝置之製造方法，包括以下步驟：(a)提供一基板，該基板具有一矽層及一第一氧化層，該矽層形成於該第一氧化層上；(b)移除部分該矽層，以形成一主動區，該主動區包括一第一區域及一第二區域，該第一區域定義為一通道，該第二區域具有複數個延伸部；(c)形成一閘極單元以覆蓋該通道；(d)形成一第二氧化層以覆蓋該主動區及該閘極單元；及(e)進行一離子佈植步驟，以於該等延伸部形成至少一源極及至少一汲極，其中該通道、該源極及該汲極可不沿同一直線排列。The present invention further provides a method for fabricating a metal oxide semiconductor device, comprising the steps of: (a) providing a substrate having a germanium layer and a first oxide layer, the germanium layer being formed on the first oxide layer; (b) removing a portion of the layer to form an active region, the active region comprising a first region and a second region, the first region being defined as a channel, the second region having a plurality of extensions; c) forming a gate unit to cover the channel; (d) forming a second oxide layer to cover the active region and the gate unit; and (e) performing an ion implantation step to form the extensions At least one source and at least one drain, wherein the channel, the source, and the drain are not aligned along the same line.
本發明之金屬氧化物半導體裝置之源極/汲極數(電極數)可根據需求利用不同光罩圖形定義而得，其中通道、源極及汲極可不沿同一直線排列，其具有彎曲的電流流向，故通道所受到的汲極引發能障衰退效應較小。並且，因電極數較多，故可提高元件積集密度及系統設計的彈性，且可使其應用的單一快閃記憶體元件具有更多位元的電性表現，且可增加元件本身轉導及降低汲極引發能障衰退效應，電流也因此提升，故在電性方面具有優異的表現。再者，因為本發明之源極及汲極可配合覆蓋式或對準式閘極以完全自我對準方式形成，所以製程簡單、製程時間短且製造成本低，適合於三維(3D)積體電路。The source/drain number (number of electrodes) of the metal oxide semiconductor device of the present invention can be defined by using different mask patterns according to requirements, wherein the channel, the source and the drain are not arranged in the same straight line, and have a curved current. The flow direction, so the bungee induced by the channel causes less energy degradation effect. Moreover, since the number of electrodes is large, the component collection density and the flexibility of the system design can be improved, and the single flash memory component to be applied can have more bits of electrical performance, and the component itself can be transduced. And the reduction of the bungee triggers the energy-degradation effect, and the current is also improved, so it has excellent performance in terms of electrical properties. Furthermore, since the source and the drain of the present invention can be formed in a completely self-aligned manner with the overlay or alignment gate, the process is simple, the process time is short, and the manufacturing cost is low, and is suitable for three-dimensional (3D) integration. Circuit.
參考圖1至圖11，其顯示本發明金屬氧化物半導體裝置之製造方法。配合參考圖1及圖2，首先提供一基板100，該基板100具有一底層10、一矽層11及一第一氧化層12，該第一氧化層12形成於該底層10上，該矽層11形成於該第一氧化層12上。其中，該底層10可為矽(Si)層，該基板100係可為矽覆絕緣(SOI)基板、玻璃基板、塑膠基版或塊材(BULK)基板。Referring to Figures 1 through 11, there is shown a method of fabricating a metal oxide semiconductor device of the present invention. Referring to FIG. 1 and FIG. 2, a substrate 100 is provided. The substrate 100 has a bottom layer 10, a germanium layer 11 and a first oxide layer 12. The first oxide layer 12 is formed on the bottom layer 10. 11 is formed on the first oxide layer 12. The bottom layer 10 may be a bismuth (Si) layer, and the substrate 100 may be a silicon-on-insulator (SOI) substrate, a glass substrate, a plastic base or a bulk (BULK) substrate.
接著，移除部分該矽層11，以形成一主動區111。其中，本發明係以微影技術移除部分該矽層11。該主動區111包括一第一區域112及一第二區域113，該第一區域112定義為一通道(以下該通道之元件符號同該第一區域)，該第二區域113具有複數個延伸部114。在本實施例中，該通道112位於該主動區111之中央區域，該等延伸部114則分佈於該通道112周圍，使得該主動區111實質上呈T形。Then, a portion of the germanium layer 11 is removed to form an active region 111. Among them, the present invention removes a portion of the germanium layer 11 by lithography. The active area 111 includes a first area 112 and a second area 113. The first area 112 is defined as a channel (the element symbol of the channel is the same as the first area), and the second area 113 has a plurality of extensions. 114. In this embodiment, the channel 112 is located in a central region of the active region 111, and the extensions 114 are distributed around the channel 112 such that the active region 111 is substantially T-shaped.
要強調的是，根據不同需求及應用使用特定形狀之光罩，則所形成之該主動區111實質上可呈L形(如圖3所示)、十字形(如圖4所示)、梳形(如圖5所示)、齒輪形(如圖6所示)等，但不限於上述該等形狀，且該等延伸部114可對稱或不對稱地分佈於該通道112周圍。It should be emphasized that, according to different needs and applications, a photomask of a specific shape is used, and the active region 111 formed can be substantially L-shaped (as shown in FIG. 3), cross-shaped (as shown in FIG. 4), and combed. The shape (as shown in FIG. 5), the gear shape (as shown in FIG. 6), and the like, but not limited to the above-described shapes, and the extensions 114 may be symmetrically or asymmetrically distributed around the passage 112.
配合參考圖2及圖7，地毯式形成一閘極氧化層131以覆蓋該主動區111及該第一氧化層12。參考圖8，地毯式形成一閘極層132以覆蓋該閘極氧化層131。配合參考圖2及圖9，移除部分該閘極氧化層131及部分該閘極層132。在本實施例中係利用微影技術移除部分該閘極氧化層131及部分該閘極層132，以形成一閘極單元13。其中，在本實施例中未移除之該閘極氧化層131及該閘極層132覆蓋該通道112之頂面且覆蓋部分該等延伸部114。Referring to FIG. 2 and FIG. 7, a gate oxide layer 131 is formed on the carpet to cover the active region 111 and the first oxide layer 12. Referring to FIG. 8, a gate layer 132 is formed in a carpet pattern to cover the gate oxide layer 131. Referring to FIG. 2 and FIG. 9, a portion of the gate oxide layer 131 and a portion of the gate layer 132 are removed. In this embodiment, a portion of the gate oxide layer 131 and a portion of the gate layer 132 are removed by lithography to form a gate unit 13. The gate oxide layer 131 and the gate layer 132 that are not removed in this embodiment cover the top surface of the channel 112 and cover portions of the extensions 114.
參考圖10，要注意的是，若移除部分該閘極氧化層131及部分該閘極層132之步驟中，係使用寬度等於該通道112寬度之光罩，則未移除之該閘極氧化層131及該閘極層132是對準地形成於該通道112上，而不覆蓋該等延伸部114。Referring to FIG. 10, it is noted that if a portion of the gate oxide layer 131 and a portion of the gate layer 132 are removed, a mask having a width equal to the width of the channel 112 is used, and the gate is not removed. The oxide layer 131 and the gate layer 132 are formed in alignment on the channel 112 without covering the extensions 114.
配合參考圖9、圖11及圖12，形成一第二氧化層14以覆蓋該主動區111及該閘極單元13，其中，圖12係顯示將該主動區111、該等延伸部114及該閘極單元13上方相對位置之該第二氧化層14撥除之示意圖，以更清楚描述及說明本發明金屬氧化物半導體裝置1(即金屬氧化物半導體電晶體，MOSFET)之內部結構。Referring to FIG. 9 , FIG. 11 and FIG. 12 , a second oxide layer 14 is formed to cover the active region 111 and the gate unit 13 , wherein FIG. 12 shows the active region 111 , the extension portions 114 , and the like A schematic diagram of the second oxide layer 14 at a relative position above the gate unit 13 is omitted to more clearly describe and explain the internal structure of the metal oxide semiconductor device 1 (i.e., metal oxide semiconductor transistor, MOSFET) of the present invention.
在本實施例中，其係以沉積方法形成該第二氧化層14(圖11)。接著，以該第二氧化層14做為離子佈植時之散射層，進行一離子佈植步驟，以於該等延伸部114形成至少一源極115及至少一汲極116(圖12)，其中，該通道112、該源極115及該汲極116係可不沿同一直線排列。在本實施例中，係於該等延伸部114形成一源極115及二汲極116，其中該源極115位於T形之縱向底端，該等汲極116位於T形之橫向二側端。在其他應用中，亦可於該等延伸部114形成二源極及一汲極，而該汲極位於T形之縱向底端，該等源極位於T形之橫向二側端。要注意的是，該主動區111亦可為其他形狀(如圖3至圖6)，該等延伸部114可形成有一個或複數個源極及一個或複數個汲極，且源極及汲極之位置可自由排列設置。In the present embodiment, the second oxide layer 14 is formed by a deposition method (Fig. 11). Next, the second oxide layer 14 is used as a scattering layer for ion implantation, and an ion implantation step is performed to form at least one source 115 and at least one drain 116 (FIG. 12) in the extensions 114. The channel 112, the source 115, and the drain 116 may not be aligned along the same line. In this embodiment, a source 115 and a second drain 116 are formed in the extensions 114. The source 115 is located at the longitudinal bottom end of the T-shape, and the drains 116 are located at the lateral sides of the T-shape. . In other applications, the two sources and one of the drains may be formed in the extensions 114, and the drains are located at the longitudinal bottom ends of the T-shapes, and the sources are located at the lateral two ends of the T-shape. It should be noted that the active area 111 may also have other shapes (such as FIG. 3 to FIG. 6). The extensions 114 may be formed with one or more sources and one or more plurality of drains, and the source and the cathode. The position of the poles can be arranged freely.
再配合參考圖2、圖9、圖11及圖12，本發明之金屬氧化物半導體裝置1包括：一基板100、一閘極單元13及一第二氧化層14。其中，該基板100可為矽覆絕緣(SOI)基板、玻璃基板或塊材(BULK)基板。該基板100具有一底層10、一矽層11及一第一氧化層12，其中該底層10可為矽(Si)層。該第一氧化層12形成於該底層10上，該矽層11形成於該第一氧化層12上，該矽層11具有一主動區111，該主動區111包括一第一區域112及一第二區域113。在本實施例中，該第一區域112定義為一通道(以下該通道之元件符號同該第一區域)，該第二區域113具有複數個延伸部114，該等延伸部114具有至少一源極115及二汲極116，其中，該通道112、該源極115及該等汲極116可不沿同一直線排列。在本實施例中，該通道112位於該主動區111之中央區域，該等延伸部114則分佈於該通道112周圍，使得該主動區111實質上呈T形。2, 9, 11, and 12, the MOS device 1 of the present invention includes a substrate 100, a gate unit 13, and a second oxide layer 14. The substrate 100 may be a silicon-on-insulator (SOI) substrate, a glass substrate or a bulk (BULK) substrate. The substrate 100 has a bottom layer 10, a germanium layer 11 and a first oxide layer 12, wherein the bottom layer 10 can be a germanium (Si) layer. The first oxide layer 12 is formed on the bottom layer 10. The germanium layer 11 is formed on the first oxide layer 12. The germanium layer 11 has an active region 111. The active region 111 includes a first region 112 and a first layer. Two areas 113. In this embodiment, the first region 112 is defined as a channel (the component symbol of the channel is the same as the first region), and the second region 113 has a plurality of extensions 114, and the extensions 114 have at least one source. The pole 115 and the second drain 116, wherein the channel 112, the source 115 and the drains 116 may not be aligned along the same line. In this embodiment, the channel 112 is located in a central region of the active region 111, and the extensions 114 are distributed around the channel 112 such that the active region 111 is substantially T-shaped.
要強調的是，該主動區111亦可實質上呈L形(如圖3所示)、十字形(如圖4所示)、梳形(如圖5所示)、齒輪形(如圖6所示)等，但不限於上述該等形狀，且該等延伸部114可具有一源極及複數個汲極、一汲極及複數個源極，或複數個汲極及複數個源極，另外，該等延伸部114可對稱或不對稱地分佈於該通道周圍，而源極及汲極之位置可自由排列設置。It should be emphasized that the active area 111 can also be substantially L-shaped (as shown in FIG. 3), cross-shaped (as shown in FIG. 4), comb-shaped (as shown in FIG. 5), and gear-shaped (FIG. 6). And the like, but not limited to the above shapes, and the extensions 114 may have a source and a plurality of drains, a drain and a plurality of sources, or a plurality of drains and a plurality of sources. In addition, the extensions 114 may be symmetrically or asymmetrically distributed around the channel, and the positions of the source and the drain may be arranged freely.
在本實施例中，該閘極單元13包括一閘極氧化層131及一閘極層132。該閘極氧化層131覆蓋該通道112之頂面且覆蓋該源極115與該等汲極116間之部分延伸部114。較佳地，該閘極氧化層131係為二氧化矽(SiO2 )，亦可為現今選用之各種高介電係數(High K)絕緣材質。In the embodiment, the gate unit 13 includes a gate oxide layer 131 and a gate layer 132. The gate oxide layer 131 covers the top surface of the via 112 and covers a portion of the extension 114 between the source 115 and the drains 116. Preferably, the gate oxide layer 131 is cerium oxide (SiO 2 ), and may also be various high dielectric constant (High K) insulating materials selected today.
要注意的是，在其他應用中該閘極氧化層131亦可對準地形成於該通道112上，而不覆蓋該等延伸部114側面(如圖10所示)。上述僅係以T形主動區為例說明，可以理解的是，閘極氧化層是形成於各種形狀之主動區(如圖3至圖6)上。It is noted that in other applications the gate oxide layer 131 can also be formed in alignment on the via 112 without covering the sides of the extensions 114 (as shown in FIG. 10). The above description is only taking the T-shaped active region as an example. It can be understood that the gate oxide layer is formed on active regions of various shapes (as shown in FIGS. 3 to 6).
該閘極層132覆蓋該閘極氧化層131。其中，該閘極層132可為多晶矽閘極、金屬閘極或當今使用之任何閘極層。在本實施例中，除該通道112上方相對位置之該閘極單元13之外，由於該源極115與該等汲極116間之該等延伸部114側面具有該閘極氧化層131及該閘極層132，其可視為另外二閘極單元，因此就本實施例之金屬氧化物半導體裝置1而言，其共具有三個閘極單元，藉此可提升該源極115與該等汲極116間之電流驅動力。The gate layer 132 covers the gate oxide layer 131. The gate layer 132 can be a polysilicon gate, a metal gate, or any gate layer used today. In this embodiment, in addition to the gate unit 13 at the relative position above the channel 112, the gate oxide layer 131 and the side of the extension portion 114 between the source 115 and the drain 116 are The gate layer 132, which can be regarded as the other two gate units, has a total of three gate units for the MOS device 1 of the present embodiment, whereby the source 115 and the NMOS can be raised. The current driving force between poles 116.
在本實施例中，該第二氧化層14係地毯式的覆蓋在該主動區111、該閘極單元13及該第一氧化層上(如圖11所示)，其在此是做為離子佈植時之散射層。較佳地，該第二氧化層14係為二氧化矽。In this embodiment, the second oxide layer 14 is carpet-covered on the active region 111, the gate unit 13 and the first oxide layer (as shown in FIG. 11), which is herein used as an ion. Scattering layer when implanted. Preferably, the second oxide layer 14 is cerium oxide.
圖13至圖16為習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之比較結果。其中，本發明具多源極之金屬氧化物半導體裝置中之等效通道長度(Lg)係定義為每一源極與通道接面寬度之中間位置至最接近之汲極側邊之距離；本發明具多汲極之金屬氧化物半導體裝置之等效通道長度係定義為每一汲極與通道接面寬度之中間位置至最接近之源極側邊之距離。13 to 16 show the results of comparison between a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. The equivalent channel length (Lg) in the multi-source metal-oxide-semiconductor device of the present invention is defined as the distance from the middle of each source-to-channel junction width to the closest drain side; The equivalent channel length of the inventive multi-drain metal oxide semiconductor device is defined as the distance from the middle of each of the drains to the closest source side.
圖13顯示習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之導通電流-漏電流關係圖。其中，曲線L131、L132及L133分別表示習知金屬氧化物半導體裝置、本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置，在汲極偏壓為1.0V時之導通電流-漏電流關係曲線。如圖13所示，在相同汲極偏壓下，本發明具多源極或多汲極之金屬氧化物半導體裝置具有較高之導通電流及較低之漏電流，故具有較佳之性能表現。Figure 13 is a graph showing the conduction current-drain current relationship between a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. Wherein, the curves L131, L132, and L133 respectively represent a conventional metal oxide semiconductor device, a multi-source metal oxide semiconductor device of the present invention, and a multi-drain metal oxide semiconductor device of the present invention, wherein the drain bias is The on-current-leakage current curve at 1.0V. As shown in FIG. 13, under the same threshold voltage, the multi-source or multi-drain metal oxide semiconductor device of the present invention has a higher on-current and a lower leakage current, so that it has better performance.
圖14顯示習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之等效通道長度-門檻電壓關係圖。其中，曲線L141、L142及L143分別表示習知金屬氧化物半導體裝置、本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置，在汲極偏壓為0.05V時之等效通道長度-門檻電壓關係曲線。如圖14所示，本發明具多源極或多汲極之金屬氧化物半導體裝置具有較小之門檻電壓偏離現象(roll-off phenomenon)。其中，在極小之汲極偏壓下，門檻電壓偏離現象小至可被忽略。Figure 14 is a graph showing the equivalent channel length-threshold voltage of a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. Wherein, the curves L141, L142, and L143 respectively represent a conventional metal oxide semiconductor device, the multi-source metal oxide semiconductor device of the present invention, and the multi-drain metal oxide semiconductor device of the present invention, wherein the drain bias is Equivalent channel length at 0.05V - threshold voltage curve. As shown in FIG. 14, the multi-source or multi-drain metal oxide semiconductor device of the present invention has a small threshold voltage roll-off phenomenon. Among them, under the extremely small buckling bias, the threshold voltage deviation phenomenon is small enough to be ignored.
圖15為一習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之等效通道長度-汲極引發能障衰退效應(DIBL)關係圖。其中，曲線L151、L152及L153分別表示習知金屬氧化物半導體裝置、本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置，在汲極偏壓為0.05V及1.0V時所計算得之等效通道長度-汲極引發能障衰退效應(DIBL)關係曲線。如圖15所示，在相同汲極偏壓下，本發明具多源極之金屬氧化物半導體裝置具有最佳之汲極引發能障衰退效應；而本發明具多汲極之金屬氧化物半導體裝置之汲極引發能障衰退效應較大(僅小幅大於習知金屬氧化物半導體裝置之汲極引發能障衰退效應)，其係因為該等汲極電場跨越至通道區域所致。15 is an equivalent channel length-drain-induced energy-degradation effect of a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. (DIBL) diagram. Wherein, the curves L151, L152, and L153 respectively represent a conventional metal oxide semiconductor device, the multi-source metal oxide semiconductor device of the present invention, and the multi-drain metal oxide semiconductor device of the present invention, wherein the drain bias is The equivalent channel length calculated at 0.05V and 1.0V - the dipole induced energy barrier decay effect (DIBL) curve. As shown in FIG. 15, the multi-source metal-oxide-semiconductor device of the present invention has an optimum buckling-inducing energy-reducing effect under the same gate bias voltage; and the multi-drain metal oxide semiconductor of the present invention The buckling of the device induces a large effect of the energy barrier degradation (only slightly larger than the buckling effect of the conventional metal oxide semiconductor device), which is caused by the electric field crossing the channel region.
圖16顯示習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之等效通道長度-次臨界擺幅(subthreshold swing)關係圖。其中，曲線L161、L162及L163分別表示習知金屬氧化物半導體裝置、本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置，在汲極偏壓為1.0V時之等效通道長度-次臨界擺幅關係曲線。如圖16所示，在相同汲極偏壓下，本發明具多源極或多汲極之金屬氧化物半導體裝置同樣具有極低之次臨界擺幅，且可同時改善短通道效應(Short-Channel Effects，SCEs)。16 shows an equivalent channel length-subthreshold swing of a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. relation chart. Wherein, the curves L161, L162, and L163 respectively represent a conventional metal oxide semiconductor device, the multi-source metal oxide semiconductor device of the present invention, and the multi-drain metal oxide semiconductor device of the present invention, wherein the drain bias is Equivalent channel length-sub-threshold swing relationship curve at 1.0V. As shown in FIG. 16, the multi-source or multi-drain metal oxide semiconductor device of the present invention also has a very low sub-threshold swing under the same gate bias, and can simultaneously improve the short channel effect (Short- Channel Effects, SCEs).
本發明之金屬氧化物半導體裝置之源極/汲極數(電極數)，可根據需求利用不同光罩圖形定義而得。其中通道、源極及汲極不像傳統鰭式金屬氧化物半導體電晶體(FINEFT)存在同一平面(即可不沿同一直線排列)，其具有彎曲的電流流向，即，不僅只有單一流向，所以通道所受到的汲極引發能障衰退效應較傳統金屬氧化物半導體電晶體小，並且，因電極數較多，故可提高元件積集密度及系統設計的彈性，且可使其應用的單一快閃記憶體元件具有更多位元的電性表現，且可增加元件本身轉導，電流也因此提升。此外，因為本發明之源極及汲極可配合覆蓋式或對準式閘極以完全自我對齊方式形成，所以製程簡單、製程時間短且製造成本低。The source/drain number (number of electrodes) of the metal oxide semiconductor device of the present invention can be defined by using different mask patterns as needed. Wherein the channel, the source and the drain are not in the same plane as the conventional fin metal oxide semiconductor transistor (FINEFT) (ie, not aligned along the same line), and have a curved current flow direction, that is, not only a single flow direction, but the channel The buckling effect of the buckling induced energy barrier is smaller than that of the conventional metal oxide semiconductor transistor, and because of the large number of electrodes, the element collection density and the flexibility of the system design can be improved, and a single flash can be applied for the application. The memory component has more electrical representations of the bits and can increase the transduction of the components themselves, resulting in an increase in current. In addition, since the source and the drain of the present invention can be formed in a completely self-aligned manner with the overlay or alignment gate, the process is simple, the process time is short, and the manufacturing cost is low.
另外，本發明金屬氧化物半導體裝置亦有閘極氧化層及閘極層覆蓋通道之頂面且覆蓋源極與汲極間之結構，其在上側及二側形成多個通道，因此在相同的製程條件下，具有較佳之電流驅動力。In addition, the metal oxide semiconductor device of the present invention also has a gate oxide layer and a gate layer covering the top surface of the channel and covering the structure between the source and the drain, and forming a plurality of channels on the upper side and the two sides, and thus in the same Under the process conditions, it has better current driving force.
綜上所述，本發明金屬氧化物半導體裝置在電性方面，不論是導通/漏電流、汲極引發能障衰退效應、次臨界擺幅及轉導率等，都具有更優異的表現。In summary, the metal oxide semiconductor device of the present invention has superior performance in terms of electrical properties, such as conduction/leakage current, buckling-induced energy barrier degradation effect, sub-threshold swing, and transduction rate.
上述實施例僅為說明本發明之原理及其功效，並非限制本發明。因此習於此技術之人士對上述實施例進行修改及變化仍不脫本發明之精神。本發明之權利範圍應如後述之申請專利範圍所列。The above embodiments are merely illustrative of the principles and effects of the invention and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims.
1．．．本發明之金屬氧化物半導體裝置1. . . Metal oxide semiconductor device of the present invention
10．．．底層10. . . Bottom layer
11．．．矽層11. . . Layer
12．．．第一氧化層12. . . First oxide layer
13．．．閘極單元13. . . Gate unit
14．．．第二氧化層14. . . Second oxide layer
100．．．基板100. . . Substrate
111．．．主動區111. . . Active zone
112．．．第一區域112. . . First area
113．．．第二區域113. . . Second area
114．．．延伸部114. . . Extension
115．．．源極115. . . Source
116．．．汲極116. . . Bungee
131．．．閘極氧化層131. . . Gate oxide layer
132．．．閘極層132. . . Gate layer
圖1至圖11顯示本發明金屬氧化物半導體裝置之製造方法；其中，圖11顯示本發明金屬氧化物半導體裝置之示意圖；1 to 11 are views showing a method of manufacturing a metal oxide semiconductor device of the present invention; wherein, FIG. 11 is a view showing a metal oxide semiconductor device of the present invention;
圖12顯示本發明金屬氧化物半導體裝置之內部結構示意圖；Figure 12 is a view showing the internal structure of the metal oxide semiconductor device of the present invention;
圖13顯示習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之導通電流-漏電流關係圖；Figure 13 is a graph showing the relationship between a conventional metal oxide semiconductor device and the multi-source metal oxide semiconductor device of the present invention and the on-state current-drain current of the multi-drain metal oxide semiconductor device of the present invention;
圖14顯示習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之等效通道長度-門檻電壓關係圖；14 is a diagram showing an equivalent channel length-threshold voltage relationship between a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention;
圖15為一習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之等效通道長度-汲極引發能障衰退效應(DIBL)關係圖；及15 is an equivalent channel length-drain-induced energy-degradation effect of a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. (DIBL) relationship diagram; and
圖16顯示習知金屬氧化物半導體裝置與本發明具多源極之金屬氧化物半導體裝置及本發明具多汲極之金屬氧化物半導體裝置之等效通道長度-次臨界擺幅(subthreshold swing)關係圖。16 shows an equivalent channel length-subthreshold swing of a conventional metal oxide semiconductor device and a multi-source metal oxide semiconductor device of the present invention and a multi-drain metal oxide semiconductor device of the present invention. relation chart.
1．．．本發明之金屬氧化物半導體裝置1. . . Metal oxide semiconductor device of the present invention
10．．．底層10. . . Bottom layer
12．．．第一氧化層12. . . First oxide layer
14．．．第二氧化層14. . . Second oxide layer
111．．．主動區111. . . Active zone
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| TW200715528A (en) * | 2005-06-30 | 2007-04-16 | Intel Corp | Block contact architectures for nanoscale channel transistors |
| US20080067613A1 (en) * | 2006-09-15 | 2008-03-20 | Anderson Brent A | Field effect transistor with raised source/drain fin straps |
| US20080283925A1 (en) * | 2005-11-21 | 2008-11-20 | Joerg Berthold | Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement |
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| TW200715528A (en) * | 2005-06-30 | 2007-04-16 | Intel Corp | Block contact architectures for nanoscale channel transistors |
| US20080283925A1 (en) * | 2005-11-21 | 2008-11-20 | Joerg Berthold | Multi-Fin Component Arrangement and Method for Manufacturing a Multi-Fin Component Arrangement |
| US20080067613A1 (en) * | 2006-09-15 | 2008-03-20 | Anderson Brent A | Field effect transistor with raised source/drain fin straps |
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