TWI390694B - 用以生產半導體封裝的基體 - Google Patents

用以生產半導體封裝的基體 Download PDF

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TWI390694B
TWI390694B TW094121814A TW94121814A TWI390694B TW I390694 B TWI390694 B TW I390694B TW 094121814 A TW094121814 A TW 094121814A TW 94121814 A TW94121814 A TW 94121814A TW I390694 B TWI390694 B TW I390694B
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Taiwan
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insulating layer
layer
psr
conductive pattern
pattern
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TW094121814A
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TW200608550A (en
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Chang Soo Jang
Jae Chul Ryu
Dong Kwan Won
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Samsung Techwin Co Ltd
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Publication of TW200608550A publication Critical patent/TW200608550A/zh
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Description

用以生產半導體封裝的基體
本發明係關於一種母基板用來生產自該母基板形成的半導體封裝和單位基板的，其中基板的彎曲變形可以被降低。
半導體封裝技術的一個主要趨勢是追求半導體封裝的尺寸或外型之縮小，使得附於電路板之上的半導體封裝可具有小高度並佔據小一點的面積。根據這個現代趨勢，一種稱為『board－on－chip』的封裝技術已被發展出來，其中一個半導體晶片附著於一個單位基板之上，佔據著約等於半導體晶片大小的面積。例如，在典型的『board－on－chip』封裝中，基板所佔的表面積不大於半導體晶片大小的1.2倍第1圖為傳統『board－on－chip』封裝的截面圖。參考第1圖，『board－on－chip』封裝50包括有一個半導體晶片40，有著形成於其中間上表面電極墊41。半導體晶片40藉著一種絕緣黏著劑45和一個單位基板10相連。半導體晶片40的電極墊41藉由著導線42並經由單位基板10的狹縫16而和單位基板10的銲線墊(wire－bonding pad)14連接。為了保持打線部分和外界隔絕，半導體晶片40的上表面（從第1圖的角度來看）和單位基板10的一些部分要被包封樹脂30所覆蓋。
依然參考第1圖，一個線路圖樣12藉電路連通銲線墊14和球墊(ballpad)15，以及一個光錫抗蝕(photo solder resist)層13形成於絕緣層11之上並覆蓋線路圖樣12。錫球(solder ball)20形成於球墊15之上並與抗蝕層(resist layer)13的外部接觸，以使此『board－on－chip』封裝50和外部的線路版（未示於圖）在電路上為通路。
在半導體封裝製造過程中，數個單位基板會以陣列圖樣形成於一個母板之內，並各有一個半導體晶片鑲於每一個單位基板之上，而後這些完製的封裝經由切割過程被區分成數個個別的半導體封裝。為了製造母板，一個導電線路圖案（通常由銅做成）會形成於FR－4或BT的絕緣層之上，而後將液態的光錫抗蝕劑(photo solder resist)鍍於絕緣層之上使之覆蓋線路圖案，而光錫抗蝕劑於高溫時在光錫抗蝕層之上變硬。然而，當受熱的母板（有光錫抗蝕層覆蓋其上）冷卻到周圍的溫度時，因為光錫抗蝕層、線路圖案和液態的光錫抗蝕劑具有相異的相對熱膨脹係數，母板容易變彎曲。這種變形會傳達到從母板分割成數片的單位基板。單位基板的變形會導致位於單位基板的球墊之上的錫球之間的高度不一致。結果，因為錫球之間的高度不一致，將很難確保半導體封裝和外部線路板之間的通路連接，因而兩者之間的不良接觸。同時在皆下來的製程中也很難正確地處理彎曲的母板，例如半導體晶片鑲上單位基板的過程及單位基板的切割過程，這些步驟都在母板的形成之後才進行的。
本發明提供一種用於製造半導體封裝和單位基板的母板，可以減低在製造半導體元件過程中所發生的彎曲變形。
本發明同時提供一種用於製造半導體封裝的母板，在母板形成之後的後續製程中，因不需額外之負擔來處理基板的平坦問題，因而易於處理。
根據本發明的觀點，我們提供一種用於製造半導體元件之單位基板的母板，而此母板包括：一個有著相互面對的第一和第二表面的絕緣層；分別形成於絕緣層的第一和第二表面之上的上導電圖案和下導電圖案；分別形成於絕緣層的第一和第二表面之上的且覆蓋至少一部分上下導電圖案面積的上光錫抗蝕層和下光錫抗蝕(photo solder resist，PSR)層。當藉由通過絕緣層中線的參考面將母板區分成上部和下部時，上部的等效熱膨脹係數可由以下公式所定義：α upper ＝，其中的α b 、α c 和α p 分別為上絕緣層、上導電圖案以及上PSR層的熱膨脹係數；而E b 、E c 和E p 分別為上絕緣層、上導電圖案以及上PSR層的彈性模數；而v b 、v c 和v p 則分別為上絕緣層、上導電圖案以及上PSR層的體積比。下部的等效熱膨脹係數可由以下公式所定義：α lower ＝，其中的α b 、α c 和α p 分別為下絕緣層、下導電圖案以及下PSR層的熱膨脹係數；而E b 、E c 和E p 分別為下絕緣層、下導電圖案以及下PSR層的彈性模數；而v b 、v c 和v p 則分別為下絕緣層、下導電圖案以及下PSR層的體積比。
α upper 相比於α lower 的等效熱膨脹係數比值(α upper /α lower )選定界於0.975和1.165之間。
在此所謂的上部的體積比值v i （如v b 、v c 和v p ）之定義為每一特定部分（如上絕緣層、上導電圖案和上PSR層）的體積相對於整個上部體積之比值，可由下列公式表示：v i ＝。而下部的體積比值v j （如v b 、v c 和v p ）之定義為每一特定部分（如下絕緣層、下導電圖案和下PSR層）的體積相對於整個下部體積之比值，可由下列公式表示：v j ＝α upper /α lower 一般較常選定界於0.99和1.09之間。
導電線路圖案一般偏好用銅(Cu)做成，而絕緣層偏好用FR－4或BT樹脂做成。
根據本發明的另一觀點，我們提供一種藉由切割母板所形成的單位基板，以在此單位基板內製造半導體元件。此母板包括：一個有著相互面對的第一和第二表面的絕緣層；分別形成於絕緣層的第一和第二表面之上的上導電圖案和下導電圖案；分別形成於絕緣層的第一和第二表面之上的且覆蓋至少一部分上下導電圖案面積的上光錫抗蝕層和下光錫抗蝕(photo solder resist，PSR)層。當藉由通過絕緣層中線的參考面將母板區分成上部和下部時，上部的等效熱膨脹係數可由以下公式所定義：α upper ＝，其中的α b 、α c 和α p 分別為上絕緣層、上導電圖案以及上PSR層的熱膨脹係數；而E b 、E c 和E p 分別為上絕緣層、上導電圖案以及上PSR層的彈性模數；而v b 、v c 和v p 則分別為上絕緣層、上導電圖案以及上PSR層的體積比。下部的等效熱膨脹係數可由以下公式所定義：α lower ＝，其中的α b 、α c 和α p 分別為下絕緣層、下導電圖案以及下PSR層的熱膨脹係數；而E b 、E c 和E p 分別為下絕緣層、下導電圖案以及下PSR層的彈性模數；而v b 、v c 和v p 則分別為下絕緣層、下導電圖案以及下PSR層的體積比。等效熱膨脹係數比(α upper /α lower )選定界於0.975和1.165之間。一般較常將α upper /α lower 選定界於0.99和1.09之間。
以下，本發明將藉由參考示範性的實施例之相關圖示加以細述。
第2A圖和第3圖為根據本發明之實施例所構建的用以從中製造半導體封裝的母板100（指包含有單位基板之陣列的原始基板），其中，第2A圖顯示母板100的某一表面，而第3圖顯示母板100的另一表面。
參考第2A圖，數個單位基板180以陣列形式排列於母板100之上，此單位基板之陣列可同時提供數個封裝。亦即，在半導體晶片加附於每一個單位基板180上之後，母板100被切割成數個個別的封裝。
導體圖案120和覆蓋其上的光錫防蝕(PSR)層130在母板100的絕緣層110之第一表面110A之上形成絕緣層110可以形成於環氧樹脂如FR－4或BT樹脂之上。導體圖案120由一個具有優異導電率的金屬物質（譬如銅）所構成。例如，導體圖案120可藉著堆疊薄銅層而後再藉光微影(photo－lithography)過程繪製圖案。有一些導體圖案120在單位基板180之內形成，並提供線路圖案121使得可以由此傳輸；其他的導體圖案120形成於單位基板180陣列的外圍而構成另一些擋片圖案122。
第2B圖介紹第2A圖中單位基板180的細節。
參考第2A圖，曝接於單位基板180之表面的銲線墊140和球墊150藉由對應的線路圖案121彼此連為通路。當單位基板180和一個半導體晶片（未示於圖）組裝起來的時候，有一導線（未示於圖）連接到對應的銲線墊140，而線路圖案121便藉由此導線和半導體晶片連為通路。為此，有一狹縫160在單位基板180的中心附近形成，而這個導線便經由狹縫160從它所接觸的半導體晶片的墊片延伸連通到銲線墊140。一個錫球（未示於圖）被固定附於球墊150之上，線路圖案121藉由此錫球連通到外部的線路板。
再回去看第2A圖，擋片圖案122只有一種機械上的作用，而沒有做為電路或是電容器等電子上之功用，它們可以排成如第2A圖所示的晶格形式。如第3圖所示，這樣的擋片圖案122也同樣地形成於絕緣層110的第二表面110B之上。這樣的擋片圖案122一般偏好以晶格形式排列在絕緣層110的第二表面110B的所有表面之上。因為線路圖案並未在第二表面110B之上形成，在第二表面110B上的導體圖案120就只是一般的擋片圖案122。
擋片圖案122可以強化母板100的力量，並防止母板100的顫動，而且有一個重要功能就是減少母板100的彎曲形變。因為擋片圖案122在第一表面110A和第二表面110B之上形成，則起因於第一表面110A（含線路圖案121）和第二表面110B（不含線路圖案121）不同的熱膨脹率所導致的母板100之彎曲形變便可被減小。現在參考第2A圖和第2B圖，光錫抗蝕層（PSR層）130除了銲線墊140和球墊150（由此行程對應的洞）的範圍之外全都被導體圖案120所覆蓋。PSR層130一半藉由在絕緣層110（含導體圖案120）之上圖一層液態的光錫抗蝕劑(LPSR)而後硬化所形成。根據本發明之實施例，LPSR物質利用絲網印刷的方式而塗上，而後經過幾十分鐘處於70度C以上的過程而硬化變乾。如第3圖所示，PSR層130同時也在絕緣層110的第二表面110B之上形成，因而覆蓋了擋片圖案122。
第4圖為第2A圖中沿著IV－IV的線截過的截面之部分放大圖；在第4圖中參考面P代表一個將母板100化分成等厚度之上下兩部分（如上部100U和下部100L）的想像面，而在對應支參考數字之後的參考字母U代表所指的參考數字或元件的上部，字母L則代表下部。因此，上部100U的上導體圖案120(U)同時代表位於絕緣層110（見第2圖）之第一（上）表面之上的線路圖案121和擋片圖案122，下部100L的下導體圖案120(L)同時代表位於絕緣層110（見第3圖）之第二（下）表面之上的線路圖案121和擋片圖案122。上導體圖案120(U)和下導體圖案120(L)具有相較上不同的圖案，因此，上部100U和下部10oL具有不等量的導電金屬（例如銅）。所以，母板100在後續製程中有彎曲的潛在可能，尤其是受熱過程，例如LPSR層的硬化過程。然而，本發明可以藉由調整每個部分的大小或其相對於母板100的體積比來有效地減小這樣的彎曲形變。這在後文會有更詳細的敘述。
從熱膨脹係數α b 、α c 和α p ，彈性模數Eb 、Ec 和Ep 以及上部絕緣層100(U)、上導體圖案120(U)、和上PSR層130(U)的體積比值vb , vc 和vp ，上部100U的銅的等效熱膨脹係數可由以下的公式(1)表示。在此，下標字母b、c和p分別用於代表上部絕緣層100(U)、上導體圖案120(U)和上PSR層130(U)。
其中的體積比值vb 、vc 和vp 分別為上部絕緣層100(U)、上導體圖案120(U)、和上PSR層130(U)的體積相對於整個上部100U之體積的比值。例如，上PSR層130(U)的體積比可由以下之公式(2)來表示： 其中的V b 、V c 和V p 分別代表上部絕緣層100(U)、上導體圖案120(U)、和上PSR層130(U)的體積。
上部絕緣層100(U)、上導體圖案120(U)、和上PSR層130(U)的熱膨脹係數α b 、α c 和α p ，彈性模數Eb 、Ec 和Ep 列表於下列之表格(1)。熱膨脹係數α b 、α c 和α p ，彈性模數Eb 、Ec 和Ep 乃特定物質的本質性常數，因此和下部的值相同。
同樣的，從熱膨脹係數α b 、α c 和α p ，彈性模數Eb 、Ec 和Ep 以及下部絕緣層100(L)、下導體圖案120(L)、和下PSR層130(L)的體積比值vb , vc 和vp ，下部100U的銅的等效熱膨脹係數可由以下的公式(3)表示。在此，下標字母b、c和p分別用於代表下部絕緣層100(L)、下導體圖案120(L)和下PSR層130(L)。
其中的體積比值vb 、vc 和vp 分別為下部絕緣層100(L)、下導體圖案120(L)、和下PSR層130(L)的體積相對於整個下部100L之體積的比值。例如，下導體圖案120(L)的體積比可由以下之公式(4)來表示：
其中的V b 、V c 和V p 分別代表下部絕緣層100(L)、下導體圖案120(L)、和下PSR層130(L)的體積。
如第5圖所示，當具有不同的熱膨脹係數的上部100U和下部100L受到溫度變化時，這兩個部分的長度會變得不同因而會導致母板的彎曲。如下列公式(5)所表示的，母板100的彎曲形變可由等效熱膨脹係數之比值α ratio 來表示，（以下，將由等效CTE比來代表α ratio ）α ratio 之定義為α upper 和α lower 之比值。
更仔細地說，如第6圖所示的，母板的彎曲形變的比值通常正比於等效CTE比。此結果得自於利用有限元素法(FEM)計算具有不同等效CTE比的母板之彎曲形變比(d/L)。參考第5圖，母板100之彎曲形變比d/L係因為彎曲形變所致之長度減縮值d相對於母板100的總長(L)之比值。如第5(a)圖所示，當母板100向下彎時，彎曲形變比(d/L)定義為正值；如第5(b)圖所示，當母板100向上彎時，彎曲形變比(d/L)定義為負值。
參考第6圖，當等效CTE比(α ratio )之值為1.033時，彎曲形變比(d/L)為0%。如果α ratio 大於1.033，d/L為正值，如果α ratio 小於1.033 d/L為負值。如圖所示，彎曲形變比d/L約正比於等效CTE比α ratio 。為了維持彎曲形變比(d/L)界於－1%到＋1%r間之允許值，一般最好將等效CTE比(α ratio )定於0.99到1.09之間。因為母板的彎曲形變可藉由選擇PSR層的硬化條件，和（或）藉由硬化之後的退火製程而減低，等效CTE比(α ratio )可以設定介於0.975和1.165之間以維持彎曲形變比d/L在－1.5%和＋1.5%之間，這樣的允許範圍比上文所述的較不嚴格。
在此將根據設計使母板具有特定的等效CTE比(α ratio )的方法做更進一步的介紹。
如上所述，在公式(5)中，等效CTE比(α ratio )定義為α upper 和α lower （分別由公式(1)和公式(3)所表示）之比值。因為每個成分的熱膨脹係數α b 、α c 和α p ，彈性模數Eb 、Ec 和Ep 乃該特定物質的本質性常數，可藉由調整每個成分的體積比vb , v0 和vp 來得到等效CTE比(α ratio )之目標值。更進一步地藉由參考第4圖來說明，為了分別調整導體圖案120(U)和120(L)或PSR層130(U)和130(L)的表面積，必須改變半導體封裝上的設計。因此，要調整每個成分的厚度很容易，但是調整其表面積不容易。然而，因為導體圖案120(U)和120(L)的尺寸和半導體封裝的電氣特性相關密切，調整導體圖案120(U)和120(L)的厚度t1和t2也不容易。因此，為了使等效CTE比之值介於允許範圍內，最好是調整PSR層130(U)和130(L)的厚度t10和t20，因為它們不會直接影響半導體封裝的電氣特性。以下的實驗乃為了釐清因調整PSR層的厚度所導致的彎曲形變之減小並將實際產品的結果與FEM分析的結果（如第6圖所示）比較。在這些實驗中，FEM分析和實際產品的測試在相對於兩個母板其各有不同上部厚度的PSR層之情形下進行，以得到這兩種母板的彎曲形變。這些實驗的結果表示於下面的表格2。
在此，從實驗2代表相對於實驗1所得之彎曲形變的相對比例之彎曲形變。如列表2所示，從FEM分析所得的彎曲形變0.24以及從實際產品測試所得的彎曲形變0.34彼此有些不同，但其值仍大致上相似。如FEM分析和實際產品測試的分析結果所示，實驗2中的彎曲形變都小於實驗1中的彎曲形變。尤其是，如上述實驗的結果所示，當和實驗1的結果相比，實驗2中的彎曲形變減小超過了60%。如上所述，可藉由調整PSR層的厚度大幅地減少彎曲形變。
根據如上所述之本發明，最佳或較優良的母板（以及從母板所得的單位基板）設計可以有效地被設定以達到減小母板的彎曲形變。亦即，藉由提供設計好的參數（如PSR層的厚度和等效CTE比）以及在可接受的彎曲形變下，它們的允許範圍，在母板形成之後的製程中，因為母板沒有過大的彎曲形，可以容易地處理母板，因而可以提升封裝的產量。因此，可以改善截自母板的單位基板內的錫球的共面性，而且半導體封裝和外度線路板之間的導電性也因為減少了兩者之間的不良接觸而獲得改善。
儘管我們在前文中描述本發明的優先實例以作為介紹，然而任何熟習此技術者皆瞭解，在不違背本發明的範圍與精神下，仍有可能有不同的修改、變化、增附或替代。本發明的範圍與精神將由以下的專利申請範圍來顯明。
 （先前技術）
10．．．單位基板
12．．．線路圖樣
13．．．光錫抗蝕(photo solder resist)層
14．．．銲線墊
15．．．球墊(ball pad)
20．．．錫球(solder ball)
30．．．包封樹脂
45．．．絕緣黏著劑
42．．．導線
41．．．電極墊
40．．．半導體晶片
50．．．『board－on－chip』封裝
（本發明）
100．．．母板
110．．．絕緣層
110A．．．（絕緣層）第一表面
110B．．．（絕緣層）第二表面
120．．．導體圖案
121．．．線路圖案
122．．．擋片圖案
130．．．光錫防蝕(PSR)層
140．．．銲線墊
150．．．球墊
160．．．狹縫
180．．．單位基板
U．．．上部
L．．．下部
第1圖為傳統的半導體封裝的截面圖；第2A圖為根據本發明之實施例的母板表面之闡釋圖；第2B圖為第2A圖中單位基板的放大圖；第3圖為第2A圖中母板由另一面闡釋的平面圖；第4圖為第2A圖中沿著IV－IV的線截過的截面之部分放大圖；第5圖為常發生在製程中的母板彎曲現象的示意圖；第6圖則在闡釋母板的等效熱膨脹係數比值和彎曲形變比值的關係。
100．．．母板
110．．．絕緣層
110B．．．（絕緣層）第二表面
120．．．導體圖案
122．．．擋片圖案
130．．．光錫防蝕(PSR)層

Claims (8)

  1. 一種用以生產半導體元件的母板，此母板包括：一個有著相互面對的第一和第二表面的絕緣層；分別形成於絕緣層的第一和第二表面之上的上導電圖案和下導電圖案；分別形成於絕緣層的第一和第二表面之上的且覆蓋至少一部分上下導電圖案面積的上光錫抗蝕層和下光錫抗蝕(photo solder resist，PSR)層；其中的母板藉由通過絕緣層中線的參考面將母板區分成上部和下部時，其中上部的等效熱膨脹係數可由以下公式所定 義：， 在此式中的α b 、α c 和α p 分別為上絕緣層、上導電圖案以及上PSR層的熱膨脹係數；而E b 、E c 和E p 分別為上絕緣層、上導電圖案以及上PSR層的彈性模數；而v b 、v c 和v p 則分別為上絕緣層、上導電圖案以及上PSR層的體積比；下部的等效熱膨脹係數可由以下公式所定義： 其中的α b 、α c 和α p 分別為下絕緣層、下導電圖案以及下PSR層的熱膨脹係數；而E b 、E c 和E p 分別為下絕緣層、下導電圖案以及下PSR層的彈性模數；而v b 、v c 和v p 則分別為下絕緣層、下導電圖案以及下PSR層的體積 比；α upper 相比於α lower 的等效熱膨脹係數比(α upper /α lower )選定界於0.975和1.165之間。
  2. 如專利申請範圍第1項所述之母板，其中的α upper /α lower 一般較常將之選定界於0.99和1.09之間。
  3. 如專利申請範圍第1項所述之母板，其中的上、下導體圖案一般偏好用銅(Cu)做成，而絕緣層偏好用FR-4或BT樹脂做成。
  4. 如專利申請範圍第1項所述之母板，其中絕緣層的第一表面之上的上導體圖案包括：給單位基板的陣列形式的線路圖案位於母板的表面中間用以傳遞電訊號，以及陣列型式的擋片圖案位於母板表面的周圍面積。
  5. 如專利申請範圍第4項所述之母板，其中的上、下PSR層，除了線路圖案的面積之外，分別覆蓋上、下導電圖案整個面積。
  6. 如專利申請範圍第1項所述之母板，其中位於絕緣層的第二表面上的下導體圖案乃為一個擋片圖案的陣列，並不傳遞電訊號。
  7. 一種用以提供半導體封裝的單位基板，其特徵在於：所述單位基板係經由一母板切割所形成，該母板包括：一個有著相互面對的第一和第二表面的絕緣層；分別形成於絕緣層的第一和第二表面之上的上導電圖案和下導電圖案； 分別形成於絕緣層的第一和第二表面之上的且覆蓋至少一部分上下導電圖案面積的上光錫抗蝕層和下光錫抗蝕(photo solder resist，PSR)層；其中的母板藉由通過絕緣層中線的參考面將母板區分成上部和下部時，其中上部的等效熱膨脹係數可由以下公式所定 義：， 在此式中的α b 、α c 和α p 分別為上絕緣層、上導電圖案以及上PSR層的熱膨脹係數；而E b 、E c 和E p 分別為上絕緣層、上導電圖案以及上PSR層的彈性模數；而v b 、v c 和v p 則分別為上絕緣層、上導電圖案以及上PSR層的體積比；下部的等效熱膨脹係數可由以下公式所定義： 其中的α b 、α c 和α p 分別為下絕緣層、下導電圖案以及下PSR層的熱膨脹係數；而E b 、E c 和E p 分別為下絕緣層、下導電圖案以及下PSR層的彈性模數；而v b 、v c 和v p 則分別為下絕緣層、下導電圖案以及下PSR層的體積比；定義為α upper 相比於α lower 的等效熱膨脹係數比(α upper /α lower )選定界於0.975和1.165之間。
  8. 如專利申請範圍第7項所述之單位基板，其中的α upper /α lower 一般較常將之選定界於0.99和1.09之間。
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