TWI388863B - Test device, transmit circuit and control methods thereof - Google Patents

Test device, transmit circuit and control methods thereof Download PDF

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TWI388863B
TWI388863B TW98118033A TW98118033A TWI388863B TW I388863 B TWI388863 B TW I388863B TW 98118033 A TW98118033 A TW 98118033A TW 98118033 A TW98118033 A TW 98118033A TW I388863 B TWI388863 B TW I388863B
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data
timing
unit
test
reference clock
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TW201000928A (en
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Junichi Matsumoto
Yoshinori Kawaume
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Advantest Corp
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
    • G01R31/31726—Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators

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  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Description

測試裝置、傳送電路、測試裝置的控制方法以及傳送電路的控制方法Test device, transmission circuit, control method of test device, and control method of transmission circuit

本發明是有關於一種測試裝置、傳送電路、測試裝置的控制方法以及傳送電路的控制方法。本發明特別是有關於一種對被測試元件進行測試的測試裝置及測試裝置的控制方法、以及將資料及表示該資料是否有效的資料賦能信號自發送電路向接收電路傳送的傳送電路及傳送電路的控制方法。The present invention relates to a test apparatus, a transmission circuit, a control method of the test apparatus, and a control method of the transmission circuit. More particularly, the present invention relates to a test device and a test device control method for testing a device to be tested, and a transfer circuit and a transfer circuit for transmitting data and a data enable signal indicating whether the data is valid from a transmitting circuit to a receiving circuit. Control method.

對半導體等進行測試的測試裝置具有：產生對給予被測試元件的測試信號的變化點進行指定的時序(timing)信號的時序產生器(例如，參照專利文獻1)。時序產生器給予表示自基準時脈(reference clock)的時序至測試週期的開始時序為止的延遲時間的測試週期資料、以及表示自測試週期的開始時序至變化點為止的延遲時間的時序資料。並且，時序產生器使用延遲電路來使基準時脈相應地延遲測試週期資料及時序資料中所示的延遲時間，從而產生時序信號。A test apparatus that tests a semiconductor or the like has a timing generator that generates a timing signal that specifies a change point of a test signal given to a device under test (for example, refer to Patent Document 1). The timing generator gives test cycle data indicating a delay time from the timing of the reference clock to the start timing of the test cycle, and timing data indicating the delay time from the start timing of the test cycle to the change point. Moreover, the timing generator uses a delay circuit to delay the reference clock by the delay time shown in the test period data and the timing data, thereby generating a timing signal.

【專利文獻1】日本專利特開2004-361343號公報然而，測試裝置藉由連續連接的多個正反器(flip-flop)而傳播由週期產生器所產生的測試週期資料，並給予至後段的時序產生器。但近年來隨著被測試元件的高性能化以及多引腳(pin)化，測試週期資料的位元(bit)數正在增加。而且，自週期產生器向時序產生器傳播測試週期資料的正反器的段數亦在增加。[Patent Document 1] Japanese Laid-Open Patent Publication No. 2004-361343. However, the test apparatus propagates the test period data generated by the period generator by a plurality of flip-flops connected in series, and gives it to the latter stage. Timing generator. However, in recent years, with the high performance of the device under test and the multi-pin, the number of bits of the test cycle data is increasing. Moreover, the number of segments of the flip-flop that propagates the test period data from the period generator to the timing generator is also increasing.

而且，測試裝置有時會在一個測試週期的範圍內產生多個時序信號。在此情況時，時序產生器藉由每當給予測試週期資料時巡迴地逐個選擇並列連接的多個延遲電路並使其動作，從而可在一個測試週期的範圍內產生多個時序信號。Moreover, the test device sometimes generates multiple timing signals over a range of test cycles. In this case, the timing generator can generate a plurality of timing signals within a range of one test period by alternately selecting and operating a plurality of delay circuits connected in parallel each time the test period data is given.

然而，近年來隨著被測試元件的高性能化，測試裝置在一個測試週期範圍內應產生的時序信號的數量增加，從而應並列連接的多個延遲電路的數量在增加。上述方面成為測試裝置的消耗電力增加的原因。However, in recent years, with the high performance of the components to be tested, the number of timing signals that the test apparatus should generate in one test cycle range is increased, so that the number of delay circuits to be connected in parallel is increasing. The above aspects are the cause of the increase in power consumption of the test device.

為了解決上述課題，在本發明的第一形態中提供一種對被測試元件進行測試的測試裝置以及該測試裝置的控制方法，此測試裝置包括：測試週期產生器，與基準時脈同步地產生測試週期信號以及測試週期資料，其中上述測試週期信號表示成為測試週期的開始時序的基準的時序，上述測試週期資料表示自上述測試週期信號至測試週期的開始時序為止的延遲量；以及時序產生器，將由上述測試週期資料指定的測試週期的開始時序作為基準，而產生在與上述被測試元件之間授受信號的時序，且，上述測試週期產生器包括：週期產生部，產生上述測試週期資料以及上述測試週期信號；資料獲取部，與上述基準時脈同步地獲取上述測試週期資料，並向上述時序產生器輸出；以及時脈閥(clock gate)部，在未產生上述測試週期信號的週期的情況時，停止對上述資料獲取部供給上述基準時脈。In order to solve the above problems, in a first aspect of the present invention, a test apparatus for testing a device under test and a control method of the test device are provided, the test device comprising: a test period generator for generating a test in synchronization with a reference clock a period signal and a test period data, wherein the test period signal indicates a timing that becomes a reference for a start timing of the test period, the test period data indicates a delay amount from the test period signal to a start timing of the test period; and a timing generator, Generating a timing of receiving and receiving a signal between the test element and the test element specified by the test cycle data, and the test cycle generator includes: a cycle generation unit that generates the test cycle data and the foregoing a test period signal; the data acquisition unit acquires the test period data in synchronization with the reference clock, and outputs the data to the timing generator; and a clock gate unit, in a case where the period of the test period signal is not generated Stop the above information Measuring section for supplying the reference clock.

在本發明的第二形態中，提供一種傳送電路以及該傳送電路的控制方法，該傳送電路將資料以及表示上述資料是否有效的資料賦能信號自發送電路向接收電路傳送，此傳送電路包括：資料獲取部，與基準時脈同步地自上述發送電路獲取上述資料並向上述接收電路輸出；以及時脈閥部，在自上述發送電路接收到表示上述資料為無效的上述資料賦能信號的情況時，停止對上述資料獲取部供給上述基準時脈。In a second aspect of the present invention, there is provided a transmission circuit and a control method of the transmission circuit, the transmission circuit transmitting data and a data enabling signal indicating whether the data is valid from a transmitting circuit to a receiving circuit, the transmitting circuit comprising: The data acquisition unit acquires the data from the transmission circuit in synchronization with the reference clock and outputs the data to the reception circuit, and the clock valve unit receives the data enable signal indicating that the data is invalid from the transmission circuit. At this time, the supply of the reference clock to the data acquisition unit is stopped.

在本發明的第三形態中，提供一種對被測試元件進行測試的測試裝置以及該測試裝置的控制方法，此測試裝置包括：時序資料產生部，產生時序資料以及時序賦能信號，其中上述時序資料對表示在與上述被測試元件之間授受信號的時序的時序信號的產生時序進行指定，上述時序賦能信號表示上述時序資料是否有效；計數部，與基準時脈同步動作，自上述時序資料產生部接收有效的上述時序資料之後，與該時序資料中所含的以大於等於上述基準時脈的週期的單位來表示時間的上位側資料數相應地對基準時脈進行計數之後，輸出該時序資料的上述上位側資料以外的下位側資料以及表示該時序資料有效的上述時序賦能信號；以及時脈閥部，在上述計數部未對有效的上述時序資料中所含的上述上位側資料數進行計數的情況時，停止對上述計數部供給上述基準時脈。In a third aspect of the present invention, a test apparatus for testing a device under test and a control method of the test device are provided, the test device comprising: a timing data generation unit that generates timing data and a timing enable signal, wherein the timing is The data pair specifies a timing of generating a timing signal at a timing of receiving and receiving a signal with the device under test, wherein the timing enable signal indicates whether the timing data is valid; and the counting unit operates in synchronization with the reference clock, from the timing data After receiving the valid timing data, the generating unit outputs the timing after counting the reference clock corresponding to the number of upper side data indicating the time in the unit of the period of the reference clock, which is included in the time series data. The lower side data other than the upper side data of the data and the timing enable signal indicating that the time series data is valid; and the clock valve part, the number of the upper side data included in the time series data that is not valid in the counting unit When the counting is performed, the supply of the base to the counting unit is stopped. Clock.

再者，上述發明的概要並未列舉本發明的全部必要特徵，該些特徵群的次組合(subcombination)亦可成為發明。Furthermore, the summary of the above invention does not recite all the essential features of the present invention, and subcombination of these feature groups may also be an invention.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

以下，透過發明的實施形態來說明本發明，但以下的實施形態並不限定申請專利範圍的發明。而且，實施形態中所說明的特徵的所有組合並非限於發明內容所必需。Hereinafter, the present invention will be described by way of embodiments of the invention, but the following embodiments do not limit the invention of the claims. Moreover, all combinations of the features described in the embodiments are not necessarily limited to the details of the invention.

圖1一併表示本實施形態的測試裝置10的構成與被測試元件200。測試裝置10將測試信號給予被測試元件200，並根據該測試信號來將自被測試元件200輸出的響應信號與期待值進行比較，藉此對被測試元件200進行測試。測試裝置10具有：圖案產生部20、測試週期產生器22、時序產生器24、波形成形部26、驅動器28、位準比較器(level comparator)30、時序比較器(timing comparator)32及判定部34。Fig. 1 also shows the configuration of the test apparatus 10 of the present embodiment and the device under test 200. The test apparatus 10 gives a test signal to the device under test 200, and compares the response signal output from the device under test 200 with an expected value based on the test signal, thereby testing the device under test 200. The test apparatus 10 includes a pattern generation unit 20, a test period generator 22, a timing generator 24, a waveform shaping unit 26, a driver 28, a level comparator 30, a timing comparator 32, and a determination unit. 34.

圖案產生部20產生對給予被測試元件200的測試信號的波形進行指定的測試圖案以及指定對應於測試信號之給予而應自被測試元件200輸出的響應信號的邏輯值的期待值圖案。而且，圖案產生部20產生對測試週期進行指定的資料，該測試週期成為用以對測試信號的波形變化(邊緣)的時序以及響應信號與期待值的比較時序進行指定的基準。而且，圖案產生部20在每個測試週期產生延遲資料，該延遲資料表示自該測試週期的開始時序至測試信號的波形變化的時序為止的延遲時間、或者表示自測試週期 的開始時序至響應信號與期待值的比較時序為止的延遲時間。The pattern generating portion 20 generates a test pattern for designating a waveform of a test signal given to the device under test 200 and an expected value pattern for designating a logical value corresponding to a response signal to be output from the device under test 200 corresponding to the giving of the test signal. Further, the pattern generation unit 20 generates data specifying the test period, which is a reference for specifying the timing of the waveform change (edge) of the test signal and the comparison timing of the response signal and the expected value. Moreover, the pattern generating portion 20 generates a delay data indicating a delay time from the start timing of the test period to the timing of the waveform change of the test signal, or the self-test period, in each test cycle. The delay time from the start timing to the comparison timing of the response signal and the expected value.

測試週期產生器22與基準時脈同步地產生成為測試週期的開始時序的基準的測試週期信號、以及表示自測試週期信號至測試週期的開始時序為止的延遲量的測試週期資料。作為一例，測試週期產生器22可自圖案產生部20接收指定測試週期的資料，並根據所接收到的資料而生成測試週期資料。並且，測試週期產生器22與基準時脈同步地產生所生成的測試週期資料以及測試週期信號。The test cycle generator 22 generates a test cycle signal which is a reference for the start timing of the test cycle and a test cycle data indicating the delay amount from the test cycle signal to the start timing of the test cycle in synchronization with the reference clock. As an example, the test period generator 22 may receive the data specifying the test period from the pattern generation unit 20, and generate test period data based on the received data. And, the test period generator 22 generates the generated test period data and the test period signal in synchronization with the reference clock.

時序產生器24將由測試週期資料所指定的測試週期的開始時序作為基準，而產生在與被測試元件200之間授受信號的時序。此處，將產生測試週期信號的基準時脈的週期稱為：『測試週期信號表示有效的週期』，將未產生測試週期信號的基準時脈的週期稱為：『基準週期信號表示無效的週期』。而且，在本實施形態中，在稱為有效的測試週期資料的情況時，表示在測試週期信號表示有效的時序中獲取的測試週期資料；在稱為無效的測試週期資料的情況時，表示在測試週期信號表示無效的時序中獲取的測試週期資料。即，在本實施形態中，測試週期信號作為表示測試週期資料有效或者無效的信號而發揮作用。作為一例，時序產生器24可在自藉由有效的測試週期資料所指定的時序起、延遲了由對應於該測試週期的延遲資料所指定的延遲時間的時序中，產生作為脈波(pulse)的時序信號。The timing generator 24 generates a timing at which a signal is received and received between the device under test 200, using the start timing of the test period specified by the test period data as a reference. Here, the period of the reference clock that generates the test period signal is referred to as: "the test period signal indicates a valid period", and the period of the reference clock that does not generate the test period signal is referred to as: "the reference period signal indicates an invalid period. 』. Further, in the present embodiment, in the case of the case of the effective test period data, the test period data acquired in the timing at which the test period signal indicates effective is indicated; in the case of the data called the invalid test period data, it is indicated in the case The test period signal indicates the test period data acquired in the invalid timing. That is, in the present embodiment, the test period signal functions as a signal indicating whether the test period data is valid or invalid. As an example, the timing generator 24 may generate a pulse as a pulse from a timing specified by the valid test period data and delayed by a delay time specified by the delay data corresponding to the test period. Timing signal.

波形成形部26將自時序產生器24給予的時序信號作為基準，而生成對測試圖案進行成形的測試信號。即，波形成形部26生成具有下述波形的測試信號，該波形是由測試圖案所指定的波形，且為在時序信號的時序中位準發生變化的波形。The waveform shaping unit 26 generates a test signal for shaping the test pattern by using the timing signal given from the timing generator 24 as a reference. That is, the waveform shaping unit 26 generates a test signal having a waveform which is a waveform designated by the test pattern and which is a waveform whose level changes in the timing of the timing signal.

驅動器28將藉由波形成形部26所生成的測試信號供給至被測試元件200。位準比較器30接收對應於測試信號而從被測試元件200輸出的響應信號，並輸出表示與所接收到的響應信號的位準相應的邏輯值的邏輯值信號。The driver 28 supplies the test signal generated by the waveform shaping portion 26 to the device under test 200. The level comparator 30 receives the response signal output from the device under test 200 corresponding to the test signal, and outputs a logic value signal indicating a logical value corresponding to the level of the received response signal.

時序比較器32以自時序產生器24所給予的時序信號的時序，而取入由位準比較器30輸出的邏輯值信號所表示的邏輯值。判定部34對時序比較器32所取入的邏輯值與由圖案產生部20所產生的期待值圖案而指定的期待值進行比較，並輸出比較結果。作為一例，判定部34可在時序比較器32所取入的邏輯值與期待值相一致的情況時，輸出表示合格(pass)的比較結果；而在時序比較器32所取入的邏輯值與期待值不一致的情況時，輸出表示不合格(fail)的比較結果。The timing comparator 32 takes in the logic value represented by the logic value signal output from the level comparator 30 at the timing of the timing signal given from the timing generator 24. The determination unit 34 compares the logical value taken in by the timing comparator 32 with the expected value specified by the expected value pattern generated by the pattern generation unit 20, and outputs the comparison result. As an example, the determination unit 34 may output a comparison result indicating a pass when the logical value taken in by the timing comparator 32 matches the expected value; and the logical value taken in the timing comparator 32 and When the expected values do not match, a comparison result indicating a failure is output.

圖2表示測試週期產生器22輸出的測試週期資料的位元構成的一例。測試週期資料表示該測試週期資料給予至時序產生器24的、與該測試裝置10的基準時脈同步的時序，即，表示自時序產生器24接收到測試週期資料的時序至由該測試週期資料指定的測試週期的開始時序為止的延遲時間。FIG. 2 shows an example of the bit structure of the test period data outputted by the test period generator 22. The test period data indicates the timing at which the test period data is given to the timing generator 24 in synchronization with the reference clock of the test apparatus 10, that is, the timing from the timing generator 24 receiving the test period data to the data of the test period. The delay time from the start timing of the specified test cycle.

測試週期資料包括多個位元。例如在圖2的例子中，測試週期資料包含(J+K)位元(J、K為自然數)。The test cycle data includes multiple bits. For example, in the example of FIG. 2, the test period data contains (J+K) bits (J, K are natural numbers).

作為一例，測試週期資料的基準位置的位元(例如圖2中的n位置的位元)表示與基準時脈的一個週期(T時間)相應的延遲時間。並且，測試週期資料自基準位置的位元向上位每前進一個位元，則各位元表示基準時脈的一個週期的2倍、4倍、8倍、．．．2K 倍(K為自然數)的延遲時間。而且，測試週期資料自基準位置的位元向下位每前進一個位元，則各位元表示基準時脈的一個週期的1/2倍、1/4倍、1/8倍、．．．、2-J 倍(J為自然數)的延遲時間。As an example, a bit of the reference position of the test period data (for example, a bit at the n position in FIG. 2) indicates a delay time corresponding to one cycle (T time) of the reference clock. Moreover, the test period data is forwarded by one bit from the bit position of the reference position, and each bit represents 2 times, 4 times, 8 times of a period of the reference clock. . . 2 K times (K is a natural number) delay time. Moreover, the test period data is forwarded by one bit from the bit position of the reference position to the next bit, and each bit represents 1/2 times, 1/4 times, 1/8 times of a period of the reference clock. . . , 2 - J times (J is a natural number) delay time.

以下，在本實施形態中，將測試週期資料中表示小於等於基準時脈的一個週期(T)的延遲時間的部分稱為：『測試週期資料的下位位元』。而且，在本實施形態中，將測試週期資料中的表示大於等於基準時脈的兩個週期(2×T)的延遲時間的部分稱為：『測試週期資料的上位位元』。即，在本實施形態中，測試週期資料包括：上位位元以及下位位元，其中上位位元表示自時序產生器24接收到測試週期資料的時序至測試週期的開始時序為止的延遲時間中的、大於基準時脈的週期的單位的時間，而下位位元表示小於等於基準時脈的週期的單位的時間。Hereinafter, in the present embodiment, a portion of the test period data indicating a delay time equal to or less than one cycle (T) of the reference clock is referred to as "lower bit of the test period data". Further, in the present embodiment, the portion of the test period data indicating the delay time of two cycles (2 × T) equal to or larger than the reference clock is referred to as "the upper bit of the test period data". That is, in the present embodiment, the test period data includes: an upper bit and a lower bit, wherein the upper bit indicates a delay time from the timing at which the timing generator 24 receives the test period data to the start timing of the test period. The time is greater than the unit of the period of the reference clock, and the lower bit represents the time less than or equal to the unit of the period of the reference clock.

圖3之(A)~(C)表示基準時脈、測試週期產生器22所輸出的測試週期資料以及測試週期信號。測試週期產生器22使測試週期資料以及測試週期信號與基準時脈同步地作為一對而輸出。進而，測試週期產生器22在每個測試週期依序輸出測試週期資料以及表示有效的測試週期信號。在此情況時，測試週期產生器22在基準時脈的一個週期中並不同時輸出大於等於兩個測試週期資料。(A) to (C) of FIG. 3 indicate the reference clock, the test period data output by the test period generator 22, and the test period signal. The test period generator 22 outputs the test period data and the test period signal as a pair in synchronization with the reference clock. Further, the test period generator 22 sequentially outputs the test period data and the valid test period signal in each test cycle. In this case, the test period generator 22 does not simultaneously output two test period data in one cycle of the reference clock.

因此，在某個測試週期不足基準時脈的兩個週期(2×T)的情況時，即，在自藉由某個測試週期資料指定的測試週期的開始時序至藉由下一個測試週期資料指定的測試週期的開始時序為止的間隔不足兩個週期的情況時，測試週期產生器22以基準時脈的週期(T)的間隔而連續輸出該兩個測試週期資料。即，在測試週期資料的上位位元為0的情況時，以基準時脈的週期的間隔而連續輸出該測試週期資料與下一個測試週期資料。Therefore, when a test cycle is less than two cycles of the reference clock (2×T), that is, from the start timing of the test cycle specified by a certain test cycle data to the data of the next test cycle When the interval between the start timings of the designated test cycles is less than two cycles, the test cycle generator 22 continuously outputs the two test cycle data at the interval of the reference clock cycle (T). That is, when the upper bit of the test period data is 0, the test period data and the next test period data are continuously output at intervals of the period of the reference clock.

圖4表示本實施形態的測試週期產生器22的構成。測試週期產生器22具有：週期產生部38及傳送電路40。Fig. 4 shows the configuration of the test cycle generator 22 of the present embodiment. The test cycle generator 22 has a cycle generation unit 38 and a transmission circuit 40.

週期產生部38自圖案產生部20接收指定測試週期的資料，並對應於所接收到的資料而與基準時脈同步地產生測試週期資料以及測試週期信號。傳送電路40與基準時脈同步地自週期產生部38獲取測試週期資料以及測試週期信號，並向時序產生器24傳送。The period generation unit 38 receives the data specifying the test period from the pattern generation unit 20, and generates the test period data and the test period signal in synchronization with the reference clock in accordance with the received data. The transmission circuit 40 acquires the test period data and the test period signal from the period generation unit 38 in synchronization with the reference clock, and transmits it to the timing generator 24.

圖5表示本實施形態的傳送電路40的構成。傳送電路40包括：下位位元獲取用正反器42、上位位元獲取用正反器44、測試週期信號獲取用正反器46、資料獲取部48、檢測部50、時脈賦能信號(clock enable signal)傳送電路52、第一時脈閥部54、資料切換部56、以及測試週期信號傳送電路58。Fig. 5 shows the configuration of the transmission circuit 40 of this embodiment. The transmission circuit 40 includes a lower bit acquiring flip-flop 42 , an upper bit acquiring flip-flop 44 , a test period signal acquiring flip-flop 46 , a data acquiring unit 48 , a detecting unit 50 , and a clock enable signal ( The clock enable signal 52, the first clock valve unit 54, the data switching unit 56, and the test period signal transmission circuit 58.

下位位元獲取用正反器42以基準時脈的時序而獲取由週期產生部38產生的測試週期資料的下位位元。上位位元獲取用正反器44以基準時脈的時序而獲取由週期產生部38產生的測試週期資料的上位位元。測試週期信號獲取用正反器46以基準時脈的時序而獲取由週期產生部38產生的測試週期信號。The lower bit acquiring flip-flop 42 acquires the lower bit of the test period data generated by the period generating portion 38 at the timing of the reference clock. The upper bit acquiring flip-flop 44 acquires the upper bit of the test period data generated by the period generating unit 38 at the timing of the reference clock. The test period signal acquisition flip-flop 46 acquires the test period signal generated by the period generation unit 38 at the timing of the reference clock.

資料獲取部48與基準時脈同步地獲取測試週期資料，並向時序產生器24輸出。作為一例，資料獲取部48可包括：下位位元傳送電路60以及上位位元傳送電路62。下位位元傳送電路60與基準時脈同步地獲取測試週期資料的下位位元，並向時序產生器24輸出。下位位元傳送電路60與基準時脈同步地獲取測試週期資料的上位位元，並向時序產生器24輸出。The data acquisition unit 48 acquires the test period data in synchronization with the reference clock and outputs it to the timing generator 24. As an example, the data acquisition unit 48 may include a lower bit transfer circuit 60 and an upper bit transfer circuit 62. The lower bit transfer circuit 60 acquires the lower bit of the test period data in synchronization with the reference clock and outputs it to the timing generator 24. The lower bit transfer circuit 60 acquires the upper bit of the test period data in synchronization with the reference clock and outputs it to the timing generator 24.

檢測部50檢測出週期產生部38所產生的測試週期資料的上位位元與預定值是否一致。在本實施形態中，將0設定為上位位元的預定值。即，在本實施形態中，檢測部50檢測出週期產生部38所產生的測試週期資料的上位位元是否為0。藉此，檢測部50可對以基準時脈的週期而連續輸出該測試週期資料與下一個測試週期資料的情況進行檢測。進而，檢測部50檢測出週期產生部38是否產生表示測試週期資料無效的測試週期信號，即，檢測出是否為未產生測試週期信號的週期。The detecting unit 50 detects whether or not the upper bit of the test period data generated by the period generating unit 38 matches the predetermined value. In the present embodiment, 0 is set as a predetermined value of the upper bit. In other words, in the present embodiment, the detecting unit 50 detects whether or not the upper bit of the test period data generated by the period generating unit 38 is 0. Thereby, the detecting unit 50 can detect that the test period data and the next test period data are continuously outputted in the cycle of the reference clock. Further, the detecting unit 50 detects whether or not the cycle generating unit 38 generates a test cycle signal indicating that the test cycle data is invalid, that is, whether or not a cycle in which the test cycle signal is not generated is detected.

並且，檢測部50產生表示是否將用於獲取上位位元的基準時脈向資料獲取部48供給的時脈賦能信號。更詳細而言，在週期產生部38產生表示測試週期資料無效的測試週期信號的情況時(即，在未產生測試週期信號的週期的情況時)，或者在週期產生部38產生的測試週期資料的上位位元與預定值(在本實施形態中為0)相一致的情況時，檢測部50產生表示無效的時脈賦能信號。而且，在週期產生部38產生表示測試週期資料有效的測試週期信號(即，在產生測試週期信號的週期的情況時)且週期產生部38產生的測試週期資料的上位位元與預定值(在本實施形態中為0)不一致的情況時，檢測部50產生表示有效的時脈賦能信號。Further, the detecting unit 50 generates a clock enable signal indicating whether or not the reference clock for acquiring the upper bit is supplied to the data acquiring unit 48. More specifically, when the period generating unit 38 generates a test period signal indicating that the test period data is invalid (that is, when the period of the test period signal is not generated), or the test period data generated by the period generating unit 38, When the upper bit matches the predetermined value (0 in the present embodiment), the detecting unit 50 generates a clock enable signal indicating that the bit is invalid. Further, the period generating portion 38 generates a test period signal indicating that the test period data is valid (that is, when the period of the test period signal is generated) and the upper bit of the test period data generated by the period generating portion 38 and the predetermined value (at In the case where 0) does not coincide in the present embodiment, the detecting unit 50 generates a clock enable signal indicating that it is valid.

時脈賦能信號傳送電路52與基準時脈同步地獲取檢測部50輸出的時脈賦能信號並傳播。作為一例，時脈賦能信號傳送電路52可與藉由簣料獲取部48而傳播的測試週期資料同步地將檢測部50輸出的時脈賦能信號，藉由連續連接的多個段的正反器來進行傳播。The clock enable signal transmission circuit 52 acquires and propagates the clock enable signal output from the detecting unit 50 in synchronization with the reference clock. As an example, the clock enable signal transmission circuit 52 can synchronize the clock enable signal output from the detecting unit 50 with the test period data propagated by the data acquisition unit 48 by the continuous connection of a plurality of segments. Counter to spread.

第一時脈閥部54接收基準時脈，並將所接收到的基準時脈作為用於獲取測試週期資料的上位位元的基準時脈而供給至資料獲取部48。作為一例，第一時脈閥部54將接收到的基準時脈供給至上位位元傳送電路62。此處，在週期產生部38產生表示測試週期資料無效的測試週期信號的情況時(即，在未產生測試週期信號的週期的情況時)，或者，在檢測出測試週期資料的上位位元與預定值(在本實施形態中為0)相一致的情況時，第一時脈閥部54停止供應資料獲取部48用於獲取該測試週期資料的上位位元的基準時脈。若在資料獲取部48藉由連續連接的多個正反器來依序傳播測試週期資料的上位位元的情況時，作為一例，第一時脈閥部54可停止對多個正反器中的傳播該測試週期資料的正反器供給基準時脈。更詳細而言，作為一例，在藉由時脈賦能信號傳送電路52而同步傳播的、藉由某段正反器所獲取的時脈賦能信號表示停止供給基準時脈的情況時，第一時脈閥部54可停止對上位位元傳送電路62中的下一段正反器供給基準時脈。The first clock valve unit 54 receives the reference clock and supplies the received reference clock to the data acquisition unit 48 as a reference clock for acquiring the upper bit of the test period data. As an example, the first clock valve unit 54 supplies the received reference clock to the upper bit transfer circuit 62. Here, when the period generating unit 38 generates a test period signal indicating that the test period data is invalid (that is, when the period of the test period signal is not generated), or when the upper bit of the test period data is detected, When the predetermined value (0 in the present embodiment) coincides, the first clock valve unit 54 stops the supply of the data acquisition unit 48 for acquiring the reference clock of the upper bit of the test period data. When the data acquisition unit 48 sequentially propagates the upper bits of the test period data by the plurality of flip-flops connected in series, the first clock valve unit 54 can be stopped in the plurality of flip-flops as an example. The forward and reverse of the test cycle data is supplied to the reference clock. More specifically, as an example, when the clock enable signal acquired by a certain flip-flop is synchronously propagated by the clock enable signal transmission circuit 52, when the supply of the reference clock is stopped, the first The one-time valve portion 54 can stop supplying the reference clock to the next-stage flip-flop in the upper bit transfer circuit 62.

除以上之外，作為一例，亦可為下述構成，即：在週期產生部38產生表示測試週期資料無效的測試週期信號的情況時(即，在未產生測試週期信號的週期的情況時)，第一時脈閥部54停止供給資料獲取部48用於獲取該測試週期資料的上位位元以及上位位元以外的位元的基準時脈。作為一例，可為下述構成，即：在週期產生部38產生表示測試週期資料無效的測試週期信號的情況時，第一時脈閥部54停止用於獲取該測試週期資料的所有位元的基準時脈。In addition to the above, as an example, when the cycle generation unit 38 generates a test cycle signal indicating that the test cycle data is invalid (that is, when the cycle of the test cycle signal is not generated) The first clock valve unit 54 stops the supply of the data acquisition unit 48 for acquiring the upper bit of the test period data and the reference clock of the bit other than the upper bit. As an example, when the cycle generation unit 38 generates a test cycle signal indicating that the test cycle data is invalid, the first clock valve unit 54 stops all the bits for acquiring the test cycle data. Baseline clock.

在檢測出測試週期資料的上位位元與預定值(在本實施形態中為0)相一致的情況時，資料切換部56將預定值取代自資料獲取部48輸出的測試週期資料的上位位元，而供給至時序產生器24。在本實施形態中，在檢測出測試週期資料的上位位元為0的情況時，資料切換部56將0取代來自資料獲取部48的上位位元，而供給至時序產生器24。When the upper bit of the test period data is detected to coincide with the predetermined value (0 in the present embodiment), the data switching unit 56 replaces the predetermined value with the upper bit of the test period data output from the data acquisition unit 48. And supplied to the timing generator 24. In the present embodiment, when it is detected that the upper bit of the test period data is 0, the data switching unit 56 substitutes 0 for the upper bit from the data acquisition unit 48 and supplies it to the timing generator 24.

測試週期信號傳送電路58與基準時脈同步地獲取週期產生部38所輸出的測試週期信號並傳播。作為一例，測試週期信號傳送電路58可與藉由資料獲取部48而傳播的測試週期資料同步地藉由連續連接的多段正反器，來傳播週期產生部38所輸出的時脈賦能信號。The test period signal transmission circuit 58 acquires and propagates the test period signal output from the period generation unit 38 in synchronization with the reference clock. As an example, the test period signal transmission circuit 58 can propagate the clock enable signal output from the period generating unit 38 by the continuously connected multi-segment flip-flops in synchronization with the test period data propagated by the data acquisition unit 48.

圖6以及圖7表示傳送電路40的具體的電路構成的一例。圖6表示資料獲取部48以及資料切換部56的構成的一例。圖7表示檢測部50、時脈賦能信號傳送電路52、第一時脈閥部54以及測試週期信號傳送電路58的構成的一例。6 and 7 show an example of a specific circuit configuration of the transmission circuit 40. FIG. 6 shows an example of the configuration of the material acquisition unit 48 and the data switching unit 56. FIG. 7 shows an example of the configuration of the detecting unit 50, the clock enable signal transmitting circuit 52, the first clock valve unit 54, and the test period signal transmission circuit 58.

作為一例，下位位元傳送電路60例如可包含：如圖6所示的、與基準時脈同步動作的n個(n為大於等於2的整數)連續連接的正反器64-1~64-n。如此之下位位元傳送電路60與基準時脈同步地藉由最前段的正反器64-1而獲取測試週期資料的下位位元，且依序向後段的正反器64傳播，並自最終段的正反器64-n而向時序產生器24輸出。As an example, the lower bit transfer circuit 60 may include, for example, n flip-flops 64-1 to 64 which are continuously connected to the reference clock as shown in FIG. 6 (n is an integer equal to or greater than 2). n. The lower bit transfer circuit 60 thus acquires the lower bit of the test period data by the front-end flip-flop 64-1 in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop 64, and finally The segment flip-flop 64-n is output to the timing generator 24.

作為一例，上位位元傳送電路62可包含：如圖6所示的、與下位位元傳送電路60所包含的正反器64為相同數量的(即n個)連續連接的正反器66-1~66-n。如此之上位位元傳送電路62與基準時脈同步地藉由最前段的正反器66-1而獲取測試週期資料的上位位元，且依序向後段的正反器66傳播，並自最終段的正反器66-n而向時序產生器24輸出。再者，下位位元傳送電路60所包含的n個正反器66的各個與經由下述第一時脈閥部54而給予的基準時脈同步地動作。As an example, the upper bit transfer circuit 62 may include the same number (ie, n) of consecutively connected flip-flops 66 as shown in FIG. 6 and the flip-flops 64 included in the lower bit transfer circuit 60. 1~66-n. Thus, the upper bit transfer circuit 62 acquires the upper bit of the test period data by the front-end flip-flop 66-1 in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop 66, and finally The segment flip-flop 66-n is output to the timing generator 24. Further, each of the n flip-flops 66 included in the lower bit transfer circuit 60 operates in synchronization with the reference clock supplied via the first clock valve unit 54 described below.

作為一例，檢測部50可如圖7所示般包含：檢測部內OR電路72與檢測部內AND電路74。檢測部內OR電路72接收測試週期資料的上位位元的各個，並輸出對各位元的值進行OR演算所得的結果。如此之檢測部內OR電路72輸出在測試週期資料上位位元為0的情況時表示無效、在0以外的情況時表示有效的信號。As an example, the detecting unit 50 may include a detecting unit internal OR circuit 72 and a detecting unit internal AND circuit 74 as shown in FIG. 7 . The detection unit internal OR circuit 72 receives each of the upper bits of the test period data, and outputs a result obtained by OR-calculating the value of each bit. In such a detection unit internal OR circuit 72, when the test bit data upper bit is 0, it indicates that it is invalid, and when it is other than 0, it indicates a valid signal.

檢測部內AND電路74輸出對檢測部內OR電路72的輸出信號、與週期產生部38產生的測試週期信號進行AND演算所得的結果。並且，如此之檢測部50將檢測部內AND電路74的輸出信號作為時脈賦能信號而輸出。藉此，在週期產生部38產生表示測試週期資料無效的測試週期信號的情況時(即，未產生測試週期信號的週期的情況時)，或者在週期產生部38產生的測試週期資料的上位位元為0的情況時，檢測部50可產生表示無效的時脈賦能信號。而且，在週期產生部38產生表示測試週期資料有效的測試週期信號、且週期產生部38產生的測試週期資料的上位位元為0以外的情況時，檢測部50可產生表示有效的時脈賦能信號。The detection unit internal circuit 74 outputs a result of performing an AND calculation on the output signal of the OR circuit 72 in the detection unit and the test cycle signal generated by the cycle generation unit 38. Then, the detection unit 50 outputs the output signal of the AND circuit 74 in the detection unit as a clock enable signal. Thereby, when the period generating unit 38 generates the test period signal indicating that the test period data is invalid (that is, when the period of the test period signal is not generated), or the upper level of the test period data generated by the period generating unit 38. When the element is 0, the detecting unit 50 can generate a clock enable signal indicating that it is invalid. Further, when the period generating unit 38 generates a test period signal indicating that the test period data is valid, and the upper bit of the test period data generated by the period generating unit 38 is other than 0, the detecting unit 50 can generate a clock indicating that it is valid. Can signal.

作為一例，時脈賦能信號傳送電路52可包含：如圖7所示的與上位位元傳送電路62所包含的正反器66為相同數量的(即n個)連續連接的正反器76-1~76-n。如此之時脈賦能信號傳送電路52與基準時脈同步地藉由最前段的正反器76-1而獲取檢測部50輸出的時脈賦能信號，並依序向後段的正反器76傳播。As an example, the clock enable signal transmitting circuit 52 may include the same number (ie, n) of consecutively connected flip-flops 76 as the flip-flop 66 included in the upper bit transfer circuit 62 as shown in FIG. -1~76-n. The clock enable signal transmitting circuit 52 acquires the clock enable signal output from the detecting unit 50 by the front-end flip-flop 76-1 in synchronization with the reference clock, and sequentially returns to the rear-stage flip-flop 76. propagation.

作為一例，第一時脈閥部54可如圖7所示般包含：與上位位元傳送電路62所包含的正反器66為相同數量的(即n個)閘極電路(gate circuit)78-1~78-n。n個閘極電路78-1~78-n的各個與上位位元傳送電路62所包含的n個正反器66-1~66-n的各個相對應。n個閘極電路78-1~78-n的各個接收基準時脈，並向上位位元傳送電路62所包含的對應的正反器66進行供給。As an example, the first clock valve portion 54 may include the same number (ie, n) of gate circuits 78 as the flip-flops 66 included in the upper bit transfer circuit 62, as shown in FIG. -1~78-n. Each of the n gate circuits 78-1 to 78-n corresponds to each of the n flip-flops 66-1 to 66-n included in the upper bit transfer circuit 62. Each of the n gate circuits 78-1 to 78-n receives the reference clock and supplies it to the corresponding flip-flop 66 included in the upper bit transfer circuit 62.

進而，n個閘極電路78-1~78-n的各個接收對時脈賦能信號傳送電路52內的對應的正反器76所輸入的時脈賦能信號。並且，若接收到的時脈賦能信號為有效，則n個閘極電路78-1~78-n的各個向上位位元傳送電路62所包含的對應的正反器66供給基準時脈；若接收到的時脈賦能信號為無效，則停止向上位位元傳送電路62所包含的對應的正反器66供給基準時脈。藉此，在上位位元傳送電路62藉由連續連接的n個正反器66-1~66-n而依序傳播測試週期資料的上位位元的情況時，第一時脈閥部54可停止對多個正反器66-1~66-n中的傳播該測試週期資料的正反器66供給基準時脈。Further, each of the n gate circuits 78-1 to 78-n receives a clock enable signal input to the corresponding flip-flop 76 in the clock enable signal transmission circuit 52. And, if the received clock enable signal is valid, the corresponding flip-flops 66 included in the respective upper bit transfer circuits 62 of the n gate circuits 78-1 to 78-n are supplied with the reference clock; If the received clock enable signal is invalid, the corresponding flip-flop 66 included in the upper bit transfer circuit 62 is stopped from supplying the reference clock. Thereby, when the upper bit transfer circuit 62 sequentially propagates the upper bit of the test period data by the n flip-flops 66-1 to 66-n connected in series, the first clock valve portion 54 can The reference clock is supplied to the flip-flop 66 that propagates the test period data among the plurality of flip-flops 66-1 to 66-n.

作為一例，資料切換部56可如圖6所示般包含：與測試週期資料的各個位元的值相對應的一個或者多個資料切換部內AND電路68。一個或者多個資料切換部內AND電路68的各個輸出對上位位元傳送電路62所輸出的測試週期資料的對應位元的值與時脈賦能信號傳送電路52的最終段的正反器76-n所輸出的時脈賦能信號進行AND演算所得的信號。As an example, the data switching unit 56 may include one or more data switching unit internal AND circuits 68 corresponding to the values of the respective bits of the test period data as shown in FIG. 6. The output of the AND circuit 68 in the one or more data switching sections is the value of the corresponding bit of the test period data output by the upper bit transfer circuit 62 and the flip-flop 76 of the final segment of the clock enable signal transfer circuit 52- The clock-energy signal output by n is a signal obtained by AND calculation.

並且，如此之資料切換部56將資料切換部內AND電路68的輸出信號作為測試週期資料的上位位元，而向時序產生器24輸出。藉此，在上位位元傳送電路62輸出的測試週期資料有效、且未檢測出測試週期資料的上位位元為0的情況時(即，時脈賦能信號有效的情況時)，資料切換部56可將上位位元傳送電路62輸出的值直接作為測試週期資料的上位位元，而向時序產生器24輸出。Then, the data switching unit 56 outputs the output signal of the AND circuit 68 in the data switching unit as the upper bit of the test period data to the timing generator 24. Thereby, when the test period data output by the upper bit transfer circuit 62 is valid and the upper bit of the test cycle data is not detected to be 0 (that is, when the clock enable signal is valid), the data switching unit The value output from the upper bit transfer circuit 62 can be directly used as the upper bit of the test period data, and output to the timing generator 24.

而且，在上位位元傳送電路62輸出的測試週期資料無效的情況時、或者檢測出測試週期資料的上位位元為0的情況時(即，在時脈賦能信號無效的情況時)，如此之資料切換部56可將0作為測試週期資料的上位位元而向時序產生器24輸出。藉此，在上位位元傳送電路62輸出的測試週期資料無效的情況時，資料切換部56可禁止對時序產生器24輸出無用的資料。進而，在檢測出測試週期資料的上位位元為0的情況時，資料切換部56可對時序產生器24輸出正確的資料。Moreover, when the test period data output by the upper bit transfer circuit 62 is invalid, or when the upper bit of the test cycle data is 0 (that is, when the clock enable signal is invalid), The data switching unit 56 can output 0 to the timing generator 24 as the upper bit of the test period data. Thereby, when the test period data output from the upper bit transfer circuit 62 is invalid, the material switching unit 56 can prohibit the output of the useless data to the timing generator 24. Further, when it is detected that the upper bit of the test period data is 0, the data switching unit 56 can output the correct material to the timing generator 24.

作為一例，測試週期信號傳送電路58可包含：如圖7所示的與上位位元傳送電路62所包含的正反器66為相同數量的(即n個)連續連接的正反器80-1~80-n。如此之測試週期信號傳送電路58與基準時脈同步地藉由最前段的正反器80-1而獲取週期產生部38輸出的測試週期信號，且依序向後段的正反器80傳播，並自最終段的正反器80-n向時序產生器24輸出。As an example, the test period signal transmission circuit 58 may include the same number (ie, n) of consecutively connected flip-flops 80-1 as the flip-flop 66 included in the upper bit transfer circuit 62 as shown in FIG. ~80-n. The test period signal transmission circuit 58 acquires the test period signal output from the period generation unit 38 by the front-end flip-flop 80-1 in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop 80, and The flip-flop 80-n from the final stage is output to the timing generator 24.

圖8之(A)~(N)表示傳送電路40內的各信號的時序圖(timing chart)的一例。再者，本例表示藉由連續連接的三段正反器，而將自週期產生部38輸出的8位元的測試週期資料以及測試週期信號向時序產生器24傳送的情況時的時序圖的一例。而且，本例的測試週期資料包含4位元的上位位元以及4位元的下位位元。(A) to (N) of FIG. 8 show an example of a timing chart of each signal in the transmission circuit 40. Furthermore, this example shows a timing chart in the case where the test period data of the 8-bit output from the period generating unit 38 and the test period signal are transmitted to the timing generator 24 by the three-segment flip-flop connected in series. An example. Moreover, the test period data of this example includes a 4-bit upper bit and a 4-bit lower bit.

圖8之(A)表示基準時脈。圖8之(B)的RATE_IN表示週期產生部38所產生的測試週期信號。圖8之(C)的RATEDT[7：0]_IN表示週期產生部38所產生的測試週期資料。(A) of Fig. 8 shows the reference clock. The RATE_IN of (B) of Fig. 8 indicates the test period signal generated by the period generating portion 38. The RATEDT[7:0]_IN of (C) of Fig. 8 indicates the test period data generated by the period generating unit 38.

圖8之(D)的gckl_1表示第一時脈閥部54給予至上位位元傳送電路62的第一段正反器66的基準時脈。圖8(E)的RATEDT_1[3：0]表示下位位元傳送電路60的第一段正反器64所獲取的測試週期資料的下位位元的值。圖8(F)的RATEDT_1[7：4]表示上位位元傳送電路62的第一段正反器66所獲取的測試週期資料的下位位元的值。Gckl_1 of (D) of FIG. 8 indicates the reference clock of the first-stage flip-flop 66 given to the upper bit transfer circuit 62 by the first clock valve portion 54. RATEDT_1[3:0] of Fig. 8(E) indicates the value of the lower bit of the test period data acquired by the first-stage flip-flop 64 of the lower bit transfer circuit 60. RATEDT_1[7:4] of Fig. 8(F) indicates the value of the lower bit of the test period data acquired by the first-stage flip-flop 66 of the upper bit transfer circuit 62.

圖8之(G)的gckl_2表示第一時脈閥部54給予至上位位元傳送電路62的第二段正反器66的基準時脈。圖8之(H)的RATEDT_2[3：0]表示下位位元傳送電路60的第二段正反器64所獲取的測試週期資料的下位位元的值。圖8之(I)的RATEDT_2[7：4]表示上位位元傳送電路62的第二段正反器66所獲取的測試週期資料的下位位元的值。Gckl_2 of (G) of FIG. 8 indicates the reference clock of the second-stage flip-flop 66 given to the upper bit transfer circuit 62 by the first clock valve portion 54. RATEDT_2[3:0] of (H) of FIG. 8 indicates the value of the lower bit of the test period data acquired by the second-stage flip-flop 64 of the lower bit transfer circuit 60. RATEDT_2[7:4] of (I) of Fig. 8 indicates the value of the lower bit of the test period data acquired by the second-stage flip-flop 66 of the upper bit transfer circuit 62.

圖8之(J)的gckl_3表示第一時脈閥部54給予至上位位元傳送電路62的第三段正反器66的基準時脈。圖8之(K)的RATEDT_3[3：0]表示下位位元傳送電路60的第三段正反器64所獲取的測試週期資料的下位位元的值。圖8之(L)的RATEDT_3[7：4]表示上位位元傳送電路62的第三段正反器66所獲取的測試週期資料的下位位元的值。Gckl_3 of (J) of FIG. 8 indicates the reference clock of the third-stage flip-flop 66 given to the upper bit transfer circuit 62 by the first clock valve portion 54. RATEDT_3[3:0] of (K) of FIG. 8 indicates the value of the lower bit of the test period data acquired by the third-stage flip-flop 64 of the lower bit transfer circuit 60. RATEDT_3[7:4] of (L) of Fig. 8 indicates the value of the lower bit of the test period data acquired by the third-stage flip-flop 66 of the upper bit transfer circuit 62.

圖8之(M)的RATE_OUT表示傳送電路40向時序產生器24輸出的測試週期信號。圖8之(N)的RATEDT[7：0]_OUT表示傳送電路40向時序產生器24輸出的測試週期資料。The RATE_OUT of (M) of FIG. 8 indicates the test period signal output from the transmission circuit 40 to the timing generator 24. The RATEDT[7:0]_OUT of (N) of FIG. 8 indicates the test period data output from the transfer circuit 40 to the timing generator 24.

如圖8之(C)所示，週期產生部38依序產生值為“0x0C”的測試週期資料(RATE1)、值為“0x23”的測試週期資料(RATE2)、值為“0x37”的測試週期資料(RATE3)、值為“0x05”的測試週期資料(RATE4)、以及值為“0xF1”的測試週期資料(RATE5)。As shown in (C) of FIG. 8, the cycle generation unit 38 sequentially generates test cycle data (RATE1) having a value of "0x0C", test cycle data (RATE2) having a value of "0x23", and a test having a value of "0x37". Cycle data (RATE3), test cycle data (RATE4) with a value of "0x05", and test cycle data (RATE5) with a value of "0xF1".

此處，值為“0x23”的測試週期資料(RATE2)、值為“0x37”的測試週期資料(RATE3)以及值為“0xF1”的測試週期資料(RATE5)的上位位元不為0。在此情況時，第一時脈閥部54如圖8之(D)、(G)、(J)所示般與該些測試週期資料(RATE1、RATE3、RATE5)對應地將各基準時脈供應至上位位元傳送電路62。Here, the test period data (RATE2) whose value is "0x23", the test period data (RATE3) whose value is "0x37", and the upper level of the test period data (RATE5) whose value is "0xF1" are not 0. In this case, the first clock valve unit 54 sets each reference clock corresponding to the test period data (RATE1, RATE3, RATE5) as shown in (D), (G), and (J) of FIG. It is supplied to the upper bit transfer circuit 62.

與此相對，值為“0x0C”的測試週期資料(RATE1)以及值為“0x05”的測試週期資料(RATE4)的上位位元為0。因此，在該些測試週期資料的下一個基準時脈的週期中產生其他測試週期資料(RATE2、RATE5)。在此情況時，第一時脈閥部54如圖8之(D)、(G)、(J)所示般停止向上位位元傳送電路62供給與該些測試週期資料(RATE1、RATE4)對應的各基準時脈。藉此，在測試週期資料的上位位元為0的情況時，第一時脈閥部54可降低在上位位元傳送電路62中消耗的電力。In contrast, the test period data (RATE1) having a value of "0x0C" and the upper bit of the test period data (RATE4) having a value of "0x05" are 0. Therefore, other test period data (RATE2, RATE5) are generated in the cycle of the next reference clock of the test period data. In this case, the first clock valve portion 54 stops the supply of the upper bit transfer circuit 62 and the test period data (RATE1, RATE4) as shown in (D), (G), and (J) of FIG. Corresponding reference clocks. Thereby, when the upper bit of the test period data is 0, the first clock valve portion 54 can reduce the power consumed in the upper bit transfer circuit 62.

且如圖8之(L)、(M)所示，在將值為“0x0C”的測試週期資料(RATE1)以及值為“0x05”的測試週期資料(RATE4)向時序產生器24輸出的情況時，資料切換部56將上位位元的值替換為“0”而輸出。藉此，在停止對上位位元傳送電路62供給基準時脈、而上位位元傳送電路62未傳送正確的值的情況時，資料切換部56可在最終段將替換為正確的值的測試週期資料輸出至時序產生器24。As shown in (L) and (M) of FIG. 8, the test period data (RATE1) having a value of "0x0C" and the test period data (RATE4) having a value of "0x05" are output to the timing generator 24. At this time, the data switching unit 56 outputs the value of the upper bit by replacing it with "0". Thereby, when the supply of the reference clock to the upper bit transfer circuit 62 is stopped and the upper bit transfer circuit 62 does not transmit the correct value, the data switching unit 56 can replace the test cycle with the correct value in the final stage. The data is output to the timing generator 24.

而且，如圖8之(B)所示，自值為“0x23”的測試週期資料(RATE2)至值為“0x37”的測試週期資料(RATE3)為止的測試週期信號表示無效。而且，自值為“0x37”的測試週期資料(RATE3)至值為“0x05”的測試週期資料(RATE4)為止的測試週期信號亦表示無效。在此情況時，第一時脈閥部54如圖8之(D)、(G)、(J)所示般在測試週期信號表示無效的期間內，停止向上位位元傳送電路62供給各基準時脈。藉此，在測試週期資料表示無效的情況時，第一時脈閥部54可降低在上位位元傳送電路62中消耗的電力。Further, as shown in (B) of FIG. 8, the test period signal from the test period data (RATE2) having a value of "0x23" to the test period data (RATE3) having a value of "0x37" is invalid. Moreover, the test period signal from the test period data (RATE3) having a value of "0x37" to the test period data (RATE4) having a value of "0x05" is also invalid. In this case, as shown in (D), (G), and (J) of FIG. 8, the first clock valve unit 54 stops the supply of the upper bit transfer circuit 62 during the period in which the test period signal indicates invalid. Baseline clock. Thereby, the first clock valve portion 54 can reduce the power consumed in the upper bit transfer circuit 62 when the test period data indicates that it is invalid.

如以上所述，在自週期產生部38產生表示輸出的測試週期資料無效的測試週期信號的情況時，或者檢測出測試週期資料的上位位元的值與預定值相一致的情況時，本實施形態的傳送電路40停止對資料獲取部48供給用於獲取並傳播該測試週期資料的上位位元的基準時脈。並且，在檢測出測試週期資料的上位位元的值與預定值相一致的情況時，傳送電路40將預定值取代資料獲取部48輸出的該測試週期資料的上位位元的值而輸出至時序產生器24。As described above, when the self-cycle generating unit 38 generates a test cycle signal indicating that the output test cycle data is invalid, or when detecting that the value of the upper bit of the test cycle data matches the predetermined value, the present embodiment The transmission circuit 40 of the form stops supplying the reference clock to the data acquisition unit 48 for acquiring and transmitting the upper bit of the test period data. Further, when it is detected that the value of the upper bit of the test period data coincides with the predetermined value, the transfer circuit 40 outputs the predetermined value instead of the value of the upper bit of the test period data output from the data acquisition unit 48 to the timing. Generator 24.

藉此，根據傳送電路40，可使有效的測試週期資料自週期產生部38向時序產生器24傳播，並且可停止用於傳播無效的測試週期資料的基準時脈，從而降低消耗電力。進而，根據傳送電路40，在有效的測試週期資料的上位位元為預定值的情況時，可停止用於傳播該有效測試週期資料的上位位元的基準時脈，從而降低消耗電力。Thereby, according to the transfer circuit 40, the effective test period data can be propagated from the period generating portion 38 to the timing generator 24, and the reference clock for propagating the invalid test period data can be stopped, thereby reducing power consumption. Further, according to the transmission circuit 40, when the upper bit of the valid test period data is a predetermined value, the reference clock for spreading the upper bit of the valid test period data can be stopped, thereby reducing power consumption.

尤其在測試週期資料的上位位元為0的情況時，有效的測試週期資料以基準時脈的間隔而連續傳播，因此消耗電力變大。因此，在測試週期資料的上位位元為0的情況時，藉由停止該用於傳播有效的測試週期資料的上位位元的基準時脈，可高效地降低消耗電力。In particular, when the upper bit of the test period data is 0, the effective test period data continuously propagates at the interval of the reference clock, and thus the power consumption becomes large. Therefore, when the upper bit of the test period data is 0, the power consumption can be efficiently reduced by stopping the reference clock of the upper bit for spreading the effective test period data.

再者，在如此之傳送電路40中，資料獲取部48的上位位元傳送電路62可為取代測試週期資料的上位位元(即，表示大於基準時脈的週期的單位的時間的位元部分)、而將測試週期資料中預定的至少一個位元(以下稱為對象位元)向時序產生器24傳播的構成。在此情況時，下位位元傳送電路60將測試週期資料中的對象位元以外的位元向時序產生器24傳播。Furthermore, in such a transfer circuit 40, the upper bit transfer circuit 62 of the material acquisition portion 48 may be a higher bit unit replacing the test period data (i.e., a bit portion representing a time greater than the unit of the period of the reference clock) And constructing at least one bit (hereinafter referred to as a target bit) predetermined in the test period data to the timing generator 24. In this case, the lower bit transfer circuit 60 propagates the bit other than the target bit in the test cycle data to the timing generator 24.

而且，在此情況時，檢測部50檢測對象位元是否與預定值相一致。而且，在此情況時，在週期產生部38產生表示測試週期資料無效的測試週期信號的情況時，或者在檢測出測試週期資料中的對象位元與預定值相一致的情況時，第一時脈閥部54停止供應資料獲取部48用於獲取對象位元的基準時脈。並且，在此情況時，在檢測出測試週期資料中的對象位元與預定值相一致的情況時，資料切換部56將預定值取代來自資料獲取部48的對象位元而向時序產生器24供應。即使為以上構成，傳送電路40亦可停止用於傳播該有效的測試週期資料的對象位元的基準時脈，從而降低消耗電力。Further, in this case, the detecting unit 50 detects whether or not the target bit coincides with a predetermined value. Further, in this case, when the period generating portion 38 generates a test period signal indicating that the test period data is invalid, or when detecting that the target bit in the test period data coincides with the predetermined value, the first time The pulse valve unit 54 stops the supply of the data acquisition unit 48 for acquiring the reference clock of the target bit. Further, in this case, when it is detected that the target bit in the test period data coincides with the predetermined value, the material switching unit 56 replaces the target bit from the material acquisition unit 48 with the predetermined value to the timing generator 24. supply. Even with the above configuration, the transmission circuit 40 can stop the reference clock of the target bit for propagating the valid test period data, thereby reducing power consumption.

進而，如此之傳送電路40可包含於測試裝置10以外的其他裝置中。即，傳送電路40可將資料以及表示該資料是否有效的資料賦能信號自發送電路向接收電路傳送。Further, such a transmission circuit 40 can be included in other devices than the test device 10. That is, the transmitting circuit 40 can transmit the data and the data enabling signal indicating whether the data is valid from the transmitting circuit to the receiving circuit.

在此情況時，傳送電路40取代自週期產生部38接收測試週期資料以及測試週期信號，而自發送電路接收資料以及資料賦能信號。並且，傳送電路40取代向時序產生器24輸出測試週期資料以及測試週期信號，而向接收電路輸出資料以及資料賦能信號。藉此，根據傳送電路40，即使在自發送電路向接收電路傳送資料以及資料賦能信號的情況時，亦可降低消耗電力。In this case, the transmission circuit 40 receives the test period data and the test period signal instead of the self-cycle generation unit 38, and receives the data and the data enable signal from the transmission circuit. Further, the transfer circuit 40 outputs the test period data and the test period signal to the timing generator 24, and outputs the data and the data enable signal to the receiving circuit. Thereby, according to the transmission circuit 40, even when the data and the data enable signal are transmitted from the transmission circuit to the reception circuit, the power consumption can be reduced.

圖9表示本實施形態的時序產生器24的構成。時序產生器24具有：時序資料產生部110、分配部112、多個計數延遲部114(114-1~114-m)、第一合成部116、第二合成部118、以及微延遲部120。Fig. 9 shows the configuration of the timing generator 24 of the present embodiment. The timing generator 24 includes a timing data generation unit 110, a distribution unit 112, a plurality of count delay units 114 (114-1 to 114-m), a first synthesis unit 116, a second synthesis unit 118, and a micro delay unit 120.

時序資料產生部110產生時序資料以及時序賦能信號，其中上述時序資料對表示在與被測試元件200之間授受信號的時序的時序信號的產生時序進行指定，而上述時序賦能信號表示時序資料是否有效。時序資料以小於基準時脈的週期的精度，來表示自接收到該時序資料的時序至時序信號的產生時序為止的延遲時間。The timing data generating unit 110 generates timing data and a timing enable signal, wherein the timing data indicates a timing of generating a timing signal indicating a timing of receiving a signal with the device under test 200, and the timing energizing signal indicates timing data. is it effective. The timing data indicates the delay time from the timing at which the timing data is received to the timing at which the timing signal is generated, with an accuracy smaller than the period of the reference clock.

作為一例，時序資料產生部110可包括：加算部132，將自測試週期產生器22接收到的測試週期資料、與從圖案產生部20給予的延遲資料進行相加。時序資料產生部110可將加算部132的加算結果作為時序資料而輸出。而且，時序資料產生部110可使自測試週期產生器22接收到的測試週期信號相應地延遲由測試週期資料與延遲資料的計算處理所耗費的時間，並作為時序賦能信號而輸出。As an example, the time series data generating unit 110 may include an adding unit 132 that adds the test period data received from the test period generator 22 to the delay data given from the pattern generating unit 20. The time series data generation unit 110 can output the addition result of the addition unit 132 as time series data. Further, the timing data generating unit 110 can delay the test period signal received from the test period generator 22 by the time taken by the calculation processing of the test period data and the delay data, and output it as a timing enable signal.

分配部112將自時序資料產生部110依序輸出的有效的時序資料以及時序賦能信號，分配至多個計數延遲部114中的任一個。每當自時序資料產生部110輸出有效的時序資料以及時序賦能信號時，分配部112巡迴地選擇多個計數延遲部114中的任一個，並向所選擇的一個計數延遲部114供給有效的時序資料以及時序賦能信號。The distribution unit 112 distributes the valid time series data and the timing enable signal sequentially output from the time series data generation unit 110 to one of the plurality of count delay units 114. Each time the timing data generating unit 110 outputs the valid time series data and the timing enable signal, the allocating unit 112 arbitrarily selects one of the plurality of counting delay units 114 and supplies the selected one of the counting delay units 114 to the selected one. Timing data and timing enable signals.

多個計數延遲部114的各個接收藉由分配部112所分配的時序資料以及時序賦能信號。多個計數延遲部114的各個將所接收到的時序資料分離成：該時序資料中所含的以大於等於基準時脈的週期的單位來表示延遲時間的資料部分、即上位側資料，以及該時序資料中所含的上位側資料以外的其他資料部分、即下位側資料。作為一例，上位側資料可為：以基準時脈的週期單位的精度來表示自接收該時序資料的時序至時序信號的產生時序為止的延遲時間的資料。下位側資料可為：表示延遲時間中的不足基準時脈的週期的成分的資料。Each of the plurality of count delay sections 114 receives the timing data and the timing enable signal distributed by the distribution section 112. Each of the plurality of count delay units 114 separates the received time-series data into: a data portion indicating a delay time in units of a period greater than or equal to a reference clock, which is included in the time-series data, that is, an upper-side data, and the The data portion other than the upper side data contained in the time series data, that is, the lower side data. As an example, the upper side data may be data indicating a delay time from the timing of receiving the time series data to the generation timing of the timing signal in terms of the accuracy of the period unit of the reference clock. The lower side data may be data indicating a component of the period of the delay time that is less than the reference clock period.

多個計數延遲部114的各個自接收到有效的時序資料的時序開始，與該時序資料的一部分中所含的上位側資料相應地對基準時脈進行計數。並且，多個計數延遲部114的各個自接收到時序資料的時序開始，與上位側資料相應地對基準時脈進行計數之後，輸出時序賦能信號。進而，多個計數延遲部114的各個與時序賦能信號同步地輸出該時序資料中所含的下位側資料。Each of the plurality of count delay units 114 counts the reference clock from the upper side data included in a part of the time series data, starting from the timing at which the valid time series data is received. Further, each of the plurality of count delay units 114 starts counting the timing data, and counts the reference clock in accordance with the upper side data, and then outputs the timing enable signal. Further, each of the plurality of count delay units 114 outputs the lower side data included in the time series data in synchronization with the timing enable signal.

第一合成部116將自多個計數延遲部114的各個輸出的時序賦能信號多重合成為一個信號，並供給至微延遲部120。作為一例，第一合成部116藉由OR演算而將自多個計數延遲部114的各個所輸出的時序賦能信號合成為一個信號，並供給至微延遲部120。The first synthesizing unit 116 multiplexes the timing enable signals output from the respective count delay units 114 into one signal, and supplies them to the micro delay unit 120. As an example, the first synthesizing unit 116 synthesizes the timing enable signals output from the plurality of count delay units 114 into one signal by the OR calculation, and supplies them to the micro delay unit 120.

第二合成部118將自多個計數延遲部114的各個所輸出的時序資料中包含的下位側資料多重合成為一個信號，而供給至微延遲部120。作為一例，第二合成部118藉由OR演算而將自多個計數延遲部114的各個所輸出的下位側資料多重合成為一個信號，並供給至微延遲部120。再者，在其他分配部112輸出有效的下位側資料的情況時，多個計數延遲部114的各個輸出0而作為下位側資料。The second synthesizing unit 118 multiplexes the lower side data included in the time series data output from each of the plurality of count delay units 114 into one signal, and supplies the data to the micro delay unit 120. As an example, the second synthesizing unit 118 multiplexes the lower side data output from each of the plurality of count delay units 114 into one signal by the OR calculation, and supplies the data to the micro delay unit 120. In the case where the other allocation unit 112 outputs the valid lower side data, each of the plurality of count delay units 114 outputs 0 as the lower side data.

微延遲部120使自第一合成部116接收到的時序賦能信號相應地延遲與自第二合成部118接收的時序資料中所包含的下位側資料相對應的時間。微延遲部120可為：使接收到的信號相應地延遲與所給予的設定值相應的時間的可變延遲器件。微延遲部120將延遲的時序賦能信號作為表示在與被測試元件200之間授受信號的時序的時序信號，而供應至後段的波形成形部26或者時序比較器32。The micro-delay unit 120 delays the timing enable signal received from the first synthesizing unit 116 by the time corresponding to the lower-side data included in the time series data received from the second synthesizing unit 118. The micro delay unit 120 may be a variable delay device that delays the received signal by a time corresponding to the given set value. The micro delay unit 120 supplies the delayed timing enable signal to the waveform shaping unit 26 or the timing comparator 32 of the subsequent stage as a timing signal indicating the timing at which the signal is transmitted and received with the device under test 200.

根據此種構成的時序產生器24，可藉由多個計數延遲部114而使時序賦能信號以基準時脈的週期精度受到延遲。進而，根據此種時序產生器24，可藉由微延遲部120來使藉由多個計數延遲部114的各個而延遲的時序賦能信號、進一步以不足基準時脈的週期的精度受到延遲。According to the timing generator 24 having such a configuration, the timing enable signal can be delayed by the period precision of the reference clock by the plurality of count delay sections 114. Further, according to the timing generator 24, the micro-delay unit 120 can delay the timing enable signal delayed by each of the plurality of count delay units 114 and further reduce the accuracy of the period of the reference clock.

圖10之(A)~(E)表示輸入至多個計數延遲部114的時序賦能信號的時序圖的一例。圖10之(A)表示基準時脈。圖10之(B)表示分配部112所接收的時序賦能信號。(A) to (E) of FIG. 10 show an example of a timing chart of the timing enable signal input to the plurality of count delay sections 114. (A) of Fig. 10 shows a reference clock. (B) of FIG. 10 shows the timing enable signal received by the distribution unit 112.

圖10之(C)表示第一計數延遲部114-1自分配部112接收的時序賦能信號。圖10之(D)表示第二計數延遲部114-2自分配部112接收的時序賦能信號。圖10之(E)表示第三計數延遲部114-3自分配部112接收的時序賦能信號。(C) of FIG. 10 shows a timing enable signal received from the distribution unit 112 by the first counting delay unit 114-1. (D) of FIG. 10 shows a timing enable signal received from the distribution unit 112 by the second counting delay unit 114-2. (E) of FIG. 10 shows a timing enable signal received from the distribution unit 112 by the third counting delay unit 114-3.

每當自時序資料產生部110接收時序賦能信號時，分配部112逐個地依次選擇多個計數延遲部114並分配所接收到的時序賦能信號。例如，分配部112如圖10之(C)所示，將在時刻t21時接收的時序賦能信號分配至第一計數延遲部114-1。而且，分配部112如圖10之(D)所示，將在時刻t21的下一個時刻t22時接收的時序賦能信號分配至第二計數延遲部114-2。而且，分配部112如圖10之(E)所示，將在時刻t22的下一個時刻t23時接收的時序賦能信號分配至第三計數延遲部114-3。Each time the timing data generation unit 110 receives the timing enable signal, the distribution unit 112 sequentially selects the plurality of count delay units 114 one by one and allocates the received timing enable signal. For example, the distribution unit 112 assigns the timing enable signal received at time t21 to the first count delay unit 114-1 as shown in FIG. 10(C). Further, as shown in (D) of FIG. 10, the distribution unit 112 distributes the timing enable signal received at the next time t22 at time t21 to the second count delay unit 114-2. Further, as shown in FIG. 10(E), the distribution unit 112 assigns the timing enable signal received at the next time t23 at the time t22 to the third count delay unit 114-3.

圖11之(A)~(H)表示自多個計數延遲部114輸出的時序賦能信號以及下位側資料的時序圖的一例。(A) to (H) of FIG. 11 show an example of a timing chart of the timing enable signal and the lower side data output from the plurality of count delay units 114.

圖11之(A)表示自第一計數延遲部114-1輸出的時序賦能信號。圖11之(B)表示自第一計數延遲部114-1輸出的下位側資料。圖11之(C)表示自第二計數延遲部114-2輸出的時序賦能信號。圖11之(D)表示自第二計數延遲部114-2輸出的下位側資料。圖11之(E)表示自第三計數延遲部114-3輸出的時序賦能信號。圖11之(F)表示自第三計數延遲部114一3輸出的下位側資料。(A) of Fig. 11 shows a timing enable signal output from the first count delay unit 114-1. (B) of Fig. 11 shows the lower side data output from the first counting delay unit 114-1. (C) of Fig. 11 shows the timing enable signal output from the second count delay portion 114-2. (D) of Fig. 11 shows the lower side data output from the second counting delay unit 114-2. (E) of Fig. 11 shows the timing enable signal output from the third count delay portion 114-3. (F) of Fig. 11 shows the lower side data outputted from the third counting delay unit 114-3.

圖11之(E)表示自第一合成部116輸出的時序賦能信號。圖11之(F)表示自第二合成部118輸出的下位側資料。(E) of FIG. 11 shows the timing enable signal output from the first synthesizing section 116. (F) of Fig. 11 shows the lower side data output from the second synthesizing unit 118.

第一合成部116將自多個計數延遲部114的各個所各別地輸出的時序賦能信號多重合成為一個信號，並供給至微延遲部120。同樣地，第二合成部118將自多個計數延遲部114的各個所各別地輸出的時序資料中所包含的下位側資料多重合成為一個信號，並供給至微延遲部120。The first synthesizing unit 116 multiplexes the timing energizing signals respectively output from the respective plurality of counting delay units 114 into one signal, and supplies them to the micro delay unit 120. Similarly, the second synthesizing unit 118 multiplexes the lower side data included in the time series data output from each of the plurality of count delay units 114 into one signal, and supplies the data to the micro delay unit 120.

如此，分配部112逐個巡迴地選擇多個計數延遲部114，並交錯(interleave)地執行基準時脈的週期單位的延遲處理。藉此，根據時序產生器24，即使在某個測試週期中指定的時序信號超過該測試週期、而在下一個測試週期範圍內產生，結果導致在下一個測試週期的範圍內產生多個時序信號的情況時，亦可持續產生時序信號而不會使動作出現破綻。In this manner, the allocating unit 112 selects the plurality of counting delay units 114 one by one, and interleaves the delay processing of the period unit of the reference clock. Thereby, according to the timing generator 24, even if the timing signal specified in a certain test period exceeds the test period and is generated within the next test period, the result is that a plurality of timing signals are generated within the range of the next test period. At the same time, timing signals can be continuously generated without causing flaws in the action.

圖12表示計數延遲部114的構成。多個計數延遲部114的各個具有相同的構成。計數延遲部114包括：計數部140、狀態保持部142、以及第二時脈閥部144。FIG. 12 shows the configuration of the count delay unit 114. Each of the plurality of count delay sections 114 has the same configuration. The counting delay unit 114 includes a counting unit 140, a state holding unit 142, and a second clock valve unit 144.

計數部140與自第二時脈閥部144給予的基準時脈同步地動作。計數部140在自時序資料產生部110接收到有效的時序資料後，與該時序資料中包含的、以大於等於基準時脈的週期的單位來表示時間的上位側資料相應地對基準時脈進行計數之後，輸出該時序資料的上位側資料以外的下位側資料以及表示該時序資料有效的時序賦能信號。作為一例，計數部140在狀態保持部142保持有：表示處於計數中的狀態信號，且計數值達到對上位側資料數進行計數之後的值的情況時，可輸出表示時序資料有效的時序賦能信號。The counting unit 140 operates in synchronization with the reference clock given from the second clock valve unit 144. After receiving the valid time series data from the time series data generating unit 110, the counting unit 140 performs the reference clock on the upper side data indicating the time in units of the period equal to or longer than the reference clock, which is included in the time series data. After the counting, the lower side data other than the upper side data of the time series data and the timing enable signal indicating that the time series data is valid are output. As an example, when the state holding unit 142 holds a state signal indicating that the count value has reached a value after counting the number of data on the upper side, the counting unit 140 can output a timing enable indicating that the time series data is valid. signal.

作為一例，計數部140可包括：零探測部150、反轉電路152、計數器154、第一AND電路156、第一正反器158、以及第二AND電路160。零探測部150在計數器154的計數值為0的情況時輸出表示有效的信號，在計數器154的計數值為0以外的情況時輸出表示無效的信號。反轉電路152將零探測部150的輸出信號的邏輯反轉，並給予至計數器154的DEC端子。As an example, the counting unit 140 may include a zero detecting unit 150, an inverting circuit 152, a counter 154, a first AND circuit 156, a first flip-flop 158, and a second AND circuit 160. The zero detecting unit 150 outputs a signal indicating that the counter 154 has a count value of 0, and outputs a signal indicating that the counter 154 has a count value of 0 or not. The inverting circuit 152 inverts the logic of the output signal of the zero detecting portion 150 and supplies it to the DEC terminal of the counter 154.

計數器154在自分配部112給予的時序賦能信號表示有效的情況時，獲取自時序資料產生部110輸出的時序資料的上位側資料來作為計數值。並且，計數器154在給予至DEC端子的信號表示有效的情況時(即，在計數器154的計數值為0以外的情況時)，使所獲取的計數值與所給予的基準時脈同步地逐個減少。When the timing enable signal given from the allocating unit 112 indicates that it is valid, the counter 154 acquires the upper side data of the time series data output from the time series data generating unit 110 as the count value. Further, when the signal given to the DEC terminal indicates that it is valid (that is, when the count value of the counter 154 is other than 0), the counter 154 decreases the acquired count value one by one in synchronization with the given reference clock. .

第一AND電路156在零探測部150的輸出信號表示有效、且狀態保持部142輸出的狀態信號表示有效的情況時，輸出表示有效的時序賦能信號。在自分配部112給予的時序賦能信號表示有效的情況時，第一正反器158獲取自時序資料產生部110輸出的時序資料的下位側資料。在零探測部150的輸出信號表示有效、且狀態保持部142輸出的狀態信號表示有效的情況時，第二AND電路160輸出第一正反器158所獲取的下位側資料。The first AND circuit 156 outputs a timing enable signal indicating that the output signal of the zero detecting unit 150 is valid and the state signal output from the state holding unit 142 indicates that it is valid. When the timing enable signal given from the self-allocation unit 112 indicates that it is valid, the first flip-flop 158 acquires the lower-side data of the time series data output from the time series data generating unit 110. When the output signal of the zero detecting unit 150 indicates that the state signal output by the state holding unit 142 is valid, the second AND circuit 160 outputs the lower side data acquired by the first flip-flop 158.

此種構成的計數部140可在接收到有效的時序資料之後，與該時序資料中所含的上位側資料中所示的值相應地對基準時脈進行計數，在計數之後輸出下位側資料以及表示時序資料有效的時序賦能信號。The counting unit 140 having such a configuration can count the reference clock corresponding to the value shown in the upper side data included in the time series data after receiving the valid time series data, and output the lower side data after the counting and A timing enable signal indicating that the timing data is valid.

狀態保持部142保持了表示計數部140是否處於有效的時序資料中所含的上位側資料數的計數中的狀態信號。作為一例，狀態保持部142可輸出在計數部140處於計數中的情況時表示有效、在計數部140不處於計數中的情況時表示無效的狀態信號。The state holding unit 142 holds a state signal indicating whether or not the counting unit 140 is in the count of the number of upper side data included in the valid time series data. As an example, the state holding unit 142 can output a state signal indicating that it is valid when the counting unit 140 is counting, and indicating that it is invalid when the counting unit 140 is not counting.

作為一例，狀態保持部142可包括：第一OR電路162以及第二正反器164。在計數部140的零探測部150的輸出信號表示有效的情況時(即，在計數器154的計數值為0的情況時)，或者在自分配部112所給予的時序賦能信號表示有效的情況時，第一OR電路162輸出表示有效的信號。第二正反器164與基準時脈同步地動作，在第一OR電路162的輸出信號表示有效的情況時，第二正反器164獲取自分配部112所給予的時序賦能信號。當自分配部112給予表示有效的時序賦能信號時，如此之第一OR電路162開始保持表示有效的值。並且，第一OR電路162對應於計數器154的計數值變為0而開始保持表示無效的值。隨後，第一OR電路162持續保持表示無效的值，直至下一次被給予表示有效的時序賦能信號為止。As an example, the state holding unit 142 may include a first OR circuit 162 and a second flip-flop 164. When the output signal of the zero detecting unit 150 of the counting unit 140 indicates that it is valid (that is, when the count value of the counter 154 is 0), or when the timing energizing signal given by the self-allocation unit 112 indicates that it is valid. At the time, the first OR circuit 162 outputs a signal indicating that it is valid. The second flip-flop 164 operates in synchronization with the reference clock. When the output signal of the first OR circuit 162 indicates that it is valid, the second flip-flop 164 acquires the timing enable signal given from the distribution unit 112. When the self-allocation portion 112 gives a timing enable signal indicating that it is valid, the first OR circuit 162 thus starts to hold a value indicating that it is valid. Further, the first OR circuit 162 starts to hold a value indicating that it is invalid, corresponding to the count value of the counter 154 becoming zero. Subsequently, the first OR circuit 162 continues to hold the value indicating invalid until the next time it is given a valid timing enable signal.

在計數部140未對有效的時序資料中所包含的上位側資料數進行計數的情況時，第二時脈閥部144停止對計數部140供給基準時脈。更詳細而言，第二時脈閥部144對應於接收到表示時序資料有效的時序賦能信號，而開始對計數部140供給基準時脈。並且，第二時脈閥部144對應於計數部140的計數值已達到對上位側資料數進行計數之後的值，而停止對計數部140供給基準時脈。When the counting unit 140 does not count the number of upper side data included in the valid time series data, the second clock valve unit 144 stops supplying the reference clock to the counting unit 140. More specifically, the second clock valve unit 144 starts to supply the reference clock to the counting unit 140 in response to receiving the timing enable signal indicating that the timing data is valid. Further, the second clock valve unit 144 stops the supply of the reference clock to the counting unit 140 in response to the fact that the count value of the counting unit 140 has reached the value obtained by counting the number of data on the upper side.

作為一例，第二時脈閥部144可包含：第二OR電路166以及閘極電路168。在計數部140的零探測部150的輸出信號表示無效的情況時(即，計數器154的計數值為0以外的情況時)，或者在自分配部112所給予的時序賦能信號表示有效的情況時，第二OR電路166輸出表示有效的時脈賦能信號。As an example, the second clock valve portion 144 may include a second OR circuit 166 and a gate circuit 168. When the output signal of the zero detecting unit 150 of the counting unit 140 indicates that it is invalid (that is, when the count value of the counter 154 is other than 0), or when the timing energizing signal given by the self-allocation unit 112 indicates that it is valid. At the time, the second OR circuit 166 outputs a clock enable signal indicating that it is valid.

閘極電路168自第二OR電路166接收時脈賦能信號。並且，在時脈賦能信號表示有效的情況時(即，計數器154的計數值為0以外的情況時、或者自分配部112所給予的時序賦能信號表示有效的情況時)，閘極電路168向計數部140內的計數器154以及第一正反器158供給基準時脈。在時脈賦能信號表示無效的情況時，閘極電路168停止向計數部140內的計數器154以及第一正反器158供給基準時脈。Gate circuit 168 receives a clock enable signal from second OR circuit 166. Further, when the clock enable signal indicates that it is valid (that is, when the count value of the counter 154 is other than 0, or when the timing enable signal given from the distribution unit 112 indicates that it is valid), the gate circuit 168 supplies the reference clock to the counter 154 and the first flip-flop 158 in the counting unit 140. When the clock enable signal indicates that it is invalid, the gate circuit 168 stops supplying the reference clock to the counter 154 and the first flip-flop 158 in the counting unit 140.

更詳細而言，第二時脈閥部144對應於接收到表示時序資料有效的時序賦能信號，而開始對計數器154以及第一正反器158供給基準時脈。並且，第二時脈閥部144對應於計數器154的計數值已達到0，而停止對計數器154以及第一正反器158供給基準時脈。In more detail, the second clock valve unit 144 starts to supply the reference clock to the counter 154 and the first flip-flop 158 in response to receiving the timing enable signal indicating that the timing data is valid. Further, the second clock valve portion 144 stops supplying the reference clock to the counter 154 and the first flip-flop 158 corresponding to the count value of the counter 154 having reached zero.

如此之計數延遲部114，在計數部140有效地動作的期間對該計數部140供給基準時脈，在計數部140未有效地動作的期間停止對該計數部140供給基準時脈。藉此，計數延遲部114可降低計數部140的消耗電流。The counting delay unit 114 supplies the reference clock to the counting unit 140 while the counting unit 140 is operating normally, and stops the supply of the reference clock to the counting unit 140 while the counting unit 140 is not operating normally. Thereby, the counting delay unit 114 can reduce the current consumption of the counting unit 140.

圖13之(A)~(I)表示計數延遲部114內的各信號的時序圖的一例。圖13之(A)表示基準時脈。圖13之(B)表示計數延遲部114所接收的時序賦能信號。圖13之(C)表示計數延遲部114所接收的時序賦能信號。圖13之(D)表示計數器154的計數值。(A) to (I) of FIG. 13 show an example of a timing chart of each signal in the count delay unit 114. (A) of Fig. 13 shows a reference clock. (B) of FIG. 13 shows the timing enable signal received by the count delay unit 114. (C) of FIG. 13 shows the timing enable signal received by the counting delay unit 114. (D) of Fig. 13 shows the count value of the counter 154.

圖13之(E)表示第二正反器164所輸出的狀態信號。圖13之(F)表示第一正反器158所保持的下位側資料。圖13之(G)表示給予至計數器154以及第一正反器158的基準時脈。圖13之(H)表示計數延遲部114所輸出的時序賦能信號。圖13之(I)表示計數延遲部114所輸出的下位側資料。(E) of FIG. 13 shows a state signal output from the second flip-flop 164. (F) of Fig. 13 shows the lower side data held by the first flip-flop 158. (G) of FIG. 13 shows the reference clocks given to the counter 154 and the first flip-flop 158. (H) of FIG. 13 shows the timing enable signal output from the counting delay unit 114. (I) of FIG. 13 shows the lower side data output by the counting delay unit 114.

計數延遲部114如圖13之(B)所示，於時刻t41時自分配部112接收表示有效的時序賦能信號。當自分配部112接收到表示有效的時序賦能信號時，第二正反器164如圖13之(E)所示般，自下一個基準時脈的時序開始保持表示有效的值。As shown in FIG. 13(B), the count delay unit 114 receives a timing enable signal indicating that it is valid from the allocating unit 112 at time t41. When the self-allocation unit 112 receives the timing enable signal indicating that it is valid, the second flip-flop 164 maintains a value indicating that it is valid from the timing of the next reference clock as shown in FIG. 13(E).

而且，當自分配部112接收到表示有效的時序賦能信號時，閘極電路168如圖13之(G)所示般，於下一個基準時脈的時序(時刻t42)開始對計數器154以及第一正反器158供給基準時脈(gclk)。其結果是，計數器154如圖13之(D)所示般，取入接收到時序賦能信號的時序中的時序資料的上位側資料(例如0x8)來作為計數值，隨後，逐個減少(decrement)計數值。而且，第一正反器158如圖13之(F)所示般，取入接收到時序賦能信號的時序中的時序資料的下位側資料(例如0xC)。Further, when the self-allocation unit 112 receives the timing enable signal indicating that it is valid, the gate circuit 168 starts the counter 154 at the timing of the next reference clock (time t42) as shown in (G) of FIG. The first flip-flop 158 supplies a reference clock (gclk). As a result, as shown in (D) of FIG. 13, the counter 154 takes in the upper side data (for example, 0x8) of the time series data in the timing at which the timing enable signal is received as the count value, and then decreases one by one (decrement). ) count value. Further, as shown in (F) of FIG. 13, the first flip-flop 158 takes in the lower side data (for example, 0xC) of the time series data in the timing at which the timing enable signal is received.

第一AND電路156如圖13之(H)所示般，在計數器154的計數值達到0的時刻t43時，輸出時序賦能信號。而且，第二AND電路160如圖13之(I)所示般，與第一AND電路156輸出時序賦能信號同步地輸出第一正反器158所保持的下位側資料。As shown in (H) of FIG. 13, the first AND circuit 156 outputs a timing enable signal when the count value of the counter 154 reaches 0 at time t43. Further, as shown in (I) of FIG. 13, the second AND circuit 160 outputs the lower side data held by the first flip-flop 158 in synchronization with the output timing enable signal of the first AND circuit 156.

並且，閘極電路168如圖13之(G)所示般，當計數器154的計數值達到0時，在下一個基準時脈的時序(時刻t44)停止對計數器154以及第一正反器158供給基準時脈(gclk)。而且，第二正反器164如圖13之(E)所示般，當計數器154的計數值達到0時，自下一個基準時脈的時序開始保持表示無效的值。Further, as shown in (G) of FIG. 13, when the count value of the counter 154 reaches 0, the gate circuit 168 stops supplying the counter 154 and the first flip-flop 158 at the timing of the next reference clock (time t44). Reference clock (gclk). Further, as shown in (E) of FIG. 13, when the count value of the counter 154 reaches 0, the second flip-flop 164 maintains a value indicating that it is invalid from the timing of the next reference clock.

如此，計數延遲部114可在計數部140有效地動作的期間對該計數部140供給基準時脈，在計數部140未有效地動作的期間停止對該計數部140供給基準時脈。藉此，計數延遲部114可降低計數部140的消耗電流。In this manner, the counting delay unit 114 can supply the reference clock to the counting unit 140 while the counting unit 140 is operating normally, and stop supplying the reference clock to the counting unit 140 while the counting unit 140 is not operating normally. Thereby, the counting delay unit 114 can reduce the current consumption of the counting unit 140.

進而，上述計數延遲部114亦可作為計數電路而包含於測試裝置10以外的其他裝置中。即，計數延遲部114可作為對自發送電路所給予的資料進行計數的計數電路而發揮作用。Further, the counting delay unit 114 may be included in other devices than the testing device 10 as a counting circuit. That is, the count delay unit 114 can function as a counter circuit that counts data given from the transmission circuit.

在此情況時，計數延遲部114取代自時序資料產生部110接收時序資料以及時序賦能信號，而自發送電路接收資料以及資料賦能信號。並且，計數延遲部114取代輸出時序賦能信號，而輸出資料賦能信號。藉此，根據計數延遲部114，即使在對藉由自發送電路所給予的資料而表示的資料數進行計數的情況時亦可降低消耗電力。In this case, the count delay unit 114 receives the timing data and the timing enable signal instead of the timing data generation unit 110, and receives the data and the data enable signal from the transmission circuit. Further, the count delay unit 114 outputs a data enable signal instead of the output timing enable signal. Thereby, the count delay unit 114 can reduce the power consumption even when the number of pieces of data indicated by the data given from the transmission circuit is counted.

以上使用實施形態對發明進行了說明，但發明的技術範圍並不限定於上述實施形態中揭示的範圍內。本領域技術人員應明確的是，於上述實施形態中可添加各種變更或改良。由申請專利範圍當明確，添加此種變更或改良的實施形態亦可包含於發明的技術範圍內。The invention has been described above using the embodiments, but the technical scope of the invention is not limited to the scope disclosed in the above embodiments. It will be apparent to those skilled in the art that various modifications and improvements can be added to the above embodiments. It is to be understood that the scope of the patent application is intended to be included in the technical scope of the invention.

應留意的是，申請專利範圍、說明書以及圖式中所示的裝置、系統、程式(program)以及方法中的動作、程序、步驟以及階段等的各處理的執行順序只要未特別明示「最先」、「首先」等，而且只要未在後處理中用到前處理的輸出，則可按任意的順序來實現。關於申請專利範圍、說明書以及圖式中的動作流程，即便為了方便起見而使用了「首先」、「其次」等來進行說明，亦並不意味著必需以此順序來實施。It should be noted that the order of execution of the processes, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, the description, and the drawings is not specifically stated as the first. ", first", etc., and as long as the pre-processed output is not used in post-processing, it can be implemented in any order. The operation flow in the patent application scope, the specification, and the drawings, even if it is used for the sake of convenience, "first", "second", etc., does not mean that it must be implemented in this order.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10．．．測試裝置10. . . Test device

20．．．圖案產生部20. . . Pattern generation department

22．．．測試週期產生器twenty two. . . Test cycle generator

24．．．時序產生器twenty four. . . Timing generator

26．．．波形成形部26. . . Waveform forming department

28．．．驅動器28. . . driver

30．．．位準比較器30. . . Level comparator

32．．．時序比較器32. . . Timing comparator

34．．．判定部34. . . Judgment department

38．．．週期產生部38. . . Cycle generation department

40．．．傳送電路40. . . Transmission circuit

42．．．下位位元獲取用正反器42. . . Lower bit acquisition flip-flop

44．．．上位位元獲取用正反器44. . . Upper bit acquisition flip-flop

46．．．測試週期信號獲取用正反器46. . . Test cycle signal acquisition flip-flop

48．．．資料獲取部48. . . Data acquisition department

50．．．檢測部50. . . Detection department

52．．．時脈賦能信號傳送電路52. . . Clock shaping signal transmission circuit

54．．．第一時脈閥部54. . . First clock valve

56．．．資料切換部56. . . Data switching department

58．．．測試週期信號傳送電路58. . . Test cycle signal transmission circuit

60．．．下位位元傳送電路60. . . Lower bit transfer circuit

62．．．上位位元傳送電路62. . . Upper bit transfer circuit

64、64-1~64-n、66、66-1~66-n、76、76-1~76-n、80、80-1~80-n．．．正反器64, 64-1~64-n, 66, 66-1~66-n, 76, 76-1~76-n, 80, 80-1~80-n. . . Positive and negative

68．．．資料切換部內AND電路68. . . AND circuit in data switching unit

72．．．檢測部內OR電路72. . . Detection unit internal OR circuit

74．．．檢測部內AND電路74. . . In-circuit AND circuit

78、78-1~78-n、168．．．閘極電路78, 78-1~78-n, 168. . . Gate circuit

110．．．時序資料產生部110. . . Timing data generation department

112‧‧‧分配部112‧‧‧Distribution Department

114、114-1~114-m‧‧‧計數延遲部114, 114-1~114-m‧‧‧ Counting delay

116‧‧‧第一合成部116‧‧‧First Synthesis Department

118‧‧‧第二合成部118‧‧‧Second Synthesis Department

120‧‧‧微延遲部120‧‧‧Micro Delay Department

132‧‧‧加算部132‧‧‧Additional Department

140‧‧‧計數部140‧‧‧Counting Department

142‧‧‧狀態保持部142‧‧‧State Maintenance Department

144‧‧‧第二時脈閥部144‧‧‧Second clock valve

150‧‧‧零探測部150‧‧‧ Zero Detection Department

152‧‧‧反轉電路152‧‧‧Reversing circuit

154‧‧‧計數器154‧‧‧ counter

156‧‧‧第一AND電路156‧‧‧First AND circuit

158‧‧‧第一正反器158‧‧‧First forward and reverse

160‧‧‧第二AND電路160‧‧‧Second AND circuit

162‧‧‧第一OR電路162‧‧‧First OR circuit

164‧‧‧第二正反器164‧‧‧second flip-flop

166‧‧‧第二OR電路166‧‧‧Second OR circuit

200‧‧‧被測試元件200‧‧‧tested components

t21、t22、t23、t41、t42、t43、t44‧‧‧時刻T21, t22, t23, t41, t42, t43, t44‧‧‧

圖1一併表示本實施形態的測試裝置10的構成與被測試元件200。Fig. 1 also shows the configuration of the test apparatus 10 of the present embodiment and the device under test 200.

圖2表示測試週期產生器22輸出的測試週期資料的位元構成的一例。FIG. 2 shows an example of the bit structure of the test period data outputted by the test period generator 22.

圖3之(A)~(C)表示基準時脈、測試週期產生器22輸出的測試週期資料以及測試週期信號。(A) to (C) of FIG. 3 indicate the reference clock, the test period data output by the test period generator 22, and the test period signal.

圖4表示本實施形態的測試週期產生器22的構成。Fig. 4 shows the configuration of the test cycle generator 22 of the present embodiment.

圖5表示本實施形態的傳送電路40的構成。Fig. 5 shows the configuration of the transmission circuit 40 of this embodiment.

圖6表示資料獲取部48以及資料切換部56的構成的一例。FIG. 6 shows an example of the configuration of the material acquisition unit 48 and the data switching unit 56.

圖7表示檢測部50、時脈賦能信號傳送電路52、第一時脈閥部54以及測試週期信號傳送電路58的構成的一例。FIG. 7 shows an example of the configuration of the detecting unit 50, the clock enable signal transmitting circuit 52, the first clock valve unit 54, and the test period signal transmission circuit 58.

圖8之(A)~(N)表示傳送電路40內的各信號的時序圖的一例。(A) to (N) of FIG. 8 show an example of a timing chart of each signal in the transmission circuit 40.

圖9表示本實施形態的時序產生器24的構成。Fig. 9 shows the configuration of the timing generator 24 of the present embodiment.

圖10之(A)~(E)表示輸入至多個計數延遲部114的時序賦能信號的時序圖的一例。(A) to (E) of FIG. 10 show an example of a timing chart of the timing enable signal input to the plurality of count delay sections 114.

圖11之(A)~(H)表示自多個計數延遲部114輸出的時序賦能信號以及下位側資料的時序圖的一例。(A) to (H) of FIG. 11 show an example of a timing chart of the timing enable signal and the lower side data output from the plurality of count delay units 114.

圖12表示計數延遲部114的構成。FIG. 12 shows the configuration of the count delay unit 114.

圖13之(A)~(I)表示計數延遲部114內的各信號的時序圖的一例。(A) to (I) of FIG. 13 show an example of a timing chart of each signal in the count delay unit 114.

10．．．測試裝置10. . . Test device

20．．．圖案產生部20. . . Pattern generation department

22．．．測試週期產生器twenty two. . . Test cycle generator

24．．．時序產生器twenty four. . . Timing generator

26．．．波形成形部26. . . Waveform forming department

28．．．驅動器28. . . driver

30．．．位準比較器30. . . Level comparator

32．．．時序比較器32. . . Timing comparator

34．．．判定部34. . . Judgment department

200．．．被測試元件200. . . Tested component

Claims (14)

一種測試裝置，對被測試元件進行測試，上述測試裝置包括：測試週期產生器，與基準時脈同步地產生測試週期信號以及測試週期資料，其中，上述測試週期信號表示成為測試週期的開始時序的基準的時序，上述測試週期資料表示自上述測試週期信號至測試週期的開始時序為止的延遲量；以及時序產生器，將由上述測試週期資料指定的測試週期的開始時序作為基準，而產生在與上述被測試元件之間授受信號的時序，且上述測試週期產生器包括：週期產生部，產生上述測試週期資料以及上述測試週期信號；資料獲取部，與上述基準時脈同步地獲取上述測試週期資料，並向上述時序產生器輸出；檢測部，檢測上述週期產生部所產生的上述測試週期資料中的上位位元的預定數量是否為0；以及時脈閥部，在未產生上述測試週期信號的情況時，或者在上述檢測部檢測出上述測試週期資料的上述上位位元為0的情況時，停止對上述資料獲取部供給上述基準時脈，以致於防止上述上位位元的獲取。 A test device for testing a component under test, the test device comprising: a test cycle generator for generating a test cycle signal and a test cycle data in synchronization with a reference clock, wherein the test cycle signal is indicative of a start timing of the test cycle a timing of the reference, wherein the test period data indicates a delay amount from the test period signal to a start timing of the test period; and the timing generator generates a start timing of the test period specified by the test period data as a reference The timing of the signal is received between the tested components, and the test cycle generator includes: a cycle generating unit that generates the test cycle data and the test cycle signal; and a data acquisition unit that acquires the test cycle data in synchronization with the reference clock. And outputting to the timing generator; the detecting unit detects whether a predetermined number of upper bits in the test period data generated by the period generating unit is 0; and the clock valve unit does not generate the test period signal When, or in the above inspection When the detecting unit detects that the upper bit of the test period data is 0, the sampling unit stops supplying the reference clock to the data acquiring unit, so that the acquisition of the upper bit is prevented. 如申請專利範圍第1項所述之測試裝置，其中，上述時脈閥部在未產生上述測試週期信號的週期的 情況時，或者在檢測出上述測試週期資料中的上述至少一個位元與上述預定值一致的情況時，停止供給上述資料獲取部用於獲取上述至少一個位元的上述基準時脈，上述測試週期產生器更包括：資料切換部，在檢測出上述測試週期資料中的上述至少一個位元與上述預定值相一致的情況時，將上述預定值取代來自上述資料獲取部的上述至少一個位元而向上述時序產生器供給。 The test device of claim 1, wherein the clock valve portion is in a period in which the test period signal is not generated. In a case, or when detecting that the at least one bit in the test period data matches the predetermined value, stopping the supply of the reference data acquisition unit for acquiring the reference clock of the at least one bit, the test period The generator further includes: a data switching unit that replaces the at least one bit from the data acquiring unit when detecting that the at least one bit in the test period data matches the predetermined value It is supplied to the above timing generator. 如申請專利範圍第2項所述之測試裝置，其中，上述週期產生部產生上述測試週期資料以及上述測試週期信號，上述測試週期資料包括：上述上位位元以及下位位元，其中，上述上位位元表示在至測試週期的開始時序為止的時間中的大於上述基準時脈的週期的單位的時間，上述下位位元表示小於等於上述基準時脈的週期的單位的時間，上述資料切換部在檢測出上述測試週期資料的上述上位位元為0的情況時，將0取代來自上述資料獲取部的上述上位位元而供給至上述時序產生器。 The test apparatus of claim 2, wherein the period generating unit generates the test period data and the test period signal, wherein the test period data includes: the upper bit and a lower bit, wherein the upper bit The element indicates a time greater than a unit of a period of the reference clock in a time from the start timing of the test period, and the lower bit indicates a time equal to or less than a unit of a period of the reference clock, and the data switching unit detects When the upper bit of the test cycle data is 0, the upper bit from the data acquisition unit is replaced with 0 and supplied to the timing generator. 如申請專利範圍第3項所述之測試裝置，其中，上述資料獲取部包括：下位位元傳送電路，與上述基準時脈同步地藉由最前段的正反器而獲取上述測試週期資料的上述下位位元，且依序向後段的正反器傳播，並自最終段的正反器向上述時序產生器輸出；以及 上位位元傳送電路，與上述基準時脈同步地藉由最前段的正反器而獲取上述測試週期資料的上述上位位元，且依序向後段的正反器傳播，並自最終段的正反器向上述時序產生器輸出，且上述測試週期產生器包括：時脈賦能信號傳送電路，與上述基準時脈同步地藉由最前段的正反器而獲取表示是否供給用於獲取上述上位位元的上述基準時脈的時脈賦能信號，並依序向後段的正反器傳播；以及測試週期信號傳送電路，與上述基準時脈同步地藉由最前段的正反器而獲取上述測試週期信號，且依序向後段的正反器傳播，並自最終段的正反器向上述時序產生器輸出，且上述時脈閥部在藉由上述時脈賦能信號傳送電路而傳播的某段上述時脈賦能信號表示停止供給上述基準時脈的情況時，停止對上述上位位元傳送電路中的下一段正反器供給上述基準時脈。 The test apparatus according to claim 3, wherein the data acquisition unit includes: a lower bit transfer circuit that acquires the test cycle data by the frontmost flip-flop in synchronization with the reference clock a lower bit, and sequentially propagates to the rear of the flip-flop, and outputs from the flip-flop of the final segment to the timing generator; and The upper bit transfer circuit acquires the upper bit of the test period data by the front-end flip-flop in synchronization with the reference clock, and sequentially propagates to the rear-stage flip-flop, and from the final segment The counter is output to the timing generator, and the test period generator includes: a clock enable signal transmitting circuit that acquires, by the front-end flip-flop, synchronously with the reference clock to indicate whether or not the supply is for acquiring the upper level a clock enable signal of the above reference clock of the bit, and sequentially propagates to the flip-flop of the subsequent stage; and a test period signal transmission circuit that acquires the above by the front-end flip-flop in synchronization with the reference clock Testing the periodic signal, and sequentially propagating to the rear-stage flip-flop, and outputting from the flip-flop of the final segment to the timing generator, and the clock valve portion is propagated by the clock-energy signal transmitting circuit When a certain period of the clock enable signal indicates that the supply of the reference clock is stopped, the supply of the reference clock to the next flip-flop in the upper bit transfer circuit is stopped. 如申請專利範圍第4項所述之測試裝置，其中，上述資料切換部在自上述時脈賦能信號傳送電路的最終段接收到表示停止供給上述基準時脈的上述時脈賦能信號的情況時，將0取代自上述上位位元傳送電路的最終段所輸出的上述測試週期資料的上述上位位元，而輸出至上述時序產生器。 The test apparatus according to claim 4, wherein the data switching unit receives the clock enable signal indicating that the supply of the reference clock is stopped from the final stage of the clock enable signal transmission circuit. At this time, 0 is substituted for the upper bit of the test period data output from the final stage of the upper bit transfer circuit, and is output to the timing generator. 一種傳送電路，將資料以及表示上述資料是否有效 的資料賦能信號自發送電路向接收電路傳送，上述資料包含：預定數量的上位位元，上述上位位元表示大於基準時脈的週期的期間的單位的時間；以及一或多個下位位元，上述下位位元表示小於等於上述基準時脈的週期的期間的單位的時間，上述傳送電路更包括：資料獲取部，與基準時脈同步地自上述發送電路獲取上述資料，並向上述接收電路輸出；檢測部，檢測週期產生部所產生的測試週期資料中的上述上位位元的預定數量是否為0；以及時脈閥部，在自上述發送電路接收到表示上述資料為無效的上述資料賦能信號的情況時，或者在上述檢測部檢測出上述資料的上述上位位元為0的情況時，停止對上述資料獲取部供給上述基準時脈，以致於防止上述上位位元的獲取。 A transmission circuit that records data and indicates whether the above data is valid The data enable signal is transmitted from the transmitting circuit to the receiving circuit, the data comprising: a predetermined number of upper bits, the upper bit indicating a time greater than a period of the period of the reference clock; and one or more lower bits The lower bit indicates a time unit that is less than or equal to a period of the period of the reference clock, and the transmission circuit further includes: a data acquisition unit that acquires the data from the transmission circuit in synchronization with the reference clock and to the receiving circuit And a detection unit that detects whether the predetermined number of the upper bits in the test period data generated by the detection period generating unit is 0; and the clock valve unit receives the data indicating that the data is invalid from the transmitting circuit In the case of the energy signal, or when the detection unit detects that the upper bit of the data is 0, the supply of the reference clock to the data acquisition unit is stopped, so that the acquisition of the upper bit is prevented. 如申請專利範圍第6項所述之傳送電路，更包括：檢測部，檢測上述資料中的預定的至少一個位元是否與預定值相一致，且上述時脈閥部在自上述發送電路接收到表示上述資料為無效的上述資料賦能信號的情況時，或者檢測出上述資料中的上述至少一個位元與上述預定值相一致的情況時，停止供給上述資料獲取部用於獲取上述至少一個位元的上述基準時脈，上述傳送電路更包括：資料切換部，在檢測出上述資 料中的上述至少一個位元與上述預定值相一致的情況時，將上述預定值取代來自上述資料獲取部的上述至少一個位元而供給至上述接收電路。 The transmission circuit of claim 6, further comprising: a detecting unit, detecting whether a predetermined at least one bit in the data matches a predetermined value, and the clock valve portion is received from the transmitting circuit When the data enabling signal is invalid, or when detecting that the at least one bit in the data matches the predetermined value, the supply of the data acquiring unit is stopped to acquire the at least one bit. The above reference clock of the element, the transmission circuit further includes: a data switching unit that detects the above-mentioned resources When the at least one bit in the material matches the predetermined value, the predetermined value is supplied to the receiving circuit instead of the at least one bit from the data acquiring unit. 一種測試裝置，對被測試元件進行測試，上述測試裝置包括：時序資料產生部，產生時序資料以及時序賦能信號，其中，上述時序資料對表示在與上述被測試元件之間授受信號的時序的時序信號的產生時序進行指定，上述時序賦能信號表示上述時序資料是否有效；計數部，與基準時脈同步動作，自上述時序資料產生部接收有效的上述時序資料之後，與該時序資料中所含的以大於等於上述基準時脈的週期的單位來表示時間的上位側資料數相應地對基準時脈進行計數之後，上述計數部輸出該時序資料的上述上位側資料以外的下位側資料、以及表示該時序資料有效的上述時序賦能信號；以及時脈閥部，在上述計數部未對有效的上述時序資料中所含的上述上位側資料數進行計數的情況時，停止對上述計數部供給上述基準時脈。 A test device for testing a component to be tested, the test device comprising: a timing data generating section, generating timing data and a timing enable signal, wherein the timing data pair indicates a timing of receiving and receiving a signal between the component to be tested The timing signal generation timing is specified, and the timing enable signal indicates whether the timing data is valid; the counting unit operates in synchronization with the reference clock, and after receiving the valid timing data from the timing data generation unit, and the timing data The counting unit displays the number of upper side data indicating the time in units of the period of the reference clock, and the counting unit outputs the lower side data other than the upper side data of the time series data, and The timing enable signal indicating that the time series data is valid; and the clock valve unit stops supplying the counting unit when the counting unit does not count the number of the upper side data included in the valid time series data. The above reference clock. 如申請專利範圍第8項所述之測試裝置，其中，上述時脈閥部對應於接收到表示上述時序資料有效的上述時序賦能信號，而開始對上述計數部供給上述基準時脈，對應於上述計數部的計數值達到對上述上位側資料數進行計數之後的值，而停止對上述計數部供給上述基準時脈。 The test apparatus according to claim 8, wherein the clock valve unit starts to supply the reference clock to the counting unit in response to receiving the timing enable signal indicating that the timing data is valid, and corresponds to The count value of the counting unit reaches a value obtained by counting the number of the upper side data, and the supply of the reference clock to the counting unit is stopped. 如申請專利範圍第9項所述之測試裝置，更包括：狀態保持部，保持表示上述計數部是否處於有效的上述時序資料中所含的上述上位側資料數的計數中的狀態信號，且上述計數部在上述狀態保持部保持有表示處於計數中的上述狀態信號，且計數值達到對上述上位側資料數進行計數之後的值的情況時，輸出表示上述時序資料有效的上述時序賦能信號。 The test apparatus according to claim 9, further comprising: a state holding unit that holds a state signal indicating whether the counting unit is in a count of the number of the upper side data included in the valid time series data, and the above When the state holding unit holds the state signal indicating that the count is reached, and the count value reaches a value obtained by counting the number of the upper side data, the counting unit outputs the timing enable signal indicating that the time series data is valid. 如申請專利範圍第10項所述之測試裝置，更包括：多個上述計數部、上述時脈閥部以及上述狀態保持部的組；以及分配部，將自上述時序資料產生部依序輸出的有效的上述時序資料以及表示上述時序資料有效的上述時序賦能信號分配至多個上述組的各個。 The test apparatus according to claim 10, further comprising: a plurality of the counting unit, the clock valve unit, and the state holding unit; and a distribution unit that sequentially outputs the time series data generating unit The above-described timing data that is valid and the timing enable signal indicating that the timing data is valid are allocated to each of the plurality of groups. 一種測試裝置的控制方法，上述測試裝置對被測試元件進行測試，其中，上述測試裝置包括：測試週期產生器，與基準時脈同步地產生測試週期信號以及測試週期資料，其中，上述測試週期信號表示成為測試週期的開始時序的基準的時序，上述測試週期資料表示自上述測試週期信號至測試週期的開始時序為止的延遲量；以及時序產生器，將由上述測試週期資料所指定的測試週期的開始時序作為基準，而產生在與上述被測試元件之 間授受信號的時序，且上述測試週期產生器包括：週期產生部，產生上述測試週期資料以及上述測試週期信號；資料獲取部，與上述基準時脈同步地獲取上述測試週期資料，並向上述時序產生器輸出；以及檢測部，檢測上述週期產生部所產生的上述測試週期資料中的上位位元的預定數量是否為0；且在未產生上述測試週期信號的情況時，或者在上述檢測部檢測出上述測試週期資料的上述上位位元為0的情況時，停止對上述資料獲取部供給上述基準時脈，以致於防止上述上述位元的獲取。 A control device for testing a test device, wherein the test device includes: a test cycle generator that generates a test cycle signal and a test cycle data in synchronization with a reference clock, wherein the test cycle signal a timing indicating a timing of starting the test cycle, the test cycle data indicating a delay amount from the test cycle signal to a start timing of the test cycle; and a timing generator for starting the test cycle specified by the test cycle data The timing is used as a reference and is generated in the same component as the above Interleaving the timing of the signal, and the test cycle generator includes: a period generating unit that generates the test period data and the test period signal; and a data acquisition unit that acquires the test period data in synchronization with the reference clock and to the timing a detector output, wherein the detecting unit detects whether a predetermined number of upper bits in the test period data generated by the period generating unit is 0; and when the test period signal is not generated, or in the detecting unit When the above-mentioned upper bit of the test cycle data is 0, the supply of the reference clock to the data acquisition unit is stopped, so that the acquisition of the bit is prevented. 一種傳送電路的控制方法，上述傳送電路將資料以及表示上述資料是否有效的資料賦能信號自發送電路向接收電路傳送，其中，上述資料包含：預定數量的上位位元，上述上位位元表示大於基準時脈的週期的期間的單位的時間；以及一或多個下位位元，上述下位位元表示小於等於上述基準時脈的週期的期間的單位的時間，上述傳送電路包括：資料獲取部，與基準時脈同步地自上述發送電路獲取上述資料並輸出至上述接收電路；以及檢測部，檢測上述上位位元的預定數量是否為0；且 在自上述發送電路接收到表示上述資料為無效的上述資料賦能信號的情況時，或者在上述檢測部檢測出上述資料的上述上位位元為0的情況時，停止對上述資料獲取部供給上述基準時脈，以致於防止上述上位位元的獲取。 A control method for a transmission circuit, wherein the transmission circuit transmits data and a data enabling signal indicating whether the data is valid from a transmitting circuit to a receiving circuit, wherein the data includes: a predetermined number of upper bits, wherein the upper bit indicates greater than a time unit of a period of a period of the reference clock; and one or more lower bits indicating a time unit of a period less than or equal to a period of the reference clock, the transmission circuit including: a data acquisition unit, Acquiring the above-mentioned data from the transmitting circuit in synchronization with the reference clock and outputting to the receiving circuit; and detecting unit detecting whether the predetermined number of the upper bits is 0; When the data transmission signal indicating that the data is invalid is received from the transmission circuit, or when the detection unit detects that the upper bit of the data is 0, the supply of the data acquisition unit to the data acquisition unit is stopped. The reference clock is such that the acquisition of the above upper bits is prevented. 一種測試裝置的控制方法，上述測試裝置對被測試元件進行測試，其中，上述測試裝置包括：時序資料產生部，產生時序資料以及時序賦能信號，其中上述時序資料對表示在與上述被測試元件之間授受信號的時序的時序信號的產生時序進行指定，上述時序賦能信號表示上述時序資料是否有效；以及計數部，與基準時脈同步動作，自上述時序資料產生部接收有效的上述時序資料之後，與該時序資料中所含的以大於等於上述基準時脈的週期的單位來表示時間的上位側資料數相應地對基準時脈進行計數之後，上述計數部輸出該時序資料的上述上位側資料以外的下位側資料、以及表示該時序資料有效的上述時序賦能信號，且在上述計數部未對有效的上述時序資料中所含的上述上位側資料數進行計數的情況時，停止對上述計數部供給上述基準時脈。A control device for testing a test device, wherein the test device includes: a timing data generating unit that generates timing data and a timing enable signal, wherein the timing data pair is represented by the tested component Specifying a timing of generating a timing signal between timings, wherein the timing enable signal indicates whether or not the timing data is valid; and the counting unit operates in synchronization with the reference clock to receive the valid timing data from the timing data generating unit After that, the counting unit outputs the upper side of the time series data after the reference clock is counted in accordance with the number of upper side data indicating the time in the unit of the period of the reference clock, which is included in the time series data. The lower side data other than the data, and the timing enable signal indicating that the time series data is valid, and when the counting unit does not count the number of the upper side data included in the valid time series data, the above is stopped. The counting unit supplies the reference clock.
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