TWI388697B - 基體上之電動沉積及圖案化程序的遮罩和方法 - Google Patents

基體上之電動沉積及圖案化程序的遮罩和方法 Download PDF

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Publication number
TWI388697B
TWI388697B TW095117708A TW95117708A TWI388697B TW I388697 B TWI388697 B TW I388697B TW 095117708 A TW095117708 A TW 095117708A TW 95117708 A TW95117708 A TW 95117708A TW I388697 B TWI388697 B TW I388697B
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Taiwan
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mask
substrate
conductive layer
particles
charged particles
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TW095117708A
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TW200706704A (en
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Oscar Khaselev
Brian Lewis
Michael Marczi
Bawa Singh
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Fry Metals Inc
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    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
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Description

基體上之電動沉積及圖案化程序的遮罩和方法
本發明係有關藉由將粉末、粒子、球體、或其他材料沉積於基體上，用以產生經圖案化的物件之遮罩和方法。此技術之應用包括(但不限於)顯示技術(於玻璃、塑膠、圖案化磷等之上的導電與絕緣跡線(trace))、印刷電子(可銲的表面/可銲的保護劑層、導體、電介質、被動元件等)、醫學(圖案化檢定化學、藥劑量測量等)、平行組裝程序(RFID晶粒、電子元件等)、以及其他方面。
在許多的應用中，希望能以預定圖案塗施粒子至基體。一種如此之應用為形成於矽晶圓、印刷電路板、倒裝晶片、以及BGA次載具上之銲料合金的圖案。國際專利申請公開案WO2005/033352(PCT/US2004/022143)(美國公開案第2005/0106329號)揭露一種金屬粒子(例如錫或錫合金粉末)的電動沉積之程序，作為於電子部分與元件上形成可銲的表面與結構之方法。
在電動沉積程序中，即將被塗覆之具有經遮蔽的表面與未經遮蔽的表面之基體係浸入具有電動調色劑(toner)的電解液中。典型之用於電動沉積錫粉末的電解液(色劑)係由溶劑(例如Isopar)、電荷導向體(例如石油磺酸鋇(barium petronate))、以及金屬粒子所構成。為了確保電動沉積的程序，第二(對向)電極亦浸入該電解液中且施加 電壓於兩個電極之間。在所施加的電場的影響之下，經充電的粉末粒子被沉積於經塗覆的基體之未經遮蔽的表面上。用於發生此程序之一項要求為：即將被塗覆之表面應為導電的且易電氣地連接至電壓電源。此要求限制對具有至少一個完整的導電層之基體電動沉積的應用。
本發明的產品是一種用於涉及電動沉積與於非導電的基體上及於具有隔離的導電表面上圖案化的方法之遮罩。這些基體包括具有或不具有隔離的導電表面之玻璃、聚合物、陶瓷、半導體、以及疊層。
此遮罩與方法可以許多製造操作方式應用於沉積粒子，其中希望沉積粒子於基體上的圖案中，特別是於非導電的基體上。這些應用包括(但不限於)顯示技術(於玻璃、塑膠、圖案化磷等之上的導電與絕緣跡線(trace))、印刷電子(可銲的表面/可銲的保護劑層、導體、電介質、被動元件等)、醫學(圖案化檢定化學、藥劑量測量等)、平行組裝程序(RFID晶粒、電子元件等)、以及其他方面。
在本發明的一態樣中，沉積係以如美國專利申請案第10/888,286號(公開號2005/0106329)所實施之沉積相同的方式來予以實施，該申請案的整個揭露內容係併入於此作為參考。然而，該遮罩可應用於涉及關聯於基體表面與對向電極的浸沒電極之其他沉積方法。
本發明之前述方法適合用來沉積大範圍的尺寸大小之 金屬粒子。在一方法中，該等粒子為粉末，典型上具有介於約2微米與約100微米間的平均粒子大小。在另一方法中，他們為中型的粒子，例如具有介於約50微米與約500微米間的平均粒子大小。在另一方法中，他們為較大的球體，例如具有至少約100微米、例如介於約100微米與約1mm之間、或介於約300微米與約1mm間的平均直徑。球體的優點為：相較於粉末的50%稠密(dense)之等級，其為100%稠密。又，由於球體較相同體積的粉末被較佳地界定，且由於較小的球體在回銲後能夠被用來產生相同的銲料量(而為較大體積的粉末)，故球體能以較粉末的體積更為精細的間距來予以沉積。球體亦幫助上述的單一遮罩技術，其中遮罩孔洞係較沉積高度淺了許多。
用於沉積的粒子之準備涉及給予電荷於該處，其使得該等粒子電動地移動。假設滿足此準則，該準備方法對本發明而言並非關鍵的。該等粒子能如本技術中所描述者來予以準備，且依據下列例示性、非限制性、以及非詳盡的替換方法。舉例來說，針對錫合金銲料粉末塗覆，Joncryl 682樹脂(可購自美國Johnson Polymer,LLC of Studevant,Wis.)可溶解於甲醇至濃度20%，然後噴灑塗覆於Type 6 Sn63Pb37銲料粉末(獲得自德國Welco GmbH,Potsdam)上。噴灑係藉由美國Coating Place,Inc.of Verona,Wis.的Wurster Process來予以達成。接著，針對調色劑準備，將經塗覆的粉末(120g)加入1公升的Isopar G於1.4公升的燒杯中，且以適當的混合器(例如可購自美國Victory Engineering,Hillside,N.J.的”The Agitator”)攪拌。並不使用磁性攪拌棒，這是因為攪拌棒會自粉末磨掉塗覆層。將電荷導向體(21滴，每滴-0.016ml)添加入該混合物且持續攪拌至少四個小時。該調色劑可在室溫下放兩天以老化。該調色劑避免在高溼度環境(>60%RH)中，以維持穩定的性能。
對於前述電荷導向體的準備，舉例來說，將石油磺酸鋇(10g)(可購自美國Crompton Corporation of Middlebury,Conn.)添加入Isopar G(90g)(可購自美國ExxonMobil Chemical Company of Houston,Tex.)於200ml燒杯中。該燒杯係置於經加熱的攪拌盤上且將該燒杯加熱/攪拌直到其到達80-90℃的溫度。將高度精鍊的水(10g)(亦即高度蒸餾的純水)一次一滴(約16微升)的加入，且同時持續攪拌並加熱該溶液。在加入所有的水之後，再將該溶液加熱及攪拌一個小時。接著不須加熱但仍持續攪拌直到該溶液冷卻。注意會形成棕褐色(tan-colored)的沉澱物。將該混合物於室溫下放置一天以老化，接著過濾並丟棄該沉澱物。
於其他實施例中，為了準備該等粒子，該等粒子係塗覆以選自離子介面活性劑材料、非離子材料(例如非離子聚合物、有機酸與/或鹼)、及其混合物之材料。根據該塗覆層是如何實際地予以實施，該塗覆層媒質亦可含有溶劑。亦即，若塗覆層係藉由注入於溶液、噴灑溶液、或暴露於流體化床中的溶液來予以達成，則需要溶劑。另一方面，若該塗覆層係藉由電漿塗覆程序等等來予以達成，則不 需要溶劑。依據本發明，在適合用來塗覆的介面活性劑材料之粒子中為揭露於美國專利公告第2005/0100735號案中所揭示者。
前述塗覆材料使得經塗覆的粒子經得起以電荷導向體的處理，使得該等粒子能夠以電荷導向體來予以處理，以使該等粒子可電動地移動。此塗覆層提供一種以例如非常羥性的表面或非常酸的表面(其可與隨後塗施之電荷導向體起反應)為特徵的表面。於選擇塗覆材料方面，若該等粒子為即將被使用作為銲料之金屬粒子，則較佳選擇當其被使用作為銲料時於最終粉末中提供助熔(fluxing)功能之一者。
在此變化的粒子包括：粒子體；在粒子體上的促進附著於電荷導向體材料之上述的塗覆媒質其中，塗覆媒質係選自由陰離子物種、非離子物種、陽離子物種、酸、鹼、及其混合所組成的群組中；以及在塗覆媒質上之上述的電荷導向體材料，其中該電荷導向體材料具有正或負電荷並藉此致使該等粒子體能夠電動地移動。
應注意，為了在本發明的程序中使用該等粒子，將該等粒子被導引入含有電解質或聚電解質的溶液(也被稱為電荷導向體)中。適合的電解質或聚電解質之例包括(但不限於)前述之公開案中所揭露者。這因而產生電動移動的粒子，以供使用於沉積程序中。
之後，藉由盤式乾燥(pan drying)、噴霧乾燥、或其他適合的方式只使該等粒子乾燥。電解質或聚電解質之功 能為促進電荷的維持，使得該等電荷將以所想要的電動方式反應。
於沉積的準備中，將該等粒子係與具有適合的電介質性質之液體結合而變濕。如此之液體的一例為Isopar產品。另一例為3-M公司的產品(商標名稱為Fluorinert)。經結合之粒子與液體的範圍為從約2重量%的粒子至高達約90重量%的粒子。該等粒子以體積計構成該混合物的約2%至約60%。
依據本發明，使用遮罩，該遮罩提供：a)電動沉積所需要的電氣連接、以及b)從經沉積的材料圖案化以形成各種結構。於第1與2圖中的遮罩10具有第一層12(為電介質材料)，以及第二層14(為電導體)。用於第一層的較佳材料為乾式光阻膜，例如環氧物疊層。用於第二層(亦即導電層14)的較佳材料為不鏽鋼、鎳、鋁、鉬、以及鉻。該遮罩具有開口16，其提供於基體上的圖案化。為了簡明，此處所顯示的遮罩僅有一列的開口；但是，典型上該遮罩具有許多列，如同第6與7圖所顯示者。
該遮罩可藉由將電介質材料12塗覆於導電材料14上來予以製備，其係藉由層疊(lamination)、膠黏、旋轉塗覆、浸泡塗覆、或經由類似於網板印刷的模板印刷。該等開口16可於塗施電介質之前就在該等導電材料上，或者在塗覆電以介質後被鑽孔。
在一實施例中，該導電層14係以非導電的塗覆層12(其界定遮罩的電介質層)塗覆於其上。該非導電塗覆層12 可為乾式光阻膜，例如環氧物疊層。在一實施例中，此塗覆層12可含有感光劑(photoimageable agent)。舉例來說，可選自以壓克力為基底的、以聚醯亞胺為基底的、商用之以環氧物為基底的PWB銲料遮罩塗覆層、以及各式各樣之商用的有機感光光聚合物塗覆層。一種適合的聚合物為厚膜旋轉塗佈式(spin-on)感光聚合物，可供使用於名稱AZPDP100XT，或以酚醛清漆為基底的AZPLP-100之下，兩者皆可購於美國Clariant of Bridgewater,N.J.。另一種為以聚苯乙烯為基底的材料，商標名稱為Futurrex。此塗覆層(該遮罩的電介質層12)係例如至少約1微米，例如對於矽晶圓的銲料凸塊(solder bumping)，為介於約1微米與約250微米之間的厚度。該導電層14為例如介於約50微米與約1公分之間的厚度。
如果依據供應者的規格而有需要，則將該遮罩10置於例如箱型烤箱進行硬化，以使形成電介質層12的聚合物硬化。
在實施此方法中，如第3與4圖所顯示，將該遮罩10置於基體20的表面上，而該基體20的表面係用來接收所沉積的粒子。將經遮蔽的基體浸入包括即將被沉積的粒子24之容器34中的電解液28中，如第5圖所示意顯示者。經由電源30而將電壓施加於該遮罩10之導電層14與浸入於電解液中的對向電極26之間。
在電場的影響下，電解液中之帶電粒子24被吸引至導電層14之暴露出的區域，因而沉積於該基體20上且充填遮 罩10中的開口16。特別是，在遮罩的導電層與對向電極之間建立電位，藉以電動地吸引帶電粒子至遮罩開口中之導電層上的露出表面，以沉積該等帶電粒子於該等遮罩開口中。這些遮罩開口界定該經遮蔽的基體之未經遮蔽的表面。這些未經遮蔽的表面可實質地或完全地為非導電的表面。在沉積後，可藉由熔化、燒結、或固化(熱、UV、催化劑)而將該等粒子熔接於基體。
依據本發明而沉積的粒子包括金屬、金屬合金、聚合物與其他有機物、陶瓷、半導體、以及無機化合物之粒子。舉例來說，所沉積的粒子包括(但不限於)美國專利公開案第2005/0106329號以及申請案序號第10/888,619號(公開號第2005/0100735)所揭露者，其整個揭露內容係併入於此作為參考。依據本發明，有機或無機粒子被塗覆以便使得經塗覆的粒子可經得起以電荷導向體的處理，使得該等粒子因而可被致使為電動地或靜電地移動。在一較佳實施例中，該等粒子係由選自下列金屬及合金中之材料所製成的：錫、錫/鉛、錫/銀/銅、錫/銀、銅、錫/銀/鉍、錫/鉍、錫/鉛/鉍、等等。藉由此方法所沉積之該等粒子(例如，前述以錫為基底或其他的粒子)的特性包括：奈米粉末、微米大小的圓外粉末(round powder)、大至300微米的大粒子、等等。
在實現本發明之該方法中，將具有塗施遮罩於其處之基體浸入於即將被沉積的粒子24之懸浮液28中，如第5圖所示。該遮罩的導電表面14用作電極，且在鄰近該基體處 有一浸入的對向電極26。在兩電極之間施加電位30，以驅動該帶電的粒子至該基體。該懸浮液性質係設計來提供正確的液相導電率與粒子電荷對質量的比值。因為該等粒子被吸引至施加於該遮罩上的導電層14之電位，且不被吸引至該遮罩的電介質表面12，所以獲得到影像對比。由於電荷載子經由電解質而遷移至遮罩材料，故遮罩上的電荷建立。
該沉積驅動力係主要將帶電粒子吸引至施加於該遮罩之導電層14的電位之相反的電荷電磁極。該導電層14係裝附於電氣連接，以施加電位於該導電層14與對向電極26之間。將該基體浸入粒子漿(電動溶液)28中。浸入於該粒子漿中的該對向電極26完成了電路。在一較佳實施例中，如第5圖所示，該基體垂直定向於該粒子漿的頂表面上。
於該等粒子被處理而具有負的化學電荷之情形中，施加具有遮罩10之導電層14為正極的電位於該遮罩與對向電極26之間。替換地，於該等粒子被處理而具有正電荷之情形中，施加具有遮罩10之導電層14為負極的電位於該遮罩的導電層。舉例來說，電路的負端係裝附於該粒子漿之對向電極板上，且正端係裝附於該遮罩的導電層上。或者，電路的正端係裝附於該粒子漿之對向電極板上，而負端係裝附於該遮罩的導電層上。
該粒子漿28中之帶電粒子24被吸引至導電層14，其被建立為極性與該等粒子上的電荷相反之端。帶電粒子移動經過由介於該遮罩的導電層與該對向電極之間的電位所產 生之電場。有了裝附於電源供應器之相反極的電極與對向電極(該電源供應器建立電位於該兩電極之間)，該等粒子係電動地沉積至該基體之鄰近該遮罩之導電部分之未經遮蔽部分上的孔洞16中。在此實施例中，不需要施加電暈電荷(corona charge)至該遮罩之電介質層12。該遮罩用作機械的或靜電的障壁。靜電電荷由於載子流經電解質而建立於該遮罩之電介質層12上，其形成電場，而該電場電氣地推動帶電粒子進入該遮罩中的孔洞中。
此方法涉及具有例如50+/-50V至500+/-500V的AC電位之單一沉積步驟。另一替代實施例涉及改變施加於該遮罩之導電層與該對向電極之間的電位，以造成沉積。在一實施例中，此係涉及在所有的或少於所有的沉積期間，電壓之緩慢地向上掃掠(sweeping)或斜升(ramping)。在另一實施例中，此係涉及以更階梯式地方式增加電位。舉例來說，其涉及以介於約50+/-50V與約500+/-500V之間的電位來達成的沉積第一週期；及以介於約200+/-200V與約300+/-300V之間的電位來達成沉積的第二與第三週期。這三個重複(iteratoin)大略對應於三個階段的沉積，此三個階段涉及a)充填凹部的底部；b)充填凹部到達頂部，與非導電層的頂部齊平；以及c)過充填(overfill)已經被沉積之粒子的頂部。其他實施例使用重複之數目(不同於3個)上的改變，從兩個至數個。因為該等遮罩孔洞被更有次序地充填，故此階梯式沉積似乎提供更稠密的沉積且較少孔隙(voiding)或收聚(pinching)。
關於該沉積程序之其他參數，該電位被施加為正弦波，或是較佳被施加為鋸齒波。頻率係介於約10Hz與1000Hz之間，較佳為介於約50Hz與500Hz之間，更佳為介於約75Hz與150Hz之間。用於此沉積的時間週期係在約2秒至約30秒的範圍內，例如在約5秒至約20秒的範圍內，或者在一特定實施例中，在約8秒至約15秒的範圍內。在一實施例中，該基體與該對向電極之間的距離是介於約5mm與約6mm之間。一般建議此距離是介於約3mm與約10mm之間，最典型的是介於約4mm與約7mm之間。
不被特別的定理所拘限，據信在該基體的最深特徵上之金屬粒子的早期沉積期間，相對較弱的電位會導致比如果該電位係較強的情況下有較少的粒子被吸引至導電層14，從而降低在短的時間期間有太多的粒子擠進該特徵中的機會。若該電位起初較強，則粒子會很積極地擠進該特徵中並夾止(pinch off)凹部開口至該基體，或導致過多的孔隙。起初較弱的電位較不積極地移動粒子，使得該等粒子可緊緊的聚集在該基體上，而沒有眾多的粒子被同時強迫進入該非導電層中的凹部中。
在適當的暫留時間後，將該基體垂直地移開或以不平行於該溶液的頂部表面之某種角度來移開。在一較佳實施例中，在移開期間，該基體係以與垂直呈介於約15度與約75度的角度。也已經發現如上所述之與靜電模式有關之基體的振動與電動模式有關係有利。
在沉積後，以含有沉積粒子之遮罩開口面朝下的方式 ，該基體係藉由短暫浸入沖洗溶液中來予以選擇性地清洗。此亦可藉由原位清洗於與沉積之相同的容器中來予以完成，其涉及同時移除粒子漿及更換成無粒子的沖洗溶液。
該基體接著可選擇性地遭受到電暈電荷，以對該等沉積粒子施予靜電夾(electrostatic clamp)。特別是，將具有例如5千伏至7千伏特之電位的電暈產生器越過該基體，以施予電暈電荷。這會幫助保持該等粒子在位，這是因為被施加至該遮罩的靜電力。
藉由暴露該基體於提高的溫度(其視該粒子漿中的溶劑之本質而定，典型上在30℃至60℃的範圍中)而使殘餘的溶劑乾掉。這會產生如第9圖所示具有銲料粉末粒子於其上之類型的基體。
接著藉由將該銲料置於例如標準多區域銲料回銲爐或較佳為低氧(<100 ppm，更佳<20ppm)回銲爐而回銲。較佳將該基體從下方加熱。在回銲期間，該金屬粒子上的塗覆層起銲劑的作用。輔助助熔(例如，以噴塗用(sprayed-on)液態銲劑)亦能被用來幫助回銲。將遮罩移除，其產生具有銲料凸塊於其上之基體。
在以不同方式使用本發明之遮罩的進一步變化中，使用分開的印刷工具，而本發明的遮罩界定該圖案於該印刷工具上，在該圖案中，該等粒子即將被轉移至該基體。此印刷工具為具有平坦表面之絕緣支撐件，且該遮罩類似於第4圖所顯示地被塗施於該處，除了使用平坦工具表面來代替基體20之外。代表性的印刷工具係以例如聚醯亞胺與 環氧物的材料所構成、具有介於約1微米與約200微米的厚度、以及工具表面之直徑大小的範圍為從約1公分至約100公分。
具有遮罩10於其上之該工具係充滿著粒子與液體混合物，且施加電位於該遮罩的導電層與該對向電極之間，使得該等粒子佔用該工具之並未由該遮罩所屏蔽的部分(亦即，在孔洞16中)。照這樣，該工具表面係暴露於電介質流體中的粒子(該等粒子具有電化學電荷)中，藉以造成一些該等粒子沉積於該工具表面之未經遮蔽的區域上，且因而產生經圖案化的工具表面，連同該等粒子係在未遮蔽的區域上。任何未予束縛的粒子係藉由施加純電介質液體媒介(vehicle)而從該工具中被清洗出來。此方法在與具有平均大小至少約100微米(例如介於約100微米與約1mm之間)之金屬球體一起工作時特別成功。
該矽晶圓或其他基體(該等粒子將從該工具轉移到那裡)係藉由預先以電介質液體弄濕來予以製備。該基體係裝附於徹底接地的支撐件。
轉移至該基體係以下列方式來予以達成：藉由緊密地暴露該經圖案化的工具表面(其係黏附有粒子)至電子裝置的表面或其他基體，藉以從該經圖案化的工具表面轉移至少一部份的粒子量至該基體的表面之由該經圖案化的工具表面上的圖案所界定的基體圖案中。在一實施例中，為了達成此，該帶電與經沖洗的工具係置於即將被圖案化的基體表面上，該基體與該工具表面具有介於約20微米與300 微米之間的間隙。由於該基體相較於該工具有較低的電荷電位，故該等粒子轉移至該基體，保持於該工具表面上之由該等粒子所界定的相同圖案。替換地，施加於該遮罩的導電層之電位可在此時改變，以促使轉移至該基體。或者，若該基體本身是導電的，則可施加促使該轉移的電位至該基體。
接著從該基體蒸發該電介質液體。藉由傳統的銲料回銲技術(例如在烤箱中烘烤該基體，以加熱該基體與銲料至回銲溫度)，使該銲料熔化並熔接於該基體。
例1
使用非導電疊層作為基體。準備好遮罩，該遮罩為塗覆有銲料遮罩且具有直徑125微米之開口的銅層。第6與7圖例舉該具有遮罩塗施於該處的基體。該沉積係實施於與WO 2005/033352所說明者類似的染色劑中，連同其電解液含有Isopar、120g/l預處理銲料粉末、以及0.5ml的10%石油磺酸鋇溶液。將該塗施有遮罩之基體與對向電極一起浸入該電解液中。在該銅層與該對向電極之間施加200V的電壓。在20秒之後，銲料粉末會充填於該遮罩中的沉積開口。第8與9圖顯示該在該等銲料粉末粒子沉積後之基體。
例2
如第10圖所示，在該圖案中，藉由以上程序來製備包 含不銹鋼導電層與還氧物疊層之遮罩。將該遮罩置於PWB基體上，如第11圖所示。藉由以上程序，將銲料粉末沉積於該遮罩之開口中，以產生銲料粒子於該基體上，如第12圖所示。這舉例說明了本發明之用於以緊密的間距來沉積的能力以及寬線(wide line)能力。
雖然本發明之方法與材料係主要說明塗施金屬粒子至基體於上下文中，但該等方法與材料亦可應用於非金屬粒子的沉積，其係假設該等粒子的本質為可施予電化學電荷。這涉及了非金屬粉末之處理的例子包括：磷光體、玻璃、陶瓷、半導體材料(例如用於平面顯示器等等)之沉積。
在不超出本發明較廣的範疇下可做出各種改變，所有於前述說明與顯示於隨附圖示所包含者僅為例示用而非用於限制本發明。前述有關有限數目的實施例僅為例示之目的。本發明之範疇係由所附申請專利範圍所定義且在不超出本發明範疇下可做出各種修改。
10‧‧‧遮罩
12‧‧‧第一層
14‧‧‧第二層
16‧‧‧開口
20‧‧‧基體
24‧‧‧粒子
26‧‧‧對向電極
28‧‧‧電解液
30‧‧‧電源供應器
34‧‧‧容器
第1圖係本發明之遮罩的示意頂視圖。
第2圖係沿著2-2線所取出的側視剖面圖。
第3圖係將本發明之遮罩塗施於基體的示意頂視圖。
第4圖係沿著3-3線所取出的側視剖面圖。
第5圖係示意例舉本發明之遮罩的使用。
第6與7圖係將本發明之遮罩塗施於基體的照片。
第8與9圖係第6與7圖的遮罩與基體，具有銲料金屬粒 子沉積於遮罩中之照片。
第10圖係本發明之遮罩的照片。
第11圖係將本發明之遮罩塗施於PWB基體的照片。
第12圖係將銲料粉末沉積至第11圖之遮罩的開口中之照片。
10‧‧‧遮罩
20‧‧‧基體

Claims (21)

  1. 一種用以塗施帶電粒子的圖案至基體之方法，包括下列步驟：塗施具有導電層、電介質層、以及遮罩開口之遮罩至該基體，且該遮罩之該導電層在該基體與該電介質層之間，以產生具有由該等遮罩開口所界定之未經遮蔽的表面之經遮蔽的基體；將該經遮蔽的基體浸入含有該等帶電粒子的電解液中；以及在該遮罩之該導電層與對向電極之間建立電位，藉以電動地吸引該等帶電粒子至該導電層上之暴露出的區域，藉以沉積該等帶電粒子於該等遮罩開口中。
  2. 如申請專利範圍第1項之方法，其中，該等帶電粒子為具有介於約2微米與約100微米間的平均大小之粉末粒子。
  3. 如申請專利範圍第1項之方法，其中，該等帶電粒子具有介於約50微米與約500微米之間的平均大小。
  4. 如申請專利範圍第1項之方法，其中，該等帶電粒子具有介於約300微米與約1mm之間的平均大小。
  5. 如申請專利範圍第1項至第4項中任何一項之方法，其中，該等帶電粒子為以錫為基底之粒子。
  6. 如申請專利範圍第1項至第4項中任何一項之方法，其中，該等帶電粒子係由選自下列金屬及合金中之材料所製成的：錫、錫/鉛、錫/銀/銅、錫/銀、銅、錫/銀/鉍、錫 /鉍、以及錫/鉛/鉍。
  7. 一種塗施於基體以促進帶電粒子電動沉積於該基體上的遮罩，該遮罩包括導電層、附著於該導電層之電介質層、以及界定用於該帶電粒子之沉積於該基體上的圖案之遮罩開口。
  8. 如申請專利範圍第7項之遮罩，其中，該電介質層包括環氧物疊層。
  9. 如申請專利範圍第7項之遮罩，其中，該導電層包括選自不鏽鋼、鎳、鋁、鉬、以及鉻中的材料。
  10. 如申請專利範圍第7項之遮罩，其中，該導電層包括不鏽鋼。
  11. 如申請專利範圍第7項之遮罩，其中，該電介質層包括環氧物疊層且該導電層包括不鏽鋼。
  12. 如申請專利範圍第7項之遮罩，其中，該電介質層包括環氧物疊層且該導電層包括鎳。
  13. 如申請專利範圍第7項之遮罩，其中，該電介質層包括環氧物疊層且該導電層包括鋁。
  14. 如申請專利範圍第7項之遮罩，其中，該電介質層包括環氧物疊層且該導電層包括鉬。
  15. 如申請專利範圍第7項之遮罩，其中，該電介質層包括環氧物疊層且該導電層包括鉻。
  16. 一種用以塗施帶電粒子的圖案至基體之方法，包括下列步驟：塗施如申請專利範圍第7項至第15項中任一項之該遮 罩至該基體，以產生經遮蔽的基體；將該經遮蔽的基體浸入含有該等帶電粒子的電解液中；以及在該遮罩之該導電層與對向電極之間建立電位，藉以電動地吸引該等帶電粒子至該導電層上之暴露出的區域，藉以沉積該等帶電粒子於該等遮罩開口中。
  17. 如申請專利範圍第1項至第4項中任何一項之方法，其中，該導電層具有介於約50微米與約1cm之間的厚度，且該電介質層具有介於約1微米與約250微米之間的厚度。
  18. 如申請專利範圍第5項之方法，其中，該導電層具有介於約50微米與約1cm之間的厚度，且該電介質層具有介於約1微米與約250微米之間的厚度。
  19. 如申請專利範圍第16項之方法，其中，該導電層具有介於約50微米與約1cm之間的厚度，且該電介質層具有介於約1微米與約250微米之間的厚度。
  20. 如申請專利範圍第1項至第4項中任何一項之方法，其中，該基體為非導電的。
  21. 如申請專利範圍第16項之方法，其中，該基體為非導電的。
TW095117708A 2005-05-18 2006-05-18 基體上之電動沉積及圖案化程序的遮罩和方法 TWI388697B (zh)

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7538429B2 (en) * 2006-08-21 2009-05-26 Intel Corporation Method of enabling solder deposition on a substrate and electronic package formed thereby
US8216441B2 (en) * 2007-12-10 2012-07-10 Applied Materials, Inc. Electrophoretic solar cell metallization process and apparatus
US8323748B2 (en) * 2009-05-15 2012-12-04 Achrolux Inc. Methods for forming uniform particle layers of phosphor material on a surface
KR101104681B1 (ko) * 2010-01-08 2012-01-16 서울대학교산학협력단 비전도성 기판 상에 하전 입자를 부착하는 방법
CN103030097B (zh) * 2012-12-12 2015-06-17 中北大学 基于静电场自聚焦的圆片级低维纳米结构的制备方法
US10685766B2 (en) 2016-04-18 2020-06-16 Littelfuse, Inc. Methods for manufacturing an insulated busbar
US20170301434A1 (en) * 2016-04-18 2017-10-19 Littelfuse, Inc. Methods for manufacturing an insulated busbar
CN107723753B (zh) * 2017-09-27 2021-04-27 上海瑞尔实业有限公司 高强度高韧性镍金属遮蔽工装制备方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3431887A (en) * 1963-11-13 1969-03-11 Polymer Corp Apparatus for coating articles in a fluidized bed
JPH04211193A (ja) * 1990-03-22 1992-08-03 Canon Inc 導電回路部材、導電回路部材の製造方法、導電性ペースト及び電子機器
US5981043A (en) * 1996-04-25 1999-11-09 Tatsuta Electric Wire And Cable Co., Ltd Electroconductive coating composition, a printed circuit board fabricated by using it and a flexible printed circuit assembly with electromagnetic shield
US5817374A (en) * 1996-05-31 1998-10-06 Electrox Corporation Process for patterning powders into thick layers
CA2286326C (en) * 1997-04-04 2007-06-26 Adam L. Cohen Article, method, and apparatus for electrochemical fabrication
TW552243B (en) * 1997-11-12 2003-09-11 Jsr Corp Process of forming a pattern on a substrate
US6153348A (en) * 1998-08-07 2000-11-28 Parelec Llc Electrostatic printing of conductors on photoresists and liquid metallic toners therefor
US6781612B1 (en) * 1998-10-13 2004-08-24 Electrox Corporation Electrostatic printing of functional toner materials for electronic manufacturing applications
US6579652B1 (en) * 1999-11-23 2003-06-17 Electrox Corporation Durable electrostatic printing plate and method of making the same
US6524758B2 (en) * 1999-12-20 2003-02-25 Electrox Corporation Method of manufacture of printed wiring boards and flexible circuitry
TW495809B (en) * 2000-02-28 2002-07-21 Semiconductor Energy Lab Thin film forming device, thin film forming method, and self-light emitting device
AU2002226093A1 (en) 2000-12-15 2002-06-24 Electrox Corp. Process for the manufacture of novel, inexpensive radio frequency identificationdevices
JP2002223059A (ja) * 2001-01-24 2002-08-09 Sharp Corp 微細パターン形成方法
JP2004526994A (ja) 2001-02-08 2004-09-02 エレクトロックス コーポレイション 段になった表面を有する改良された静電印刷版
WO2002071465A1 (en) 2001-03-02 2002-09-12 Electrox Corp. Process for the manufacture of large area arrays of discrete components
US6803092B2 (en) * 2001-06-26 2004-10-12 3M Innovative Properties Company Selective deposition of circuit-protective polymers
US6780249B2 (en) * 2002-12-06 2004-08-24 Eastman Kodak Company System for producing patterned deposition from compressed fluid in a partially opened deposition chamber
US6790483B2 (en) * 2002-12-06 2004-09-14 Eastman Kodak Company Method for producing patterned deposition from compressed fluid
TWI329534B (en) * 2003-07-09 2010-09-01 Fry Metals Inc Coating metal particles
WO2005033352A2 (en) 2003-07-09 2005-04-14 Fry's Metals, Inc. Deposition and patterning process
JP2007277619A (ja) * 2006-04-05 2007-10-25 Electroplating Eng Of Japan Co 電気泳動による粒子堆積方法

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EP1882056A2 (en) 2008-01-30
JP5301269B2 (ja) 2013-09-25
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