TWI386771B

TWI386771B - Voltage regulator and ac-dc converter

Info

Publication number: TWI386771B
Application number: TW98115793A
Authority: TW
Inventors: Rogelio L Erbito Jr
Original assignee: Vanguard Int Semiconduct Corp
Priority date: 2009-05-13
Filing date: 2009-05-13
Publication date: 2013-02-21
Also published as: TW201040684A

Description

穩壓器以及交流對直流轉換器Voltage regulator and AC to DC converter

本發明係有關於一種穩壓器(voltage regulator)，特別是有關於一種交流對直流轉換器的穩壓器。The present invention relates to a voltage regulator, and more particularly to a voltage regulator for an AC to DC converter.

一般而言，交流對直流轉換器可直接使用於交流輸入線。在交流對直流轉換器中，整流電路可直接將來自於交流線上的交流輸入電壓轉換成具有漣波(ripple)之直流電壓，其中配置於整流電路輸出端的穩壓器可對具有漣波之直流電壓進行調整，以減少漣波的情況發生。In general, the AC to DC converter can be used directly on the AC input line. In the AC-to-DC converter, the rectifier circuit can directly convert the AC input voltage from the AC line into a DC voltage with a ripple, wherein the regulator disposed at the output of the rectifier circuit can have a DC with chopping The voltage is adjusted to reduce the occurrence of chopping.

第1圖係顯示傳統交流對直流轉換器100。交流對直流轉換器100包括整流電路110以及分路調節電路(shunt regulator circuit)120。整流電路110可將高交流電壓HVAC轉換成高直流電壓HVDC(單極性電壓)。由於漣波的存在，使得高直流電壓HVDC為非固定電壓。為了能提供穩定的高直流電壓HVDC，使用平流電容器(smoothing capacitor)C1對高直流電壓HVDC進行濾波，以便減少漣波。分路調節電路120包括電阻R、齊納(Zener)二極體Z以及電容C2，其中分路調節電路120可消除任何剩餘的漣波並可對不同之供應電壓以及負載維持調整。根據直流電壓HVDC，電阻R以及齊納二極體Z會產生已調整之直流電壓。電容C2並聯於齊納二極體Z，用以進一步減少漣波與二極體雜訊。Figure 1 shows a conventional AC to DC converter 100. The AC to DC converter 100 includes a rectifier circuit 110 and a shunt regulator circuit 120. The rectifier circuit 110 can convert the high AC voltage HVAC into a high DC voltage HVDC (unipolar voltage). Due to the presence of chopping, the high DC voltage HVDC is a non-fixed voltage. In order to provide a stable high DC voltage HVDC, a high DC voltage HVDC is filtered using a smoothing capacitor C1 to reduce chopping. The shunt regulation circuit 120 includes a resistor R, a Zener diode Z, and a capacitor C2, wherein the shunt regulator circuit 120 can eliminate any remaining chopping and can maintain adjustments for different supply voltages and loads. According to the DC voltage HVDC, the resistor R and the Zener diode Z generate an adjusted DC voltage. Capacitor C2 is connected in parallel to Zener diode Z to further reduce chopping and diode noise.

整流電路110以及分路調節電路120係由離散電阻、電容以及二極體所組成。然而，離散元件的成本較高且會佔用到較多的印刷電路板面積。此外，在分路調節電路120內，由於持續流經電阻R以及齊納二極體Z的電流，將導致有耗電的情況存在。同時，假如傳統穩壓電路係操作在高壓下(例如120V或240V AC)，則耗電的情況將會更嚴重。因此，需要一種超高壓穩壓器。The rectifier circuit 110 and the shunt regulation circuit 120 are composed of discrete resistors, capacitors, and diodes. However, the cost of discrete components is higher and will Occupy more printed circuit board area. Further, in the shunt regulation circuit 120, since the current flowing through the resistor R and the Zener diode Z continues to flow, power consumption may occur. At the same time, if the traditional voltage regulator circuit is operated under high voltage (such as 120V or 240V AC), the power consumption will be more serious. Therefore, there is a need for an ultra high voltage regulator.

本發明提供一種穩壓器，包括：一輸入節點，用以接收一供應電壓；一輸出節點，用以提供一供應電壓；一第一電晶體，耦接於上述輸入節點以及一第一節點之間；一第一電阻，耦接於上述輸入節點以及上述第一電晶體的閘極之間；一第二電晶體，耦接於上述第一節點以及上述輸出節點之間；一放大器，具有一反相輸入端以及用以接收一參考電壓之一非反相輸入端；一第二電阻，耦接於上述反相輸入端以及一接地端之間；一第三電晶體，耦接於上述第二電阻以及上述第二電晶體的閘極之間，其中上述第三電晶體係由上述放大器的輸出所控制；以及，一第四電晶體，耦接於上述第三電晶體以及上述第一節點之間，其中上述第四電晶體的閘極係耦接於上述第二電晶體的閘極。The present invention provides a voltage regulator comprising: an input node for receiving a supply voltage; an output node for providing a supply voltage; a first transistor coupled to the input node and a first node a first resistor coupled between the input node and the gate of the first transistor; a second transistor coupled between the first node and the output node; an amplifier having a An inverting input terminal and a non-inverting input terminal for receiving a reference voltage; a second resistor coupled between the inverting input terminal and a ground terminal; a third transistor coupled to the first Between the two resistors and the gate of the second transistor, wherein the third transistor system is controlled by the output of the amplifier; and a fourth transistor coupled to the third transistor and the first node The gate of the fourth transistor is coupled to the gate of the second transistor.

再者，本發明提供一種交流對直流轉換器，包括：一輸入節點，用以接收一交流電壓；一輸出節點，用以提供一供應電壓；一整流電路，用以將上述交流電壓轉換成一直流電壓；以及一穩壓器，用以接收上述直流電壓以產生上述供應電壓。上述穩壓器包括：一第一電晶體，耦接於上述整流電路以及一第一節點之間；一第一電阻，耦接於上述整流電路以及上述第一電晶體的閘極之間；一第二電晶體，耦接於上述第一節點以及上述輸出節點之間；一放大器，具有一反相輸入端以及用以接收一參考電壓之一非反相輸入端；一第二電阻，耦接於上述反相輸入端以及一接地端之間；一第三電晶體，耦接於上述第二電阻以及上述第二電晶體的閘極之間，其中上述第三電晶體係由上述放大器的輸出所控制；一第四電晶體，耦接於上述第三電晶體以及上述第一節點之間，其中上述第四電晶體的閘極係耦接於上述第二電晶體的閘極；一第一開關，耦接於上述第二電晶體的閘極以及上述第一節點之間；以及一判斷電路，用以根據上述供應電壓以及上述參考電壓而控制上述第一開關。當上述參考電壓大於一第一電壓時，上述第一開關為不導通，以及當上述參考電壓小於一第二電壓時，上述第一開關為導通，其中上述第一電壓係大於上述第二電壓。Furthermore, the present invention provides an AC-to-DC converter comprising: an input node for receiving an AC voltage; an output node for providing a supply voltage; and a rectifier circuit for converting the AC voltage into a DC current And a voltage regulator for receiving the DC voltage to generate the supply voltage. The voltage regulator includes: a first transistor coupled between the rectifier circuit and a first node; a first resistor coupled to the first resistor a rectifier circuit and a gate of the first transistor; a second transistor coupled between the first node and the output node; an amplifier having an inverting input and receiving a reference a non-inverting input terminal; a second resistor coupled between the inverting input terminal and a ground terminal; a third transistor coupled to the second resistor and the gate of the second transistor Between the poles, wherein the third transistor system is controlled by the output of the amplifier; a fourth transistor coupled between the third transistor and the first node, wherein the gate of the fourth transistor Is coupled to the gate of the second transistor; a first switch coupled between the gate of the second transistor and the first node; and a determining circuit for using the supply voltage and the The first switch is controlled by the reference voltage. When the reference voltage is greater than a first voltage, the first switch is non-conductive, and when the reference voltage is less than a second voltage, the first switch is conductive, wherein the first voltage is greater than the second voltage.

為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：The above and other objects, features and advantages of the present invention will become more <RTIgt;

實施例：Example:

第2圖係顯示根據本發明一實施例所述之交流對直流轉換器200。交流對直流轉換器200從輸入節點N_in 接收高交流電壓HVAC，並經由輸出節點N_out 提供供應電壓VCC。交流對直流轉換器200包括整流電路210以及穩壓器220。由於高阻隔電壓及電流的特性，整流電路210為離散元件。整流電路210將高交流電壓HVAC轉換成高直流電壓HVDC。穩壓器220對高直流電壓HVDC進行調整以產生供應電壓VCC。在一實施例中，藉由積體電路之高壓製程能力，穩壓器220可設置於積體電路內。Figure 2 shows an AC to DC converter 200 in accordance with an embodiment of the present invention. The AC-to-DC converter 200 receives a high AC voltage HVAC from the input node N _in and provides a supply voltage VCC via the output node N _out . The AC to DC converter 200 includes a rectifier circuit 210 and a voltage regulator 220. Due to the high barrier voltage and current characteristics, the rectifier circuit 210 is a discrete component. The rectifier circuit 210 converts the high AC voltage HVAC into a high DC voltage HVDC. The regulator 220 adjusts the high DC voltage HVDC to generate the supply voltage VCC. In one embodiment, the voltage regulator 220 can be disposed in the integrated circuit by the high voltage process capability of the integrated circuit.

第3圖係顯示根據本發明一實施例所述之交流對直流轉換器內穩壓器300之方塊圖。穩壓器300可從輸入節點N_in 接收輸入電壓HVDC，並經由輸出節點N_out 提供供應電壓VCC至負載C_load 。穩壓器300包括主電路310以及判斷電路320。此外，穩壓器300更包括電晶體SW1、二極體D1、電晶體M5以及二極體串(diode chain)330。電晶體SW1係耦接於電晶體M2的閘極以及節點N₁ 之間，其為作為開關使用之電晶體，用以控制主電路310是否正常操作。二極體D1係耦接於電晶體M2以及輸出節點N_out 之間。二極體串330具有四個二極體D2-D5，其中各二極體係以由電晶體M1之閘極至電晶體M5之順向導通方向而電性連接。電晶體M5係耦接於二極體串330以及接地端GND之間，而電晶體M5之閘極係耦接於輸出節點N_out 。在此實施例中，電晶體M5與二極體串330可形成保護電路，以避免電壓V_G 及電壓V_S 的增加會超過穩壓器300內元件的崩潰電壓。Figure 3 is a block diagram showing an AC-to-DC converter internal voltage regulator 300 in accordance with an embodiment of the present invention. The voltage regulator 300 can receive the input voltage HVDC from the input node N _in and supply the supply voltage VCC to the load C _load via the output node N _out . The voltage regulator 300 includes a main circuit 310 and a determination circuit 320. In addition, the voltage regulator 300 further includes a transistor SW1, a diode D1, a transistor M5, and a diode chain 330. SW1-based transistor coupled to the gate of transistor M2 and between the node N _1, which is used as the switching transistor for controlling whether or not the main circuit 310 to operate normally. The diode D1 is coupled between the transistor M2 and the output node _Nout . The diode string 330 has four diodes D2-D5, wherein each of the two-pole systems is electrically connected by a forward conduction direction from the gate of the transistor M1 to the transistor M5. The transistor M5 is coupled between the diode string 330 and the ground GND, and the gate of the transistor M5 is coupled to the output node _Nout . In this embodiment, the transistor M5 and the diode string 330 can form a protection circuit to prevent the voltage V _G and the voltage V _S from increasing beyond the breakdown voltage of the components in the regulator 300.

在主電路310中，電晶體M1與電阻R1為高壓元件，其可根據半導體製程的技術而承受400V或更高的電壓。在正常操作期間，儘管高壓元件是操作於低電壓下，其仍會遭受到較大的壓降。電阻R1係耦接於輸入節點N_in 以及二極體串330之間。電晶體M1係耦接於輸入節點N_in 以及節點N₁ 之間，其中電晶體M1的閘極係耦接於電阻R1。透過電阻R1，可對電晶體M1進行偏壓，使得電晶體M1能操作在飽和區。因此，可從輸入節點N_in 提供電流至節點N₁ 。如第3圖所顯示，電晶體M1之閘極上的電壓V_G 係相等於供應電壓VCC再加上電晶體M5之閘極對源極電壓以及四個二極體的壓降，其中二極體的壓降為跨在二極體D2-D5之順向電壓。值得注意的是，二極體串330內二極體的數量是根據不同設計及應用而決定。電晶體M2係耦接於節點N₁ 以及二極體D1之間，而電晶體M4係耦接於節點N₁ 以及電晶體M3之間，其中電晶體M2與電晶體M4形成電流鏡對，其可控制從電晶體M1流至輸出節點N_out 的電流。此外，電晶體M2與M4的閘極皆耦接至開關SW1。流經電晶體M4的電流係由電晶體M3所控制。電晶體M3係耦接於電晶體M4以及電阻R2之間，並由放大器312的輸出所控制。放大器312具有反相輸入端(-)與非反相輸入端(+)，其中非反相輸入端係用以接收參考電壓V_ref 而反相輸入端係耦接於電阻R2。因此，根據下列算式(1)，可計算出流經電晶體M2的電流I_M2 ：其中K為電晶體M2之寬長比(W/L)對電晶體M4之寬長比的比值。值得注意的是，電晶體M2之寬長比係大於電晶體M4之寬長比，因此流經電晶體M2的電流會大於流經電晶體M4的電流。再者，流經電晶體M2的電流係相同於流經電晶體M1與二極體D1之電流，即電流I。二極體D1可允許電流I從輸入節點N_in 流至輸出節點N_out ，但是會阻隔來自於輸出節點N_out 之反向電流。電流I會對負載C_load 進行充電，使得供應電壓VCC會開始增加。In the main circuit 310, the transistor M1 and the resistor R1 are high voltage elements which can withstand a voltage of 400 V or higher depending on the technology of the semiconductor process. During normal operation, although the high voltage component is operating at a low voltage, it will still experience a large voltage drop. The resistor R1 is coupled between the input node N _in and the diode string 330 . The transistor M1 is coupled between the input node N _in and the node N ₁ , wherein the gate of the transistor M1 is coupled to the resistor R1 . The transistor M1 can be biased through the resistor R1 so that the transistor M1 can operate in the saturation region. Therefore, current can be supplied from the input node N _in to the node N ₁ . As shown in FIG. 3, the voltage V _G on the gate of the transistor M1 is equal to the supply voltage VCC plus the gate-to-source voltage of the transistor M5 and the voltage drop of the four diodes, wherein the diode The voltage drop is the forward voltage across the diode D2-D5. It is worth noting that the number of diodes in the diode string 330 is determined according to different designs and applications. The transistor M2 is coupled between the node N ₁ and the diode D1, and the transistor M4 is coupled between the node N ₁ and the transistor M3, wherein the transistor M2 forms a current mirror pair with the transistor M4. controllable current of the output node N _out to flow from the transistor M1. In addition, the gates of the transistors M2 and M4 are all coupled to the switch SW1. The current flowing through the transistor M4 is controlled by the transistor M3. The transistor M3 is coupled between the transistor M4 and the resistor R2 and controlled by the output of the amplifier 312. The amplifier 312 has an inverting input terminal (-) and a non-inverting input terminal (+), wherein the non-inverting input terminal is configured to receive the reference voltage V _ref and the inverting input terminal is coupled to the resistor R2. Therefore, according to the following formula (1), the current I _M2 flowing through the transistor M2 can be calculated: Where K is the ratio of the aspect ratio (W/L) of the transistor M2 to the aspect ratio of the transistor M4. It is worth noting that the width-to-length ratio of the transistor M2 is greater than the aspect ratio of the transistor M4, so the current flowing through the transistor M2 is greater than the current flowing through the transistor M4. Furthermore, the current flowing through the transistor M2 is the same as the current flowing through the transistor M1 and the diode D1, that is, the current I. The diode D1 can allow the current I to flow from the input node N _in to the output node N _out , but will block the reverse current from the output node N _out . Current I charges the load C _load so that the supply voltage VCC begins to increase.

參考第3圖，判斷電路320包括分壓單元340、兩比較器350及360、控制電路370以及四個電晶體M6、M7、SW2與SW3。在此實施例中，電晶體SW2以及電晶體SW3為作為開關使用之電晶體。分壓單元340係耦接於輸出節點N_out 以及接地端GND之間，並包括電阻R3、R4及R5。再者，分壓單元340可根據供應電壓VCC而提供電壓V₁ 與電壓V₂ ，其中電壓V₁ 係大於電壓V₂ 。電阻R4係耦接於電阻R3與R5之間，而電壓V₁ 與電壓V₂ 之間的電壓差為跨在電阻R4上的電壓(即電阻R4的跨壓)。比較器350對電壓V₁ 與參考電壓V_ref 進行比較以產生比較信號S_c1 ，而比較器360對電壓V₂ 與參考電壓V_ref 進行比較以產生比較信號S_c2 。控制電路370會根據比較信號S_c1 及S_c2 來控制開關SW2以及開關SW3是否導通。控制電路370包括D型正反器372以及反相器374。反相器374接收比較信號S_c1 以產生信號S_c1B 。D型正反器372包括資料端D、重置端RST用以接收信號S_c1 、時脈端CLK用以接收比較信號S_c2 以及兩輸出端Q及QB，其中輸出端QB所提供之資料為輸出端Q所提供之資料的補數。開關SW2係耦接於節點N₂ 以及接地端GND之間，而其控制端係耦接於輸出端Q。開關SW3係耦接於節點N₃ 及接地端GND之間，而其控制端係耦接於輸出端QB。電晶體M6係耦接於節點N₁ 及節點N₂ 之間，而電晶體M7係耦接於節點N₁ 及節點N₃ 間，其中電晶體M6以及電晶體M7的閘極係分別耦接於節點N₃ 以及節點N₂ 。此外，開關SW1控制端係耦接於節點N₂ 。Referring to FIG. 3, the decision circuit 320 includes a voltage dividing unit 340, two comparators 350 and 360, a control circuit 370, and four transistors M6, M7, SW2, and SW3. In this embodiment, the transistor SW2 and the transistor SW3 are transistors used as switches. The voltage dividing unit 340 is coupled between the output node N _out and the ground GND, and includes resistors R3, R4, and R5. Furthermore, the voltage dividing unit 340 can provide the voltage V ₁ and the voltage V ₂ according to the supply voltage VCC, wherein the voltage V ₁ is greater than the voltage V ₂ . Department of resistor R4 is coupled between the resistors R3 and R5, the voltage V ₁ is the voltage difference between _the voltage V across the resistor R4 as a voltage (i.e. the voltage across the resistor R4). Comparator 350 pairs of voltage V ₁ is compared with the reference voltage V _ref to generate a comparison signal S _c1, and the comparator 360 compares the voltage V ₂ is compared with the reference voltage V _ref to generate a comparison signal S _c2. The control circuit 370 controls whether the switch SW2 and the switch SW3 are turned on based on the comparison signals S _c1 and S _c2 . Control circuit 370 includes a D-type flip-flop 372 and an inverter 374. Inverter 374 receives comparison signal S _c1 to generate signal S _c1B . The D-type flip-flop 372 includes a data terminal D, a reset terminal RST for receiving the signal S _c1 , a clock terminal CLK for receiving the comparison signal S _c2 and two output terminals Q and QB, wherein the data provided by the output terminal QB is The complement of the data provided by the output Q. The switch SW2 is coupled between the node N ₂ and the ground GND, and the control end is coupled to the output terminal Q. The switch SW3 is coupled between the node N ₃ and the ground GND, and the control end is coupled to the output terminal QB. The transistor M6 is coupled between the node N ₁ and the node N ₂ , and the transistor M7 is coupled between the node N ₁ and the node N ₃ , wherein the gates of the transistor M6 and the transistor M7 are respectively coupled to Node N ₃ and node N ₂ . In addition, the control terminal of the switch SW1 is coupled to the node N ₂ .

首先，供應電壓VCC為低電壓位準。由於電壓V₁ 小於參考電壓V_ref ，因此比較信號S_c1 為邏輯位準“1”，於是D型正反器372被重置。同時地，比較信號S_c2 為邏輯位準“0”。由輸出端Q及輸出端QB所提供之信號分別為邏輯位準“0”與“1”，因此開關SW2為不導通而開關SW3為導通。在開關SW3為導通的情況下，節點N₃ 上的電壓V₃ 會被拉低。接著，在開關SW2為不導通的情況下，具有低電壓位準的電壓V₃ 將會導通電晶體M6，以上拉節點N₂ 上的電壓V₄ 。接著，電壓V₄ 被上拉至高電壓位準，使得開關SW1變為不導通。當開關SW1為不導通時，電流鏡對(電晶體M2與M4)為正常工作，而流經電晶體M2的電流I會對負載C_load 進行充電，以維持供應電壓VCC能繼續增加。在分壓單元340中，電壓V₁ 以及電壓V₂ 係與供應電壓VCC成比例增加，其中根據下列算式(2)和(3)可分別計算出電壓V₁ 和電壓V₂ ：當供應電壓VCC持續增加時，電壓V₁ 將會變得比參考電壓V_ref 還要高。接著，比較信號S_c1 會從邏輯位準“1”變為“0”，其將使得D型正反器372準備去接收時脈信號。當供應電壓VCC仍繼續增加時，電壓V₂ 會變得比參考電壓V_ref 還要高，其將使得比較信號S_c2 會從邏輯位準“0”變為“1”。由於D型正反器372為邊緣觸發之D型正反器，比較信號S_c2 的轉變將會觸發D型正反器372以改變其輸出狀態。由輸出端Q所提供之信號的初始狀態為邏輯位準“0”。在觸發發生之後，由於D型正反器372之輸入信號S_c1B 為邏輯位準“1”，因此由輸出端Q所提供之信號會由邏輯位準“0”變為邏輯位準“1”。First, the supply voltage VCC is at a low voltage level. Since the voltage V _{1 is} smaller than the reference voltage V _ref , the comparison signal S _c1 is at the logic level "1", and then the D-type flip-flop 372 is reset. Simultaneously, the comparison signal S _c2 is a logic level "0". The signals provided by the output terminal Q and the output terminal QB are logic levels "0" and "1", respectively, so the switch SW2 is non-conductive and the switch SW3 is turned on. In the case where the switch SW3 is turned on, the voltage V at the node N _{₃ 3} goes low. Next, in a case where the switch SW2 is not turned on, a low voltage level of the voltage V ₃ M6 will turn-crystal, pull up on the node voltage V N ₂ _4. Then, the voltage V ₄ is pulled up to a high voltage level, so that the switch SW1 becomes non-conductive. When the switch SW1 is non-conducting, the current mirror pair (the transistors M2 and M4) is normally operated, and the current I flowing through the transistor M2 charges the load C _load to maintain the supply voltage VCC to continue to increase. In the voltage dividing unit 340, the voltage V ₁ and the voltage V ₂ are proportionally increased in proportion to the supply voltage VCC, wherein the voltage V ₁ and the voltage V ₂ can be respectively calculated according to the following formulas (2) and (3): When the supply voltage VCC continues to increase, the voltage V ₁ will become higher than the reference voltage V _ref . Next, the comparison signal S _c1 will change from a logic level "1" to a "0", which will cause the D-type flip-flop 372 to be ready to receive the clock signal. When the supply voltage VCC continues to increase, the voltage V ₂ will become higher than the reference voltage V _ref , which will cause the comparison signal S _{c2 to} change from the logic level "0" to "1". Since the D-type flip-flop 372 is an edge-triggered D-type flip-flop, the transition of the comparison signal S _c2 will trigger the D-type flip-flop 372 to change its output state. The initial state of the signal provided by the output Q is a logic level "0". After the trigger occurs, since the input signal S _c1B of the D-type flip-flop 372 is a logic level "1", the signal provided by the output terminal Q is changed from the logic level "0" to the logic level "1". .

在D型正反器372的輸出狀態改變之後，開關SW2為導通而開關SW3為不導通。因此，電壓V₄ 被下拉，使得開關SW1導通。接著，電晶體M2與電晶體M4的閘極以及源極會短路。因此，電晶體M2與電晶體M4變為不導通，使得電流I停止流經電晶體M2。當電流I被停止時，負載C_load 的充電電流亦會被停止，然後負載C_load 會開始進行放電。接著，供應電壓VCC會開始下降直到電壓V₁ 些微低於參考電壓V_ref 。如先前所描述，當電壓V₁ 小於參考電壓V_ref 時，比較信號S_c1 會變為邏輯位準“1”，以對D型正反器372進行重置。接著，開關SW3為導通而開關SW2為不導通，使得電壓V_S 相同於電壓V₄ 。接著，開關SW1為不導通，然後電流鏡對(電晶體M2與M4)會開始恢復工作，以便增加供應電壓VCC。因此，供應電壓VCC可被增加至最大電壓值以及減少至最小電壓值，其中最大和最小電壓值係根據參考電壓V_ref 而決定。例如，當電壓V₂ 大於參考電壓V_ref 時，則可決定出供應電壓VCC的最大電壓值，而當電壓V₁ 小於參考電壓V_ref 時，則可決定出供應電壓VCC的最小電壓值，其中電壓V₁ 與電壓V₂ 係分別根據算式(2)和(3)所求得。再者，最大和最小電壓值可形成供應電壓VCC之操作視窗電壓。After the output state of the D-type flip-flop 372 is changed, the switch SW2 is turned on and the switch SW3 is turned off. Therefore, the voltage V ₄ is pulled down, causing the switch SW1 to be turned on. Then, the transistor M2 and the gate and source of the transistor M4 are short-circuited. Therefore, the transistor M2 and the transistor M4 become non-conductive, so that the current I stops flowing through the transistor M2. When the current I is stopped, the charging current of the load C _load is also stopped, and then the load C _load starts to discharge. Then, the supply voltage VCC will start to drop until the voltage V _{1 is} slightly lower than the reference voltage V _ref . As previously described, when the voltage V _{1 is} less than the reference voltage V _ref , the comparison signal S _c1 becomes a logic level "1" to reset the D-type flip-flop 372. Next, the switch SW3 is turned on and the switch SW2 is turned off, so that the voltage V _{S is the} same as the voltage V ₄ . Then, the switch SW1 is non-conducting, and then the current mirror pair (the transistors M2 and M4) will start to resume operation to increase the supply voltage VCC. Therefore, the supply voltage VCC can be increased to the maximum voltage value and reduced to the minimum voltage value, wherein the maximum and minimum voltage values are determined according to the reference voltage V _ref . For example, when the voltage V _{2 is} greater than the reference voltage V _ref , the maximum voltage value of the supply voltage VCC can be determined, and when the voltage V _{1 is} less than the reference voltage V _ref , the minimum voltage value of the supply voltage VCC can be determined, wherein The voltage V ₁ and the voltage V ₂ are obtained according to the equations (2) and (3), respectively. Furthermore, the maximum and minimum voltage values can form an operating window voltage of the supply voltage VCC.

藉由控制流經穩壓器300之電流I是否導通，可得到間歇的電流I，使得供應電壓VCC不會一直維持在峰值位準，因而可減少平均耗電。再者，穩壓器300可設置於積體電路內以減少印刷電路板的面積以及成本。By controlling whether the current I flowing through the regulator 300 is turned on, an intermittent current I can be obtained, so that the supply voltage VCC is not always maintained at the peak level, thereby reducing the average power consumption. Furthermore, the voltage regulator 300 can be placed in the integrated circuit to reduce the area and cost of the printed circuit board.

本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100、200‧‧‧交流對直流轉換器100,200‧‧‧AC to DC converter

110、210‧‧‧整流電路110, 210‧‧‧Rectifier circuit

120‧‧‧分路調節電路120‧‧ ‧ shunt regulation circuit

220、300‧‧‧穩壓器220, 300‧‧‧ voltage regulator

310‧‧‧主電路310‧‧‧ main circuit

312‧‧‧放大器312‧‧Amplifier

320‧‧‧判斷電路320‧‧‧Judgement circuit

330‧‧‧二極體串330‧‧‧Diode string

340‧‧‧分壓單元340‧‧‧Voltage unit

350、360‧‧‧比較器350, 360‧‧‧ comparator

370‧‧‧控制電路370‧‧‧Control circuit

372‧‧‧D型正反器372‧‧‧D type flip-flop

374‧‧‧反相器374‧‧‧Inverter

C1、C2‧‧‧電容C1, C2‧‧‧ capacitor

C_load ‧‧‧負載C _load ‧‧‧load

D1-D5‧‧‧二極體D1-D5‧‧‧ diode

GND‧‧‧接地端GND‧‧‧ ground terminal

HVAC‧‧‧高交流電壓HVAC‧‧‧High AC voltage

HVDC‧‧‧高直流電壓HVDC‧‧‧High DC voltage

M1-M7、SW1-SW3‧‧‧電晶體M1-M7, SW1-SW3‧‧‧O crystal

N₁ -N₃ ‧‧‧節點N ₁ -N ₃ ‧‧‧ nodes

N_in ‧‧‧輸入節點N _in ‧‧‧Input node

N_out ‧‧‧輸出節點N _out ‧‧‧output node

R、R1-R5‧‧‧電阻R, R1-R5‧‧‧ resistance

V₁ -V₄ 、V_G 、V_S ‧‧‧電壓V ₁ -V ₄ , V _G , V _S ‧‧‧ voltage

VCC‧‧‧供應電壓VCC‧‧‧ supply voltage

VREF‧‧‧參考電壓VREF‧‧‧reference voltage

S_c1 、S_c1B 、S_c2 ‧‧‧信號S _c1 , S _c1B , S _c2 ‧‧‧ signals

Z‧‧‧齊納二極體Z‧‧‧Zina diode

第1圖係顯示一傳統交流對直流轉換器；第2圖係顯示根據本發明一實施例所述之交流對直流轉換器；以及第3圖係顯示根據本發明一實施例所述之交流對直流轉換器內穩壓器之方塊圖。1 is a conventional AC to DC converter; FIG. 2 is an AC to DC converter according to an embodiment of the invention; and FIG. 3 is an AC pair according to an embodiment of the invention. Block diagram of the regulator in the DC converter.

300‧‧‧穩壓器300‧‧‧Regulator

310‧‧‧主電路310‧‧‧ main circuit

312‧‧‧放大器312‧‧Amplifier

320‧‧‧判斷電路320‧‧‧Judgement circuit

330‧‧‧二極體串330‧‧‧Diode string

340‧‧‧分壓單元340‧‧‧Voltage unit

350、360‧‧‧比較器350, 360‧‧‧ comparator

370‧‧‧控制電路370‧‧‧Control circuit

372‧‧‧D型正反器372‧‧‧D type flip-flop

374‧‧‧反相器374‧‧‧Inverter

C_load ‧‧‧負載C _load ‧‧‧load

D1-D5‧‧‧二極體D1-D5‧‧‧ diode

GND‧‧‧接地端GND‧‧‧ ground terminal

HVDC‧‧‧高直流電壓HVDC‧‧‧High DC voltage

M1-M7、SW1-SW3‧‧‧電晶體M1-M7, SW1-SW3‧‧‧O crystal

N₁ -N₃ ‧‧‧節點N ₁ -N ₃ ‧‧‧ nodes

N_in ‧‧‧輸入節點N _in ‧‧‧Input node

N_out ‧‧‧輸出節點N _out ‧‧‧output node

R1-R5‧‧‧電阻R1-R5‧‧‧ resistance

VCC‧‧‧供應電壓VCC‧‧‧ supply voltage

VREF‧‧‧參考電壓VREF‧‧‧reference voltage

S_c1 、S_c1B 、S_c2 ‧‧‧信號S _c1 , S _c1B , S _c2 ‧‧‧ signals

Claims

一種穩壓器，包括：一輸入節點，用以接收一供應電壓；一輸出節點，用以提供一供應電壓；一第一電晶體，耦接於上述輸入節點以及一第一節點之間；一第一電阻，耦接於上述輸入節點以及上述第一電晶體的閘極之間；一第二電晶體，耦接於上述第一節點以及上述輸出節點之間；一放大器，具有一反相輸入端以及用以接收一參考電壓之一非反相輸入端；一第二電阻，耦接於上述反相輸入端以及一接地端之間；一第三電晶體，耦接於上述第二電阻以及上述第二電晶體的閘極之間，其中上述第三電晶體係由上述放大器的輸出所控制；以及一第四電晶體，耦接於上述第三電晶體以及上述第一節點之間，其中上述第四電晶體的閘極係耦接於上述第二電晶體的閘極。 A voltage regulator comprising: an input node for receiving a supply voltage; an output node for providing a supply voltage; a first transistor coupled between the input node and a first node; a first resistor coupled between the input node and the gate of the first transistor; a second transistor coupled between the first node and the output node; and an amplifier having an inverting input And a non-inverting input terminal for receiving a reference voltage; a second resistor coupled between the inverting input terminal and a ground terminal; a third transistor coupled to the second resistor and Between the gates of the second transistor, wherein the third transistor system is controlled by the output of the amplifier; and a fourth transistor coupled between the third transistor and the first node, wherein The gate of the fourth transistor is coupled to the gate of the second transistor.

如申請專利範圍第1項所述之穩壓器，更包括：一第一二極體，耦接於上述第二電晶體以及上述輸出節點之間，用以阻隔來自於上述輸出節點之反向電流。 The voltage regulator of claim 1, further comprising: a first diode coupled between the second transistor and the output node for blocking a reversal from the output node Current.

如申請專利範圍第1項所述之穩壓器，更包括：一二極體串，耦接於上述第一電晶體的閘極，具有以串聯方式連接之複數第二二極體；以及一第五電晶體，耦接於上述二極體串以及上述接地端之間，具有耦接於上述輸出節點之閘極，其中，上述第二二極體係以由上述第一電晶體之閘極至上述第五電晶體之順向導通方向而電性連接。 The voltage regulator of claim 1, further comprising: a diode string coupled to the gate of the first transistor, a plurality of second diodes connected in series; and a fifth transistor coupled between the diode string and the grounding terminal, and having a gate coupled to the output node, wherein the second The pole system is electrically connected by a forward conduction direction from a gate of the first transistor to a fifth transistor.

如申請專利範圍第1項所述之穩壓器，更包括：一第一開關，耦接於上述第二電晶體的閘極以及上述第一節點之間，具有耦接於一第二節點之一控制端；以及一判斷電路，用以根據上述供應電壓以及上述參考電壓而控制上述第一開關。 The voltage regulator of claim 1, further comprising: a first switch coupled between the gate of the second transistor and the first node, coupled to a second node a control terminal; and a determining circuit for controlling the first switch according to the supply voltage and the reference voltage.

如申請專利範圍第4項所述之穩壓器，其中上述判斷電路包括：一分壓單元，用以根據上述供應電壓而提供一第一電壓以及一第二電壓，其中上述第一電壓係大於上述第二電壓；一第一比較器，用以對上述第一電壓與上述參考電壓進行比較，以產生一第一比較信號；以及一第二比較器，用以對上述第二電壓與上述參考電壓進行比較，以產生一第二比較信號，其中，當上述第一比較信號指示上述參考電壓大於上述第一電壓時，上述第一開關為不導通，以及當上述第二比較信號指示上述參考電壓小於上述第二電壓時，上述第一開關為導通。 The voltage regulator of claim 4, wherein the determining circuit comprises: a voltage dividing unit configured to provide a first voltage and a second voltage according to the supply voltage, wherein the first voltage system is greater than The second voltage; a first comparator for comparing the first voltage with the reference voltage to generate a first comparison signal; and a second comparator for the second voltage and the reference Comparing voltages to generate a second comparison signal, wherein when the first comparison signal indicates that the reference voltage is greater than the first voltage, the first switch is non-conducting, and when the second comparison signal indicates the reference voltage When the second voltage is less than the second voltage, the first switch is turned on.

如申請專利範圍第5項所述之穩壓器，其中上述分壓單元包括：一第三電阻，耦接於上述輸出節點；一第四電阻，耦接於上述第三電阻；一第五電阻，耦接於上述第四電阻以及上述接地端之間，其中，上述第一電壓以及上述第二電壓之間的電壓差係上述第四電阻的跨壓。 The voltage regulator according to claim 5, wherein the voltage dividing unit comprises: a third resistor coupled to the output node; a fourth resistor coupled to the third resistor; a fifth resistor coupled between the fourth resistor and the ground, wherein the first voltage And a voltage difference between the second voltages is a voltage across the fourth resistor.

如申請專利範圍第5項所述之穩壓器，其中上述判斷電路更包括：一第六電晶體，耦接於上述第一節點以及上述第二節點之間，具有耦接於一第三節點之閘極；一第七電晶體，耦接於上述第一節點以及上述第三節點之間，具有耦接於上述第二節點之閘極；一第二開關，耦接於上述第二節點以及上述接地端之間；一第三開關，耦接於上述第三節點以及上述接地端之間；以及一控制電路，用以根據上述第一比較信號以及上述第二比較信號而控制上述第二開關以及上述第三開關，其中，當上述第一比較信號指示上述參考電壓大於上述第一電壓時，上述第二開關為不導通而上述第三開關為導通，以及當上述第二比較信號指示上述參考電壓小於上述第二電壓時，上述第二開關為導通而上述第三開關為不導通。 The voltage regulator of claim 5, wherein the determining circuit further comprises: a sixth transistor coupled between the first node and the second node, coupled to a third node a gate, a seventh transistor coupled between the first node and the third node, having a gate coupled to the second node; a second switch coupled to the second node and a third switch coupled between the third node and the ground end; and a control circuit for controlling the second switch according to the first comparison signal and the second comparison signal And the third switch, wherein when the first comparison signal indicates that the reference voltage is greater than the first voltage, the second switch is non-conductive and the third switch is conductive, and when the second comparison signal indicates the reference When the voltage is less than the second voltage, the second switch is turned on and the third switch is turned off.

如申請專利範圍第7項所述之穩壓器，其中上述控制電路包括：一反相器，用以對上述第一比較信號進行反相；一D型正反器，包括：一資料端，用以接收反相之上述第一比較信號；一時脈端，用以接收上述第二比較信號；一重置端，用以接收上述第一比較信號；一第一輸出端，用以提供一第一輸出資料至上述第二開關；以及一第二輸出端，用以提供一第二輸出資料至上述第三開關，其中上述第二輸出資料為上述第一輸出資料之補數。 The voltage regulator of claim 7, wherein the control circuit comprises: An inverter for inverting the first comparison signal; a D-type flip-flop comprising: a data terminal for receiving the inverted first comparison signal; and a clock terminal for receiving the a second comparison signal; a reset terminal for receiving the first comparison signal; a first output terminal for providing a first output data to the second switch; and a second output terminal for providing a The second output data is to the third switch, wherein the second output data is a complement of the first output data.

如申請專利範圍第1項所述之穩壓器，其中上述第二電晶體以及上述第四電晶體組成一電流鏡對，且上述第二電晶體的尺寸係大於上述第四電晶體。 The voltage regulator of claim 1, wherein the second transistor and the fourth transistor form a current mirror pair, and the second transistor has a larger size than the fourth transistor.

如申請專利範圍第1項所述之穩壓器，其中上述第一電晶體以及上述第一電阻為高壓元件。 The voltage regulator of claim 1, wherein the first transistor and the first resistor are high voltage components.

一種交流對直流轉換器，包括：一輸入節點，用以接收一交流電壓；一輸出節點，用以提供一供應電壓；一整流電路，用以將上述交流電壓轉換成一直流電壓；以及一穩壓器，用以接收上述直流電壓以產生上述供應電壓，包括：一第一電晶體，耦接於上述整流電路以及一第一節點之間；一第一電阻，耦接於上述整流電路以及上述第一電晶體的閘極之間，一第二電晶體，耦接於上述第一節點以及上述輸出節點之間；一放大器，具有一反相輸入端以及用以接收一參考電壓之一非反相輸入端；一第二電阻，耦接於上述反相輸入端以及一接地端之間；一第三電晶體，耦接於上述第二電阻以及上述第二電晶體的閘極之間，其中上述第三電晶體係由上述放大器的輸出所控制；一第四電晶體，耦接於上述第三電晶體以及上述第一節點之間，其中上述第四電晶體的閘極係耦接於上述第二電晶體的閘極；一第一開關，耦接於上述第二電晶體的閘極以及上述第一節點之間，具有耦接於一第二節點之一控制端；以及一判斷電路，用以根據上述供應電壓以及上述參考電壓而控制上述第一開關，其中，當上述參考電壓大於一第一電壓時，上述第一開關為不導通，以及當上述參考電壓小於一第二電壓時，上述第一開關為導通，其中上述第一電壓係大於上述第二電壓。 An AC-to-DC converter includes: an input node for receiving an AC voltage; an output node for providing a supply voltage; a rectifier circuit for converting the AC voltage into a DC voltage; and a voltage regulator And receiving the DC voltage to generate the supply voltage, comprising: a first transistor coupled between the rectifier circuit and a first node; a first resistor coupled to the rectifier circuit and the foregoing One Between the gates of the transistor, a second transistor is coupled between the first node and the output node; an amplifier having an inverting input and receiving a non-inverting input of a reference voltage a second resistor coupled between the inverting input terminal and a ground terminal; a third transistor coupled between the second resistor and the gate of the second transistor, wherein the second The third transistor system is controlled by the output of the amplifier; a fourth transistor is coupled between the third transistor and the first node, wherein the gate of the fourth transistor is coupled to the second a gate of the transistor; a first switch coupled between the gate of the second transistor and the first node, having a control end coupled to a second node; and a determining circuit for Controlling the first switch according to the supply voltage and the reference voltage, wherein when the reference voltage is greater than a first voltage, the first switch is non-conducting, and when the reference voltage is less than a second voltage, Said first switch is turned on, wherein the first voltage is larger than the second voltage line.

如申請專利範圍第11項所述之交流對直流轉換器，其中上述穩壓器更包括：一第一二極體，耦接於上述第二電晶體以及上述輸出節點之間，用以阻隔來自於上述輸出節點之反向電流。 The AC-DC converter of claim 11, wherein the voltage regulator further includes: a first diode coupled to the second transistor and the output Between the nodes to block the reverse current from the output node.

如申請專利範圍第11項所述之交流對直流轉換器，其中上述穩壓器更包括：一二極體串，耦接於上述第一電晶體的閘極，具有以串聯方式連接之複數第二二極體；以及一第五電晶體，耦接於上述二極體串以及上述接地端之間，具有耦接於上述輸出節點之閘極，其中，上述第二二極體係以由上述第一電晶體之閘極至上述第五電晶體之順向導通方向而電性連接。 The AC-DC converter of claim 11, wherein the voltage regulator further comprises: a diode string coupled to the gate of the first transistor, having a plurality of series connected in series a second diode, coupled to the diode string and the ground terminal, having a gate coupled to the output node, wherein the second diode system is The gate of a transistor is electrically connected to the forward conduction direction of the fifth transistor.

如申請專利範圍第11項所述之交流對直流轉換器，其中上述判斷電路包括：一分壓單元，用以根據上述供應電壓而提供上述第一電壓以及上述第二電壓；一第一比較器，用以對上述第一電壓與上述參考電壓進行比較，以產生一第一比較信號；以及一第二比較器，用以對上述第二電壓與上述參考電壓進行比較，以產生一第二比較信號，其中，當上述第一比較信號指示上述參考電壓大於上述第一電壓時，上述第一開關為不導通，以及當上述第二比較信號指示上述參考電壓小於上述第二電壓時，上述第一開關為導通。 The AC-DC converter of claim 11, wherein the determining circuit comprises: a voltage dividing unit for providing the first voltage and the second voltage according to the supply voltage; a first comparator And comparing the first voltage with the reference voltage to generate a first comparison signal; and a second comparator for comparing the second voltage with the reference voltage to generate a second comparison a signal, wherein when the first comparison signal indicates that the reference voltage is greater than the first voltage, the first switch is non-conductive, and when the second comparison signal indicates that the reference voltage is less than the second voltage, the first The switch is conducting.

如申請專利範圍第14項所述之交流對直流轉換器，其中上述分壓單元包括：一第三電阻，耦接於上述輸出節點；一第四電阻，耦接於上述第三電阻；一第五電阻，耦接於上述第四電阻以及上述接地端之間，其中，上述第一電壓以及上述第二電壓之間的電壓差係上述第四電阻的跨壓。 The AC-DC converter of claim 14, wherein the voltage dividing unit comprises: a third resistor coupled to the output node; and a fourth resistor coupled to the third resistor; A fifth resistor is coupled between the fourth resistor and the ground terminal, wherein a voltage difference between the first voltage and the second voltage is a voltage across the fourth resistor.

如申請專利範圍第14項所述之交流對直流轉換器，其中上述判斷電路更包括：一第六電晶體，耦接於上述第一節點以及上述第二節點之間，具有耦接於一第三節點之閘極；一第七電晶體，耦接於上述第一節點以及上述第三節點之間，具有耦接於上述第二節點之閘極；一第二開關，耦接於上述第二節點以及上述接地端之間；一第三開關，耦接於上述第三節點以及上述接地端之間；以及一控制電路，用以根據上述第一比較信號以及上述第二比較信號而控制上述第二開關以及上述第三開關，其中，當上述第一比較信號指示上述參考電壓大於上述第一電壓時，上述第二開關為不導通而上述第三開關為導通，以及當上述第二比較信號指示上述參考電壓小於上述第二電壓時，上述第二開關為導通而上述第三開關為不導通。 The AC-DC converter of claim 14, wherein the determining circuit further comprises: a sixth transistor coupled between the first node and the second node, coupled to the first a third node, a seventh transistor coupled between the first node and the third node, having a gate coupled to the second node; a second switch coupled to the second a third switch coupled between the third node and the ground end; and a control circuit for controlling the first according to the first comparison signal and the second comparison signal The second switch and the third switch, wherein when the first comparison signal indicates that the reference voltage is greater than the first voltage, the second switch is non-conductive and the third switch is conductive, and when the second comparison signal indicates When the reference voltage is less than the second voltage, the second switch is conductive and the third switch is non-conductive.

如申請專利範圍第16項所述之交流對直流轉換器，其中上述控制電路包括：一反相器，用以對上述第一比較信號進行反相；一D型正反器，包括：一資料端，用以接收反相之上述第一比較信號；一時脈端，用以接收上述第二比較信號；一重置端，用以接收上述第一比較信號；一第一輸出端，用以提供一第一輸出資料至上述第二開關；以及一第二輸出端，用以提供一第二輸出資料至上述第三開關，其中上述第二輸出資料為上述第一輸出資料之補數。 The AC-DC converter of claim 16, wherein the control circuit comprises: an inverter for inverting the first comparison signal; and a D-type flip-flop, comprising: a data terminal for receiving the inverted first comparison signal; a clock terminal for receiving the second comparison signal; a reset terminal for receiving the first comparison signal; and a first output terminal And providing a second output data to the third switch, wherein the second output data is a complement of the first output data.

如申請專利範圍第11項所述之交流對直流轉換器，其中上述第二電晶體以及上述第四電晶體組成一電流鏡對，且上述第二電晶體的尺寸係大於上述第四電晶體。 The AC to DC converter of claim 11, wherein the second transistor and the fourth transistor form a current mirror pair, and the second transistor has a larger size than the fourth transistor.

如申請專利範圍第11項所述之交流對直流轉換器，其中上述第一電晶體以及上述第一電阻為高壓元件。 The AC to DC converter of claim 11, wherein the first transistor and the first resistor are high voltage components.