TWI386445B - Etching composition, method of preparing the same, method of etching an oxide film, and method of manufacturing a semiconductor device - Google Patents

Etching composition, method of preparing the same, method of etching an oxide film, and method of manufacturing a semiconductor device Download PDF

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TWI386445B
TWI386445B TW093131410A TW93131410A TWI386445B TW I386445 B TWI386445 B TW I386445B TW 093131410 A TW093131410 A TW 093131410A TW 93131410 A TW93131410 A TW 93131410A TW I386445 B TWI386445 B TW I386445B
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layer
etching
weight percent
oxide
etching composition
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Yong-Kyun Ko
Sang-Mun Chon
In-Hoi Doh
Pil-Kwon Jun
Sang-Mi Lee
Kwang-Shin Lim
Myoung-Ok Han
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Samsung Electronics Co Ltd
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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
    • C09K13/00—Etching, surface-brightening or pickling compositions
    • C09K13/04—Etching, surface-brightening or pickling compositions containing an inorganic acid
    • C09K13/08—Etching, surface-brightening or pickling compositions containing an inorganic acid containing a fluorine compound
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    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
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    • C—CHEMISTRY; METALLURGY
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    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D1/00—Detergent compositions based essentially on surface-active compounds; Use of these compounds as a detergent
    • C11D1/66—Non-ionic compounds
    • C11D1/72—Ethers of polyoxyalkylene glycols
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
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    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
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    • C11D3/00—Other compounding ingredients of detergent compositions covered in group C11D1/00
    • C11D3/02—Inorganic compounds ; Elemental compounds
    • C11D3/04—Water-soluble compounds
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • C—CHEMISTRY; METALLURGY
    • C11—ANIMAL OR VEGETABLE OILS, FATS, FATTY SUBSTANCES OR WAXES; FATTY ACIDS THEREFROM; DETERGENTS; CANDLES
    • C11D—DETERGENT COMPOSITIONS; USE OF SINGLE SUBSTANCES AS DETERGENTS; SOAP OR SOAP-MAKING; RESIN SOAPS; RECOVERY OF GLYCEROL
    • C11D2111/00—Cleaning compositions characterised by the objects to be cleaned; Cleaning compositions characterised by non-standard cleaning or washing processes
    • C11D2111/10—Objects to be cleaned
    • C11D2111/14—Hard surfaces
    • C11D2111/22—Electronic devices, e.g. PCBs or semiconductors

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Description

蝕刻組合物及其製備方法，蝕刻氧化物薄膜之方法，及製造半導體裝置之方法Etching composition and preparation method thereof, method of etching oxide film, and method of manufacturing semiconductor device

本發明係關於一種蝕刻組合物，且更詳言之，本發明係關於一種具有高度蝕刻選擇性之蝕刻組合物、一種製備其之方法、一種選擇性蝕刻一氧化物薄膜之方法及一種使用其製造一半導體裝置之方法。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an etching composition, and more particularly to an etching composition having a high etching selectivity, a method of preparing the same, a method of selectively etching an oxide film, and a method of using the same A method of fabricating a semiconductor device.

通常，半導體記憶體裝置(諸如DRAM或SRAM)中的電容器含有一儲存電極、一介電薄膜及一板電極。該介電薄膜通常由一具有低介電常數之材料製成，該材料諸如二氧化矽(SiO2 )、二氧化矽/氮化矽(SiO2 /Si3 N4 )及其類似物。Typically, a capacitor in a semiconductor memory device, such as a DRAM or SRAM, contains a storage electrode, a dielectric film, and a plate electrode. The dielectric film is usually made of a material having a low dielectric constant such as cerium oxide (SiO 2 ), cerium oxide/cerium nitride (SiO 2 /Si 3 N 4 ), and the like.

由於記憶體裝置之整合程度已增加至吉比特之範圍或更大，每單位單元之可用面積已減少至已在該等記憶體裝置之製造中出現問題之程度。在高度整合之裝置中可獲得的較小可用面積中形成一具有至少25 μF/單元之所要電容之電容器特別困難。Since the degree of integration of the memory device has increased to the extent of gigabit or greater, the available area per unit cell has been reduced to the extent that problems have occurred in the manufacture of such memory devices. It is particularly difficult to form a capacitor having a desired capacitance of at least 25 μF/cell in a smaller usable area available in a highly integrated device.

近來，在努力生產充足的電容時，已製造具有圓柱形狀結構之電容器。藉由利用該結構，電容器之內部與外部區域均形成電容區域。另外，增加儲存電極之高度允許電容之增加，而不占額外表面積。亦可在儲存電極上形成一半球狀晶粒(HSG)層以進一步增加電容器之表面積，藉此進一步增加電容。Recently, in an effort to produce a sufficient capacity, a capacitor having a cylindrical structure has been fabricated. By utilizing this structure, both the inner and outer regions of the capacitor form a capacitive region. In addition, increasing the height of the storage electrode allows for an increase in capacitance without occupying additional surface area. A semi-spherical grain (HSG) layer may also be formed on the storage electrode to further increase the surface area of the capacitor, thereby further increasing the capacitance.

在美國專利第6,413,813號(Jeng Erik發表)及美國專利第6,403,411號(Chih-Hsun Chu等人發表)中揭示了製造具有 HSG矽層之電容器的半導體記憶體裝置之方法。In the U.S. Patent No. 6,413,813 (published by Jeng Erik) and U.S. Patent No. 6,403,411 (issued by Chih-Hsun Chu et al.), A method of a semiconductor memory device for a capacitor of a HSG layer.

參看圖1A至1D，其為說明製造一半導體記憶體裝置之HSG電容器之習知方法之截面圖。1A through 1D are cross-sectional views showing a conventional method of fabricating an HSG capacitor of a semiconductor memory device.

如圖1A所示，隔離層15在基板10上形成以界定一活動區域。接著，在基板10之活動區域上形成閘極結構35。各個閘極結構35包括一閘電極20、一封頂層25及一隔離片30。隨後，源極/汲極區域40藉由在閘極結構35之間之一離子植入處理形成。一導電層在包括閘極結構35之基板10之整個表面上沉積，且接著將經沉積之導電層平面化以形成一接觸墊片45。一層間介電層(或層間絕緣層)50在基板10上形成。接著，圖案化層間介電層50以形成一曝露接觸墊片45之接觸孔。一導電層在層間介電層50上沉積以填充該接觸孔。接著平面化該導電層以形成一連接至接觸墊片45之儲存節點接觸插塞55。As shown in FIG. 1A, an isolation layer 15 is formed on the substrate 10 to define an active area. Next, a gate structure 35 is formed on the active region of the substrate 10. Each gate structure 35 includes a gate electrode 20, a top layer 25, and a spacer 30. Subsequently, the source/drain region 40 is formed by an ion implantation process between the gate structures 35. A conductive layer is deposited over the entire surface of the substrate 10 including the gate structure 35, and then the deposited conductive layer is planarized to form a contact pad 45. An interlayer dielectric layer (or interlayer insulating layer) 50 is formed on the substrate 10. Next, the interlayer dielectric layer 50 is patterned to form a contact hole exposing the contact pad 45. A conductive layer is deposited over the interlayer dielectric layer 50 to fill the contact holes. The conductive layer is then planarized to form a storage node contact plug 55 that is coupled to contact pads 45.

接著，如在圖1B中所示，隨後，一蝕刻中止層60及一下部犧牲層65在層間介電層50及儲存節點接觸插塞55上沉積。該蝕刻中止層60包括氮化物材料，且該下部犧牲層65包括諸如BPSG(硼磷矽酸鹽玻璃)之氧化物材料。Next, as shown in FIG. 1B, an etch stop layer 60 and a lower sacrificial layer 65 are subsequently deposited over the interlayer dielectric layer 50 and the storage node contact plugs 55. The etch stop layer 60 includes a nitride material, and the lower sacrificial layer 65 includes an oxide material such as BPSG (borophosphonite glass).

使用諸如PE-TEOS(電漿增強-正矽酸四乙酯)之氧化物材料在下部犧牲層65上形成一上部犧牲層70。隨後，蝕刻上部犧牲層70、下部犧牲層65及蝕刻中止層60以形成一曝露儲存節點接觸插塞55之儲存節點接觸孔75。An upper sacrificial layer 70 is formed on the lower sacrificial layer 65 using an oxide material such as PE-TEOS (plasma enhanced - tetraethyl orthosilicate). Subsequently, the upper sacrificial layer 70, the lower sacrificial layer 65, and the etch stop layer 60 are etched to form a storage node contact hole 75 exposing the storage node contact plug 55.

參看圖1C，在曝露之儲存節點接觸插塞55、儲存節點接觸孔75之內壁部分及上部犧牲層70上形成一摻雜多晶矽 層。接著圖案化該摻雜多晶矽層以在儲存節點接觸孔75之內壁部分及儲存節點接觸插塞55上形成一儲存電極80。接著，在儲存電極80上選擇性地形成一HSG矽層85。Referring to FIG. 1C, a doped polysilicon is formed on the exposed storage node contact plug 55, the inner wall portion of the storage node contact hole 75, and the upper sacrificial layer 70. Floor. The doped polysilicon layer is then patterned to form a storage electrode 80 on the inner wall portion of the storage node contact hole 75 and the storage node contact plug 55. Next, an HSG germanium layer 85 is selectively formed on the storage electrode 80.

接著，參看圖1D，移除上部犧牲層70及下部犧牲層65。通常，此藉由一利用氟化銨及氟化氫(LAL)蝕刻溶液之濕式蝕刻處理來實現。接著，連續地沉積一氧化物層或一氮化物層，及導電層。隨後圖案化導電層、氧化物層或氮化物層，及蝕刻中止層60以形成介電薄膜90及覆蓋儲存電極80上之一電池陣列區域之上部電極95，從而完成HSG電容器97。Next, referring to FIG. 1D, the upper sacrificial layer 70 and the lower sacrificial layer 65 are removed. Typically, this is accomplished by a wet etch process using an ammonium fluoride and hydrogen fluoride (LAL) etching solution. Next, an oxide layer or a nitride layer, and a conductive layer are continuously deposited. The conductive layer, the oxide layer or the nitride layer is then patterned, and the stop layer 60 is etched to form the dielectric film 90 and cover the upper electrode 95 of one of the battery array regions on the storage electrode 80, thereby completing the HSG capacitor 97.

該習知方法具有一缺點，即多晶矽儲存電極在HSG矽層之形成期間傾向於惡化。結果，當移除上部及下部犧牲層時，儲存電極易受損害。此將在下文中進一步解釋。This conventional method has the disadvantage that the polycrystalline germanium storage electrode tends to deteriorate during the formation of the HSG germanium layer. As a result, the storage electrode is susceptible to damage when the upper and lower sacrificial layers are removed. This will be further explained below.

圖2為在使用一習知LAL溶液蝕刻氧化物犧牲層之後的儲存電極之電子顯微鏡影像。2 is an electron microscope image of a storage electrode after etching a sacrificial oxide layer using a conventional LAL solution.

如圖2中所見，當移除上部及下部犧牲層時，多晶矽儲存電極受損害(A)。此係由於在用以生長HSG矽層之熱處理期間，儲存電極中之多晶矽結晶化。包含於用以移除氧化物犧牲層之LAL蝕刻溶液中的氟化銨(NH4 F)離子容易剝落結晶化多晶矽。因此，引入儲存電極之損害。As seen in Figure 2, the polycrystalline germanium storage electrode is damaged when the upper and lower sacrificial layers are removed (A). This is due to the crystallization of polycrystalline germanium in the storage electrode during the heat treatment for growing the HSG layer. The ammonium fluoride (NH 4 F) ions contained in the LAL etching solution used to remove the oxide sacrificial layer easily peel off the crystallized polycrystalline germanium. Therefore, the damage of the storage electrode is introduced.

在防止與LAL蝕刻溶液之使用相關之問題的努力中，已研究一種使用氟化氫與去離子水之混合比為大約5：1之蝕刻溶液來移除氧化物層之濕式蝕刻方法。In an effort to prevent problems associated with the use of LAL etching solutions, a wet etching method using an etching solution having a mixing ratio of hydrogen fluoride and deionized water of about 5:1 to remove an oxide layer has been studied.

圖3為在使用5：1氟化氫溶液蝕刻氧化物犧牲層之後的儲存電極之電子顯微鏡圖片。3 is an electron micrograph of a storage electrode after etching a sacrificial oxide layer using a 5:1 hydrogen fluoride solution.

參看圖3，當5：1氟化氫溶液用以移除上部及下部氧化物犧牲層時，與使用LAL蝕刻溶液之蝕刻處理相比，儲存電極相對未受損害。然而，在安置於基板上之蝕刻中止層上的蝕刻分散之量增加。蝕刻分散意味著蝕刻為不均勻的。另外，蝕刻之氮化物層之量亦增加，因此，當產生過蝕刻時，減少了蝕刻範圍。Referring to Figure 3, when a 5:1 hydrogen fluoride solution is used to remove the upper and lower oxide sacrificial layers, the storage electrode is relatively uncorrupted compared to the etching process using the LAL etching solution. However, the amount of etching dispersion on the etch stop layer disposed on the substrate increases. Etching dispersion means that the etching is uneven. In addition, the amount of the nitride layer to be etched also increases, so that when over-etching occurs, the etching range is reduced.

圖4A為解釋在使用習知5：1氟化氫溶液之浸漬技術之蝕刻處理之後，殘留氮化物層之厚度(蝕刻)分散之俯視圖。圖4B為解釋在使用習知5：1氟化氫溶液之循環技術之蝕刻處理之後，殘留氮化物層之厚度(蝕刻)分散之俯視圖。4A is a top plan view illustrating the thickness (etching) dispersion of the residual nitride layer after an etching process using a conventional 5:1 hydrogen fluoride solution impregnation technique. Figure 4B is a top plan view illustrating the thickness (etch) dispersion of the residual nitride layer after an etching process using a conventional 5:1 hydrogen fluoride solution cycle technique.

參看圖4A，執行一浸漬類型濕式蝕刻處理大約670秒。殘留在基板上之氮化物層之平均厚度大約為419。其最大厚度大約為442，且其最小厚度大約為373。即，在氮化物層之最大厚度與最小厚度之間的差值大約為69。因此，可得出結論，即對於氮化物層而言蝕刻處理為不均勻的。Referring to Figure 4A, a immersion type wet etch process is performed for approximately 670 seconds. The average thickness of the nitride layer remaining on the substrate is approximately 419. . Its maximum thickness is about 442 And its minimum thickness is about 373 . That is, the difference between the maximum thickness and the minimum thickness of the nitride layer is approximately 69. . Therefore, it can be concluded that the etching process is uneven for the nitride layer.

參看圖4B，執行一循環類型濕式蝕刻處理大約750秒。殘留在基板上之氮化物層之平均厚度大約為425。其最大厚度大約為444，且其最小厚度大約為405。即，在殘留氮化物層之最大厚度與最小厚度之間之差值大約為39。與浸漬類型濕蝕刻相比，該差值大大減少，但是對於氮化物層而言該濕蝕刻處理仍為不均勻的。Referring to Figure 4B, a cycle type wet etch process is performed for approximately 750 seconds. The average thickness of the nitride layer remaining on the substrate is approximately 425 . Its maximum thickness is about 444 And its minimum thickness is about 405 . That is, the difference between the maximum thickness and the minimum thickness of the residual nitride layer is approximately 39. . This difference is greatly reduced compared to the immersion type wet etch, but the wet etch process is still non-uniform for the nitride layer.

5：1氟化氫溶液之PH大約為1，即強酸。因此，濕式蝕刻處理在強酸環境下執行。結果，氮化物層被不均勻地蝕刻 且氮化物層之分散較高。另外，自基板之傾斜部分或背面部分剝落之顆粒可在基板之表面部分上在濕式蝕刻處理期間被吸收以致引入軟熔類型之缺陷。The pH of the 5:1 hydrogen fluoride solution is about 1, which is a strong acid. Therefore, the wet etching treatment is performed in a strong acid environment. As a result, the nitride layer is etched unevenly And the dispersion of the nitride layer is higher. In addition, particles peeled off from the inclined portion or the back portion of the substrate may be absorbed during the wet etching process on the surface portion of the substrate to introduce a defect of the reflow type.

根據本發明之一態樣，一種蝕刻組合物包括大約0.1至8重量百分比之氟化氫(HF)，大約10至25重量百分比之氟化銨(NH4 F)，大約0.0001至3重量百分比之非離子聚合物界面活性劑，及水(H2 O)。According to one aspect of the invention, an etching composition comprises from about 0.1 to 8 weight percent hydrogen fluoride (HF), from about 10 to 25 weight percent ammonium fluoride (NH 4 F), and from about 0.0001 to 3 weight percent nonionic Polymeric surfactant, and water (H 2 O).

根據本發明之另一態樣，一種製備蝕刻組合物之方法包括以下步驟：藉由將非離子聚合物界面活性劑與氟化氫溶液混合來製備第一混合物溶液，及藉由將水與該第一混合物溶液混合來製備第二混合物溶液。接著藉由將氟化銨溶液與該第二混合物溶液混合來製備蝕刻組合物。According to another aspect of the present invention, a method of preparing an etching composition includes the steps of: preparing a first mixture solution by mixing a nonionic polymer surfactant with a hydrogen fluoride solution, and by using water with the first The mixture solution is mixed to prepare a second mixture solution. An etching composition is then prepared by mixing an ammonium fluoride solution with the second mixture solution.

仍根據本發明之另一態樣，一種蝕刻方法包括以下步驟：在一基板上形成一氮化物層；在該氮化物層上方形成一氧化物層；及圖案化該氧化物層以形成曝露該氮化物層之接觸孔。接著，在該曝露之氮化物層及該接觸孔之內側壁部分上形成一多晶矽層圖案，且使用蝕刻組合物來移除該氧化物層。該蝕刻組合物包括非離子聚合物界面活性劑，其選擇性地吸附於多晶矽層圖案之表面部分，以鈍化該多晶矽層圖案。According to still another aspect of the present invention, an etching method includes the steps of: forming a nitride layer on a substrate; forming an oxide layer over the nitride layer; and patterning the oxide layer to form an exposed Contact hole of the nitride layer. Next, a polysilicon layer pattern is formed on the exposed nitride layer and the inner sidewall portion of the contact hole, and the oxide layer is removed using an etching composition. The etching composition includes a nonionic polymer surfactant selectively adsorbed to a surface portion of the polysilicon layer pattern to passivate the polysilicon layer pattern.

又根據本發明之另一態樣，一種製造半導體裝置之方法包括以下步驟：在一半導體基板上形成一蝕刻中止層；在該蝕刻中止層上形成第一氧化物層；在該第一氧化物層上 形成第二氧化物層；及部分地移除第一及第二氧化物層以曝露一接觸區域。接著，形成一多晶矽層圖案，其接觸該接觸區域，且使用蝕刻組合物來移除第一與第二氧化物層。該蝕刻組合物包括非離子聚合物界面活性劑，其選擇性地吸附於多晶矽層圖案之表面部分，以鈍化該多晶矽層圖案。According to still another aspect of the present invention, a method of fabricating a semiconductor device includes the steps of: forming an etch stop layer on a semiconductor substrate; forming a first oxide layer on the etch stop layer; and forming the first oxide layer Layer Forming a second oxide layer; and partially removing the first and second oxide layers to expose a contact region. Next, a polysilicon layer pattern is formed that contacts the contact regions and the first and second oxide layers are removed using an etching composition. The etching composition includes a nonionic polymer surfactant selectively adsorbed to a surface portion of the polysilicon layer pattern to passivate the polysilicon layer pattern.

下面參考多個較佳但非限制性之實施例來描述本發明。該等實施例係關於一種蝕刻組合物，一種製備蝕刻組合物之方法，一種蝕刻方法，及一種製造半導體裝置之方法。The invention is described below with reference to a number of preferred but non-limiting embodiments. The embodiments are directed to an etching composition, a method of preparing an etching composition, an etching method, and a method of fabricating a semiconductor device.

蝕刻組合物Etching composition

根據本發明之一實施例之蝕刻組合物包括氟化氫、氟化銨、非離子聚合物界面活性劑、及水。The etching composition according to an embodiment of the present invention includes hydrogen fluoride, ammonium fluoride, a nonionic polymer surfactant, and water.

一種具有大約40至60重量百分比之濃度之氟化氫(HF)溶液可用以製備該蝕刻組合物。包含於該蝕刻組合物之氟化氫的量較佳在大約0.1至大約0.8重量百分比之範圍內。A hydrogen fluoride (HF) solution having a concentration of about 40 to 60 weight percent can be used to prepare the etching composition. The amount of hydrogen fluoride contained in the etching composition is preferably in the range of from about 0.1 to about 0.8% by weight.

一具有大約30至50重量百分比之濃度之氟化銨(NH4 F)溶液可用以製備該蝕刻組合物。包含於該蝕刻組合物之氟化銨之量較佳地在大約10至大約25重量百分比之範圍內。A solution of ammonium fluoride (NH 4 F) having a concentration of about 30 to 50 weight percent can be used to prepare the etching composition. The amount of ammonium fluoride contained in the etching composition is preferably in the range of from about 10 to about 25 weight percent.

當非離子聚合物界面活性劑之量低於大約0.0001重量百分比時，由於顆粒之背面吸收之缺陷之防止將會不充分，且當界面活性劑之量超過大約3重量百分比時，防止缺陷之改進較為微小。因此，非離子聚合物界面活性劑之量基於組合物之總量較佳在大約0.0001至大約3重量百分比之範 圍內，且更佳在大約0.001至大約0.02重量百分比之範圍內。When the amount of the nonionic polymer surfactant is less than about 0.0001% by weight, the prevention of defects due to backside absorption of the particles will be insufficient, and when the amount of the surfactant exceeds about 3 weight%, the improvement of defects is prevented. It is relatively small. Accordingly, the amount of nonionic polymeric surfactant is preferably from about 0.0001 to about 3 weight percent based on the total amount of the composition. Within the circumference, and more preferably in the range of from about 0.001 to about 0.02 weight percent.

非離子聚合物界面活性劑可包括一種具有親水性與疏水性之非離子聚合物(即，非離子聚合物既具有親水基又具有疏水基)。The nonionic polymeric surfactant can include a nonionic polymer having hydrophilicity and hydrophobicity (ie, the nonionic polymer has both a hydrophilic group and a hydrophobic group).

非離子聚合物界面活性劑之實例包括聚乙二醇與聚丙二醇之嵌段共聚物(替代地稱作"乙二醇/丙二醇嵌段共聚物"，其為具有環氧乙烷及環氧丙烷鏈之嵌段共聚物且其藉由共聚乙二醇與丙二醇單體來製造)、聚乙二醇與聚丙二醇之隨機共聚物(替代地稱作"乙二醇/丙二醇隨機共聚物"，其為具有環氧乙烷及環氧丙烷鏈之隨機共聚物且其藉由共聚乙二醇與丙二醇單體來製造)、聚氧化乙烯與聚氧化丙烯之嵌段共聚物(替代地稱作"環氧乙烷/環氧丙烷"嵌段共聚物，其為具有氧化乙烯及環氧丙烷鏈之嵌段共聚物且其藉由共聚環氧乙烷與環氧丙烷單體來製造)、或聚氧化乙烯與聚氧化丙烯之隨機共聚物(替代地稱作"環氧乙烷/環氧丙烷隨機共聚物"，其為具有環氧乙烷及環氧丙烷鏈之隨機共聚物且其藉由共聚環氧乙烷/環氧丙烷單體來製造)。Examples of nonionic polymeric surfactants include block copolymers of polyethylene glycol and polypropylene glycol (alternatively referred to as "ethylene glycol/propylene glycol block copolymers" having ethylene oxide and propylene oxide. a block copolymer of a chain and made by copolymerizing ethylene glycol with a propylene glycol monomer), a random copolymer of polyethylene glycol and polypropylene glycol (alternatively referred to as "ethylene glycol/propylene glycol random copolymer", a block copolymer having a random copolymer of ethylene oxide and a propylene oxide chain and copolymerized with ethylene glycol and a propylene glycol monomer), a block copolymer of polyethylene oxide and polypropylene oxide (alternatively referred to as a "ring" Oxyethane/propylene oxide "block copolymer, which is a block copolymer having ethylene oxide and propylene oxide chains and which is produced by copolymerizing ethylene oxide with a propylene oxide monomer), or polyoxidation a random copolymer of ethylene and polypropylene oxide (alternatively referred to as "ethylene oxide/propylene oxide random copolymer" which is a random copolymer having ethylene oxide and propylene oxide chains and which is copolymerized by a ring Manufactured from oxyethylene/propylene oxide monomer).

較佳地，非離子聚合物界面活性劑具有下列結構：H-(OCH2 CH2 )x -(OCH(CH3 )CH2 )y -(OCH2 CH2 )z -OH其中x、y及z為正整數，且平均分子量之重量大約為3000或更少。Preferably, the nonionic polymeric surfactant has the structure: H-(OCH 2 CH 2 ) x -(OCH(CH 3 )CH 2 ) y -(OCH 2 CH 2 ) z -OH wherein x, y and z is a positive integer and the average molecular weight is about 3,000 or less.

具有上述結構之聚乙二醇與聚丙二醇之嵌段共聚物包括商業可獲得之Synperonic PE/L64或Synperonic PE/L61，其由德國之FLUKA公司製造。Synperonic PE/L64或 Synperonic PE/L61為基於醇淨化並洗滌之分散劑，且產生少量副產品，藉此其有利於環境且具有較好可濕性。Synperonic PE/L64具有大約2900或更少之分子量及大約1.05 g/ml之密度。Synperonic PE/L61具有大約2000或更少之分子量及大約1.02 g/ml之密度。The block copolymer of polyethylene glycol and polypropylene glycol having the above structure includes commercially available Synperonic PE/L64 or Synperonic PE/L61, which is manufactured by FLUKA, Germany. Synperonic PE/L64 or Synperonic PE/L61 is a dispersant based on alcohol purification and washing, and produces a small amount of by-products, which is environmentally friendly and has good wettability. Synperonic PE/L64 has a molecular weight of about 2900 or less and a density of about 1.05 g/ml. Synperonic PE/L61 has a molecular weight of about 2000 or less and a density of about 1.02 g/ml.

或者，非離子聚合物界面活性劑可包括聚醇非離子聚合物界面活性劑。聚醇非離子界面活性劑之實例包括聚醇單酯及二酯、其環氧乙烷添加劑、脂肪族烷醇醯胺(aliphatic alkanol amide)、其環氧乙烷添加劑及其類似物。聚醇之實例可包括丙三醇、異戊四醇、山梨聚糖等。Alternatively, the nonionic polymeric surfactant can comprise a polyalcoholic nonionic polymeric surfactant. Examples of the polyalcoholic nonionic surfactant include polyalcohol monoesters and diesters, ethylene oxide additives thereof, aliphatic alkanol amides, ethylene oxide additives thereof, and the like. Examples of the polyol may include glycerin, pentaerythritol, sorbitan, and the like.

山梨聚糖酯之環氧乙烷添加劑可用作一較佳聚醇非離子界面活性劑。當用一諸如氫氧化鈉之催化劑加熱山梨醇(sorbit)與脂族酸時，山梨醇脫水產生山梨聚糖。因此形成之山梨聚糖與脂族酸反應產生酯化合物。The sorbitan ester ethylene oxide additive can be used as a preferred polyol nonionic surfactant. When a sorbit and an aliphatic acid are heated with a catalyst such as sodium hydroxide, the sorbitol is dehydrated to produce sorbitan. The sorbitan formed thus reacts with an aliphatic acid to produce an ester compound.

聚山梨醇酯80之結構如下列山梨聚糖脂之實例所說明： 其中w、x、y及z為正整數。The structure of polysorbate 80 is illustrated by the following examples of sorbitan grease: Where w, x, y, and z are positive integers.

上述化合物之化學結構如下列化學式所說明： The chemical structure of the above compounds is as follows:

包括聚山梨醇酯60、聚山梨醇酯65及其類似物之山梨聚糖酯的環氧乙烷添加劑亦可用於本發明之實施例。Ethylene oxide additives comprising sorbitan esters of polysorbate 60, polysorbate 65 and the like can also be used in embodiments of the invention.

將在下文中描述一種用於在一氧化物層之選擇性蝕刻期間，藉由非離子聚合物來鈍化一多晶矽層之機制。A mechanism for passivating a polysilicon layer by a nonionic polymer during selective etching of an oxide layer will be described below.

圖5A與5B為用於解釋藉由本發明之一實施例之蝕刻組合物來鈍化一多晶矽層之機制的示意性截面圖。5A and 5B are schematic cross-sectional views for explaining a mechanism for passivating a polysilicon layer by an etching composition according to an embodiment of the present invention.

圖5A中，當將具有疏水基與親水基之非離子聚合物作為界面活性劑添加進包括氟化銨、氟化氫及水之溶液中時，如圖5B中所示，非離子聚合物選擇性地吸附於多晶矽層表面。界面活性劑之吸收在隨後之氧化物層之濕蝕刻期間有助於保護多晶矽層。即，當選擇性地蝕刻氧化物層時，由於非離子聚合物之存在可最小化或避免對多晶矽層之損害。而且，可獲得氮化物層之蝕刻均勻性。In FIG. 5A, when a nonionic polymer having a hydrophobic group and a hydrophilic group is added as a surfactant to a solution including ammonium fluoride, hydrogen fluoride, and water, as shown in FIG. 5B, the nonionic polymer is selectively selected. Adsorbed on the surface of the polycrystalline layer. The absorption of the surfactant helps to protect the polysilicon layer during the wet etching of the subsequent oxide layer. That is, when the oxide layer is selectively etched, damage to the polysilicon layer can be minimized or avoided due to the presence of the nonionic polymer. Moreover, the etching uniformity of the nitride layer can be obtained.

蝕刻組合物之製備Preparation of etching composition

圖6為說明根據本發明之一實施例製備蝕刻組合物之方法的流程圖。6 is a flow chart illustrating a method of preparing an etch composition in accordance with an embodiment of the present invention.

參看圖6，在步驟S10中，將具有大約50重量百分比濃度及大約0.1至8重量百分比之最終濃度的氟化氫(HF)溶液添加進一容器中。接著，在步驟S20中，將大約0.0001至3重量百分比，較佳為大約0.001至0.02重量百分比之界面活性劑添加進該氟化氫溶液中。在步驟S30中，將因此獲得之氟化氫溶液與界面活性劑之混合物攪拌大約3個小時或更多以均勻地混合該溶液以製備第一混合物溶液(該步驟稱作第一混合步驟)。Referring to Figure 6, in step S10, a hydrogen fluoride (HF) solution having a concentration of about 50 weight percent and a final concentration of about 0.1 to 8 weight percent is added to a container. Next, in step S20, about 0.0001 to 3 weight percent, preferably about 0.001 to 0.02 weight percent of the surfactant is added to the hydrogen fluoride solution. In step S30, the thus obtained mixture of the hydrogen fluoride solution and the surfactant is stirred for about 3 hours or more to uniformly mix the solution to prepare a first mixture solution (this step is referred to as a first mixing step).

在步驟S40中，向第一混合物溶液添加一預定量之水(H2 O)。在步驟S50，將因此獲得之混合物攪拌大約3個小時或更多以均勻地將該第一混合物溶液與水混合以製備第二混合物溶液(該步驟稱作第二混合步驟)。In step S40, a predetermined amount of water (H 2 O) is added to the first mixture solution. In step S50, the thus obtained mixture is stirred for about 3 hours or more to uniformly mix the first mixture solution with water to prepare a second mixture solution (this step is referred to as a second mixing step).

在步驟S60中，向第二混合物溶液添加具有大約40重量百分比之濃度的氟化銨溶液，使得氟化銨溶液之最終濃度大約為10至25重量百分比。在步驟S70中，將第二混合物溶液與氟化銨溶液均勻地攪拌大約12個小時或更多以獲得均勻混合之蝕刻組合物(該步驟稱作第三混合步驟)。In step S60, an ammonium fluoride solution having a concentration of about 40% by weight is added to the second mixture solution such that the final concentration of the ammonium fluoride solution is about 10 to 25 weight percent. In step S70, the second mixture solution and the ammonium fluoride solution are uniformly stirred for about 12 hours or more to obtain a uniformly mixed etching composition (this step is referred to as a third mixing step).

一循環泵與一過濾器連接至該容器以循環並過濾第一混合物溶液、第二混合物溶液及蝕刻組合物中的顆粒。在第一混合物溶液、第二混合物溶液及蝕刻組合物之製備期間，所有溶液及蝕刻組合物保持在大約10至大約40℃之溫度。A circulation pump is coupled to the vessel to filter to circulate and filter the particles of the first mixture solution, the second mixture solution, and the etching composition. All of the solution and etching composition are maintained at a temperature of from about 10 to about 40 °C during the preparation of the first mixture solution, the second mixture solution, and the etching composition.

若各個組份並未如上文所述被添加及攪拌，則氟化銨可潛在地與氟化氫反應產生NH4 FHF2 晶體，藉此產生不具有 所要特性之蝕刻組合物。When the individual components described above are not added and stirred, ammonium fluoride may then be reacted with hydrogen fluoride to produce potentially NH 4 FHF 2 crystals, thereby producing the etching composition has the desired characteristics.

實例1Example 1

將具有大約50重量百分比之濃度之氟化氫(HF)溶液添加進一容器中，接著將少量界面活性劑添加進具有該氟化氫溶液之容器中。可使用市售之由德國FLUKA公司製造的Synperonic PE/L64來作為界面活性劑。攪拌包括界面活性劑之氟化氫溶液超過3個小時，以製備第一混合物溶液。向該第一混合物溶液添加水(H2 O)。攪拌水與該第一混合物溶液超過3個小時，以獲得均勻混合之第二混合物溶液。A solution of hydrogen fluoride (HF) having a concentration of about 50 weight percent is added to a vessel, followed by a small amount of surfactant added to the vessel having the hydrogen fluoride solution. A commercially available Synperonic PE/L64 manufactured by FLUKA, Germany, can be used as a surfactant. The hydrogen fluoride solution including the surfactant was stirred for more than 3 hours to prepare a first mixture solution. Water (H 2 O) was added to the first mixture solution. The water and the first mixture solution were stirred for more than 3 hours to obtain a uniformly mixed second mixture solution.

向第二混合物溶液添加具有大約40重量百分比之濃度的氟化銨溶液，使得該氟化銨之最終濃度大約為10至25重量百分比。攪拌第二混合物溶液與氟化銨溶液超過12個小時，以製備均勻混合之蝕刻組合物。An ammonium fluoride solution having a concentration of about 40% by weight is added to the second mixture solution such that the final concentration of the ammonium fluoride is about 10 to 25 weight percent. The second mixture solution was stirred with the ammonium fluoride solution for more than 12 hours to prepare a uniformly mixed etching composition.

將一循環泵與一過濾器連接至該容器，以循環並過濾第一混合物溶液、第二混合物溶液及蝕刻組合物中的顆粒。在第一混合物溶液、第二混合物溶液及蝕刻組合物之製備期間，該溶液保持在大約10至大約40℃之溫度。A circulation pump and a filter are coupled to the vessel to circulate and filter the particles of the first mixture solution, the second mixture solution, and the etching composition. The solution is maintained at a temperature of from about 10 to about 40 ° C during the preparation of the first mixture solution, the second mixture solution, and the etching composition.

獲得包含大約18重量百分比之氟化銨、大約4.5重量百分比之氟化氫及大約0.001至0.02重量百分比之非離子聚合物界面活性劑的蝕刻組合物。An etching composition comprising about 18 weight percent ammonium fluoride, about 4.5 weight percent hydrogen fluoride, and about 0.001 to 0.02 weight percent nonionic polymeric surfactant is obtained.

實例2Example 2

以如實例1中所描述之相同方式製備蝕刻組合物，除了使用Synperonic PE/L64及polysorbate 80代替Synperonic PE/L64來用作界面活性劑以外。所獲得之蝕刻組合物包含 大約18重量百分比之氟化銨及大約4.5重量百分比之氟化氫及大約10 ppm之非離子界面活性劑、Synperonic PE/L64及大約200 ppm之聚山梨醇酯80。An etching composition was prepared in the same manner as described in Example 1, except that Synperonic PE/L64 and polysorbate 80 were used instead of Synperonic PE/L64 as a surfactant. The obtained etching composition comprises About 18 weight percent ammonium fluoride and about 4.5 weight percent hydrogen fluoride and about 10 ppm nonionic surfactant, Synperonic PE/L64, and about 200 ppm polysorbate 80.

實例3Example 3

以如實例1中所描述之相同方式製備蝕刻組合物，除了使用聚山梨醇酯80代替Synperonic PE/L64來用作界面活性劑以外。所獲得之蝕刻組合物包含大約18重量百分比之氟化銨及大約4.5重量百分比之氟化氫，及作為非離子界面活性劑之大約200 ppm之聚山梨醇酯80。An etching composition was prepared in the same manner as described in Example 1, except that polysorbate 80 was used instead of Synperonic PE/L64 for use as a surfactant. The resulting etch composition comprises about 18 weight percent ammonium fluoride and about 4.5 weight percent hydrogen fluoride, and about 200 ppm polysorbate 80 as a nonionic surfactant.

比較實例1Comparative example 1

藉由將氟化氫(HF)與去離子水(D.I.水)以大約5：1之混合比混合來製備蝕刻組合物。An etching composition was prepared by mixing hydrogen fluoride (HF) with deionized water (D.I. water) at a mixing ratio of about 5:1.

比較實例2Comparative example 2

藉由將大約40重量百分比之氟化銨、大約50重量百分比之氟化氫及去離子水以大約5：1：5之混合比混合，並接著添加相同莫耳比之C8 H17 NH2 與C9 H19 COOH以將界面活性劑之濃度調整至大約200 ppm來製備蝕刻組合物(LAL 500水溶液)。By mixing about 40% by weight of ammonium fluoride, about 50% by weight of hydrogen fluoride and deionized water in a mixing ratio of about 5:1:5, and then adding the same molar ratio of C 8 H 17 NH 2 and C 9 H 19 COOH An etching composition (LAL 500 aqueous solution) was prepared by adjusting the concentration of the surfactant to about 200 ppm.

比較實例3Comparative example 3

藉由將相同莫耳比之C8 H17 NH2 與C9 H19 COOH添加進比較實例1之蝕刻組合物中以將界面活性劑之濃度調整至大約200 ppm來製備蝕刻組合物。An etching composition was prepared by adding the same molar ratio of C 8 H 17 NH 2 and C 9 H 19 COOH to the etching composition of Comparative Example 1 to adjust the concentration of the surfactant to about 200 ppm.

比較實例4Comparative example 4

以與比較實例2中所描述之相同方式製備蝕刻組合物，除 了未添加界面活性劑之外。An etching composition was prepared in the same manner as described in Comparative Example 2, except No surfactant was added.

蝕刻氧化物層Etching oxide layer

圖7A至7C為說明藉由使用根據本發明之蝕刻組合物選擇性地蝕刻在一氧化物層、一氮化物層及一多晶矽層中之一氧化物層之方法的截面圖。圖7A至7C中，為簡單起見，並未展示或描述在一基板與一氮化物層之間的下層結構。7A through 7C are cross-sectional views illustrating a method of selectively etching an oxide layer in an oxide layer, a nitride layer, and a polysilicon layer by using the etching composition according to the present invention. In Figures 7A through 7C, the underlying structure between a substrate and a nitride layer is not shown or described for simplicity.

參看圖7A，在諸如矽晶圓之基板100上連續地形成一氮化物層105、第一氧化物層110及第二氧化物層115。在該實例中，氮化物層105使用氮化矽(SiN)形成，第一氧化物層110使用BPSG形成，且第二氧化物層115使用PE-TEOS形成。Referring to FIG. 7A, a nitride layer 105, a first oxide layer 110, and a second oxide layer 115 are successively formed on a substrate 100 such as a germanium wafer. In this example, the nitride layer 105 is formed using tantalum nitride (SiN), the first oxide layer 110 is formed using BPSG, and the second oxide layer 115 is formed using PE-TEOS.

參看圖7B，部分地蝕刻第二氧化物層115及第一氧化物層110以形成一用於藉由微影技術曝露氮化物層105之接觸孔120。在通過接觸孔120在曝露之氮化物層105上及在接觸孔120之內側壁及第二氧化物層115上形成一多晶矽層之後，圖案化該多晶矽層以形成一多晶矽層圖案125。Referring to FIG. 7B, the second oxide layer 115 and the first oxide layer 110 are partially etched to form a contact hole 120 for exposing the nitride layer 105 by lithography. After forming a polysilicon layer on the exposed nitride layer 105 through the contact hole 120 and on the inner sidewall of the contact hole 120 and the second oxide layer 115, the polysilicon layer is patterned to form a polysilicon layer pattern 125.

參看圖7C，第二氧化物層115及第一氧化物層110藉由使用根據本發明之一實施例之上文所述之蝕刻組合物的濕式蝕刻處理來蝕刻。亦部分地蝕刻基板100上之氮化物層105之上部部分。此處，由於該實施例之蝕刻組合物包括非離子聚合物，其吸附於多晶矽層圖案125之表面部分，以鈍化該多晶矽層圖案125，因此在蝕刻第一與第二氧化物層110與115期間，多晶矽層圖案125之損害可顯著地減少。另外，與習知LAL或5：1氟化氫蝕刻溶液相比，改良了在氮化物層105上的蝕刻均勻性。將在下文描述蝕刻處理之後在氮化物 層105、第一與第二氧化物層110與115、及多晶矽層圖案125上的蝕刻結果。Referring to FIG. 7C, the second oxide layer 115 and the first oxide layer 110 are etched by a wet etching process using the above-described etching composition according to an embodiment of the present invention. The upper portion of the nitride layer 105 on the substrate 100 is also partially etched. Here, since the etching composition of this embodiment includes a nonionic polymer which is adsorbed on a surface portion of the polysilicon layer pattern 125 to passivate the polysilicon layer pattern 125, the first and second oxide layers 110 and 115 are etched. During this time, the damage of the polysilicon layer pattern 125 can be significantly reduced. In addition, the etching uniformity on the nitride layer 105 is improved as compared to the conventional LAL or 5:1 hydrogen fluoride etching solution. Will be described below in the etching process after the nitride Etching results on layer 105, first and second oxide layers 110 and 115, and polysilicon layer pattern 125.

蝕刻實驗1Etching experiment 1

圖8A至8D為說明在藉由使用根據本發明之實例1獲得之蝕刻組合物及根據比較實例1至3獲得之蝕刻組合物之濕式蝕刻處理中用於PE-TEOS層、BPSG層、氮化矽層(SiN)及多晶矽層之蝕刻速率之圖。圖8A對應於氮化矽層之蝕刻結果；圖8B對應於BPSG層之蝕刻結果；圖8C對應於PE-TEOS層之蝕刻結果；及圖8D對應於多晶矽層之蝕刻結果。8A to 8D are diagrams for explaining a PE-TEOS layer, a BPSG layer, and a nitrogen in a wet etching treatment by using the etching composition obtained according to Example 1 of the present invention and the etching composition obtained according to Comparative Examples 1 to 3. A plot of the etch rate of the bismuth layer (SiN) and the polysilicon layer. 8A corresponds to the etching result of the tantalum nitride layer; FIG. 8B corresponds to the etching result of the BPSG layer; FIG. 8C corresponds to the etching result of the PE-TEOS layer; and FIG. 8D corresponds to the etching result of the polysilicon layer.

參看圖8A，在藉由使用實例1之蝕刻組合物之濕式蝕刻處理蝕刻PE-TEOS層與BPSG層期間，用於氮化矽層之平均蝕刻速率大約為每分鐘26。其最大蝕刻速率大約為每分鐘27，且其最小蝕刻速率大約為每分鐘24。因此，蝕刻速率分散僅大約為每分鐘3。Referring to FIG. 8A, during etching of the PE-TEOS layer and the BPSG layer by wet etching treatment using the etching composition of Example 1, the average etching rate for the tantalum nitride layer is approximately 26 per minute. . Its maximum etch rate is approximately 27 per minute And its minimum etch rate is approximately 24 per minute . Therefore, the etch rate dispersion is only about 3 per minute. .

相反，當使用根據比較實例1之氟化氫蝕刻溶液時，用於氮化矽層之平均蝕刻速率大約為每分鐘76。其最大蝕刻速率大約為每分鐘86，且其最小蝕刻速率大約為每分鐘65。因此，蝕刻速率分散大約為每分鐘21。In contrast, when the hydrogen fluoride etching solution according to Comparative Example 1 was used, the average etching rate for the tantalum nitride layer was about 76 per minute. . Its maximum etch rate is approximately 86 per minute And its minimum etch rate is approximately 65 per minute . Therefore, the etch rate is spread approximately at 21 per minute. .

當使用根據比較實例2之LAL 500蝕刻溶液時，用於氮化物層之平均蝕刻速率大約為每分鐘14。其最大蝕刻速率大約為每分鐘15，且其最小蝕刻速率大約為每分鐘13。因此，蝕刻速率分散大約為每分鐘2，其很低。When the LAL 500 etching solution according to Comparative Example 2 was used, the average etching rate for the nitride layer was about 14 per minute. . Its maximum etch rate is approximately 15 per minute And its minimum etch rate is approximately 13 per minute . Therefore, the etch rate is spread approximately 2 per minute It is very low.

當使用根據比較實例3之蝕刻組合物時，用於氮化物層之平均蝕刻速率大約為每分鐘46。其最大蝕刻速率大約為 每分鐘49，且其最小蝕刻速率大約為每分鐘43。因此，蝕刻速率分散大約為每分鐘6。When the etching composition according to Comparative Example 3 was used, the average etching rate for the nitride layer was about 46 per minute. . Its maximum etch rate is approximately 49 per minute And its minimum etch rate is approximately 43 per minute . Therefore, the etch rate is spread around 6 per minute. .

因此，與習知蝕刻組合物相比，在藉由使用實例1之蝕刻組合物蝕刻PE-TEOS層與BPSG層期間，大大改良了氮化矽層之蝕刻均勻性。Therefore, the etching uniformity of the tantalum nitride layer is greatly improved during etching of the PE-TEOS layer and the BPSG layer by using the etching composition of Example 1 as compared with the conventional etching composition.

參看圖8B，在藉由使用根據實例1之蝕刻組合物之濕蝕刻處理中，用於BPSG層之平均蝕刻速率大約為每分鐘2303。其最大蝕刻速率大約為每分鐘2390，且其最小蝕刻速率大約為每分鐘2215。因此，蝕刻速率分散大約為每分鐘175。Referring to FIG. 8B, in the wet etching process by using the etching composition according to Example 1, the average etching rate for the BPSG layer is about 2303 per minute. . Its maximum etch rate is approximately 2390 per minute And its minimum etch rate is approximately 2215 per minute . Therefore, the etch rate is spread around 175 per minute. .

當使用根據比較實例1之氟化氫蝕刻溶液時，用於BPSG層之平均蝕刻速率大約為每分鐘5885。其最大蝕刻速率大約為每分鐘6298，且其最小蝕刻速率大約為每分鐘5472。因此，蝕刻速率分散大約為每分鐘826。即，用於BPSG層之蝕刻速率增加而BPSG層之蝕刻均勻性大大降低。When the hydrogen fluoride etching solution according to Comparative Example 1 was used, the average etching rate for the BPSG layer was approximately 5885 per minute. . Its maximum etch rate is approximately 6298 per minute And its minimum etch rate is approximately 5472 per minute . Therefore, the etch rate is spread around 826 per minute. . That is, the etch rate for the BPSG layer is increased and the etching uniformity of the BPSG layer is greatly reduced.

當使用根據比較實例2之LAL 500蝕刻溶液時，用於BPSG層之平均蝕刻速率大約為每分鐘582。其最大蝕刻速率大約為每分鐘591，且其最小蝕刻速率大約為每分鐘572。因此，蝕刻速率分散大約為每分鐘19，其很低。儘管可獲得BPSG層之蝕刻均勻性，但是當使用習知LAL 500蝕刻溶液時，蝕刻速率大大降低了。When the LAL 500 etching solution according to Comparative Example 2 was used, the average etching rate for the BPSG layer was approximately 582 per minute. . Its maximum etch rate is approximately 591 per minute And its minimum etch rate is approximately 572 per minute . Therefore, the etch rate is spread approximately at 19 per minute. It is very low. Although the etching uniformity of the BPSG layer can be obtained, the etching rate is greatly reduced when the conventional LAL 500 etching solution is used.

當使用根據比較實例3之蝕刻組合物時，用於BPSG層之平均蝕刻速率大約為每分鐘3939。其最大蝕刻速率大約 為每分鐘4181，且其最小蝕刻速率大約為每分鐘3696。因此，蝕刻速率分散大約為每分鐘485。儘管可獲得BPSG層之充分的蝕刻速率，但是BPSG層之蝕刻均勻性降低。When the etching composition according to Comparative Example 3 was used, the average etching rate for the BPSG layer was approximately 3939 per minute. . Its maximum etch rate is approximately 4181 per minute And its minimum etch rate is approximately 3696 per minute . Therefore, the etch rate is spread around 485 per minute. . Although a sufficient etch rate of the BPSG layer is obtained, the etching uniformity of the BPSG layer is lowered.

因此，當應用根據本發明之實施例之蝕刻組合物時，BPSG層以一適當蝕刻速率蝕刻，而與習知蝕刻組合物相比具有蝕刻均勻性。Thus, when an etch composition in accordance with an embodiment of the present invention is applied, the BPSG layer is etched at a suitable etch rate with etch uniformity as compared to conventional etch compositions.

參看圖8C，在藉由使用根據實例1之蝕刻組合物之濕蝕刻處理中，用於PE-TEOS層之平均蝕刻速率大約為每分鐘3124。其最大蝕刻速率大約為每分鐘3132，且其最小蝕刻速率大約為每分鐘3116。因此，蝕刻速率分散僅大約為每分鐘16，其很低。Referring to FIG. 8C, in the wet etching process by using the etching composition according to Example 1, the average etching rate for the PE-TEOS layer is about 3,124 per minute. . Its maximum etch rate is approximately 3132 per minute And its minimum etch rate is approximately 3116 per minute . Therefore, the etch rate dispersion is only about 16 per minute. It is very low.

當使用根據比較實例1之氟化氫蝕刻溶液時，用於PE-TEOS層之平均蝕刻速率大約為每分鐘3031。其最大蝕刻速率大約為每分鐘3529，且其最小蝕刻速率大約為每分鐘2533。因此，蝕刻速率分散大約為每分鐘996。即，當使用習知5：1氟化氫蝕刻溶液時，用於PE-TEOS層之蝕刻速率降低，同時PE-TEOS層之蝕刻均勻性亦大大降低。When the hydrogen fluoride etching solution according to Comparative Example 1 was used, the average etching rate for the PE-TEOS layer was approximately 3031 per minute. . Its maximum etch rate is approximately 3529 per minute And its minimum etch rate is approximately 2533 per minute . Therefore, the etch rate is spread around 996 per minute. . That is, when a conventional 5:1 hydrogen fluoride etching solution is used, the etching rate for the PE-TEOS layer is lowered, and the etching uniformity of the PE-TEOS layer is also greatly lowered.

當使用根據比較實例2之LAL 500蝕刻溶液時，用於PE-TEOS層之平均蝕刻速率大約為每分鐘1262。其最大蝕刻速率大約為每分鐘1316，且其最小蝕刻速率大約為每分鐘1208。因此，蝕刻速率分散大約為每分鐘108，其很低。儘管可獲得PE-TEOS層之蝕刻均勻性，但是當使用習知LAL 500蝕刻溶液時，蝕刻速率大大降低。When the LAL 500 etching solution according to Comparative Example 2 was used, the average etching rate for the PE-TEOS layer was approximately 1262 per minute. . Its maximum etch rate is approximately 1316 per minute And its minimum etch rate is approximately 1208 per minute . Therefore, the etch rate is spread approximately at 108 per minute. It is very low. Although the etching uniformity of the PE-TEOS layer can be obtained, the etching rate is greatly reduced when the conventional LAL 500 etching solution is used.

當使用根據比較實例3之蝕刻組合物時，用於PE-TEOS層之平均蝕刻速率大約為每分鐘2408。其最大蝕刻速率大約為每分鐘3195，且其最小蝕刻速率大約為每分鐘1620。因此，蝕刻速率分散大約為每分鐘1575。儘管可獲得PE-TEOS層之高蝕刻速率，但是當使用習知LAL 500蝕刻溶液時，PE-TEOS層之蝕刻均勻性降低。When the etching composition according to Comparative Example 3 was used, the average etching rate for the PE-TEOS layer was approximately 2408 per minute. . Its maximum etch rate is approximately 3195 per minute And its minimum etch rate is approximately 1620 per minute . Therefore, the etch rate is approximately 1575 per minute. . Although a high etch rate of the PE-TEOS layer is obtained, the etching uniformity of the PE-TEOS layer is reduced when a conventional LAL 500 etch solution is used.

因此，當藉由使用根據本發明之實例1之蝕刻組合物蝕刻PE-TEOS層時，獲得較好蝕刻速率及適當蝕刻均勻性。Therefore, when the PE-TEOS layer is etched by using the etching composition according to Example 1 of the present invention, a better etching rate and appropriate etching uniformity are obtained.

參看圖8D，在藉由使用實例1之蝕刻組合物之濕蝕刻處理蝕刻PE-TEOS層及BPSG層期間，用於多晶矽層之平均蝕刻速率大約為每分鐘9。其最大蝕刻速率大約為每分鐘9.8，且其最小蝕刻速率大約為每分鐘8.8。因此，蝕刻速率分散僅大約為每分鐘1。即，在蝕刻處理期間，多晶矽層被適當地鈍化。Referring to FIG. 8D, during the etching of the PE-TEOS layer and the BPSG layer by the wet etching treatment using the etching composition of Example 1, the average etching rate for the polysilicon layer is about 9 per minute. . Its maximum etch rate is approximately 9.8 per minute And its minimum etch rate is approximately 8.8 per minute . Therefore, the etch rate dispersion is only about 1 per minute. . That is, the polysilicon layer is suitably passivated during the etching process.

當使用根據比較實例1之氟化氫蝕刻溶液時，用於多晶矽層之平均蝕刻速率大約為每分鐘8。其最大蝕刻速率大約為每分鐘8.4，且其最小蝕刻速率大約為每分鐘7.5。因此，蝕刻速率分散大約為每分鐘1。When the hydrogen fluoride etching solution according to Comparative Example 1 was used, the average etching rate for the polysilicon layer was about 8 per minute. . Its maximum etch rate is approximately 8.4 per minute And its minimum etch rate is approximately 7.5 per minute . Therefore, the etch rate is spread around 1 per minute. .

當使用根據比較實例2之LAL 500蝕刻溶液時，用於多晶矽層之平均蝕刻速率大約為每分鐘8。其最大蝕刻速率大約為每分鐘8.5，且其最小蝕刻速率大約為每分鐘7.5。因此，蝕刻速率分散大約為每分鐘1，其很低。When the LAL 500 etching solution according to Comparative Example 2 was used, the average etching rate for the polysilicon layer was about 8 per minute. . Its maximum etch rate is approximately 8.5 per minute And its minimum etch rate is approximately 7.5 per minute . Therefore, the etch rate is spread around 1 per minute. It is very low.

當使用根據比較實例3之蝕刻組合物時，用於多晶矽層之平均蝕刻速率大約為每分鐘8。其最大蝕刻速率大約為每 分鐘8.4，且其最小蝕刻速率大約為每分鐘7.5。因此，蝕刻速率分散大約為1。When the etching composition according to Comparative Example 3 was used, the average etching rate for the polysilicon layer was about 8 per minute. . Its maximum etch rate is approximately 8.4 per minute And its minimum etch rate is approximately 7.5 per minute . Therefore, the etch rate is dispersed by about 1.

如圖8A至8D中所說明，在藉由使用根據本發明之實例1之蝕刻組合物蝕刻諸如PE-TEOS層及BPSG層之氧化物層期間，可有效地鈍化多晶矽層。另外，可充分地獲得氧化物層及氮化物層之蝕刻均勻性。As illustrated in FIGS. 8A to 8D, the polycrystalline germanium layer can be effectively passivated during etching of an oxide layer such as a PE-TEOS layer and a BPSG layer by using the etching composition according to Example 1 of the present invention. In addition, the etching uniformity of the oxide layer and the nitride layer can be sufficiently obtained.

蝕刻實驗2Etching experiment 2

圖9A至9D為說明在藉由使用根據本發明之實例2與3獲得之蝕刻組合物及根據比較實例4獲得之蝕刻組合物之濕蝕刻處理中，用於PE-TEOS層、BPSG層、氮化矽層及多晶矽層之蝕刻速率之圖。圖9A對應於氮化矽層之蝕刻結果；圖9B對應於BPSG層之蝕刻結果；圖9C對應於PE-TEOS層之蝕刻結果；圖9D對應於多晶矽層之蝕刻結果。9A to 9D are diagrams for explaining a PE-TEOS layer, a BPSG layer, and a nitrogen in a wet etching treatment by using an etching composition obtained according to Examples 2 and 3 of the present invention and an etching composition obtained according to Comparative Example 4. A plot of the etch rate of the bismuth layer and the polysilicon layer. 9A corresponds to the etching result of the tantalum nitride layer; FIG. 9B corresponds to the etching result of the BPSG layer; FIG. 9C corresponds to the etching result of the PE-TEOS layer; and FIG. 9D corresponds to the etching result of the polysilicon layer.

參看圖9A，在藉由使用根據實例2之蝕刻組合物之濕蝕刻處理蝕刻PE-TEOS層與BPSG層期間，用於氮化矽層之平均蝕刻速率大約為每分鐘32。其最大蝕刻速率大約為每分鐘33，且其最小蝕刻速率大約為每分鐘30。因此，蝕刻速率分散僅大約為每分鐘3。Referring to FIG. 9A, during etching of the PE-TEOS layer and the BPSG layer by wet etching treatment using the etching composition according to Example 2, the average etching rate for the tantalum nitride layer is approximately 32 per minute. . Its maximum etch rate is approximately 33 per minute And its minimum etch rate is approximately 30 per minute . Therefore, the etch rate dispersion is only about 3 per minute. .

當使用根據實例3之蝕刻組合物時，用於氮化矽層之平均蝕刻速率大約為每分鐘30。其最大蝕刻速率大約為每分鐘32，且其最小蝕刻速率大約為每分鐘29。因此，蝕刻速率分散亦大約為每分鐘3，其很低。When the etching composition according to Example 3 is used, the average etching rate for the tantalum nitride layer is about 30 per minute. . Its maximum etch rate is approximately 32 per minute And its minimum etch rate is approximately 29 per minute . Therefore, the etch rate dispersion is also about 3 per minute. It is very low.

當使用根據比較實例4之蝕刻組合物時，用於氮化矽層之平均蝕刻速率大約為每分鐘32。其最大蝕刻速率大約為 每分鐘34，且其最小蝕刻速率大約為每分鐘30。因此，蝕刻速率分散僅大約為每分鐘4。When the etching composition according to Comparative Example 4 was used, the average etching rate for the tantalum nitride layer was about 32 per minute. . Its maximum etch rate is approximately 34 per minute And its minimum etch rate is approximately 30 per minute . Therefore, the etch rate dispersion is only about 4 per minute. .

因此，當使用根據本發明之實例之蝕刻組合物蝕刻PE-TEOS與BPSG氧化物層時，與習知蝕刻溶液相比，增強了在蝕刻期間之氮化矽層的蝕刻均勻性。Therefore, when the PE-TEOS and BPSG oxide layers are etched using the etching composition according to the example of the present invention, the etching uniformity of the tantalum nitride layer during etching is enhanced as compared with the conventional etching solution.

參看圖9B，在藉由使用根據實例2之蝕刻組合物之濕蝕刻處理期間，用於BPSG層之平均蝕刻速率大約為每分鐘1978。其最大蝕刻速率大約為每分鐘2155，且其最小蝕刻速率大約為每分鐘1800。因此，蝕刻速率分散大約為每分鐘355。Referring to FIG. 9B, during the wet etching process by using the etching composition according to Example 2, the average etching rate for the BPSG layer is approximately 1978 per minute. . Its maximum etch rate is approximately 2155 per minute And its minimum etch rate is approximately 1800 per minute . Therefore, the etch rate is spread around 355 per minute. .

當使用根據實例3之蝕刻組合物時，用於BPSG層之平均蝕刻速率大約為每分鐘1360。其最大蝕刻速率大約為每分鐘1381，且其最小蝕刻速率大約為每分鐘1339。因此，蝕刻速率分散大約為每分鐘42。當使用根據實例3之蝕刻組合物時，用於BPSG層之蝕刻速率降低。然而，大大改良了BPSG層之蝕刻均勻性。When using the etching composition according to Example 3, the average etching rate for the BPSG layer is approximately 1360 per minute. . Its maximum etch rate is approximately 1381 per minute And its minimum etch rate is approximately 1339 per minute . Therefore, the etch rate is spread approximately at 42 per minute. . When the etching composition according to Example 3 was used, the etching rate for the BPSG layer was lowered. However, the etching uniformity of the BPSG layer is greatly improved.

當使用根據比較實例4之蝕刻組合物時，用於BPSG層之平均蝕刻速率大約為每分鐘2796。其最大蝕刻速率大約為每分鐘2889，且其最小蝕刻速率大約為每分鐘2703。因此，蝕刻速率分散大約為每分鐘186，其很低。When the etching composition according to Comparative Example 4 was used, the average etching rate for the BPSG layer was approximately 2,796 per minute. . Its maximum etch rate is approximately 2889 per minute And its minimum etch rate is approximately 2703 per minute . Therefore, the etch rate is approximately 186 per minute. It is very low.

因此，當根據本發明之實例2與3之蝕刻組合物用於蝕刻BPSG層時，與其中不包括如比較實例4中之界面活性劑的蝕刻組合物相比，蝕刻速率降低。Therefore, when the etching compositions according to Examples 2 and 3 of the present invention were used to etch the BPSG layer, the etching rate was lowered as compared with the etching composition in which the surfactant as in Comparative Example 4 was not included.

參看圖9C，在藉由使用根據實例2之蝕刻組合物之濕蝕刻 處理中，用於PE-TEOS層之平均蝕刻速率大約為每分鐘2802。其最大蝕刻速率大約為每分鐘3048，且其最小蝕刻速率大約為每分鐘2556。因此，蝕刻速率分散大約為每分鐘492。Referring to FIG. 9C, in the wet etching process by using the etching composition according to Example 2, the average etching rate for the PE-TEOS layer is about 2802 per minute. . Its maximum etch rate is approximately 3048 per minute And its minimum etch rate is approximately 2556 per minute . Therefore, the etch rate is spread approximately 492 per minute. .

當使用根據實例3之蝕刻組合物時，用於PE-TEOS層之平均蝕刻速率大約為每分鐘2358。其最大蝕刻速率大約為每分鐘2581，且其最小蝕刻速率大約為每分鐘2135。因此，蝕刻速率分散大約為每分鐘446。When the etching composition according to Example 3 was used, the average etching rate for the PE-TEOS layer was approximately 2358 per minute. . Its maximum etch rate is approximately 2581 per minute And its minimum etch rate is approximately 2135 per minute . Therefore, the etch rate is spread around 446 per minute. .

當使用根據比較實例4之蝕刻組合物時，用於PE-TEOS層之平均蝕刻速率大約為每分鐘3532。其最大蝕刻速率大約為每分鐘3639，且其最小蝕刻速率大約為每分鐘3424。因此，蝕刻速率分散僅大約為每分鐘215，其很低。當使用根據比較實例4之蝕刻組合物蝕刻PE-TEOS層時，可獲得蝕刻均勻性。然而，蝕刻速率極低。When the etching composition according to Comparative Example 4 was used, the average etching rate for the PE-TEOS layer was approximately 3532 per minute. . Its maximum etch rate is approximately 3639 per minute And its minimum etch rate is approximately 3,424 per minute . Therefore, the etch rate dispersion is only about 215 per minute. It is very low. When the PE-TEOS layer was etched using the etching composition according to Comparative Example 4, etching uniformity was obtained. However, the etching rate is extremely low.

因此，當使用根據本發明之一實施例之蝕刻組合物蝕刻PE-TEOS層時，獲得適當蝕刻均勻性。Therefore, when the PE-TEOS layer is etched using the etching composition according to an embodiment of the present invention, appropriate etching uniformity is obtained.

參看圖9D，在藉由使用根據實例2之蝕刻組合物之濕蝕刻處理蝕刻PE-TEOS及BPSG層期間，用於多晶矽層之平均蝕刻速率大約為每分鐘32。其最大蝕刻速率大約為每分鐘46，且其最小蝕刻速率大約為每分鐘18。因此，蝕刻速率分散大約為每分鐘28。Referring to FIG. 9D, during the etching of the PE-TEOS and BPSG layers by the wet etching process using the etching composition according to Example 2, the average etching rate for the polysilicon layer is approximately 32 per minute. . Its maximum etch rate is approximately 46 per minute And its minimum etch rate is approximately 18 per minute . Therefore, the etch rate is spread around 28 per minute. .

當使用根據實例3之蝕刻組合物時，用於多晶矽層之平均蝕刻速率大約為每分鐘26。其最大蝕刻速率大約為每分鐘35，且其最小蝕刻速率大約為每分鐘16。因此，蝕 刻速率分散大約為每分鐘19。When the etching composition according to Example 3 was used, the average etching rate for the polysilicon layer was about 26 per minute. . Its maximum etch rate is approximately 35 per minute And its minimum etch rate is approximately 16 per minute . Therefore, the etch rate is spread approximately at 19 per minute. .

當使用根據比較實例4之蝕刻組合物時，用於多晶矽層之平均蝕刻速率大約為每分鐘128。其最大蝕刻速率大約為每分鐘131，且其最小蝕刻速率大約為每分鐘125。因此，蝕刻速率分散大約為每分鐘3，其相當低。然而，用於多晶矽層之蝕刻速率為不良的高。When the etching composition according to Comparative Example 4 was used, the average etching rate for the polysilicon layer was about 128 per minute. . Its maximum etch rate is approximately 131 per minute And its minimum etch rate is approximately 125 per minute . Therefore, the etch rate is spread approximately 3 per minute It is quite low. However, the etching rate for the polysilicon layer is unfavorably high.

由於自實例2與3獲得之蝕刻組合物比自比較實例4獲得之蝕刻組合物展現較低蝕刻速率，所以自實例2與3獲得之蝕刻組合物較佳。Since the etching compositions obtained from Examples 2 and 3 exhibited lower etching rates than the etching compositions obtained from Comparative Example 4, the etching compositions obtained from Examples 2 and 3 were preferred.

如圖9A至9D中所說明的，當使用根據本發明之蝕刻組合物蝕刻諸如PE-TEOS層及BPSG層之氧化物層時，關於氧化物層在蝕刻速率中展示一較大差別，關於氮化物層在蝕刻速率中展示一較小差別，且關於多晶矽層展示一很低蝕刻速率。因此，向蝕刻組合物中添加界面活性劑對於獲得較佳蝕刻結果係有效的。As illustrated in Figures 9A through 9D, when an oxide layer such as a PE-TEOS layer and a BPSG layer is etched using the etching composition according to the present invention, a large difference is exhibited in the etching rate with respect to the oxide layer, regarding nitrogen The layer exhibits a small difference in etch rate and exhibits a very low etch rate with respect to the polysilicon layer. Therefore, the addition of a surfactant to the etching composition is effective for obtaining a better etching result.

製造半導體裝置之方法Method of manufacturing a semiconductor device

圖10A至10E為說明根據本發明之一實施例製造一半導體裝置之方法的截面圖。在圖10A至10E中，相同參考數字代表相同元件。10A through 10E are cross-sectional views illustrating a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. In FIGS. 10A to 10E, the same reference numerals denote the same elements.

圖10A為說明一用於在半導體基板150(其上形成包括一閘極結構175之電晶體結構183)上形成第一墊片200及第二墊片205之步驟的截面圖。FIG. 10A is a cross-sectional view illustrating a step of forming a first spacer 200 and a second spacer 205 on a semiconductor substrate 150 on which a transistor structure 183 including a gate structure 175 is formed.

參看圖10A，藉由使用一諸如淺槽隔離(STI)方法或矽之局部氧化(LOCOS)方法之絕緣方法來在該半導體基板150 上形成一隔離層155以將該半導體基板150分成一活動區域及一場區域。Referring to FIG. 10A, the semiconductor substrate 150 is formed by using an insulating method such as a shallow trench isolation (STI) method or a local oxidation (LOCOS) method of germanium. An isolation layer 155 is formed thereon to divide the semiconductor substrate 150 into an active area and a field area.

藉由一熱氧化方法或一化學氣相沉積(CVD)方法在半導體基板150上形成一薄閘極氧化物層(未展示)。在該薄閘極氧化物層上順序地形成第一導電層(未展示)及第一遮罩層(未展示)。第一導電層及第一遮罩層分別對應於一閘極導電層及一閘極遮罩層。第一導電層藉由使用雜質摻雜多晶矽形成並圖案化以形成一閘極導電圖案165。第一導電層亦可作為一具有摻雜多晶矽及複晶金屬矽化物(polycide)之結構而形成。A thin gate oxide layer (not shown) is formed on the semiconductor substrate 150 by a thermal oxidation method or a chemical vapor deposition (CVD) method. A first conductive layer (not shown) and a first mask layer (not shown) are sequentially formed on the thin gate oxide layer. The first conductive layer and the first mask layer respectively correspond to a gate conductive layer and a gate mask layer. The first conductive layer is formed and patterned by doping the polysilicon with an impurity to form a gate conductive pattern 165. The first conductive layer may also be formed as a structure having doped polysilicon and a polycide.

圖案化第一遮罩層以形成一閘極遮罩圖案170，且使用對第一層間介電層195(隨後形成)具有蝕刻選擇性之材料形成該第一遮罩層。舉例而言，當第一層間介電層195使用氧化物形成時，第一遮罩層使用諸如氮化矽之氮化物形成。The first mask layer is patterned to form a gate mask pattern 170, and the first mask layer is formed using a material having an etch selectivity to the first interlayer dielectric layer 195 (which is subsequently formed). For example, when the first interlayer dielectric layer 195 is formed using an oxide, the first mask layer is formed using a nitride such as tantalum nitride.

第一光阻薄膜(未展示)沉積在第一遮罩層上，且曝露並顯影該第一光阻薄膜以獲得第一光阻圖案(未展示)。藉由使用第一光阻圖案作為蝕刻遮罩來連續地圖案化第一遮罩層、第一導電層及閘極氧化物層以形成一閘極結構175，其包括一閘極氧化物圖案160、一閘極導電圖案165及閘極遮罩圖案170。A first photoresist film (not shown) is deposited on the first mask layer, and the first photoresist film is exposed and developed to obtain a first photoresist pattern (not shown). The first mask layer, the first conductive layer and the gate oxide layer are successively patterned by using the first photoresist pattern as an etch mask to form a gate structure 175 including a gate oxide pattern 160 a gate conductive pattern 165 and a gate mask pattern 170.

使用諸如氮化矽之氮化物在半導體基板150上及在閘極結構175上形成第一介電層(未展示)。接著，各向異性地蝕刻第一介電層以形成如在閘極結構175之側壁上之閘極隔離片的第一隔離片180。A first dielectric layer (not shown) is formed over the semiconductor substrate 150 and over the gate structure 175 using a nitride such as tantalum nitride. Next, the first dielectric layer is anisotropically etched to form a first spacer 180 of the gate spacer as on the sidewalls of the gate structure 175.

隨後，在藉由離子植入處理將雜質藉由將閘極結構175用作離子植入遮罩而摻雜進在閘極結構175之間曝露之半導體基板150之後，執行一熱處理以形成第一接觸區域185及第二接觸區域190，即，源極/汲極區域。因此，形成具有第一與第二接觸區域185與190之MOS電晶體結構183。Subsequently, after the impurities are doped into the semiconductor substrate 150 exposed between the gate structures 175 by using the gate structure 175 as an ion implantation mask by ion implantation processing, a heat treatment is performed to form the first The contact region 185 and the second contact region 190, that is, the source/drain regions. Thus, a MOS transistor structure 183 having first and second contact regions 185 and 190 is formed.

將第一與第二接觸區域185與190分成一電容器接觸區域及一位元線接觸區域，並分別連接電容器之第一墊片200及位元線之第二墊片205(後續步驟)。換言之，第一接觸區域185對應於與第一墊片200連接之儲存節點接觸區域，而第二接觸區域190則對應於與第二墊片205連接之位元線接觸區域。The first and second contact regions 185 and 190 are divided into a capacitor contact region and a one-element contact region, and the first spacer 200 of the capacitor and the second spacer 205 of the bit line are respectively connected (subsequent steps). In other words, the first contact region 185 corresponds to the storage node contact region connected to the first spacer 200, and the second contact region 190 corresponds to the bit line contact region connected to the second spacer 205.

使用氧化物材料在包括電晶體結構183之半導體基板150之整個表面部分上形成第一層間介電層195。第一層間介電層195可為BPSG、USG或HDP-CVD氧化物材料。A first interlayer dielectric layer 195 is formed over the entire surface portion of the semiconductor substrate 150 including the transistor structure 183 using an oxide material. The first interlayer dielectric layer 195 can be a BPSG, USG or HDP-CVD oxide material.

使用化學機械拋光(CMP)處理、回蝕處理、或其組合來蝕刻層間介電層195之上部部分，以平面化第一層間介電層195之上部部分。The upper portion of the interlayer dielectric layer 195 is etched using a chemical mechanical polishing (CMP) process, an etch back process, or a combination thereof to planarize the upper portion of the first interlayer dielectric layer 195.

在經平面化之第一層間介電層195上，塗布第二光阻薄膜(未展示)。曝露並顯影該第二光阻薄膜以形成第二光阻圖案。接著，使用第二光阻圖案作為蝕刻遮罩，部分且各向異性地蝕刻第一層間介電層195，以形成曝露第一與第二接觸區域185與190之第一接觸孔198。因此，第一接觸孔198在曝露第一與第二接觸區域185與190的同時，其相對於電晶體結構183是自行對齊的。A second photoresist film (not shown) is applied over the planarized first interlayer dielectric layer 195. The second photoresist film is exposed and developed to form a second photoresist pattern. Next, the first interlayer dielectric layer 195 is partially and anisotropically etched using the second photoresist pattern as an etch mask to form a first contact hole 198 exposing the first and second contact regions 185 and 190. Thus, the first contact hole 198 is self-aligned relative to the transistor structure 183 while exposing the first and second contact regions 185 and 190.

藉由灰化處理及剝離處理來移除第二光阻圖案。在填充第一接觸孔198之第一層間介電層195上形成第二導電層(未展示)。第二導電層係藉由使用高濃度雜質摻雜多晶矽或金屬而形成。The second photoresist pattern is removed by an ashing process and a lift-off process. A second conductive layer (not shown) is formed over the first interlayer dielectric layer 195 filling the first contact hole 198. The second conductive layer is formed by doping polysilicon or metal with a high concentration of impurities.

藉由CMP處理、回蝕處理或其組合來蝕刻第二導電層直至曝露經平面化之第一層間介電層195的上表面，以形成第一墊片200與第二墊片205，其中第一與第二墊片200與205為自對齊接觸(SAC)。圖10B為說明形成一位元線及第四墊片240之步驟的截面圖。Etching the second conductive layer by CMP processing, etch back treatment, or a combination thereof until the planarized first interlayer dielectric layer 195 is exposed to form the first spacer 200 and the second spacer 205, wherein The first and second pads 200 and 205 are self-aligned contacts (SAC). FIG. 10B is a cross-sectional view illustrating a step of forming a one-dimensional line and a fourth spacer 240.

參看圖10B，使用BPSG、USG(未掺雜矽玻璃)或HDP-CVD(高密度電漿化學氣相沉積)氧化物材料在第一層間介電層195上及第一與第二墊片200、205上形成第二層間介電層210。第二層間介電層210將位元線(隨後形成)與第一儲存節點接觸墊片之第一墊片200電絕緣。Referring to FIG. 10B, BPSG, USG (undoped bismuth glass) or HDP-CVD (high density plasma chemical vapor deposition) oxide material is used on the first interlayer dielectric layer 195 and the first and second spacers. A second interlayer dielectric layer 210 is formed on 200, 205. The second interlayer dielectric layer 210 electrically insulates the bit lines (which are subsequently formed) from the first pads 200 of the first storage node contact pads.

藉由CMP處理、回蝕處理或其組合來蝕刻第二層間介電層210以平面化第二層間介電層210之上表面。The second interlayer dielectric layer 210 is etched by CMP processing, etch back processing, or a combination thereof to planarize the upper surface of the second interlayer dielectric layer 210.

第三光阻薄膜(未展示)塗覆在第二層間介電層210上。曝露並顯影第三光阻薄膜以形成第三光阻圖案(未展示)。A third photoresist film (not shown) is coated on the second interlayer dielectric layer 210. The third photoresist film is exposed and developed to form a third photoresist pattern (not shown).

藉由使用第三光阻圖案作為蝕刻遮罩來部分地蝕刻第二層間介電層210以在第二層間介電層210中形成第二接觸孔(未展示)以曝露掩埋在第一層間介電層195中之第一位元線接觸墊片的第二墊片205。第二接觸孔對應於用於將位元線與第一位元線接觸墊片之第二墊片205電連接之一位元線接觸孔。The second interlayer dielectric layer 210 is partially etched by using the third photoresist pattern as an etch mask to form a second contact hole (not shown) in the second interlayer dielectric layer 210 to be exposed to be buried between the first layers. The first bit line in the dielectric layer 195 contacts the second pad 205 of the spacer. The second contact hole corresponds to one of the bit line contact holes for electrically connecting the bit line to the second pad 205 of the first bit line contact pad.

藉由灰化處理與剝離處理來移除第三光阻圖案。接著在 填充位元線接觸孔之第二接觸孔的第二層間介電層210上順序地形成第三導電層(未展示)及第二遮罩層(未展示)。圖案化第三導電層與第二遮罩層以分別形成一位元線導電層圖案(未展示)與一位元線遮罩圖案(未展示)。The third photoresist pattern is removed by an ashing process and a lift-off process. Then at A third conductive layer (not shown) and a second mask layer (not shown) are sequentially formed on the second interlayer dielectric layer 210 filling the second contact holes of the bit line contact holes. The third conductive layer and the second mask layer are patterned to form a one-dimensional conductive layer pattern (not shown) and a one-dimensional line mask pattern (not shown), respectively.

第四光阻薄膜塗覆在第二遮罩層上。曝露並顯影該第四光阻薄膜以在第二遮罩層上形成第四光阻圖案(未展示)。藉由使用第四光阻圖案作為蝕刻遮罩來連續地圖案化第二遮罩層與第三導電層以形成填充對應於位元線接觸孔之第二接觸孔的第三墊片(未展示)，並形成包括位元線導電圖案及位元線遮罩層圖案之位元線(未展示)。A fourth photoresist film is coated on the second mask layer. The fourth photoresist film is exposed and developed to form a fourth photoresist pattern (not shown) on the second mask layer. The second mask layer and the third conductive layer are continuously patterned by using the fourth photoresist pattern as an etch mask to form a third spacer filling the second contact hole corresponding to the bit line contact hole (not shown) And forming a bit line (not shown) including a bit line conductive pattern and a bit line mask layer pattern.

第三墊片對應於第二位元線接觸墊片用於將位元線與第一位元線接觸墊片之第二墊片205電連接。第三墊片亦已知作為位元線接觸插塞之第一插塞。在隨後執行之用於形成儲存節點接觸孔之第四接觸孔270(圖10C)之蝕刻處理期間，位元線遮罩圖案鈍化位元線導電圖案。使用對氧化物、第一氧化物層260及第二氧化物層265形成之第四層間介電層250具有蝕刻選擇性之材料來形成位元線遮罩圖案。舉例而言，位元線遮罩圖案使用諸如氮化矽之氮化物形成。The third spacer corresponds to the second bit line contact pad for electrically connecting the bit line to the second pad 205 of the first bit line contact pad. The third spacer is also known as the first plug of the bit line contact plug. The bit line mask pattern passivates the bit line conductive pattern during the etching process of the fourth contact hole 270 (FIG. 10C) for subsequently forming the storage node contact hole. A material having an etch selectivity is formed using the fourth interlayer dielectric layer 250 formed of the oxide, the first oxide layer 260, and the second oxide layer 265 to form a bit line mask pattern. For example, the bit line mask pattern is formed using a nitride such as tantalum nitride.

在位元線與第二層間介電層210上形成第二介電層(未展示)。接著，各向異性地蝕刻該第二介電層以形成對應於各個位元線之側壁部分上之位元線隔離片的第二隔離片(未展示)。使用對第二層間介電層210及第三層間介電層215(隨後形成)具有蝕刻選擇性的材料來形成第二隔離片，以用於在第二儲存節點接觸墊片之第四墊片240之形成期間鈍化 位元線。A second dielectric layer (not shown) is formed over the bit line and the second interlayer dielectric layer 210. Next, the second dielectric layer is anisotropically etched to form a second spacer (not shown) corresponding to the bit line spacers on the sidewall portions of the respective bit lines. Forming a second spacer using a material having an etch selectivity to the second interlayer dielectric layer 210 and the third interlayer dielectric layer 215 (formed subsequently) for contacting the fourth spacer of the spacer at the second storage node Passivation during formation of 240 Bit line.

第三層間介電層215在第二層間介電層210上形成，同時覆蓋在其側壁部分上包括第二隔離片之位元線。第三層間介電層215使用諸如BPSG、USG及HDP-CVD氧化物之氧化合物形成。A third interlayer dielectric layer 215 is formed over the second interlayer dielectric layer 210 while covering the bit lines including the second spacers on the sidewall portions thereof. The third interlayer dielectric layer 215 is formed using an oxygen compound such as BPSG, USG, and HDP-CVD oxide.

藉由CMP處理、回蝕處理或其組合來蝕刻第三層間介電層215直至曝露位元線遮罩圖案之上表面部分，以平面化第三層間介電層215之上表面。The third interlayer dielectric layer 215 is etched by CMP processing, etch back processing, or a combination thereof until the upper surface portion of the bit line mask pattern is exposed to planarize the upper surface of the third interlayer dielectric layer 215.

第五光阻薄膜塗覆在經平面化之第三層間介電層215上。曝露並顯影該第五光阻薄膜以形成第五光阻圖案(未展示)。第三層間介電層215與第二層間介電層210使用第五光阻圖案作為蝕刻遮罩來部分地蝕刻以形成用於曝露第一墊片200之第三接觸孔238。第三接觸孔238對應於第一儲存節點接觸孔。第三接觸孔238關於位元線之側壁部分上形成之第二隔離片以自對齊方式形成。A fifth photoresist film is coated on the planarized third interlayer dielectric layer 215. The fifth photoresist film is exposed and developed to form a fifth photoresist pattern (not shown). The third interlayer dielectric layer 215 and the second interlayer dielectric layer 210 are partially etched using the fifth photoresist pattern as an etch mask to form a third contact hole 238 for exposing the first spacer 200. The third contact hole 238 corresponds to the first storage node contact hole. The third contact hole 238 is formed in a self-aligned manner with respect to the second spacer formed on the sidewall portion of the bit line.

在填充第三接觸孔238之第三層間介電層215上形成第四導電層。接著，藉由CMP處理、回蝕處理或其組合來蝕刻第四導電層直至曝露第三層間介電層215之上表面與位元線，以在第三接觸孔內形成第二儲存節點接觸墊片之第四墊片240。第四墊片240亦已知為儲存節點接觸插塞之第二插塞。第四墊片240係使用諸如雜質摻雜多晶矽之導電材料而形成。第四墊片240將第一儲存節點接觸墊片之第一墊片200與儲存電極290(參看圖9D)電連接。因此，儲存電極290藉由第一墊片200與第四墊片240電連接至儲存節點接觸區 域之第一接觸區域185。A fourth conductive layer is formed on the third interlayer dielectric layer 215 filling the third contact hole 238. Then, the fourth conductive layer is etched by CMP processing, etch back treatment or a combination thereof until the upper surface of the third interlayer dielectric layer 215 and the bit line are exposed to form a second storage node contact pad in the third contact hole. The fourth spacer 240 of the sheet. The fourth spacer 240 is also known as a second plug that stores a node contact plug. The fourth spacer 240 is formed using a conductive material such as an impurity doped polysilicon. The fourth spacer 240 electrically connects the first spacer 200 of the first storage node contact pad with the storage electrode 290 (see FIG. 9D). Therefore, the storage electrode 290 is electrically connected to the storage node contact area by the first spacer 200 and the fourth spacer 240. The first contact area 185 of the domain.

圖10C為說明形成第四接觸孔270與儲存電極290之步驟的截面圖。FIG. 10C is a cross-sectional view illustrating a step of forming the fourth contact hole 270 and the storage electrode 290.

參看圖10C，藉由BPSG、USG、SOG(玻璃上覆矽)或HDP-CVD氧化物在第二儲存節點接觸墊片之第四墊片240、位元線及第三層間介電層215上形成第四層間介電層250。第四層間介電層250將位元線與儲存電極290電分離。Referring to FIG. 10C, the fourth spacer 240, the bit line and the third interlayer dielectric layer 215 of the spacer are contacted by the second storage node by BPSG, USG, SOG (glass overlying germanium) or HDP-CVD oxide. A fourth interlayer dielectric layer 250 is formed. The fourth interlayer dielectric layer 250 electrically separates the bit lines from the storage electrodes 290.

在第四層間介電層250上形成一蝕刻中止層255。使用對第四層間介電層250、第一氧化物層260及第二氧化物層265具有蝕刻選擇性之材料，來形成該蝕刻中止層255。舉例而言，蝕刻中止層255藉由使用諸如氮化矽之氮化合物形成。此處，在藉由CMP處理、回蝕處理或其組合平面化第四層間介電層250之上表面之後，則可在經平面化之第四層間介電層250上形成蝕刻中止層255。An etch stop layer 255 is formed on the fourth interlayer dielectric layer 250. The etch stop layer 255 is formed using a material having an etch selectivity to the fourth interlayer dielectric layer 250, the first oxide layer 260, and the second oxide layer 265. For example, the etch stop layer 255 is formed by using a nitrogen compound such as tantalum nitride. Here, after planarizing the upper surface of the fourth interlayer dielectric layer 250 by CMP processing, etch back processing, or a combination thereof, an etch stop layer 255 may be formed on the planarized fourth interlayer dielectric layer 250.

在蝕刻中止層255上形成第一氧化物層260與第二氧化物層265以充當用於形成儲存電極290之模。第一氧化物層260使用BPSG或USG形成，且第二氧化物層265使用諸如PE-TEOS之氧化物材料形成。第一與第二氧化物層260、265可在蝕刻中止層255之上表面上形成至大約5000至大約50000 Å之厚度。然而，第一與第二氧化物層260與265之總厚度可根據電容器310(參看圖10E)之所要電容適當地控制。即，電容器310之高度由第一與第二氧化物層260、265之厚度決定。A first oxide layer 260 and a second oxide layer 265 are formed on the etch stop layer 255 to serve as a mold for forming the storage electrode 290. The first oxide layer 260 is formed using BPSG or USG, and the second oxide layer 265 is formed using an oxide material such as PE-TEOS. The first and second oxide layers 260, 265 may be formed to a thickness of about 5,000 to about 50,000 Å on the upper surface of the etch stop layer 255. However, the total thickness of the first and second oxide layers 260 and 265 can be appropriately controlled according to the desired capacitance of the capacitor 310 (see FIG. 10E). That is, the height of the capacitor 310 is determined by the thicknesses of the first and second oxide layers 260, 265.

在第二氧化物層265上形成第六光阻薄膜(未展示)。藉由 曝露並顯影來圖案化該第六光阻薄膜以在第二氧化物層265上形成第六光阻圖案。A sixth photoresist film (not shown) is formed on the second oxide layer 265. By The sixth photoresist film is exposed and developed to form a sixth photoresist pattern on the second oxide layer 265.

使用第六光阻圖案作為蝕刻遮罩來部分地蝕刻第二氧化物層265、第一氧化物層260、蝕刻中止層255及第四層間介電層250以形成用於曝露第四墊片240的儲存節點接觸孔之第四接觸孔270。The second oxide layer 265, the first oxide layer 260, the etch stop layer 255, and the fourth interlayer dielectric layer 250 are partially etched using the sixth photoresist pattern as an etch mask to form a fourth spacer 240 for exposure. The storage node contacts the fourth contact hole 270 of the hole.

圖10D為說明在第四接觸孔270內形成一儲存電極290之步驟的截面圖。FIG. 10D is a cross-sectional view illustrating a step of forming a storage electrode 290 in the fourth contact hole 270.

參看圖10D，藉由灰化處理與剝離處理來移除第六光阻圖案。接著，在曝露之第四墊片240及第四接觸孔270之內壁部分上形成雜質摻雜多晶矽之第五導電層。Referring to FIG. 10D, the sixth photoresist pattern is removed by an ashing process and a lift-off process. Next, a fifth conductive layer of impurity doped polysilicon is formed on the inner wall portions of the exposed fourth spacer 240 and the fourth contact hole 270.

藉由CMP處理、回蝕處理或其組合來移除一部分第五導電層直至曝露第二氧化物層265之上表面，以在第四墊片240及第四接觸孔270之內壁部分上形成一導電層圖案280。A portion of the fifth conductive layer is removed by CMP processing, etch back treatment, or a combination thereof until the upper surface of the second oxide layer 265 is exposed to form on the inner wall portions of the fourth spacer 240 and the fourth contact hole 270. A conductive layer pattern 280.

在導電圖案280之表面上選擇性地生長一HSG矽層285以形成一電連接至第一接觸區域185之儲存電極290。An HSG germanium layer 285 is selectively grown on the surface of the conductive pattern 280 to form a storage electrode 290 electrically connected to the first contact region 185.

圖10E為說明形成電容器310之步驟的截面圖。FIG. 10E is a cross-sectional view illustrating the steps of forming the capacitor 310.

參看圖10E，藉由使用根據本發明之一實施例之蝕刻組合物之濕蝕刻處理來移除第二氧化物層265與第一氧化物層260。Referring to FIG. 10E, the second oxide layer 265 and the first oxide layer 260 are removed by a wet etch process using an etch composition in accordance with an embodiment of the present invention.

在儲存電極290之底部表面、內壁部分及外壁部分上形成氮化物材料或氧化物材料之介電層薄膜295。接著，在使用金屬或雜質摻雜多晶矽之介電薄膜295上形成一上部電極300以完成電容器310。圖案化上部電極300及介電薄膜295 以將各個電容器310彼此分隔。在電容器310上形成第五層間介電層(未展示)以用於與上部導線電絕緣。上部導線在第五層間介電層上形成以形成半導體裝置。A dielectric film 295 of a nitride material or an oxide material is formed on the bottom surface, the inner wall portion, and the outer wall portion of the storage electrode 290. Next, an upper electrode 300 is formed on the dielectric film 295 doped with a metal or impurity doped polysilicon to complete the capacitor 310. Patterning the upper electrode 300 and the dielectric film 295 The respective capacitors 310 are separated from each other. A fifth interlayer dielectric layer (not shown) is formed over capacitor 310 for electrical isolation from the upper conductor. The upper wire is formed on the fifth interlayer dielectric layer to form a semiconductor device.

根據本發明之實施例，將在下文進一步描述用於藉由使用具有上文所述特性之蝕刻組合物來移除第二及第一氧化物層265與260之蝕刻處理。An etch process for removing the second and first oxide layers 265 and 260 by using an etch composition having the characteristics described above will be further described below in accordance with an embodiment of the present invention.

圖11A至11F為藉由電子顯微鏡所拍之用於說明使用根據本發明之一實施例之蝕刻組合物的第一與第二氧化物層260與265之影像。該等圖形分別說明使用蝕刻組合物分別執行大約15分鐘、大約16分鐘、大約17分鐘、大約18分鐘、大約19分鐘及大約20分鐘之濕式蝕刻處理之後的結果。11A through 11F are images taken by an electron microscope for illustrating first and second oxide layers 260 and 265 using an etching composition according to an embodiment of the present invention. The figures illustrate the results of the wet etching process performed using the etching composition for about 15 minutes, about 16 minutes, about 17 minutes, about 18 minutes, about 19 minutes, and about 20 minutes, respectively.

如圖11A至11F所說明，藉由使用多晶矽形成之儲存電極290在第二氧化物層265與第一氧化物層260之蝕刻期間並未受損害。As illustrated in FIGS. 11A through 11F, the storage electrode 290 formed by using polysilicon is not damaged during the etching of the second oxide layer 265 and the first oxide layer 260.

圖12A與12B分別為說明在使用根據本發明之一實施例之蝕刻組合物的浸漬類型蝕刻處理及循環類型蝕刻處理之後，殘留氮化物層之厚度分散之俯視圖。12A and 12B are plan views respectively illustrating the thickness dispersion of the residual nitride layer after the immersion type etching process and the cycle type etching process using the etching composition according to an embodiment of the present invention.

圖12A為說明當使用浸漬技術執行濕式蝕刻處理時蝕刻中止層255之厚度分散(其為半導體基板150上殘留氮化物層)之俯視圖。圖12B為說明當使用循環技術執行濕蝕刻處理時蝕刻中止層255之厚度分散(其為半導體基板150上殘留氮化物層)之俯視圖。FIG. 12A is a plan view illustrating the thickness dispersion of the etch stop layer 255 (which is a residual nitride layer on the semiconductor substrate 150) when the wet etching process is performed using the immersion technique. FIG. 12B is a plan view illustrating the thickness dispersion of the etch stop layer 255 (which is a residual nitride layer on the semiconductor substrate 150) when the wet etching process is performed using the recycling technique.

參看圖12A，浸漬類型濕蝕刻處理執行大約900秒。半導體基板150上之殘留蝕刻中止層255之平均厚度大約為404，其最大厚度大約為411且其最小厚度大約為395。因此，殘留蝕刻中止層255之厚度分散大約為15。即，當使用根據本發明之一實施例之蝕刻組合物執行蝕刻處理時，與習知蝕刻組合物相比，氮化物層之厚度分散實質上減少了。Referring to Figure 12A, the immersion type wet etch process is performed for approximately 900 seconds. The average thickness of the residual etch stop layer 255 on the semiconductor substrate 150 is approximately 404. , its maximum thickness is about 411 And its minimum thickness is about 395 . Therefore, the residual etching stop layer 255 has a thickness dispersion of about 15 . That is, when the etching treatment is performed using the etching composition according to an embodiment of the present invention, the thickness dispersion of the nitride layer is substantially reduced as compared with the conventional etching composition.

參看圖12B，循環類型濕蝕刻處理執行大約840秒。半導體基板150上之殘留蝕刻中止層255之平均厚度大約為470。其最大厚度大約為474，且其最小厚度大約為462。因此，殘留蝕刻中止層255之厚度分散大約為12，其很低。因此，當藉由使用根據本發明之一實施例之蝕刻組合物的濕蝕刻處理來選擇性地移除氧化物層時，顯著地改良了蝕刻均勻性。Referring to Figure 12B, a cyclic type wet etch process is performed for approximately 840 seconds. The average thickness of the residual etch stop layer 255 on the semiconductor substrate 150 is approximately 470. . Its maximum thickness is about 474 And its minimum thickness is about 462 . Therefore, the residual etching stop layer 255 has a thickness dispersion of about 12 It is very low. Therefore, when the oxide layer is selectively removed by the wet etching treatment using the etching composition according to an embodiment of the present invention, the etching uniformity is remarkably improved.

根據本發明之實施例，蝕刻組合物(藉此使用多晶矽形成一圖案或一儲存電極)可有效地被鈍化，即，保護使其免受過蝕刻。當藉由使用蝕刻組合物之濕蝕刻處理來移除氧化物層時，移除該氧化物層而具有高蝕刻選擇性，且多晶矽層被保護以免受損害。另外，與習知蝕刻組合物相比，大大地改良了藉由用於選擇性地移除氧化物層之濕蝕刻處理所產生的蝕刻均勻性。In accordance with embodiments of the present invention, the etching composition (by which a polysilicon is used to form a pattern or a storage electrode) can be effectively passivated, i.e., protected from overetching. When the oxide layer is removed by a wet etching process using an etching composition, the oxide layer is removed to have high etching selectivity, and the polysilicon layer is protected from damage. In addition, the etching uniformity produced by the wet etching process for selectively removing the oxide layer is greatly improved as compared with the conventional etching composition.

儘管參看隨附實施例詳細地描述了本發明，但是，可不背離本發明之真實精神及範疇而使用各種修改、替代之構造及均等物。While the invention has been described in detail with reference to the embodiments the embodiments

10,100‧‧‧基板10,100‧‧‧substrate

15,155‧‧‧隔離層15,155‧‧‧ isolation layer

20‧‧‧閘極電極20‧‧‧gate electrode

25‧‧‧封頂層25‧‧‧ top

30‧‧‧隔離片30‧‧‧Isolation

35‧‧‧閘極結構35‧‧‧ gate structure

40‧‧‧源極/汲極區域40‧‧‧Source/bungee area

45‧‧‧接觸墊片45‧‧‧Contact gasket

50‧‧‧層間介電層50‧‧‧Interlayer dielectric layer

55,75‧‧‧儲存節點接觸插塞55,75‧‧‧Storage node contact plug

60‧‧‧蝕刻中止層60‧‧‧ etching stop layer

65‧‧‧下部犧牲層65‧‧‧ lower sacrificial layer

70‧‧‧上部犧牲層70‧‧‧ upper sacrificial layer

75‧‧‧儲存節點接觸孔75‧‧‧Storage node contact hole

80,290‧‧‧儲存電極80,290‧‧‧ storage electrode

85‧‧‧HSG矽層85‧‧‧HSG layer

90‧‧‧介電薄膜90‧‧‧ dielectric film

95‧‧‧上部電極95‧‧‧Upper electrode

97‧‧‧HSG電容器97‧‧‧HSG capacitor

105‧‧‧氮化物層105‧‧‧ nitride layer

110‧‧‧第一氧化物層110‧‧‧First oxide layer

115‧‧‧第二氧化物層115‧‧‧Second oxide layer

120‧‧‧接觸孔120‧‧‧Contact hole

125‧‧‧多晶矽層圖案125‧‧‧ Polycrystalline layer pattern

150‧‧‧半導體基板150‧‧‧Semiconductor substrate

165‧‧‧閘極導電圖案165‧‧‧ gate conductive pattern

170‧‧‧閘極遮罩圖案170‧‧‧ gate mask pattern

175‧‧‧閘極結構175‧‧‧ gate structure

180‧‧‧第一隔離片180‧‧‧First spacer

183‧‧‧電晶體結構183‧‧‧Optoelectronic structure

185‧‧‧第一接觸區域185‧‧‧First contact area

190‧‧‧第二接觸區域190‧‧‧Second contact area

195‧‧‧第一層間介電層195‧‧‧First interlayer dielectric layer

198‧‧‧第一接觸孔198‧‧‧First contact hole

200‧‧‧電容器200‧‧‧ capacitor

200‧‧‧第一墊片200‧‧‧First gasket

205‧‧‧第二墊片205‧‧‧second gasket

210‧‧‧第二層間介電層210‧‧‧Second interlayer dielectric layer

215‧‧‧第三層間介電層215‧‧‧ Third interlayer dielectric layer

238‧‧‧第三接觸孔238‧‧‧ third contact hole

240‧‧‧第四墊片240‧‧‧fourth gasket

250‧‧‧第四層間介電層250‧‧‧4th interlayer dielectric layer

255‧‧‧蝕刻中止層255‧‧‧etch stop layer

260‧‧‧第一氧化物層260‧‧‧First oxide layer

265‧‧‧第二氧化物層265‧‧‧Second oxide layer

270‧‧‧第四接觸孔270‧‧‧4th contact hole

280‧‧‧導電層圖案280‧‧‧ Conductive layer pattern

285‧‧‧HSG矽層285‧‧‧HSG layer

290‧‧‧儲存電極290‧‧‧Storage electrode

295‧‧‧介電薄膜295‧‧‧ dielectric film

300‧‧‧上部電極300‧‧‧Upper electrode

310‧‧‧電容器310‧‧‧ capacitor

圖1A至1D為說明製造具有HSG電容器之習知半導體記 憶體裝置之方法的截面圖；圖2為藉由電子顯微鏡所拍之在使用習知LAL溶液蝕刻處理氧化物層之後的儲存電極之影像；圖3為藉由電子顯微鏡所拍之在使用習知5：1氟化氫溶液蝕刻處理氧化物層之後的儲存電極之影像；圖4A與4B分別為代表在使用習知5：1氟化氫溶液之浸漬類型蝕刻處理及循環類型蝕刻處理之後，殘留氮化物層之厚度分散之俯視圖；圖5A與5B為說明藉由根據本發明之一實施例的蝕刻組合物鈍化多晶矽層之機制的示意性截面圖；圖6為說明製備根據本發明之一實施例的蝕刻組合物之方法的流程圖；圖7A至7C為說明藉由使用根據本發明之一實施例的蝕刻組合物在氧化物層、氮化物層及多晶矽層中選擇性地蝕刻氧化物層之方法的截面圖；圖8A至8D為說明在藉由使用根據本發明之實例1獲得之蝕刻組合物及根據比較實例1至3獲得之蝕刻組合物之濕式蝕刻處理中用於PE-TEOS層、BPSG層、氮化矽層及多晶矽層之蝕刻速率之圖；圖9A至9D為說明在藉由使用根據本發明之實例2與3獲得之蝕刻組合物及根據比較實例4獲得之蝕刻組合物之濕蝕刻處理中用於PE-TEOS層、BPSG層、氮化矽層及多晶矽層之蝕刻速率之圖；圖10A至10E為說明一種製造根據本發明之一實施例的 半導體裝置之方法的截面圖；圖11A至11F為藉由電子顯微鏡所拍之展示使用根據本發明之一實施例之蝕刻組合物蝕刻之氧化物層之影像；及圖12A與12B分別為代表在使用根據本發明之一實施例之蝕刻溶液進行浸漬類型蝕刻處理及循環類型蝕刻處理之後，殘留氮化物層之厚度分散之俯視圖。1A to 1D are diagrams illustrating the fabrication of a conventional semiconductor having a HSG capacitor FIG. 2 is a cross-sectional view of a method of etching an oxide layer using a conventional LAL solution by an electron microscope; FIG. 3 is a photograph taken by an electron microscope. 5:1 image of the storage electrode after etching the oxide layer by the hydrogen fluoride solution; FIGS. 4A and 4B respectively represent the residual nitride layer after the immersion type etching treatment and the circulation type etching treatment using the conventional 5:1 hydrogen fluoride solution. FIG. 5A and FIG. 5B are schematic cross-sectional views illustrating a mechanism for passivating a polysilicon layer by an etching composition according to an embodiment of the present invention; FIG. 6 is a view illustrating preparation of an etching according to an embodiment of the present invention. A flow chart of a method of the composition; FIGS. 7A to 7C are diagrams illustrating a method of selectively etching an oxide layer in an oxide layer, a nitride layer, and a polysilicon layer by using an etching composition according to an embodiment of the present invention; FIG. 8A to FIG. 8D are diagrams illustrating wet etching of an etching composition obtained by using Example 1 according to the present invention and an etching composition obtained according to Comparative Examples 1 to 3. A diagram of the etching rates for the PE-TEOS layer, the BPSG layer, the tantalum nitride layer, and the polysilicon layer; FIGS. 9A to 9D are diagrams illustrating the etching composition obtained by using Examples 2 and 3 according to the present invention and Comparing the etching rates for the PE-TEOS layer, the BPSG layer, the tantalum nitride layer, and the polysilicon layer in the wet etching process of the etching composition obtained in Example 4; FIGS. 10A to 10E are diagrams illustrating the fabrication according to one embodiment of the present invention. Case A cross-sectional view of a method of a semiconductor device; FIGS. 11A through 11F are views showing an oxide layer etched using an etching composition according to an embodiment of the present invention by an electron microscope; and FIGS. 12A and 12B are representative A plan view in which the thickness of the residual nitride layer is dispersed after performing an immersion type etching process and a cycle type etching process using an etching solution according to an embodiment of the present invention.

(無元件符號說明)(no component symbol description)

Claims (15)

一種蝕刻組合物，其包含大約0.1至8重量百分比之氟化氫(HF)、大約10至25重量百分比之氟化銨(NH4 F)、大約0.0001至3重量百分比之非離子聚合物界面活性劑及水(H2 O)，其中該非離子聚合物界面活性劑具有H-(OCH2 CH2 )x -(OCH(CH3 )CH2 )y -(OCH2 CH2 )z -OH之結構，其中x、y及z為正整數，且其中該非離子聚合物界面活性劑之平均分子量大約為3000或更少，或其中該非離子聚合物界面活性劑包含聚醇非離子聚合物界面活性劑，其係如下列結構所表示之添加聚氧化乙烯之山梨聚糖酯， 其中w、x、y及z為正整數。An etching composition comprising about 0.1 to 8 weight percent hydrogen fluoride (HF), about 10 to 25 weight percent ammonium fluoride (NH 4 F), about 0.0001 to 3 weight percent nonionic polymer surfactant, and Water (H 2 O), wherein the nonionic polymer surfactant has a structure of H-(OCH 2 CH 2 ) x -(OCH(CH 3 )CH 2 ) y -(OCH 2 CH 2 ) z -OH, wherein X, y, and z are positive integers, and wherein the nonionic polymeric surfactant has an average molecular weight of about 3,000 or less, or wherein the nonionic polymeric surfactant comprises a polyalcoholic nonionic polymeric surfactant, Adding polyoxyethylene sorbitan ester as indicated by the following structure, Where w, x, y, and z are positive integers. 如請求項1之蝕刻組合物，其中該非離子聚合物界面活性劑之量為大約0.001至大約0.02重量百分比之範圍。 The etching composition of claim 1, wherein the amount of the nonionic polymeric surfactant is in the range of from about 0.001 to about 0.02 weight percent. 一種製備蝕刻組合物之方法，該方法包含以下步驟：藉由將非離子聚合物界面活性劑與氟化氫溶液混合來製備第一混合物溶液；藉由將水與該第一混合物溶液混合來製備第二混合物溶液；及藉由將氟化銨溶液與該第二混合物溶液混合以製備該蝕刻組合物，其包含大約0.1至8重量百分比之氟化氫 (HF)、大約10至25重量百分比之氟化銨(NH4 F)、大約0.0001至3重量百分比之非離子聚合物界面活性劑及水(H2 O)，其中該非離子聚合物界面活性劑具有H-(OCH2 CH2 )x -(OCH(CH3 )CH2 )y -(OCH2 CH2 )z -OH之結構，其中x、y及z為正整數，且其中該非離子聚合物界面活性劑之平均分子量大約為3000或更少，或其中該非離子聚合物界面活性劑包含聚醇非離子聚合物界面活性劑，其係如下列結構所表示之添加聚氧化乙烯之山梨聚糖酯， 其中w、x、y及z為正整數。A method of preparing an etching composition, the method comprising the steps of: preparing a first mixture solution by mixing a nonionic polymer surfactant with a hydrogen fluoride solution; preparing a second by mixing water with the first mixture solution a mixture solution; and preparing the etching composition by mixing an ammonium fluoride solution with the second mixture solution, comprising about 0.1 to 8 weight percent hydrogen fluoride (HF), and about 10 to 25 weight percent ammonium fluoride ( NH 4 F), about 0.0001 to 3 weight percent of a nonionic polymeric surfactant and water (H 2 O), wherein the nonionic polymeric surfactant has H-(OCH 2 CH 2 ) x -(OCH(CH) 3 ) a structure of CH 2 ) y -(OCH 2 CH 2 ) z -OH, wherein x, y and z are positive integers, and wherein the nonionic polymer surfactant has an average molecular weight of about 3,000 or less, or The nonionic polymer surfactant comprises a polyalcohol nonionic polymer surfactant, which is added with a polyoxyethylene sorbitan ester as represented by the following structure, Where w, x, y, and z are positive integers. 如請求項3之方法，其中該非離子聚合物界面活性劑與氟化氫溶液以大約10至40℃之溫度範圍，混合大約3小時或更久。 The method of claim 3, wherein the nonionic polymeric surfactant is mixed with the hydrogen fluoride solution at a temperature ranging from about 10 to 40 ° C for about 3 hours or longer. 如請求項3之方法，其中該水與該第一混合物溶液以大約10至40℃之溫度範圍，混合大約3小時或更久。 The method of claim 3, wherein the water and the first mixture solution are mixed at a temperature ranging from about 10 to 40 ° C for about 3 hours or longer. 如請求項3之方法，其中該第二混合物溶液與該氟化銨溶液以大約10至40℃之溫度範圍，混合大約12小時或更久。 The method of claim 3, wherein the second mixture solution is mixed with the ammonium fluoride solution at a temperature ranging from about 10 to 40 ° C for about 12 hours or longer. 如請求項3之方法，其中在該第一混合物溶液、該第二混合物溶液及該蝕刻組合物之製備期間，過濾包含在該第一混合物溶液、該第二混合物溶液及該蝕刻組合物中之顆粒。 The method of claim 3, wherein during the preparation of the first mixture solution, the second mixture solution, and the etching composition, the filtering is included in the first mixture solution, the second mixture solution, and the etching composition. Particles. 如請求項3之方法，其中該氟化氫溶液之濃度為大約40至60重量百分比之範圍。 The method of claim 3, wherein the concentration of the hydrogen fluoride solution is in the range of about 40 to 60 weight percent. 如請求項3之方法，其中該氟化銨溶液之濃度為大約30至50重量百分比之範圍。 The method of claim 3, wherein the concentration of the ammonium fluoride solution is in the range of about 30 to 50 weight percent. 一種蝕刻方法，其包含以下步驟：在一基板上形成一氮化物層；形成一氧化物層；圖案化該氧化物以形成一曝露該氮化物層之接觸孔；在該曝露之氮化物層及該接觸孔之一內側壁部分上，形成一多晶矽層圖案；及使用蝕刻組合物移除該氧化物層，其中該蝕刻組合物包含大約0.1至8重量百分比之氟化氫(HF)、大約10至25重量百分比之氟化銨(NH4 F)、大約0.0001至3重量百分比之非離子聚合物界面活性劑及水(H2 O)，其中該非離子聚合物界面活性劑具有H-(OCH2 CH2 )x -(OCH(CH3 )CH2 )y -(OCH2 CH2 )z -OH之結構，其中x、y及z為正整數，且其中該非離子聚合物界面活性劑之平均分子量大約為3000或更少，或其中該非離子聚合物界面活性劑包含聚醇非離子聚合物界面活性劑，其係如下列結構所表示之添加聚氧化乙烯之山梨聚糖酯， 其中w、x、y及z為正整數，其中該非離子聚合物界面活 性劑選擇性地吸附於該多晶矽層之表面部分，以鈍化該多晶矽層圖案。An etching method comprising the steps of: forming a nitride layer on a substrate; forming an oxide layer; patterning the oxide to form a contact hole exposing the nitride layer; and exposing the exposed nitride layer and Forming a polysilicon layer pattern on an inner sidewall portion of the contact hole; and removing the oxide layer using an etching composition, wherein the etching composition comprises about 0.1 to 8 weight percent hydrogen fluoride (HF), about 10 to 25 A weight percentage of ammonium fluoride (NH 4 F), about 0.0001 to 3 weight percent of a nonionic polymeric surfactant, and water (H 2 O), wherein the nonionic polymeric surfactant has H-(OCH 2 CH 2 a structure of x -(OCH(CH 3 )CH 2 ) y -(OCH 2 CH 2 ) z -OH, wherein x, y and z are positive integers, and wherein the average molecular weight of the nonionic polymer surfactant is about 3000 or less, or wherein the nonionic polymeric surfactant comprises a polyalcoholic nonionic polymeric surfactant, which is a polyoxyethylene sorbitan ester as indicated by the following structure, Wherein w, x, y and z are positive integers, wherein the nonionic polymer surfactant is selectively adsorbed on a surface portion of the polysilicon layer to passivate the polysilicon layer pattern. 如請求項10之蝕刻方法，其中該形成氧化物層之步驟包含：在該氮化物層上形成一第一氧化物層；及在該第一氧化物層上形成一第二氧化物層。 The etching method of claim 10, wherein the step of forming an oxide layer comprises: forming a first oxide layer on the nitride layer; and forming a second oxide layer on the first oxide layer. 如請求項11之蝕刻方法，其中該氮化物層包含氮化矽該第一氧化物層包含BPSG(硼磷矽酸鹽玻璃)，且該第二氧化物層包含PE-TEOS(電漿增強-正矽酸四乙酯)。 The etching method of claim 11, wherein the nitride layer comprises tantalum nitride, the first oxide layer comprises BPSG (borophosphonite glass), and the second oxide layer comprises PE-TEOS (plasma enhancement - Tetraethyl orthoacetate). 一種製造一半導體裝置之方法，該方法包含以下步驟：在一半導體基板上形成一蝕刻中止層；在該蝕刻中止層上形成一第一氧化物層；在該第一氧化物層上形成一第二氧化物層；部分地移除該第一與該第二氧化物層以曝露一接觸區域；形成一接觸該接觸區域之多晶矽層圖案；及使用蝕刻組合物移除該第一與該第二氧化物層，其中該蝕刻組合物包含大約0.1至8重量百分比之氟化氫(HF)、大約10至25重量百分比之氟化銨(NH4 F)、大約0.0001至3重量百分比之非離子聚合物界面活性劑及水(H2 O)，其中該非離子聚合物界面活性劑具有H-(OCH2 CH2 )x -(OCH(CH3 )CH2 )y -(OCH2 CH2 )z -OH之結構，其中x、y及z為正整數，且其中該非離子聚合物界面活性劑之平均分子量大約為3000或更少，或其中該非離 子聚合物界面活性劑包含聚醇非離子聚合物界面活性劑，其係如下列結構所表示之添加聚氧化乙烯之山梨聚糖酯， 其中w、x、y及z為正整數，其中該非離子聚合物界面活性劑選擇性地吸附於該多晶矽層圖案之表面部分，以鈍化該多晶矽層圖案。A method of fabricating a semiconductor device, the method comprising the steps of: forming an etch stop layer on a semiconductor substrate; forming a first oxide layer on the etch stop layer; forming a first layer on the first oxide layer a second oxide layer; partially removing the first and second oxide layers to expose a contact region; forming a polysilicon layer pattern contacting the contact region; and removing the first and second regions using an etching composition An oxide layer, wherein the etching composition comprises about 0.1 to 8 weight percent hydrogen fluoride (HF), about 10 to 25 weight percent ammonium fluoride (NH 4 F), and about 0.0001 to 3 weight percent nonionic polymer interface An active agent and water (H 2 O), wherein the nonionic polymer surfactant has H-(OCH 2 CH 2 ) x -(OCH(CH 3 )CH 2 ) y -(OCH 2 CH 2 ) z -OH a structure wherein x, y and z are positive integers, and wherein the nonionic polymeric surfactant has an average molecular weight of about 3000 or less, or wherein the nonionic polymeric surfactant comprises a polyalcoholic nonionic polymeric surfactant , which is represented by the following structure Adding polyoxyethylene sorbitan ester, Wherein w, x, y and z are positive integers, wherein the nonionic polymer surfactant is selectively adsorbed on a surface portion of the polysilicon layer pattern to passivate the polysilicon layer pattern. 如請求項13之方法，其中該蝕刻中止層包含氮化矽材料，該第一氧化物層包含BPSG，且該第二氧化物層包含PE-TEOS。 The method of claim 13, wherein the etch stop layer comprises a tantalum nitride material, the first oxide layer comprises BPSG, and the second oxide layer comprises PE-TEOS. 如請求項13之方法，其進一步包含以下步驟：在該多晶矽層圖案上形成一HSG矽層；在該HSG矽層上形成一介電薄膜；及在該介電層上形成一板電極。 The method of claim 13, further comprising the steps of: forming a HSG germanium layer on the polysilicon layer pattern; forming a dielectric film on the HSG germanium layer; and forming a plate electrode on the dielectric layer.
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