TW556238B

TW556238B - One-cylinder stack capacitor and method for fabricating the same

Info

Publication number: TW556238B
Application number: TW91120456A
Authority: TW
Inventors: Jung-Hwan Oh; Ki-Hyun Hwang; Jae-Young Park; In-Seak Hwang; Young-Wook Park
Original assignee: Samsung Electronics Co Ltd
Priority date: 2002-05-02
Filing date: 2002-09-09
Publication date: 2003-10-01

Abstract

An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

Description

556238 五、發明説明（1 ) 發明背景 1 ·發明範疇本發明通常相關於單柱體堆疊（ocs)電容器及其製造方法’本發明尤其相關於已由雙模形成的oc 雙模製造OCS電容器的方法。 2 ·相關技藝說明由於半導體裝置的記憶單元密度增加，而已減少記情單疋所佔面積，容量係與電容器電介質的介電常數及電容器電極的表面積成比例，因此需要選擇增加介電常數的電介質’及/或增加電容器電極的表面積以增加容量。惟採用新介電材料通常為昂貴且耗時，其中常需要供應新製造設備，查證介電材料的可靠性，及碟定具備介電材料量產裝置的能力。因此，常以增加電極表面積為 ’以滿足增加具備習用電介質(如由氣㈣及氧二= 組成的介電（NO)層等）的裝置容量。在習用128百萬位元（或更少wDRAM中使用半球形顆粒 (HSG)電極’以增加電極的有效表面積，惟由於在電極表面存在则，而使電極間空間的任何減少受限，因而在W 百萬位70 (或更高）的高積體裝置中無法施加這些電極。如是這般，在單柱體堆疊（0CS)健存電極的例子，例如通常將電極高度由i.4㈣增加至!.6 _的高度，視為增加其容量最有效率的方法。兹將參照至圖W說明習用〇以儲存電極的製造，尤1 是一般使用單模而形成具有少於1>2帥設計規定的⑽電裝訂 t -6- 本紙張尺度適用中國國家標準(CNS) Α4規格(210X297公釐）五、發明説明（2 ) 合為儲存電極。參照至圖1，其表面具有接觸插頭1 $的内層絕緣層H)上形成―姓刻停止層（未示），及形成一氧化層 (未：)至厚度hl，其大致上與想要的電極高度對應。接續將乳化層及㈣停止層姓刻人具有下钱刻停止層20的氧化权乂此方式，在接觸插頭i 5上界定一開口 4〇，藉此曝露接觸插頭15。之後，如圖2所示，在開口 40的側壁上及接觸插頭15上沈積多晶矽，而形成-柱形電極50。參照圖3的電子掃描顯微鏡（sem)像片，如前述，如高積體裝置的例子’為增加其容量，想、增加〇cs電容器電極的问度至1.6 #m(或更高）。惟如果氧化模層的高度由μ增加至h2(、力1.8 //m)及仍維持開口 4()的較低關鍵尺寸⑷，則須注 ^刻限制設定開口 4G的側壁斜度，@可在相鄰的⑽電容器儲存電極間形成橋接B(圖2及3)，藉此而引起雙位元破壞。著力於避開雙位元破壞，可藉由減少開口 4〇的下關鍵尺寸⑷而減少開口 4〇的上關鍵尺寸（a)。惟，此方法不利之處在於，在開口 4〇底部減少表面積而減少容量。亦應注意，發生雙位元破壞會造成儲存電極掉落而觸及鄰近電極，如是這般，有必要考量電極的結構性整合。茲參照至圖4，意即已確定分開儲存電極而使單元隔離之後，即藉由濕蝕將氧化模3〇移除。在此濕蝕過程期間，可將蝕刻劑滲入各儲存電極50與一蝕刻停止層2〇間的介面，藉此而蝕刻夾層絕緣層10。此可使儲存電極的底座變弱而造成儲存電極傾斜且觸及鄰近的電極，圖5A以電子掃描顯微鏡（SEM)像片說明一範例，其中掉落的電極造成具有@ 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公爱) 五、發明說明（形狀圖案的凹陷；而圖5B以電子電極掉入只+ T描頌极叙（SEM)像片說明评入另一電極的剖面圖。因此，對新的OCS電容器結構及1制1 增加，A + p π + /、衣仏方法的需求不斷其中即使電容器高度在h6 ，亦可古ϋ μ (次更阿）專級的例子有效避免鄰近電極間的凹陷及橋接。發明總結根據本發明一方面，製層絕綾展^ 电谷扣電極的方法，包括於夾層#而二衣度延伸入該夾層絕緣表面而形成之表面上形成一上沈積-下^ ρ 層；於姓刻停止層採雜物Γ 由於下模層形成期間在下模層添加下❹ 將下模層退火而調整下模層之濕蝕比；於广镇層上沈積一上模層，I中之濕#比小於調整過形成一、曰，乾姓上模層、下模層及姑刻停止層，以 :模声：口 ’其中至少曝露接觸插頭表面之-部分；㈣近==層，致使下模層之開口尺寸增加，並曝露鄰 =表面之㈣停止層之表面部分；及於上及下模 :開口表面、I虫刻停止層之表面部分及導電插頭之曝露表面上沈積一導電材料。根據本發明另一方面，製造電容器之方法，包括於夾声絕緣層上形成一下電極，於下電極上形成一介電層，及於介電層上形成一上電極’在此下電極的形成，包括於夾声絕緣層表面上及-導電插頭以一深度延伸入該夾層絕緣層表面而形成之表面上形成一蚀刻停止層；於敍刻停止層上沈積-下模層’及藉由於下模層形成期間在下模層雜物，及藉由將下模層退火而 „a π I下模層之濕蝕比；於下模層上沈積一上模層，其中上模声、曰之濕姓比小於調整過下模層濕#比；乾蚀上模層、下模層及姓刻停止層… 成一開口’其中至少曝露接觸插頭表面之-部㈡姓：杈層及下模層，致使在下模層之 ] 尺寸增加，並曝露鄭近導電插頭表面之蝕刻停止層 +备郇噌之表面部分；及於上及下模層之開口表面、|虫刻停止層之矣、層之表面部分及導電插頭之曝露表面上沈積一導電材料。仍根據本發明另—方面’一電容器包括具有一表面之爽層絕緣層；-導電插頭以一深度延伸入夹層絕緣層内；— 蚀刻停止層於絕緣層上延伸並曝露導電插頭；—柱形下電極由柱形侧壁及底部壁界定，底部壁於導電插頭表面及鄰近導電插頭之部分蚀刻停止層上延伸，其中柱形侧壁由底部壁向上延伸而遠離夹層絕緣層表面；一介電層於柱形下電極上形成；及一上電極於介電層上形成。柱形電極之柱㈣由-上柱㈣部分、—下柱形壁部分及位於上下柱形 i 4刀間之中間柱形壁部分而界定。上柱形壁部分之直徑及下柱形壁部分之直徑越遠離底部壁表面越增加，其中中間柱形側壁部分之直徑越遠離底部壁表面越減少，及556238 V. Description of the invention (1) Background of the invention 1. The scope of the present invention is generally related to single-cylinder stacked (OCs) capacitors and manufacturing methods thereof. method. 2 · Relevant technical descriptions Due to the increase in the density of memory cells in semiconductor devices, the area occupied by memory cards has been reduced. The capacity is proportional to the dielectric constant of the capacitor dielectric and the surface area of the capacitor electrodes. Therefore, it is necessary to choose a dielectric with an increased dielectric constant. 'And / or increase the surface area of the capacitor electrode to increase capacity. However, the use of new dielectric materials is usually expensive and time-consuming. Often, new manufacturing equipment needs to be supplied to verify the reliability of the dielectric materials, and it is determined that the dielectric materials have the capacity to mass-produce devices. Therefore, increasing the surface area of the electrode is often used to increase the device capacity with conventional dielectrics (such as a dielectric (NO) layer composed of gas and oxygen). Hemispherical particle (HSG) electrodes' are used in conventional 128 megabit (or less wDRAM) to increase the effective surface area of the electrodes, but any reduction in inter-electrode space is limited due to the presence on the electrode surface, and therefore in These electrodes cannot be applied in W million-bit 70 (or higher) high-volume devices. As such, examples of single-cylinder stacked (0CS) viable electrodes, for example, usually increase the electrode height from i.4㈣ to The height of! .6 _ is regarded as the most efficient way to increase its capacity. The following will explain the manufacturing of storage electrodes with reference to Figure W, especially 1 is generally formed using a single mode with less than 1 &2; handsome design Prescribed book binding t -6- This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) V. Description of the invention (2) Combined into storage electrode. Refer to Figure 1, the surface has a contact plug 1 $ An inner-layer insulation layer (H) is formed on the inner-layer insulation layer (not shown), and an oxide layer (not :) is formed to a thickness hl, which substantially corresponds to the desired electrode height. The emulsion layer and the stop layer are engraved to have the right to oxidize the stop layer 20. In this way, an opening 40 is defined in the contact plug i5, thereby exposing the contact plug 15. Thereafter, as shown in FIG. 2, polycrystalline silicon is deposited on the side wall of the opening 40 and the contact plug 15 to form a columnar electrode 50. Referring to the scanning electron microscope (SEM) image of FIG. 3, as mentioned above, as an example of a high-volume device, to increase its capacity, it is desired to increase the resolution of the capacitor capacitor electrode to 1.6 #m (or higher). However, if the height of the oxide mold layer is increased from μ to h2 (, force 1.8 // m) and the lower critical dimension of the opening 4 () is still maintained, it is necessary to note ^ to limit the setting of the sidewall slope of the opening 4G, @ 可A bridging B is formed between the storage electrodes of the adjacent pseudocapacitors (Figs. 2 and 3), thereby causing double-bit destruction. Focusing on avoiding double bit destruction, the upper key size (a) of the opening 40 can be reduced by reducing the lower key size ⑷ of the opening 40. However, this method has the disadvantage that the surface area is reduced at the bottom of the opening 40 and the capacity is reduced. It should also be noted that the occurrence of double-bit destruction will cause the storage electrode to fall and touch adjacent electrodes. If so, it is necessary to consider the structural integration of the electrodes. Reference is made to FIG. 4, which means that it has been determined that after the storage electrodes are separated to isolate the cells, the oxide mold 30 is removed by wet etching. During this wet etching process, an etchant can be infiltrated into the interface between each storage electrode 50 and an etch stop layer 20 to thereby etch the interlayer insulating layer 10. This can weaken the base of the storage electrode, causing the storage electrode to tilt and touch the adjacent electrode. Figure 5A illustrates an example using an SEM image, where a falling electrode causes a @ (CNS) A4 specification (210X297 public love) 5. Description of the invention (concave of shape and pattern; and Figure 5B shows the cross section of the other electrode when the electronic electrode is dropped into the + T tracing polar (SEM) picture. Therefore, the new structure of OCS capacitors and the increase of one system and one system have increased the demand for A + p π + / and clothing methods. Even if the capacitor height is h6, ancient (μ) second grade examples can be effectively avoided. Depressions and bridges between adjacent electrodes. Summary of the invention According to one aspect of the present invention, a method for forming a layered valley valley electrode includes forming an insulating layer on the surface of the interlayer # and the second layer extending into the insulating surface of the interlayer. Upper deposition-lower ^ ρ layer; stop collecting debris at the last engraving layer. Γ As the lower mold layer is added during the formation of the lower mold layer, the lower mold layer is annealed to adjust the wet erosion ratio of the lower mold layer; deposited on the Guangzhen layer A mold , I 中的湿 # ratio is less than adjusted to form one, that is, the dry mold upper mold layer, lower mold layer, and engraved stop layer, with: mold sound: mouth 'which at least exposes the-contact part of the plug surface; ㈣ near = = Layer, which causes the opening size of the lower mold layer to increase and expose the adjacent surface parts of the ㈣stop layer; and on the upper and lower molds: the opening surface, the surface portion of the engraved stop layer, and the exposed surface of the conductive plug A conductive material is deposited. According to another aspect of the present invention, a method of manufacturing a capacitor includes forming a lower electrode on an acoustic insulation layer, forming a dielectric layer on the lower electrode, and forming an upper electrode on the dielectric layer. The formation of the lower electrode includes forming an etch stop layer on the surface of the sandwich insulation layer and a surface formed by the conductive plug extending into the sandwich insulation layer at a depth; depositing a lower mold layer on the narration stop layer 'And due to the inclusions in the lower mold layer during the formation of the lower mold layer, and by annealing the lower mold layer, the wet erosion ratio of the' a π I lower mold layer; depositing an upper mold layer on the lower mold layer, wherein the upper mold The ratio of the sound and the wet surname is less than the adjustment Lower mold layer wet # ratio; dry-etch the upper mold layer, the lower mold layer and the engraved stop layer ... to form an opening 'where at least the exposed contact surface of the plug-name]: the branch layer and the lower mold layer, resulting in the lower mold layer] Increase the size, and expose the surface of the etch stop layer + the surface of the conductive plug on Zheng Jin; and the opening surfaces of the upper and lower mold layers, the worm stop layer, the surface portion of the layer and the exposure of the conductive plug A conductive material is deposited on the surface. Still according to another aspect of the present invention-a capacitor includes a layered insulating layer having a surface;-a conductive plug extends into the interlayer insulating layer at a depth;-an etch stop layer extends on the insulating layer And expose the conductive plug;-the cylindrical lower electrode is defined by the cylindrical side wall and the bottom wall, the bottom wall extends on the surface of the conductive plug and a part of the etching stop layer adjacent to the conductive plug, wherein the cylindrical side wall extends upward from the bottom wall and away from The surface of the interlayer insulation layer; a dielectric layer is formed on the pillar-shaped lower electrode; and an upper electrode is formed on the dielectric layer. The pillar ㈣ of the cylindrical electrode is defined by-the upper pillar ㈣ part,-the lower cylindrical wall part, and the middle cylindrical wall part located between the upper and lower cylindrical i 4 blades. The diameter of the upper cylindrical wall portion and the diameter of the lower cylindrical wall portion increase as they move away from the bottom wall surface, and the diameter of the intermediate cylindrical side wall portion decreases as they move away from the bottom wall surface, and

A ^ C，C>B，及 C>D 其中A係上柱形壁部分最遠離底部壁表面之位置之直徑， B係上柱形壁部分最靠近底部壁表面之位置之直徑，c係下柱形壁部分最遠離底部壁表面之位置之直徑，而D係下柱形壁部分在底部壁之直徑。 -9 - 本紙張尺度適用中國國家標準(CNS) A4規格(2i〇x297公着) 55623δA ^ C, C > B, and C &D; where A is the diameter of the upper cylindrical wall portion farthest from the bottom wall surface, B is the diameter of the upper cylindrical wall portion closest to the bottom wall surface, and c is the lower The diameter of the cylindrical wall part farthest from the surface of the bottom wall, and D is the diameter of the lower cylindrical wall part at the bottom wall. -9-This paper size applies to Chinese National Standard (CNS) A4 (2i × x297) 55623δ

附圖簡單説明以下由附圖所作詳細說明中，本發明上述及其他方面與優點將更明朗化，其中：圖1及2以剖面圖說明使用單模型製造電容器之習用方法；圖3係以習用方法製造的儲存電極的電子掃描顯微鏡 (SEM)像片；圖4以另一剖面圖說明使用單模型製造電容器之習用方法；圖5Α及5Β各別以上視及側視角度所取得由習用方法製成的儲存電極SEM像片；圖ό至13以剖面圖說明根據本發明一實例，使用雙模型製造單柱體電容器的方法；圖14以剖面圖說明未滿足本發明製造條件時會發生的瑕疵；圖15至17以圖表說明而比較藉由習用使用單模型方法與本發明使用雙模型方法製成的電容器特性；圖18及19以SEM像片說明未清除下模絕緣層而製成的儲存電極中所見到的雙位元破壞；及圖20以圖表說明本發明電極的濕蝕時間與某些關鍵尺寸間的關係。發明詳細説明茲將參照至附圖說明本發明實例，請注意所呈現的圖示係為έ兒明及解釋，不一定按比例繪製。將參照至圖6-13說明根據本發明的單柱體堆疊（〇cs)電容 -10- i張尺度適用巾a a家料(CNS) A4規格(21GX 297公复〉 -------- 556238Brief Description of the Drawings The above and other aspects and advantages of the present invention will be made clearer in the following detailed description made with the accompanying drawings, in which: Figures 1 and 2 illustrate a conventional method for manufacturing a capacitor using a single model in a sectional view; Figure 3 is a conventional method Electron scanning microscope (SEM) image of the storage electrode manufactured by the method; Figure 4 illustrates another conventional method for manufacturing a capacitor using a single model; Figures 5A and 5B are obtained by conventional methods from above and side views respectively SEM image of the storage electrode formed; FIGS. 13 to 13 illustrate cross-sectional views of a method for manufacturing a single-cylinder capacitor using a dual model according to an example of the present invention; and FIG. 14 illustrates cross-sectional views of defects that may occur when the manufacturing conditions of the present invention are not met. Figures 15 to 17 compare the characteristics of capacitors made by the conventional single-model method with the dual-model method of the present invention in a graphical illustration; Figures 18 and 19 illustrate storage made without removing the lower mold insulating layer with SEM images Double bit failures seen in the electrode; and Figure 20 graphically illustrates the relationship between the wet etch time of the electrode of the present invention and certain key dimensions. Detailed Description of the Invention An example of the present invention will be described with reference to the accompanying drawings. Please note that the illustrations shown are for clarity and explanation, and are not necessarily drawn to scale. A single-cylinder stacked (0cs) capacitor according to the present invention will be described with reference to Figs. 6-13. The i-size sheet is suitable for aa household materials (CNS) A4 specifications (21GX 297 public reply) ------- -556238

’柱形（cylindrical)—詞電極，具有籠統的圓形 ’而非表示任何以純數器製造方法，如熟諳此藝者所理解在此用以表示一特殊型式的電容器、橢圓或橢圓側壁（可作成傾斜的）學觀念定義的精確幾何形狀。 ;然後如所示’在姓刻停止層12〇上連續地形成下及上模層 130及 135 〇百先參照至圖6，藉由習用製程，在一基板（未示）上形成一夾層絕緣層削及-接觸插頭__深度延伸入層1〇〇的表面内；然後在層嶋插頭155上形成一姓刻停止層12〇在姓刻4丁止層120上形成的上下模絕緣層135及13〇的後續蝕刻（稍後說明）期間，蝕刻停止層12〇係作為蝕刻障壁層，' 因此選擇蝕刻停止層120的材料要考量上下模絕緣層135及 130的#刻特性。僅以_例說明’如果上下模絕緣層⑴及 130為氧化層，則蝕刻停止層12〇可由厚度1〇〇_5⑼入的氮化矽形成。上下模絕緣層135及130構成一雙層，將蝕刻成一雙模以製造下電容器電極，形成下模絕緣層13〇的材料比上模絕緣層135的材料顯示更大的濕蝕比。矣巴緣材料的濕蝕比受植入其中的摻雜物濃度影響，劑量越大’濕餘比越高。因此，為達到上述不同的濕蝕比，下換絕緣層130可由掺雜絕緣層形成，而上模絕緣層135則由未摻雜（或較少摻雜）絕緣層形成。下模絕緣層130最好以化學氣體沈積（CVD)由摻雜氧化層形成，合適的摻雜氧化層包括硼磷矽酸鹽玻璃（BPSG)及磷 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐） 556238 五、發明説明（7 ) 矽酸鹽玻璃（PSG)。上模絕緣層135最好以電漿增強化學氣體沈積（CVD)由未摻雜氧化層形成，合適的未摻雜氧化層包括電聚增強四乙正矽酸鹽（PE_丁E〇s)層、高密度電聚⑽p) 氧化層及P-SiH4氧化層。下模絕緣層130的高度H1及上模絕緣層135的高度抝，係根據將製造的儲存電極的目標高度及上下模絕緣層出及 U0㈣刻特性而判定。尤其是下模絕緣層⑽的高度出的判定’應使其中將形成的開口能顯示上下最大直徑(稍後說明），例士口 ’下模絕緣層13〇抑觸層形成且所製成的儲存電極為L6Mm(或更大）時，下模絕緣層13〇的高度出最好在 0.5-0.6叫的範圍内’而上模絕緣層135的高度H2則在丄μ 4 範圍内。下模絕緣層職高度m及上模絕緣層出的南細’會依絕緣層所用的材料及所製成的儲存電極的目標兩度而有所不同。沈積下模絕緣層130之後，及沈積上模絕緣層⑴之前，視^可對下模絕緣層13G進行退火及/或表面清除製程。意即可藉由退火而控制下模絕緣層130的濕姓比，更特別地，為增加㈣比而在下模絕緣層_人離子，常 Ϊ Π匕I加太多，植入離子後有效地使用退火而更精確地降低濕I虫比，如士 _啦此來，植入後進行退火為微調渴蝕比的有效機制。例如，當下模絕緣層13。係由換雜糊及：:）層形成’以重量計…各為2-3%漢度時，最二）火使濕蝕比降低·叉一七二丄取灯足的_形成，以’重量;農二十濃度未大於5❶/❶時，下模絕緣層130 I________ _ k 巧張尺奴財晴 12- B7 8 五、發明説明（則無需退火。退火本身係在避免下模絕緣層13〇龜裂的溫度範圍内執行 ’溫度最好低於蝕刻停止層120的沈積溫度，例如，當蝕刻停止層120以氮化矽層形成時，最好以小於7〇〇t的溫度將下模絕緣層130退火。退火之後，亦可將下模絕緣層13〇進行表面清除製程，例如’下模絕緣層130及上模絕緣層135並非在原地形成，則形成下模絕緣層130及形成上模絕緣層135已經過一段可觀的時間，此情形下，水份會由植入下模絕緣層13〇的摻雜物吸收’因此在下模絕緣層130表面形成非晶系瑕疵層，此非晶系瑕蔽層可呈現大於其餘下模絕緣層13〇的濕蝕比。因此，最好在退火或沈積下模絕緣層13〇後，執行表面清除以移除非晶系瑕疵層；為達成此目的可使用硫酸溶劑。如一開始即避免形成非晶系瑕疵層（即在原地形成下模絕緣層130及上模絕緣層135)，或在沈積上模絕緣層135之前 ’完全未（或只一小段期間）將下模絕緣層130曝露在空氣中則可省略移除非晶系瑕疵層的清除過程。接下來’參照至圖7，使用一罩幕（未示）連續乾蚀上模絕緣層135、下模絕緣層13〇及蝕刻停止層12〇 ,以形成一開口 140 ’可使用CFX氣體（如C4f4*C3F8氣體）執行乾蝕。乾蝕的製程限制造成開口將由斜（非垂直）側壁（相對於夾層絕緣層100)而界定’換言之，開口向外以一高度方向逐漸變細 ’而使開口直徑係頂部大於底部。兹參照至圖8 ’執行一選擇性濕蝕以完成雙模138的形成 _ -13- 本紙張尺度適用中國國家標準(CNS) A4‘格(21〇X297&^)----- 五、發明説明（9 ) ’由於下絕緣模UG由難比大於上絕緣模135的材料形成，由濕蝕移除的下絕緣模13〇會多於上絕緣模135，如此一來如所不，在雙模138中界定一花瓶狀開口 14〇，。雖然只稍微蝕刻上絕緣模135，但此稍微蝕刻有利地作為形成儲存電極（猶後說明）之前的預先清除，最好按次序使用sci (NH4〇H/H2〇2/去離子水）及氫氟酸（HF)執行濕蝕。執行濕蝕有條件限制，即須在開口 14〇，内達成某些設計好的尺寸’在此稱為關鍵尺寸A、B、c、〇及£。如圖8所不，A為上絕緣模135的開口 14〇，的最大宽度（或直徑）；b為上絕緣模135的開口 140,的最小寬度(或直徑）；〔為下絕緣請的開口⑽的最大寬度（或直徑）；d為下絕緣_的開口刚’的最小寬度（或直徑）；㈣為開口⑽，底部姓刻停止層竭曝露量。舉例而言，開口 14〇，的關鍵尺寸C最好等於或小於關鍵尺寸A，此外，關鍵尺寸E最好在後續則虫過程_說明)中，於移除雙模138期間足以防止入夾層絕緣層中。 ^ 度的儲存電極，開 nm，而蝕刻停止層例如，為形成具有1 ·ό μηι(或更大）高口 140’的下關鍵尺寸d最好不少於145 120的曝露長度Ε不少於15 nm。兵他影響雙模138濕蝕條件雜物濃度（即材料的姓刻比），及濕蝕時間u 參照至圖9，順著雙模138的側壁、底部及頂電層150，導電層150界定一下電極，且可由一夕:成 -摻雜多晶矽層形成，導電層i 夕曰曰矽月 _____ -14- I紙張尺度適财a ®家標準(CNS) A4規格(21GX 297公g 14_子度F可介於㈣ 556238 五、發明説明（1〇 ’如果儲存電極具有1>6卿（或更大）的高度，則厚度F大約為 45 nm 〇接下來，如圖10所示，在使用流動性好的材料（如BPSG 、PSG或未摻雜㈣鹽玻璃_))的結果結構的整個表面沈積、，、邑緣層160，以填補開口 14〇，。然後，如圖u所示，藉由化干機械式研磨法（CMp)或乾#回，將絕緣層⑽及導電層150作部分移除，直到露出雙模138的頂部為止。接下來，如圖12A所示，使用姓刻劑將雙模138及絕緣層 160移除’而使各單元形成一具有單柱體堆疊結構的儲存電極150,在移除雙模138時，最好使用册及簡㈣混合物作為移除1虫刻劑。此處由於導電層150重疊餘刻停止層12〇, ㈣劑在移除雙模138期間，必須實質移動—段距離以參入央層絕緣層⑽，如此一來，可避免㈣劑的滲透。圖ΐ2β 以SEM像片說明根據本發明較佳實例形成的儲存電極⑼，如所示，並未見到先前製造方法的缺點。接下來，如圖13所示，形成一介電層17〇以覆蓋儲存電極 150 ’並由習肖t程形成一上電極18〇以得到一 $整的電容裔。’I電層170可為一氮氧（N〇)層，但亦可使用具夠大介電常數（k)的其他材料。再參照至圖12A，儲存電極150與接觸插頭115接觸，並具有類似花瓶的單柱體結構。特別地，儲存電極的柱形壁由在A與B之間延伸的上柱形壁部分、在之間延伸的下柱形壁部分及在B#C之間延伸的中柱形壁部分所界定。距離底部壁表面越遠，上柱形壁部分的直徑及下柱形壁部分本纸張尺度適财B a家標準(CNS) A4規格(21GX297公 -15- 556238 五、發明説明（11 ) 的直徑則越增加（向外變細），而中柱形壁部分的直徑則距離底部壁表面越遠越減少（向内變細）。根據本發明較佳實例’在配置儲存電極150時，會建立以下的關係：'Cylindrical'-the word electrode, with a general round shape, rather than any method of making a pure number, as understood by those skilled in the art, is used here to mean a special type of capacitor, ellipse or elliptical sidewall (may be Create precise geometric shapes as defined by the scientific concept. Then, as shown, 'the lower and upper mold layers 130 and 135 are successively formed on the last stop layer 120. Referring to FIG. 6, a conventional process is used to form a sandwich insulation on a substrate (not shown). The layer-cutting and -contact plug __ deeply extend into the surface of the layer 100; then, a layer 131 stop layer 12 is formed on the layer 155 plug 155 and an upper and lower mold insulating layer 135 is formed on the layer 120 During subsequent etching (described later) of 13 °, the etch stop layer 120 is used as an etching barrier layer. Therefore, when selecting the material of the etch stop layer 120, the #etching characteristics of the upper and lower mold insulating layers 135 and 130 must be considered. It will be described by way of example only. If the upper and lower mold insulating layers ⑴ and 130 are oxide layers, the etch stop layer 120 may be formed of silicon nitride with a thickness of 100-5. The upper and lower mold insulating layers 135 and 130 constitute a double layer, which will be etched into a double mold to manufacture the lower capacitor electrode. The material forming the lower mold insulating layer 13o shows a larger wet-etching ratio than the material of the upper mold insulating layer 135. The wet erosion ratio of the sampan marginal material is affected by the concentration of the dopants implanted in it. The larger the dose, the higher the wet residual ratio. Therefore, in order to achieve the above-mentioned different wet etching ratios, the replacement insulating layer 130 may be formed of a doped insulating layer, and the upper mold insulating layer 135 is formed of an undoped (or less doped) insulating layer. The lower mold insulating layer 130 is preferably formed of a doped oxide layer by chemical gas deposition (CVD). Suitable doped oxide layers include borophosphosilicate glass (BPSG) and phosphorus-11. CNS) A4 specification (210X297 mm) 556238 5. Description of the invention (7) Silicate glass (PSG). The upper mold insulating layer 135 is preferably formed of an undoped oxide layer by plasma-enhanced chemical gas deposition (CVD). Suitable undoped oxide layers include electropolymer-enhanced tetraethylorthosilicate (PE_Buteos). Layer, high-density electrodeposited p) oxide layer and P-SiH4 oxide layer. The height H1 of the lower mold insulating layer 130 and the height of the upper mold insulating layer 135 are determined based on the target height of the storage electrode to be manufactured, the upper and lower mold insulating layers, and U0 engraving characteristics. In particular, the judgement of the height of the lower mold insulating layer 应 should be such that the opening to be formed can show the maximum diameter up and down (explained later). When the storage electrode is L6Mm (or larger), the height of the lower mold insulating layer 13 is preferably in the range of 0.5-0.6, and the height H2 of the upper mold insulating layer 135 is in the range of 丄 μ4. The height m of the insulating layer of the lower mold and the thickness of the upper layer of the insulating layer of the upper mold will be different depending on the material used for the insulating layer and the target of the storage electrode made twice. After the lower mold insulating layer 130 is deposited and before the upper mold insulating layer is deposited, the lower mold insulating layer 13G may be subjected to an annealing and / or surface cleaning process, as appropriate. That is to say, the wet lasting ratio of the lower mold insulating layer 130 can be controlled by annealing. More specifically, in order to increase the ratio, the lower mold insulating layer_human ion is added too much, which is effectively used after implanting ions. Annealing to more accurately reduce the wet I-worm ratio. For example, annealing after implantation is an effective mechanism for fine-tuning the thirst erosion ratio. For example, the current mold insulating layer 13. It is formed by changing the miscellaneous paste and: :) The layers are formed 'by weight ... when each is 2-3% Han degrees, the second is) the fire reduces the wet erosion ratio. Weight; when the concentration of Nongji is not more than 5❶ / ❶, the lower mold insulation layer 130 I________ _ k Qiao Zhang Nu Nu Caiqing 12- B7 8 V. Description of the invention (There is no need for annealing. The annealing itself is to avoid the lower mold insulation layer 13 〇 The temperature within the cracking temperature range is preferably lower than the deposition temperature of the etch stop layer 120. For example, when the etch stop layer 120 is formed of a silicon nitride layer, it is preferable to lower the lower mold at a temperature of less than 700 t. The insulating layer 130 is annealed. After annealing, the lower mold insulating layer 130 can also be subjected to a surface cleaning process, for example, 'the lower mold insulating layer 130 and the upper mold insulating layer 135 are not formed in place, then the lower mold insulating layer 130 is formed and the upper layer is formed. A considerable amount of time has passed in the mold insulating layer 135. In this case, moisture will be absorbed by the dopants implanted in the lower mold insulating layer 130. Therefore, an amorphous defect layer is formed on the surface of the lower mold insulating layer 130. This amorphous The imperfect layer can exhibit a wet erosion ratio larger than that of the remaining lower mold insulating layer 13 Therefore, it is best to perform surface cleaning to remove the amorphous defect layer after annealing or depositing the lower mold insulating layer 13; for this purpose, a sulfuric acid solvent can be used. Avoid the formation of the amorphous defect layer (ie in the original The lower mold insulating layer 130 and the upper mold insulating layer 135) are formed on the ground, or before the upper mold insulating layer 135 is deposited, the lower mold insulating layer 130 is completely (or only for a short period of time) exposed to the air, and the removal of non- Removal process of the crystal defect layer. Next, referring to FIG. 7, a mask (not shown) is used to continuously dry-etch the upper mold insulating layer 135, the lower mold insulating layer 13 and the etch stop layer 12 to form an opening. 140 'CFX gas (such as C4f4 * C3F8 gas) can be used to perform dry etching. The process limitation of dry etching causes the opening to be defined by oblique (non-vertical) sidewalls (relative to the sandwich insulation layer 100)' In other words, the opening is outward with a height The direction is gradually tapered 'so that the diameter of the opening is larger at the top than at the bottom. Refer to Figure 8' Perform a selective wet etch to complete the formation of the dual mold 138_ -13- This paper size applies to China National Standard (CNS) A4 ' (21〇X 297 & ^) ----- V. Description of the invention (9) 'Since the lower insulating mold UG is formed of a material that is harder than the upper insulating mold 135, the lower insulating mold 13 removed by wet etching will be more than the upper insulating The mold 135, as it does, defines a vase-like opening 14 in the dual mold 138. Although the insulating mold 135 is only slightly etched, this slight etching is advantageously used as a pre-formation for the storage electrode (described later). Clear in advance, it is best to use sci (NH4〇H / H2〇2 / deionized water) and hydrofluoric acid (HF) in order to perform wet etching. Wet etching is conditionally limited, that is, a certain amount of These designed dimensions are referred to herein as critical dimensions A, B, c, 0 and £. As shown in Fig. 8, A is the maximum width (or diameter) of the opening 14o of the upper insulating mold 135; b is the minimum width (or diameter) of the opening 140, of the upper insulating mold 135; [the opening for the lower insulation please ⑽ is the maximum width (or diameter) of ⑽; d is the minimum width (or diameter) of the opening of the lower insulation _; ㈣ is the opening ⑽, and the bottom is engraved with the stop-exposure exposure. For example, the critical dimension C of the opening 14 is preferably equal to or smaller than the critical dimension A. In addition, the critical dimension E is preferably in the subsequent process (description), which is sufficient to prevent interlayer insulation during the removal of the dual mold 138. Layer. Storage electrode, in nm, and the etch stop layer, for example, in order to form a lower critical dimension d having a high opening 140 ′ of 1 μm (or greater), it is preferable that the exposure length E is not less than 145 120 15 nm. He influences the impurity concentration of the dual-mode 138 wet-etching conditions (that is, the material-to-cut ratio), and the wet-etching time u Refer to FIG. 9, along the side wall, the bottom and the top electrical layer 150 of the dual-mode 138, the conductive layer 150 is defined The lower electrode can be formed overnight: doped-doped polycrystalline silicon layer, and the conductive layer is a silicon layer _____ -14- I paper size suitable for a standard (CNS) A4 specification (21GX 297 g 14_ The sub-degree F can be between ㈣ 556238 and 5. Description of the invention (10) If the storage electrode has a height of 1 > 6 mm (or greater), the thickness F is about 45 nm. Next, as shown in FIG. 10, Using a flowable material (such as BPSG, PSG, or undoped osmium salt glass)), the entire structure of the structure is deposited on the entire surface of the structure 160, to fill the opening 14. Then, as shown in Figure u Using the dry mechanical grinding method (CMp) or dry back, the insulating layer 导电 and the conductive layer 150 are partially removed until the top of the dual mold 138 is exposed. Next, as shown in FIG. 12A, the last name is used. The etchant removes the dual mold 138 and the insulating layer 160, so that each unit forms a storage electrode 150 having a single pillar stack structure. When removing the dual-mode 138, it is best to use a mixture of album and simplification as an insecticide. Here, since the conductive layer 150 overlaps the rest stop layer 12o, the tincture must be substantially moved during the removal of the dual-mode 138. -A distance is used to enter the central insulating layer ⑽. In this way, the penetration of the elixir can be avoided. Figure 以 2β illustrates the storage electrode 形成 formed according to the preferred embodiment of the present invention with an SEM image. As shown, no visible Disadvantages of the previous manufacturing method. Next, as shown in FIG. 13, a dielectric layer 170 is formed to cover the storage electrode 150 ′, and an upper electrode 180 is formed by the Xi process to obtain a whole capacitor. The I electric layer 170 may be a nitrogen oxide (NO) layer, but other materials having a large dielectric constant (k) may be used. Referring to FIG. 12A again, the storage electrode 150 is in contact with the contact plug 115 and has a similar structure. The single cylindrical structure of the vase. In particular, the cylindrical wall of the storage electrode is composed of an upper cylindrical wall portion extending between A and B, a lower cylindrical wall portion extending between, and B # C It is defined by the middle cylindrical wall portion. The further away from the bottom wall surface, the straighter the upper cylindrical wall portion is. And the lower column-shaped wall portion of this paper is suitable for the standard of B home standard (CNS) A4 specifications (21GX297 public -15-556238) V. Description of the invention (11) the diameter increases (thinner), and the center column The diameter of the shaped wall portion decreases as it gets farther from the bottom wall surface (thinner). According to the preferred embodiment of the present invention, when the storage electrode 150 is configured, the following relationship is established:

A g C，C > β，及 c > D 其中Α係上柱形壁部分距離底部壁表面最遠位置之直徑， B係上柱形壁部分距離底部壁表面最近位置之直徑，c係下柱形壁部分距離底部壁表面最遠位置之直徑，而D係下柱形壁部分在底部壁之直徑。則述尺寸的要求防止鄰近儲存電極間的橋接，且能在製造儲存電極期間，藉由僅測量儲存電極頂部外徑的關鍵Z 寸A，即可線上監控儲存電極底部外徑的關鍵尺寸◦。圖14况明如果儲存電極15〇的關鍵尺寸c，大於關鍵尺寸 A ’則會發生橋接的情形，而且，即使在鄰近儲存電極間未實際發生橋接’除非設定C，小於或等於A，，不然無法確保足夠的處理邊際。根據本發明的ocs電容器特性，及製造OCS電容器中施加的多種處理參數係經由以下說明的實驗範例加以判定，應2下列實驗範例中出現的數值，會根據將製造的健存電容器的目標高度及電容而有所不同。實驗範例1 方:二用用單模製造的電容器特性，與根據本發明务使用雙模製造的電容器特性，作一比較。除了本發明係以〇.5μηι厚度的BPSg 厚度的PE-職層作為上模以形成雙模=及^ ^ 而習用方法則由 _____ - I。本紙張尺度適用中g g *標準(CNS) 4视格(咖〉〈297公着) 16- 556238 五、發明説明（12 ) 單- 1.7叫厚度的PE_TE〇s層形成單模外，係在相同條件下使用該兩種方法’製造具有16吨（或更大）儲存電容器。參照至圖15」使用單模製造的電容器各單元中大約顯示元用雙 15個雙位疋破壞’是本發明使用雙模製造的電容器（各單中=造成5個雙位元破壞）中的三倍，證明根據本發明使雙模的電容器製造方法’可在形成的單元中明顯地減少位元破壞。存所法使〃對習用方法及根據本發明方法所製造的電容器測量儲即點電容Cs，如圖16所示’各單元中，根據本發明方法製造的電容器的儲存節點電容Cs約為15作，大於習用方所製造的電容器的儲存節點電容Cs。原因是根據本發明r 用雙模的方法所形成的儲存電極，較習用方法使用單模戶）形成者，具有更大的底面積。實驗範例2 ^用由習时法使料模所製造具有14_高 μ】 =電容器’與根據本發明方法使用雙模所製造具有μ ::存的電“ ’調查位元瑕疵與充電(更新)時間的關係。如圖Π所示，根據本發明方法所形成同單位元瑕疵位準上，頬干f ^n±Ba 在相帝― 更新時間比習用方法所形成的A g C, C > β, and c > D where A is the diameter of the upper cylindrical wall portion furthest from the bottom wall surface, B is the diameter of the upper cylindrical wall portion closest to the bottom wall surface, c is The diameter of the lower cylindrical wall portion farthest from the surface of the bottom wall, and D is the diameter of the lower cylindrical wall portion at the bottom wall. Then the size requirements prevent bridges between adjacent storage electrodes, and during the manufacturing of the storage electrodes, the critical dimensions of the outer diameter at the bottom of the storage electrode can be monitored online by measuring only the key Z inch A of the outer diameter at the top of the storage electrode. Figure 14 shows that if the critical dimension c of the storage electrode 15 is larger than the critical dimension A ', bridging will occur, and even if no bridging actually occurs between adjacent storage electrodes, unless C is set to be less than or equal to A, otherwise Unable to ensure adequate processing margins. According to the characteristics of the OCs capacitor of the present invention and the various processing parameters applied in the manufacture of OCS capacitors, they are determined through the experimental examples described below. The values appearing in the following experimental examples will be based on the target height of the surviving capacitors to be manufactured and Capacitance varies. Experimental Example 1 Fang: The characteristics of a capacitor manufactured using a single mode are compared with the characteristics of a capacitor manufactured using a dual mode according to the present invention. Except that in the present invention, a PE-layer with a thickness of 0.5 μm and a thickness of BPSg is used as the upper mold to form a dual mold = and ^ ^, and the conventional method consists of _____-I. This paper is applicable to gg * standard (CNS) 4 visual grid (Ca> <297) 16- 556238 V. Description of the invention (12) Single-1.7 PE_TE0s layer with a thickness of 1 forms a single mode, and is in the same mode These two methods are used under conditions to manufacture a storage capacitor with 16 tons (or more). "Refer to Fig. 15" In each unit of a capacitor manufactured using a single-mode capacitor, approximately 15 double-bit 疋 failures are shown in each unit of the capacitor. Three-fold proves that the method of making a dual-mode capacitor according to the present invention can significantly reduce bit destruction in the formed cell. The storage method uses the conventional method and the capacitor manufactured according to the present invention to measure the storage point capacitance Cs. As shown in FIG. 16 'in each unit, the storage node capacitance Cs of the capacitor manufactured according to the present method is about 15 Is larger than the storage node capacitance Cs of the capacitor manufactured by the customer. The reason is that the storage electrode formed by the dual-mode method according to the present invention has a larger bottom area than the conventional method using a single-mode user. Experimental example 2 ^ 14_high μ manufactured by using the conventional method to make the material mold] = capacitor 'and μ :: stored electricity manufactured by using the dual mode according to the method of the present invention' 'Investigate bit defects and charging (update ) The relationship between time. As shown in Figure Π, at the same unit element defect level formed according to the method of the present invention, the f ^ n ± Ba is formed by the relative emperor-update time than the conventional method

電谷窃增加。根據本發明的各 A 現象。早70中各多出電容造成此實驗範例3 為根據本發明的電容器製谷杰Ik方法，筛選合適的絕緣材料本紙張尺_家標準(⑽）A4規格 556238 A7 B7 五、發明説明（13 ) 層用於雙模的下模，各別以一 P-SiH4層及一摻雜BPSG層形成下模，以PE-TEOS層形成上模。測量由各別雙模形成的儲存電極、開口頂部外徑的關鍵尺寸A、第二彎曲點外徑的關鍵尺寸C，及底部外徑的關鍵尺寸D，結果如表一所示0 表1 材料頂部外徑的關第二彎曲點外徑的底部外徑的關底部至頂部(D:A) 鍵尺寸A(nm) 關鍵尺寸C(nm) 鍵尺寸D(nm) 開口比率(％) P-SiH4 215 170 109 51 BPSG 205 192 149 73 如表1所示，根據本發明電容器的製造中所使用的雙模，摻雜絕緣層適合作為下模的材料層。實驗範例4 為決定下模絕緣層的適當摻雜物濃度，在相同條件下根據本發明方法製造儲存電極，但BPSG下模層中的摻雜物、硼及磷的濃度不同，然後在各別電容器測量開口頂部外徑的關鍵尺寸A、第二彎曲點外徑的關鍵尺寸C，及底部外徑的關鍵尺寸D，結果如表2所示。 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)Electric valley theft increased. A phenomenon according to the present invention. The extra capacitance in the early 70 caused this experimental example. 3 In accordance with the Gu Jie method of capacitor manufacturing of the present invention, a suitable insulating material is selected. This paper ruler_Home standard (⑽) A4 specification 556238 A7 B7 V. Description of the invention (13 ) Layer is used for the lower mold of the dual mode. Each of the P-SiH4 layer and a doped BPSG layer is used to form the lower mold, and the PE-TEOS layer is used to form the upper mold. The storage electrodes formed by the respective dual molds, the critical dimension A of the outer diameter at the top of the opening, the critical dimension C of the outer diameter of the second bending point, and the critical dimension D of the outer diameter at the bottom are shown in Table 1. 0 Table 1 Materials Top outer diameter off Second bending point outer diameter Bottom outer diameter off Bottom to top (D: A) Key size A (nm) Key size C (nm) Key size D (nm) Opening ratio (%) P- SiH4 215 170 109 51 BPSG 205 192 149 73 As shown in Table 1, according to the dual mode used in the manufacture of the capacitor of the present invention, the doped insulating layer is suitable as the material layer of the lower mold. Experimental Example 4 In order to determine the proper dopant concentration of the lower mold insulating layer, the storage electrode was manufactured according to the method of the present invention under the same conditions, but the concentrations of dopants, boron and phosphorus in the lower mold layer of BPSG were different, and then The capacitor measures the critical dimension A of the outer diameter at the top of the opening, the critical dimension C of the outer diameter of the second bending point, and the critical dimension D of the outer diameter at the bottom. The results are shown in Table 2. -18- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

裝訂 % 556238 BPSG層中B及P 的濃度(重量百分比）頂部外徑的關鍵尺寸 A(nm) 底部外徑的關鍵尺寸 D(nm) 中間至頂部(C:A)開底部至頂部(D:A)開丄主一一---———— ---二_ a、1所不，當下模絕緣層的BPSG層中的濃度增加時’顯示儲存電極由於濕蝕比增加，在底部及第二彎曲點裝Binding% 556238 Concentrations of B and P in BPSG layer (percent by weight) Critical dimension of top outer diameter A (nm) Critical dimension of bottom outer diameter D (nm) Middle to top (C: A) Open bottom to top (D: A) Kailuo main one ----------- --- two_ a, 1 No, when the concentration in the BPSG layer of the lower mold insulation layer increases, 'storage electrode' Second bending point

外，的關鍵尺寸DM皆增加。由35重量百分比的MW 重量百分比的P所形成的健存電極，其第二脊曲點外徑關訂鍵尺寸C大於頂部外徑的關鍵尺寸A，而造成謝。的中間開口比率。 f 此外’由於形㈣存電極之前的㈣製程同時亦作為預先/月除製’下模絕緣層的高蝕刻比確保足夠的預先清除效果，因此B及P濃度最好為2-3重量百分比。 “ 實驗範例5 進行實驗以決定下模絕緣層的最優厚度，其中當開口底部外控的關鍵尺寸D最大時，可伴拄 ** 第一曲點外徑的關 2寸不大於開口頂部外徑的關鍵尺寸A。特別地，當 'ϋτ模絕緣層的總厚度維持在17 μ 的厚度在〇·3μ„^〇·5μηι間變動 GTM層 θ网勒對所形成的儲存電極，測 1開口頂部外徑的關鍵尺寸Α、、 I - · 本纸張尺度適财城格(⑽㈣7公爱y 19乐一豸曲點外徑的關鍵尺 556238 五、 A7 ____B7 發明説明（15 ) 寸C ’及開π底部外徑的關鍵尺寸D，結果如表3所示表3 BPSG 層厚度(μηι) 頂部外徑的關鍵尺寸A(nm) 第二彎曲點外徑的關鍵尺寸 C(nm) 底部外徑的關鍵尺寸D(nm) 底部至頂部 (D:A)開口比率 (%) 0.3 217 164 138 64 0.5 207 198 163 79 如表3所示，厚度為0.3 pm的BPSG層，其底部開口比率 (D · A)及儲存電極的第二彎曲點外徑的關鍵尺寸◦,皆大於厚度為0.5 μηι的BPSG層者。使用具有1 ·9 μιη雙模厚度的雙模製造另外的儲存電極，但各以〇·5 μηι、0.6 μηι、0.7 μηι及0.8 μηι等不同厚度的BPSG下模層’測量各別儲存電極在開口頂部外徑的關鍵尺寸A、第二彎曲點外徑的關鍵尺寸C，及開口底部外徑的關鍵尺寸D ’結果如表4所示。表4 BPSG層的厚度(μηι) 頂部外徑的關鍵尺寸 A(nm) 第二彎曲點外徑的關鍵尺寸C(nm) 底部外徑的關鍵尺寸 D(nm) 中間開口 (C:A) 比率(％) 底部開口 (d:a)比率(％) 0.5 243 206 183 85 75 0.6 248 216 176 87 71 0.7 235 221 188 94 80 0.8 243 233 186 96 77 如表4所示，即使BPSG層的厚度增加至〇·5 μηι以上，雖然第二彎曲點外徑的關鍵尺寸C顯著改變，但底部開口比率 -20- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐) 556238 A7 B7 五、發明説明（16 ) 率改變極小，因此證明一旦作為下模的BPSG層，其厚度達到特定位準，在儲存電極底部外徑的關鍵尺寸D實質上不會受到BPSG層厚度增加的影響。因此，當下模絕緣層由 BPSG層形成時，BPSG層的厚度最好在0.5-0.6 μηι的範圍内。實驗範例6 在各別的氮化矽層上形成BPSG層，然後各別在650°C退火60分鐘及在750°C退火10分鐘，以決定形成BPSG下模層之後將執行的最優退火溫度。以750°C(大於形成氮化矽層的沈積溫度）退火之後，可在BPSG層見到許多裂縫，因此證明執行退火的溫度應低於氮化矽層的沈積溫度。實驗範例7 將BPSG下模絕緣層退火之後，不先清除BPSG層表面以移除表面瑕疵，即在BPSG層上形成上模絕緣層，然後根據本發明使用雙模形成儲存電極，然後以電子掃描顯微鏡 (SEM)觀察。結果，如圖18及19所示，在儲存電極的上下模絕緣層間的介面見到受環圈束缚的鄰近儲存電極（所謂的翼狀瑕疯（wing defects))。此類翼狀瑕疵為雙位元破壞的成因，且被認定在前述 BPSG層上形成具高蝕刻比的非晶系瑕疵層所造成，為移除這些瑕疵，形成BPSG下模絕緣層之後接著在表五所示條件下進行瑕疵層的移除，使用硫酸溶劑以執行移除瑕疵層的過程。 -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）In addition, the key dimensions DM are increased. For a surviving electrode formed by 35 weight percent of MW weight percent of P, the outer diameter of the second ridge curvature of the key is larger than the key dimension A of the outer diameter of the top, which is a cause of gratitude. The middle opening ratio. f In addition, the high etching ratio of the lower insulating layer of the lower mold insulation layer also ensures sufficient pre-cleaning effect because the fabrication process before forming the electrode is also used as a pre / month removal. Therefore, the concentration of B and P is preferably 2-3% by weight. "Experimental Example 5 Experiments are performed to determine the optimal thickness of the lower mold insulation layer. When the critical dimension D of the external control at the bottom of the opening is the largest, it can be accompanied by **. The critical dimension of the diameter A. In particular, when the total thickness of the ϋτ mode insulating layer is maintained at 17 μ, the thickness varies between 0.3 μm and 5 μm, and the GTM layer is θ meshed against the formed storage electrode, and 1 opening is measured. The key dimensions of the outer diameter of the top A,, I-· The paper size is suitable for the financial city (⑽㈣7 公爱 y 19, a key point of the outer diameter of the bending point 556238 V, A7 ____B7 Description of the invention (15) inch C 'and Open the key dimension D of the outer diameter at the bottom. The results are shown in Table 3. Table 3 BPSG layer thickness (μηι) Key dimension of the top outer diameter A (nm) Key dimension of the outer diameter of the second bending point C (nm) Bottom outer diameter Key dimension D (nm) bottom to top (D: A) opening ratio (%) 0.3 217 164 138 64 0.5 207 198 163 79 As shown in Table 3, the thickness of the BPSG layer with a thickness of 0.3 pm, the bottom opening ratio (D A) and the critical dimension of the outer diameter of the second bending point of the storage electrode, which are all larger than the BPSG with a thickness of 0.5 μηι Additional storage electrodes were made using a dual mold with a thickness of 1.9 μm dual mold, but each BPSG lower mold layer with different thicknesses, such as 0.5 μm, 0.6 μm, 0.7 μm, and 0.8 μm, was used to measure each storage. The critical dimension A of the outer diameter of the electrode at the top of the opening, the critical dimension C of the outer diameter of the second bending point, and the critical dimension D 'of the outer diameter of the bottom of the opening are shown in Table 4. Table 4 Thickness of the BPSG layer (μηι) Outside the top Critical dimension A (nm) Critical dimension of the outer diameter of the second bending point C (nm) Critical dimension of the bottom outer diameter D (nm) Middle opening (C: A) ratio (%) Bottom opening (d: a) ratio (%) 0.5 243 206 183 85 75 0.6 248 216 176 87 71 0.7 235 221 188 94 80 0.8 243 233 186 96 77 As shown in Table 4, even if the thickness of the BPSG layer is increased to 0.5 μm or more, although the second bend The critical dimension C of the point outer diameter changes significantly, but the bottom opening ratio is -20- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 556238 A7 B7 V. Description of the invention (16) The rate change is extremely small, Therefore, it proves that once the BPSG layer as the lower mold, its thickness reaches a special Level, not substantially affected by the increase in the thickness of the BPSG layer critical dimension D of the outside diameter of the reservoir electrode. Therefore, when the lower mold insulating layer is formed of a BPSG layer, the thickness of the BPSG layer is preferably in the range of 0.5-0.6 μm. Experimental Example 6 BPSG layers were formed on respective silicon nitride layers, and then annealed at 650 ° C for 60 minutes and 750 ° C for 10 minutes to determine the optimal annealing temperature to be performed after forming the BPSG lower mold layer. . After annealing at 750 ° C (greater than the deposition temperature at which the silicon nitride layer is formed), many cracks can be seen in the BPSG layer. Therefore, it is proved that the annealing temperature should be lower than the deposition temperature of the silicon nitride layer. Experimental Example 7 After annealing the BPSG lower mold insulating layer, the surface of the BPSG layer is not removed to remove surface defects, that is, an upper mold insulating layer is formed on the BPSG layer, and then a storage electrode is formed using a dual mold according to the present invention, and then scanned by electrons Microscope (SEM) observation. As a result, as shown in Figs. 18 and 19, adjacent storage electrodes (so-called wing defects) bound by a ring were seen at the interface between the upper and lower mold insulating layers of the storage electrode. Such wing-like defects are the cause of double-bit destruction and are believed to be caused by the formation of an amorphous defect layer with a high etching ratio on the aforementioned BPSG layer. In order to remove these defects, a BPSG undermold insulation layer is formed followed by The defective layer is removed under the conditions shown in Table 5. A sulfuric acid solvent is used to perform the process of removing the defective layer. -21-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

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.線 556238 A7 B7 五、發明説明（π ) 表5 樣本清除之前的中止時間(小時）清除之後的中止時間(小時）翼狀瑕疵 1 18 0 無 2 24 0 無 3 0 8 無 4 0 18 無 5 0 24 無 6 0 48 有如表5所示’即使下模絕緣層在退火之後，在以硫酸溶劑清除之前閒置不處理約24小時，如樣本i及2，可由清除而避免雙位元破壞。同理，如樣本3、4及5，如果以硫酸溶劑清除下模絕緣層24小時内形成上模層，亦可避免雙位元破壞。實驗範例8 在不同條件下（即SCI 5分鐘/HF 90秒、SCI 7分鐘/HF 90秒，及SCI 10分鐘/HF 90秒）進行上下模絕緣層的濕蝕，測量各別儲存電極的下關鍵尺寸D及底部開口比率（D ·· A )，结果如圖20所示。如圖20所示，當濕蝕時間增加，則在底部外徑的關鍵尺寸D及儲存電極的底部開^比率（〇 : a )皆增加，因此可藉由調整濕蝕時間而適當控制儲存電極在底部外徑的關鍵尺寸D。根據本發明使用雙模製造單柱體堆疊（〇cs)電容器的方法中’在避免雙位元破壞時可增加儲存電極的高度。〇cs電容器的製造方法亦確保在儲存電極的底部有夠大的關鍵尺寸足以滿足電容要求。亦可在線上監控正在製造的儲存電 •22- 本紙張尺度適财a 81家標i (CNS) A4規格(21GX 297公羞) ' -------.Line 556238 A7 B7 V. Description of the invention (π) Table 5 Suspension time before sample removal (hours) Suspension time after removal (hours) Wing defect 1 18 0 No 2 24 0 No 3 0 8 No 4 0 18 No 5 0 24 No 6 0 48 Yes As shown in Table 5, 'Even after the lower mold insulation layer is annealed, it is left untreated for about 24 hours before being cleared with sulfuric acid solvent. Samples i and 2 can be removed to avoid double-bit damage. Similarly, for samples 3, 4 and 5, if the upper mold layer is formed within 24 hours by removing the lower mold insulation layer with sulfuric acid solvent, double-bit damage can also be avoided. Experimental example 8 Under different conditions (ie, SCI 5 minutes / HF 90 seconds, SCI 7 minutes / HF 90 seconds, and SCI 10 minutes / HF 90 seconds), wet etching of the upper and lower mold insulation layers was performed, and the measurement of the respective storage electrodes was measured. The critical dimension D and the bottom opening ratio (D ·· A) are shown in Fig. 20. As shown in FIG. 20, when the wet etching time is increased, both the critical dimension D of the bottom outer diameter and the bottom opening ratio (0: a) of the storage electrode are increased. Therefore, the storage electrode can be properly controlled by adjusting the wet etching time. Key dimension D at the bottom outer diameter. In the method for manufacturing a single-cylinder stacked (Ocs) capacitor using a dual mode according to the present invention, the height of the storage electrode can be increased while avoiding double-bit destruction. 〇cs capacitor manufacturing method also ensures that there is a large enough key size at the bottom of the storage electrode to meet the capacitor requirements. It is also possible to monitor the storage electricity being manufactured online. 22- The paper size is suitable for a 81 standard i (CNS) A4 specification (21GX 297 public shame) '-------

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556238 A7 B7 五、發明説明（18 ) j 極，而能防止#刻劑滲入夾層絕緣層，及餘刻劑滲透所產；生的瑕/疵。；雖然本發明以較佳實例加以說明，但較佳實例僅作為說」明用途，熟諳此藝者應了解，不背離本發明的精神及範疇 j f l ，可對所說明的實例加以修改，不可將後附申請專利範圍 | 的範疇理解為侷限在這些實例。丨 Φ 裝 f -23- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)556238 A7 B7 V. Description of the invention (18) J pole, which can prevent #etching agent from penetrating into the interlayer insulation layer, and the remaining flaws produced by penetrating agent. Although the present invention is described with a preferred example, the preferred example is only for illustrative purposes. Those skilled in the art should understand that the illustrated example may be modified without departing from the spirit and scope of the present invention. The scope of the appended patent application | is understood to be limited to these examples.丨 Φ Pack f -23- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims

556238 A8 B8 C8556238 A8 B8 C8

1 · 一種用以製造電容器電極之方法，包括： ▲於夾層絕緣層表面上及—導電插頭表面上形成一餘刻停止層’導電插頭延伸入該夹層絕緣層表面内一深度；於蝕刻V止層上沈積一下模層，及藉由於下模層形成期間在下模層添加摻雜物，及藉由將下模層退火而調整下模層之濕蝕比； ^ 六* T工俱滘f：1 · A method for manufacturing capacitor electrodes, including: ▲ forming a stop layer on the surface of the interlayer insulation layer and-the surface of the conductive plug; the conductive plug extends into the surface of the interlayer insulation layer to a depth; Deposit a mold layer on the stop layer, and adjust the wet etching ratio of the lower mold layer by adding a dopant to the lower mold layer during the formation of the lower mold layer, and by annealing the lower mold layer; ^ 六 * T 工都滘 f :

裝小於調整過之下模層濕蝕比；乾餘上模層、下模層及钱刻停止層，以形成一開[ 其中至少曝露接觸插頭表面之一部分；濕姓上模層及下模層，致使下模層之開口尺寸增力, 並曝露鄰近導電插頭表面之姓刻停止層之表面部分；訂於上及下模層之開口表面、 ^ 蚀刻彳T止層之表面部分導電插頭之曝露表面上沈積一導電材料。 2 ·如申請專利範圍m丨員之方法，尚包括在沈積導電相後移除上及下模層。Install less than the adjusted wet erosion ratio of the lower mold layer; dry the upper mold layer, the lower mold layer, and the engraved stop layer to form an open [where at least a part of the surface of the contact plug is exposed; wet upper mold layer and lower mold layer To increase the size of the opening of the lower mold layer, and expose the surface portion of the engraved stop layer adjacent to the surface of the conductive plug; the opening surfaces of the upper and lower mold layers, and the exposure of the conductive plug on the surface of the etching stopper layer A conductive material is deposited on the surface. 2 · As for the method of applying for the patent scope, it still includes removing the upper and lower mold layers after depositing the conductive phase.

3 ·如申請專利範圍第1 换她产貝之万，去其中由化學氣體沈賴摻雜氧化物形成下模層。 4 ·如申請專利範圍第3項方法 ^貝之万沄其中至少以硼磷矽酸玻璃（BPSG)及磷矽酸鹽玻璃層。）中任-材料形成7 漿增強化學氣以電漿增強四 5 ·如申請專利範圍第1項之方法，其中由電體沈積以非摻雜氧化物形成上模層。 6·如申請專利範圍第1項之方法，其中至少 -24-3 · If the scope of patent application is the first one, change the product produced by her, and remove the lower mold layer by chemical gas deposition doped oxide. 4 · Method 3 of the scope of patent application ^ Beijing's Manufactory includes at least a borophosphosilicate glass (BPSG) and a phosphosilicate glass layer. ) Any-Material formation 7 Plasma-reinforced chemical gas Plasma-reinforced four 5 · The method as described in item 1 of the scope of the patent application, wherein the upper mold layer is formed by electro-deposition with non-doped oxide. 6. The method of claim 1 in the scope of patent application, wherein at least -24-

556238 A8 B8 C8 申请專利範圍乙正石夕酸鹽（PE_TE〇s)、高密度電漿⑴DP)氧 S1H4氧化物中任一材料形成上模層。 7 ·如申明專利範圍第丨項之方法，其中下模層以硼磷矽酸鹽玻璃（BPSG)形成，及其中磷及硼係於該退火之前添加至 BPSG。 8 ·如申呀專利範圍第7項之方法，其中以重量百分比之量添加删，及以Bps(^2-3重量百分比之量添鱗。 9.如申請專利範圍第！項之方法，其中下模層以鱗石夕酸玻离（PSG)形成’及其中磷係於該退火之前添加至。 (U申明專利範圍第9項之方法’其中以少於？犯之5重百分比之量添加碟。 Π:申請專利範圍第Η之方法，尚包括於形成上模層刚，先清除具有調整過濕蝕比之下模層表面。 12. 如申請專利範圍第丨丨項之方法，其中使用h2S〇4以清除模層表面。 13. 如申請專利範圍第1項之方法，其中藉由低邀化學氣沈積將導電層沈積成一多晶矽。 Η.如申請專利範圍第1項之方法，其中使用幻(NH4〇H/H2〇2/去離子水）與HF(氫氟酸）至少其中之一濕蝕上模層及下模層。 ’ 15·如申請專利範圍第！項之方法，具f蝕刻停止層係氮石夕，及以低於700V之溫度執行τ模層之退火。 16.如申請專利範圍第i項之方法，甲導電材料形成柱加鹽裝量之下體化 I _ -25- 本纸張·尺度適用中固國豕標準(CNS) A4規格(210X297公釐） 556238556238 A8 B8 C8 Patent application scope Any material such as ethanoate (PE_TE0s), high density plasma (DP) oxygen S1H4 oxide forms the upper mold layer. 7 · The method as stated in the scope of the patent claim, wherein the lower mold layer is formed of borophosphosilicate glass (BPSG), and the phosphorus and boron systems are added to the BPSG before the annealing. 8 · The method of item 7 of the patent scope, such as adding and deleting by weight percentage, and adding the scale by Bps (^ 2-3 weight percentage. 9. The method of applying patent scope, item !, where The lower mold layer is formed by scaly acid glass ionization (PSG) and its phosphorus is added before the annealing. (U method of claim 9 of the patent scope 'wherein it is added in an amount of less than 5 weight percent of the offense. Π: The method of applying for the scope of patent application No. ，, also includes the step of forming the upper mold layer, and first removing the surface of the mould layer with the adjusted over-wet erosion ratio. 12. For the method of applying scope of patent application 丨丨, which uses h2S〇4 to remove the surface of the mold layer. 13. For example, the method of the scope of the patent application, wherein the conductive layer is deposited into a polycrystalline silicon by low-pressure chemical gas deposition. 如. The method of the scope of the patent application, which uses The upper mold layer and the lower mold layer are wet-etched by at least one of magic (NH4〇H / H2 02 / deionized water) and HF (hydrofluoric acid). '15. If the method of the scope of patent application item No.!, F The etch stop layer is nitrogenstone, and the τ mode layer is annealed at a temperature lower than 700V. 16. According to the method of applying for item i in the scope of patent application, a conductive material is formed into a pillar and added with salt. I _ -25- This paper · size applies to China Solid Standard (CNS) A4 specification (210X297 mm) 556238

電極’其由導電插頭表面延伸之柱形壁及底部壁所界定，其中柱形壁由底部壁向上延伸而離開夾層絕緣層之表面；其中柱形電極之柱形壁由一上柱形壁部分、一下柱形壁部分及位於上下柱形壁部分間之中柱形壁部分所界定；其中距離底部壁表面越遠，上柱形壁部分之直徑及下柱形壁部分之直徑越增加，其中中柱形壁部分之直徑離底部壁表面越遠則越減少，及其中 A - C，C>B，及 C>D 其中A係上柱形壁部分距離底部壁表面最遠位置之直徑，B係上柱形壁部分距離底部壁表面最近位置之直徑，C係下柱形壁部分距離底部壁表面最遠位置之直徑，而D係下柱形壁部分在底部壁之直徑。 17·種製造電容器之方法，包括於夾層絕緣層上形成一下電極，於下電極上形成一介電層，及於介電層上形成一上電極，其中該形成下電極之步驟包括：於夾層絕緣層表面上及一導電插頭表面上形成一蝕刻停止層，該導電插頭延伸入該夾層絕緣層表面内一深度；於蝕刻停止層上沈積一下模層，及藉由於下模層形成期間在下模層添加摻雜物，及藉由將下模層退火而調整下模層之濕蝕比；於下模層表面上沈積一上模層，其中上模層之濕蝕比小於調整過之下模層濕蝕比；乾蝕上模層、下模層及蝕刻停止層，以形成一開The electrode is defined by a cylindrical wall and a bottom wall extending from the surface of the conductive plug, wherein the cylindrical wall extends upward from the bottom wall and leaves the surface of the interlayer insulation layer; wherein the cylindrical wall of the cylindrical electrode is formed by an upper cylindrical wall portion The lower cylindrical wall portion and the cylindrical wall portion defined between the upper and lower cylindrical wall portions; where the further away from the bottom wall surface, the diameter of the upper cylindrical wall portion and the diameter of the lower cylindrical wall portion increase, where The diameter of the middle cylindrical wall portion decreases as it gets farther from the bottom wall surface, and A-C, C &B; and C &D; where A is the diameter of the upper cylindrical wall portion farthest from the bottom wall surface, B The diameter of the upper cylindrical wall portion nearest the bottom wall surface, C is the diameter of the lower cylindrical wall portion furthest from the bottom wall surface, and D is the diameter of the lower cylindrical wall portion at the bottom wall. 17. A method of manufacturing a capacitor, comprising forming a lower electrode on an interlayer insulating layer, forming a dielectric layer on a lower electrode, and forming an upper electrode on the dielectric layer, wherein the step of forming the lower electrode includes: on the interlayer An etch stop layer is formed on the surface of the insulating layer and on the surface of a conductive plug, and the conductive plug extends a depth into the surface of the interlayer insulating layer; a mold layer is deposited on the etch stop layer, and the lower mold layer is formed during the formation of the lower mold layer. Adding dopants, and adjusting the wet etching ratio of the lower mold layer by annealing the lower mold layer; depositing an upper mold layer on the surface of the lower mold layer, wherein the wet etching ratio of the upper mold layer is less than the adjusted lower mold layer Layer wet-etching ratio; dry-etch the upper mold layer, the lower mold layer and the etch stop layer to form an opening

六、申請專利範園其中至少曝露接觸插頭表面之一部分；濕蝕上模層及下模層’致使下模層之開口尺並曝露鄰近導電插頭表面之蚀刻停止層之表面部分曰口及電插碩之曝絡表面上沈積一導電材料。 18:申請專利範圍第17項之方法，其中該形成下電極尚於導電材料上及開口内沈積一絕緣層；移除-部分絕緣層及導電材料，以曝露上模層；及移除絕緣層之殘餘部分及上下模層。 19.如申：專利靶圍第17項之方法，其中由化學氣體沈積摻雜氧化物形成下模層。 2〇·如申請專利範圍第17項之方法，其中至少以㈣石夕酸鹽璃（BPSG)及财酸鹽玻璃（psG)中任_材料形成下模層 21·如申請專利範圍第丨7項之方法，其中由電漿增強化學體沈積以非摻雜氧化物形成上模層。 22. 如申請專利範圍第17項之方法，其中至少以電聚增強一乙正矽酸鹽（PE-TEOS) '高密度電焚（HDp)氧化物與p_SiH 氧化物其中之一形成上模層。 23. 如申請專利範圍第17項之方法，其中下模層以硼磷矽鹽玻璃（BPSG)形成，及其中磷及硼係於該退火之前添至BPSG。 24·如申請專利範圍第23項之方法，其中以即犯之2_3重量分比之量添加硼，及以BPSG22-3重量百分比之量添加 -27- 包以玻氣四酸加百本纸張尺度適用中國國家樣準(CNS) A4規格(210X 297公着) 556238 ABCD 六、申請專利範園 '一~ 填。 25. 如申請專利範圍第17項之方法，其中下模層以磷矽酸鹽玻璃（PSG)形成，及其中填係於該退火之前添加至mg。 26. 如申凊專利範圍第25項之方法，其中以少於pSG之5重量百分比之量添加磷。 27·如申請專利範圍第17項之方法，尚包括於形成上模層之前’先清除具有調整過濕蝕比之下模層表面。 28.如申請專利範圍第27項之方法，其中使用hj%以清除下模層表面。 29·如申請專利範圍第17項之方法，其中藉由低壓化學氣體沈積將導電層沈積成一多晶矽。 30.如申請專利範圍第17項之方法，其中使用sci (NH4〇H/H2〇2/去離子水）與HF(氫氟酸）至少其中之一濕姓上模層及下模層。 31·如申請專利範圍第17項之方法，其中蝕刻停止層係氮化矽，及以低於700°C之溫度執行下模層之退火。 32·如申請專利範圍第18項之方法，其中導電材料形成柱形電極’其由導電插頭表面延伸之柱形側壁及底部壁而界定，其中柱形側壁由底部壁向上延伸而遠離夾層絕緣層之表面；其中柱形電極之柱形側壁由一上柱形壁部分、一下柱形壁部分及位於上下柱形壁部分間之中間柱形側壁部分而界定；其中上柱形壁部分之直徑及下柱形壁部分之直徑越遠 -28-6. The patent application park shall expose at least a part of the surface of the contact plug; wet etching of the upper mold layer and the lower mold layer causes the opening of the lower mold layer and exposes the surface portion of the etch stop layer adjacent to the surface of the conductive plug and the electrical plug A conductive material is deposited on the exposed surface. 18: The method of applying for item 17 of the patent scope, wherein the forming of the lower electrode still deposits an insulating layer on the conductive material and in the opening; removing-part of the insulating layer and conductive material to expose the upper mold layer; and removing the insulating layer Residue and upper and lower mold layers. 19. As claimed: The method of item 17 of the patent, wherein the lower mold layer is formed by depositing a doped oxide with a chemical gas. 2．If the method of the 17th scope of the patent application is applied, at least one of the vermiculite salt glass (BPSG) and the acid salt glass (psG) is used to form the lower mold layer 21 The method of claim 4, wherein the upper mold layer is formed by plasma-enhanced chemical deposition with undoped oxide. 22. The method according to item 17 of the patent application, wherein at least one of electro-enhanced mono-orthosilicate (PE-TEOS) 'high-density electro-chemical (HDp) oxide and p_SiH oxide is used to form an upper mold layer . 23. The method of claim 17 in which the lower mold layer is formed of borophosphosilicate glass (BPSG), and the phosphorus and boron systems are added to the BPSG before the annealing. 24. The method according to item 23 of the scope of patent application, wherein boron is added in an amount of 2 to 3 parts by weight, and BPSG22-3 is added in an amount of -27 to 27-wrapped with hyaluronic acid and 100 papers. The standard is applicable to China National Sample Standard (CNS) A4 specification (210X 297) 556238 ABCD VI. Patent application park '1 ~ Fill in. 25. The method of claim 17 in which the lower mold layer is formed of phosphosilicate glass (PSG), and the filler is added to mg before the annealing. 26. The method of claim 25, wherein phosphorus is added in an amount of less than 5 weight percent of pSG. 27. The method according to item 17 of the scope of patent application, further comprising, before the formation of the upper mold layer, first removing the surface of the lower mold layer having an adjusted wet erosion ratio. 28. The method of claim 27, wherein hj% is used to remove the surface of the lower mold layer. 29. The method according to claim 17 in which the conductive layer is deposited as a polycrystalline silicon by low-pressure chemical gas deposition. 30. The method according to item 17 of the patent application scope, wherein at least one of sci (NH4OH / H2O2 / deionized water) and HF (hydrofluoric acid) is used to wet the upper mold layer and the lower mold layer. 31. The method according to item 17 of the application, wherein the etch stop layer is silicon nitride, and the annealing of the lower mold layer is performed at a temperature lower than 700 ° C. 32. The method of claim 18, wherein the conductive material forms a cylindrical electrode, which is defined by a cylindrical side wall and a bottom wall extending from the surface of the conductive plug, wherein the cylindrical side wall extends upward from the bottom wall and away from the interlayer insulation layer. The surface of the cylindrical electrode is defined by an upper cylindrical wall portion, a lower cylindrical wall portion, and an intermediate cylindrical sidewall portion located between the upper and lower cylindrical wall portions; wherein the diameter of the upper cylindrical wall portion and The farther the diameter of the lower cylindrical wall part is

、申請專利範固離底部壁表面越增加，i i f中間柱形側壁部分之直徑越退離底部壁表面越減少，及其中 A - C，C>B，及 c>D 其中A係上柱形壁部分最遠離底部壁表面之位置輕係上柱形壁部分最靠近底部壁表面之位置之直徑 ’ C係下柱形壁部分最遠離底部壁表面之位置之直徑，而D係下柱形壁部分在底部壁之直徑。二 33·—種電容器，包括·· 具有一表面之夾層絕緣層；一導電插頭，由夾層絕緣層表面延伸一深度；一蝕刻停止層，於絕緣層上延伸並曝露導電插頭； -柱形下電極，由柱形側壁及底部壁界定，該柱形下電極於導電插頭表面及鄰近導電插頭之部分蝕刻停止層上乙伸，其中柱形側壁由底部壁向上延伸而遠離夾層絕緣層表面；一介電層，於柱形下電極上形成；及一上電極，於介電層上形成；其中柱形下電極之柱形側壁由一上柱形壁部分、一下柱形壁部分及位於上及下柱形壁部分間之卡間柱形側壁部分而界定；其中上柱形壁部分之直徑及下柱形壁部分之直徑越遠離底部壁表面越增加，其中中間柱形側壁部分之直徑越逆離底部壁表面越減少，及其中 A - C，C>B，及 C〉D -29- 本紙張尺度適用巾® 8家標準(CNS) A4規格(210X297公釐) 556238 8 8 8 8 A B c D 六、申請專利範圍其中A係上柱形壁部分最遠離底部壁表面之位置之直徑，B係上柱形壁部分最靠近底部壁表面之位置之直徑，C係下柱形壁部分最遠離底部壁表面之位置之直徑，而D係下柱形壁部分在底部壁之直徑。 34.如申請專利範圍第33項之電容器，其中蝕刻停止膜係一氮化矽膜。 35·如申請專利範圍第33項之電容器，其中下電極係一多晶矽電極。 36.如申請專利範圍第33項之電容器，其中介電層係一氧化氮（NO)層。 -30- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)2. The patent application increases as the distance from the bottom wall surface increases, and the diameter of the intermediate cylindrical side wall portion of the iif decreases as it recedes from the bottom wall surface. Among them, A-C, C > B, and c &D; where A is a cylindrical wall. The position where the part is furthest from the bottom wall surface is the diameter of the position where the upper cylindrical wall part is closest to the bottom wall surface. C is the diameter of the position where the lower cylindrical wall part is furthest from the bottom wall surface, and D is the lower cylindrical wall part. Diameter at the bottom wall. Two 33 ·· Capacitors, comprising a sandwich insulation layer with a surface; a conductive plug extending from the surface of the sandwich insulation layer to a depth; an etch stop layer extending on the insulation layer and exposing the conductive plug; The electrode is defined by a cylindrical side wall and a bottom wall. The cylindrical lower electrode is extended on the surface of the conductive plug and a part of the etching stop layer adjacent to the conductive plug. The cylindrical side wall extends upward from the bottom wall and away from the surface of the interlayer insulation layer. A dielectric layer is formed on the cylindrical lower electrode; and an upper electrode is formed on the dielectric layer; wherein the cylindrical side wall of the cylindrical lower electrode is composed of an upper cylindrical wall portion, a lower cylindrical wall portion, and an upper and a lower cylindrical portion. The space between the lower cylindrical wall part is defined by the columnar sidewall part; the diameter of the upper cylindrical wall part and the diameter of the lower cylindrical wall part increase as the distance from the bottom wall surface increases, and the diameter of the middle cylindrical side wall part is more reverse. The lower the bottom wall surface, and among them A-C, C &B; and C> D -29- This paper size is suitable for towels ® 8 standards (CNS) A4 specifications (210X297 mm) 556238 8 8 8 8 A B c D VI. The scope of patent application, where A is the diameter of the upper cylindrical wall part farthest from the bottom wall surface, B is the diameter of the upper cylindrical wall part closest to the bottom wall surface, and C is the lower cylindrical wall part The diameter of the position farthest from the bottom wall surface, and D is the diameter of the lower cylindrical wall portion at the bottom wall. 34. The capacitor of claim 33, wherein the etch stop film is a silicon nitride film. 35. The capacitor according to item 33 of the patent application, wherein the lower electrode is a polycrystalline silicon electrode. 36. The capacitor of claim 33, wherein the dielectric layer is a nitric oxide (NO) layer. -30- This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)