TWI386071B - Signal chain of an imaging system - Google Patents

Signal chain of an imaging system Download PDF

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TWI386071B
TWI386071B TW98133777A TW98133777A TWI386071B TW I386071 B TWI386071 B TW I386071B TW 98133777 A TW98133777 A TW 98133777A TW 98133777 A TW98133777 A TW 98133777A TW I386071 B TWI386071 B TW I386071B
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circuit
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TW98133777A
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TW201114267A (en
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Chih Min Liu
Mittra Amit
Chi Shao Lin
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Himax Imaging Inc
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Description

影像系統的信號鏈路 Signal link of the imaging system

本發明係有關影像感測器的信號鏈路(signal chain)，特別是關於一種黑階補償(black level compensation,BLC)及高增益信號鏈路的混合信號運算。 The present invention relates to signal chains for image sensors, and more particularly to mixed signal operations for a black level compensation (BLC) and high gain signal link.

半導體影像感測器(例如電荷耦合元件(CCD)或互補金屬氧化半導體(CMOS)感測器)普遍使用於照相機或攝影機中，用以將可見光之影像轉換為電子信號。 Semiconductor image sensors, such as charge coupled devices (CCDs) or complementary metal oxide semiconductor (CMOS) sensors, are commonly used in cameras or cameras to convert visible light images into electrical signals.

由於電子電路的非完美性質，使得影像感測器在未接收到任何光線的情形下仍然會具有漏電流。為了克服此問題，通常係讀取多列的光遮(light-shielded)像素或光學黑像素(optical black pixel)並取其平均作為光學黑階參考(optical black reference)，用以進行黑階補償(BLC)。 Due to the imperfect nature of the electronic circuitry, the image sensor still has leakage currents without receiving any light. In order to overcome this problem, a plurality of columns of light-shielded pixels or optical black pixels are usually read and averaged as an optical black reference for black level compensation. (BLC).

第一圖顯示影像感測器的信號鏈路1，其揭露於美國專利申請第12/477,899號，題為”Black Level Compensation Circuit”，其申請人同於本專利申請案的申請人。信號鏈路1於黑階補償模式中，使用黑階補償(BLC)電路10以補償可程式增益放大器(programmable gain amplifier,PGA)12，使得所形成的迴路1累積偏移值(offset value)而得以匹配類比至數位轉換器(ADC)14的零位準。信號鏈路1還包含具可變數位增益之數位增益電路16。 The first figure shows a signal link 1 of an image sensor, which is disclosed in U.S. Patent Application Serial No. 12/477,899, the entire disclosure of which is incorporated herein by reference. In the black-end compensation mode, the signal link 1 uses a black-order compensation (BLC) circuit 10 to compensate a programmable gain amplifier (PGA) 12 such that the formed loop 1 accumulates an offset value. The analog to the zero level of the digital converter (ADC) 14 is matched. Signal link 1 also includes a digital gain circuit 16 having a variable digital gain.

根據第一圖所示的信號鏈路1，數位增益電路16的最終輸出於黑階補償模式時會趨近零位準。然而，此零位準之黑階對於人眼會顯得不真實。另外，當聚集有黑雜訊時，該零位準可能會造成飽和。再者，一般的類比至數位轉換器(ADC)14因為電路的非完美性及製程的差異性，通常會具有電路偏移量。當高增益信號鏈路1具高增益的可程式增益放大器(PGA)12及高增益的數位增益電路16時，上述的問題將會變得更難控制。 According to the signal link 1 shown in the first figure, the final output of the digital gain circuit 16 approaches the zero level in the black-order compensation mode. However, the black level of this zero position will be unreal to the human eye. In addition, when there is black noise, the zero level may cause saturation. Moreover, the general analog-to-digital converter (ADC) 14 typically has a circuit offset due to circuit imperfections and process variations. When the high gain signal link 1 has a high gain programmable gain amplifier (PGA) 12 and a high gain digital gain circuit 16, the above problems will become more difficult to control.

因此，亟需提出一種新穎影像感測器之信號鏈路，用以獲得一真實的黑階輸出。再者，此新穎信號鏈路，特別是高增益的信號鏈路，還能消除類比至數位轉換器(ADC)14的電路偏移量。 Therefore, there is a need to propose a signal link of a novel image sensor for obtaining a true black level output. Moreover, this novel signal link, particularly a high gain signal chain, also eliminates the analog to digital converter (ADC) 14 circuit offset.

鑑於上述，本發明實施例的目的之一在於提出一種信號鏈路，其不受增益設定的影響，使得最終輸出的非零光學黑階對於人眼感知顯得較為真實，且可以消除類比至數位轉換器(ADC)的電路偏移量。 In view of the above, one of the objects of embodiments of the present invention is to provide a signal link that is unaffected by the gain setting, so that the final output of the non-zero optical black level is more realistic for human perception and can eliminate analog to digital conversion. Circuit offset of the (ADC).

根據本發明實施例，影像系統的信號鏈路包含三級電路。第一級電路包含可程式增益放大器(PGA)及黑階補償(BLC)電路所形成的黑階補償迴路。第二級電路包含類比至數位轉換器(ADC)，其中一暗信號偏移加至類比至數位轉換器(ADC)的輸入。第三級電路包含數位增益電路及數位迴路，用以讓影像系統的最終輸出於黑階補償模式下可穩定於一目標位準。 According to an embodiment of the invention, the signal chain of the image system comprises a three-level circuit. The first stage circuit includes a black level compensation loop formed by a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit. The second stage circuit includes an analog to digital converter (ADC) in which a dark signal offset is added to the analog to the input of the digital converter (ADC). The third stage circuit includes a digital gain circuit and a digital loop to stabilize the final output of the image system in a black level compensation mode to a target level.

根據本發明實施例之一，第三級電路的數位迴路根據目 標位準及數位增益電路的輸出以產生一數位增益前目標位準(before-digital-gain target level)，其值大約等於目標位準除以數位增益。 According to one of the embodiments of the present invention, the digital loop of the third-stage circuit is based on The output of the standard and digital gain circuits is generated to produce a before-digital-gain target level having a value approximately equal to the target level divided by the digital gain.

根據本發明另一實施例，第二級電路包含類比偏移電路，其根據數位增益前目標位準及類比至數位轉換器(ADC)的輸出以產生暗信號偏移，藉此類比至數位轉換器(ADC)的輸出可穩定於數位增益前目標位準。 In accordance with another embodiment of the present invention, the second stage circuit includes an analog offset circuit that produces a dark signal offset based on the digital gain pre-target level and analog to the output of the digital converter (ADC), thereby analog to digital conversion The output of the (ADC) can be stabilized at the target level before the digital gain.

根據本發明又一實施例，第三級電路包含數位偏移電路，其接收最終輸出及目標位準，用以產生一輸出，其再加至數位增益電路的輸出，藉此最終輸出可穩定於目標位準。 In accordance with yet another embodiment of the present invention, a third stage circuit includes a digital offset circuit that receives a final output and a target level for generating an output that is added to an output of the digital gain circuit, whereby the final output is stable Target level.

根據本發明再一實施例，第二級電路包含類比偏移電路，其根據數位暗平均數(digital dark mean)及類比至數位轉換器(ADC)的輸出以產生暗信號偏移，藉此類比至數位轉換器(ADC)的輸出可穩定於數位暗平均數。 In accordance with still another embodiment of the present invention, the second stage circuit includes an analog offset circuit that produces a dark signal offset based on the digital dark mean and analog to the output of the digital converter (ADC), thereby analogy The output to the digital converter (ADC) is stable to the digital dark average.

根據本發明實施例之特徵，使用熱像素臨界控制次系統，其根據類比至數位轉換器(ADC)的輸出以決定一熱像素臨界值，並據以阻隔熱像素信號。 In accordance with a feature of an embodiment of the invention, a thermal pixel critical control subsystem is used that determines the thermal pixel threshold based on the analog to digital output of the digital converter (ADC) and thereby blocks the pixel signal.

第二圖顯示影像系統2的信號鏈路，其包含黑補償(BLC)電路20、可程式增益放大器(PGA)22、類比至數位轉換器(ADC)24及(可變)數位增益電路26。於影像系統2中，黑階補償(BLC)電路20、可程式增益放大器(PGA)22形成迴路1，其(自光遮像素或光學黑像素)接 收一黑階信號並可使其輸出位於零位準。為了讓影像系統2的最終輸出之光學黑階參考對於人眼感知較為真實，因此在類比至數位轉換器(ADC)之前需要加入一暗信號偏移值(dark signal offset)，例如藉由加法器23加入，使得於黑階補償模式之最終輸出具有非零的目標位準，其不會受到可程式增益放大器(PGA)22和數位增益電路26的增益設定所影響。再者，類比至數位轉換器(ADC)的電路偏移量也可同時被消除。上述的目標位準具有非零值。例如，對於十位元系統的0至1023位階，可將該目標位準設於20處。 The second diagram shows the signal chain of image system 2, which includes a black compensation (BLC) circuit 20, a programmable gain amplifier (PGA) 22, an analog to digital converter (ADC) 24, and a (variable) digital gain circuit 26. In the image system 2, a black level compensation (BLC) circuit 20 and a programmable gain amplifier (PGA) 22 form a loop 1 which is connected (from a photomask or an optical black pixel). Receive a black level signal and have its output at zero level. In order for the optical black-order reference of the final output of the imaging system 2 to be realistic to the human eye, a dark signal offset needs to be added before the analog-to-digital converter (ADC), for example by an adder. The addition of 23 causes the final output of the black-order compensation mode to have a non-zero target level that is not affected by the gain settings of the programmable gain amplifier (PGA) 22 and the digital gain circuit 26. Furthermore, analog to digital converter (ADC) circuit offsets can also be eliminated at the same time. The above target level has a non-zero value. For example, for a 0 to 1023 level of a tens system, the target level can be set at 20.

第三A圖顯示本發明第一實施例之影像系統3的信號鏈路。影像系統3包含三級電路，其直接或間接地依序電性互相連接。第一級電路包含迴路1，在本實施例中為類比黑階補償迴路，其係將可程式增益放大器(PGA)32的輸出迴授至黑階補償(BLC)電路30，並將黑階補償(BLC)電路30的輸出和(自光遮像素或光學黑像素的)黑階信號，藉由加法器31，饋至可程式增益放大器(PGA)32的輸入。第一級電路(或迴路1)的實施可採用美國專利申請第12/477,899號，題為”Black Level Compensation Circuit”，其申請人同於本專利申請案的申請人。 Figure 3A shows the signal chain of the image system 3 of the first embodiment of the present invention. The imaging system 3 includes three levels of circuits that are electrically connected to each other directly or indirectly. The first stage circuit includes a loop 1, which in this embodiment is an analog black level compensation loop, which feeds the output of the programmable gain amplifier (PGA) 32 back to the black level compensation (BLC) circuit 30 and compensates for the black level. The output of the (BLC) circuit 30 and the black level signal (from the photomask or optical black pixel) are fed to the input of the programmable gain amplifier (PGA) 32 by the adder 31. The implementation of the first stage of the circuit (or circuit 1) is described in U.S. Patent Application Ser.

第二級電路包含迴路2，其係由類比至數位轉換器(ADC)34和類比偏移電路33所組成。其中，類比偏移電路33接收類比至數位轉換器(ADC)34及(自第三級電路)數位增益前目標位準(before-digital-gain target level)。根據此二輸入，類比偏移電路33因而決定出類比至數位轉換器(ADC)34之輸入，使得類比至數位轉換器(ADC)的偏移量得以消除(或受到補償)；特別的是，藉此得以決定出暗信號偏移值，使得最終輸出可以達到(非零位準)目標位準。第三B圖顯示本實施例之類比偏移電路33的詳細方塊圖。其中，類比偏移電路33使用一差值電路330，其決定二輸入之差值，藉以驅動一積分器332或數位至類比轉換器(DAC)以產生類比至數位轉換器(ADC)34之輸入。所產生的輸入連同第一級電路之輸出一併(藉由加法器35)饋至類比至數位轉換器(ADC)34。 The second stage circuit includes a loop 2 which is comprised of an analog to digital converter (ADC) 34 and an analog offset circuit 33. Wherein, the analog offset circuit 33 receives the analog-to-digital converter (ADC) 34 and (from the third-stage circuit) the digital gain pre-target level (before-digital-gain target) Level). Based on the two inputs, the analog offset circuit 33 thus determines the analogy to the input of the digital converter (ADC) 34 such that the analog to digital converter (ADC) offset is eliminated (or compensated); in particular, Thereby, the dark signal offset value is determined so that the final output can reach the (non-zero level) target level. The third B diagram shows a detailed block diagram of the analog offset circuit 33 of the present embodiment. Wherein, the analog offset circuit 33 uses a difference circuit 330 that determines the difference between the two inputs to drive an integrator 332 or a digital to analog converter (DAC) to produce an analog to analog converter (ADC) 34 input. . The resulting input is fed (by adder 35) to an analog to digital converter (ADC) 34 along with the output of the first stage circuit.

第三級電路包含迴路3，其係由數位增益電路36和比較器/除法器37所組成，其於黑階補償模式時藉由開關0閉合而形成迴路3。其中，比較器/除法器37接收(自最終輸出)目標位準和數位增益電路36的輸出。根據此二輸入，比較器/除法器37因而產生數位增益前目標位準，用以決定(第二級電路)類比至數位轉換器(ADC)34的輸出。第三C圖顯示本實施例之比較器/除法器37的詳細方塊圖。其中，比較器/除法器37使用一比較器370以比較最終輸出及目標位準。當最終輸出大於目標位準時，比較結果會停止上數計數器(up counter)372的計數，因而產生數位增益前目標位準。值得注意的是，本實施例使用上數計數器372而非數位除法器，因為後者需佔用較大電路面積。然而，在其他實施例中，也可使用數位除法器以取代上數計數器372。 The third stage circuit comprises a loop 3 consisting of a digital gain circuit 36 and a comparator/divider 37 which form a loop 3 by closing the switch 0 in the black level compensation mode. Among them, the comparator/divider 37 receives (from the final output) the target level and the output of the digital gain circuit 36. Based on the two inputs, the comparator/divider 37 thus produces a digital gain pre-target level for determining (second stage circuit) analogy to the output of the digital converter (ADC) 34. The third C diagram shows a detailed block diagram of the comparator/divider 37 of the present embodiment. Among them, the comparator/divider 37 uses a comparator 370 to compare the final output with the target level. When the final output is greater than the target level, the comparison will stop counting up counter 372, thus generating a digital gain pre-target level. It is worth noting that this embodiment uses an up-counter 372 instead of a digital divider because the latter takes up a large circuit area. However, in other embodiments, a digital divider can also be used in place of the upcount counter 372.

根據影像系統3的架構，當可程式增益放大器(PGA)32的所需類比增益及數位增益電路36的數位增益設定均完成且(平均)黑階信號已收到時，則迴路1和迴路3將可獨立運作，甚至可同時分別決定出迴路2的輸入及輸出。根據所決定之結果，迴路2即可累積所需偏移量以匹配目標位準。藉此，位於最終輸出的(非零位準)光學黑階參考對於人眼的感知將會較為真實，且可同時消除類比至數位轉換器(ADC)的電路偏移量。 According to the architecture of the imaging system 3, when the required analog gain of the programmable gain amplifier (PGA) 32 and the digital gain setting of the digital gain circuit 36 are completed and the (average) black level signal has been received, then loop 1 and loop 3 It will operate independently and even determine the input and output of loop 2 at the same time. Based on the determined result, Loop 2 can accumulate the required offset to match the target level. Thereby, the (non-zero level) optical black-order reference at the final output will be more realistic for the human eye and can simultaneously eliminate the analog-to-digital converter (ADC) circuit offset.

第四圖顯示本發明第二實施例之影像系統4的信號鏈路。本實施例的架構類似於第一實施例(第三A圖)架構，以下將說明其差異點。與前一實施例相同的方塊將以相同符號表示。對於第二級電路，本實施例的類比偏移電路33係接收一數位暗平均數(digital dark mean)，而非數位增益前目標位準。該數位暗平均數可以是類比至數位轉換器(ADC)34的預期輸出，其可藉由實驗獲得或由使用者設定。 The fourth figure shows the signal link of the image system 4 of the second embodiment of the present invention. The architecture of this embodiment is similar to the first embodiment (third A diagram) architecture, and the differences will be explained below. The same blocks as in the previous embodiment will be denoted by the same symbols. For the second stage circuit, the analog offset circuit 33 of the present embodiment receives a digital dark mean instead of the digital gain front target level. The digital dark average may be analogous to the expected output of the digital converter (ADC) 34, which may be obtained experimentally or by a user.

對於第三級電路，迴路3並未涵蓋數位增益電路36。本實施例的迴路3係將最終輸出及目標位準連接至一數位偏移電路38，其輸出則饋至一加法器39，其再連接至數位增益電路36的輸出。數位偏移電路38的實施可類似於第三B圖所示的類比偏移電路33。 For the third stage circuit, loop 3 does not encompass digital gain circuit 36. Loop 3 of the present embodiment connects the final output and target levels to a digital offset circuit 38, the output of which is fed to an adder 39, which in turn is coupled to the output of digital gain circuit 36. The implementation of the digital offset circuit 38 can be similar to the analog offset circuit 33 shown in FIG.

根據影像系統4的架構，所有三個迴路於黑階補償模式下均可獨立運作，其中，開關1連接至零位準，迴路2連接至數位暗平均數。換句話說，迴路2並不需要等待迴路3所提供的數位增益前目標位準。於補償校正之後，第一 級電路(或迴路1)的輸出接近零位準。第二級電路(或迴路2)的輸出接近數位暗平均數，其相當於類比偏移電路33的輸出。第三級電路(或迴路3)的輸出接近目標位準，其值相當於(數位暗平均數)*(數位增益)+(數位偏移電路38的輸出)。相較於前一實施例(第三A圖)，本實施例的黑階補償運作速度較快，因為三個迴路均可獨立運作。再者，本實施例的黑階補償運作可消除量化誤差，因為數位偏移電路38可精確匹配目標位準。 According to the architecture of the imaging system 4, all three circuits can operate independently in the black level compensation mode, wherein the switch 1 is connected to the zero level and the loop 2 is connected to the digital dark average. In other words, loop 2 does not need to wait for the digital gain pre-target level provided by loop 3. After the compensation correction, the first The output of the stage circuit (or loop 1) is close to zero. The output of the second stage circuit (or loop 2) is close to the digital dark average, which is equivalent to the output of the analog offset circuit 33. The output of the third stage circuit (or loop 3) is close to the target level, and its value corresponds to (digital dark average) * (digital gain) + (output of digital offset circuit 38). Compared with the previous embodiment (third A picture), the black level compensation of this embodiment operates faster because the three circuits can operate independently. Moreover, the black-order compensation operation of this embodiment can eliminate quantization errors because the digital offset circuit 38 can accurately match the target level.

第五圖顯示本發明第三實施例之影像系統5的信號鏈路。本實施例的架構類似於第二實施例(第四圖)架構，以下將說明其差異點，特別是第二級電路。與前一實施例相同的方塊將以相同符號表示。 The fifth figure shows the signal link of the image system 5 of the third embodiment of the present invention. The architecture of this embodiment is similar to the second embodiment (fourth diagram) architecture, and the differences thereof will be explained below, particularly the second-stage circuit. The same blocks as in the previous embodiment will be denoted by the same symbols.

對於第二級電路，本實施例以類比暗平均數(analog dark mean)直接饋至類比至數位轉換器(ADC)34前的加法器35，而非使用數位暗平均數，藉此可簡化第二級電路。該類比暗平均數為類比至數位轉換器(ADC)34的預期輸出，其值可大約等於數位暗平均數。類似的情形，類比暗平均數可藉由實驗獲得或由使用者設定。本實施例之黑階補償運作類似於第二實施例，亦即，三個迴路於黑階補償模式下可獨立運作。本實施例所提供的簡化架構將優於其他實施例，假設類比至數位轉換器(ADC)的偏移很小並侷限於一範圍內。 For the second stage circuit, the present embodiment feeds directly to the adder 35 analogous to the digital converter 34 (ADC) 34 with an analog dark mean instead of using a digital dark average, thereby simplifying the Secondary circuit. The analog dark average is analogous to the expected output of the digital converter (ADC) 34, and its value can be approximately equal to the digital dark average. In a similar situation, the analog dark average can be obtained experimentally or by the user. The black-order compensation operation of this embodiment is similar to the second embodiment, that is, the three loops can operate independently in the black-order compensation mode. The simplified architecture provided by this embodiment will be superior to other embodiments, assuming that the analog to digital converter (ADC) offset is small and limited to a range.

第六圖顯示本發明第四實施例之影像系統6的信號鏈路。本實施例的架構係根基於第四圖架構再增加熱像素(hot pixel)臨界控制次系統40，用以處理因製程非理想性所 造成的熱像素效應。與先前實施例相同的方塊將以相同符號表示。 The sixth figure shows the signal link of the image system 6 of the fourth embodiment of the present invention. The architecture of the present embodiment is based on the fourth graph architecture to add a hot pixel critical control subsystem 40 for processing non-idealities due to process The resulting thermal pixel effect. The same blocks as the previous embodiment will be denoted by the same symbols.

當三個迴路穩定之後，各個暗像素信號(包含熱像素)將輸入至影像系統6。臨界統計邏輯400(於數位領域)根據類比至數位轉換器(ADC)34的輸出以決定出一適當的(數位)熱像素臨界值。該決定之熱像素臨界值(藉由數位至類比轉換器(DAC)402)被轉換為類比形式。接著，此(類比)熱像素臨界值及暗像素信號被饋至迴路1中斷控制電路404。當輸入之暗像素信號的位準超過該熱像素臨界值時，迴路1中斷控制電路404即控制開關3以斷開迴路1，因而阻擋熱像素進入黑階補償(BLC)電路30。 After the three loops are stabilized, each dark pixel signal (including hot pixels) will be input to the image system 6. The critical statistical logic 400 (in the digital domain) is based on the analogy to the output of the digital converter (ADC) 34 to determine an appropriate (digital) thermal pixel threshold. The determined thermal pixel threshold (by digital to analog converter (DAC) 402) is converted to an analog form. This (analog) hot pixel threshold and dark pixel signal are then fed to loop 1 interrupt control circuit 404. When the level of the input dark pixel signal exceeds the thermal pixel threshold, loop 1 interrupts control circuit 404, i.e., controls switch 3 to open loop 1, thereby blocking thermal pixels from entering black level compensation (BLC) circuit 30.

第七圖顯示本發明第五實施例之影像系統7的信號鏈路。本實施例的架構類似於第四實施例(第六圖)架構，以下將說明其差異點。與前一實施例相同的方塊將以相同符號表示。 The seventh figure shows the signal link of the image system 7 of the fifth embodiment of the present invention. The architecture of this embodiment is similar to the fourth embodiment (sixth diagram) architecture, and the differences will be explained below. The same blocks as in the previous embodiment will be denoted by the same symbols.

在本實施例中，熱像素臨界控制次系統50包含暗像素平均濾波器500，其於數位領域將所有暗像素信號予以平均，但其根據一統計上的熱像素臨界值將熱像素予以除外。該熱像素臨界值係根據類比至數位轉換器(ADC)34的輸出所決定。 In the present embodiment, the hot pixel critical control subsystem 50 includes a dark pixel averaging filter 500 that averages all of the dark pixel signals in the digital domain, but excludes the hot pixels based on a statistically hot pixel threshold. The thermal pixel threshold is determined by the analog to digital output of the digital converter (ADC) 34.

熱像素臨界控制次系統50還包含類比偏移電路502，其類似於第四圖的類比偏移電路33，其根據數位暗平均數及類比至數位轉換器(ADC)34的輸出以提供輸入給類比至 數位轉換器(ADC)34。相較於第六圖，本實施例的像素臨界控制次系統50係運作於數位領域中。再者，本實施例的熱像素控制不涉及可程式增益放大器(PGA)32的增益設定。 The thermal pixel critical control subsystem 50 also includes an analog offset circuit 502 that is similar to the analog shift circuit 33 of the fourth graph, which provides input to the output according to the digital dark average and analog to digital converter (ADC) 34 Analogy to Digital Converter (ADC) 34. Compared to the sixth figure, the pixel critical control subsystem 50 of the present embodiment operates in the digital domain. Furthermore, the thermal pixel control of this embodiment does not involve the gain setting of the programmable gain amplifier (PGA) 32.

以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離發明所揭示之精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍內。 The above description is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; all other equivalent changes or modifications which are not departing from the spirit of the invention should be included in the following Within the scope of the patent application.

1‧‧‧信號鏈路 1‧‧‧ signal link

2‧‧‧影像系統 2‧‧‧Image system

3‧‧‧影像系統 3‧‧‧Image system

4‧‧‧影像系統 4‧‧‧Image System

5‧‧‧影像系統 5‧‧‧Image system

6‧‧‧影像系統 6‧‧‧Image system

7‧‧‧影像系統 7‧‧‧Image System

10‧‧‧黑階補償(BLC)電路 10‧‧‧Black Level Compensation (BLC) Circuit

12‧‧‧可程式增益放大器(PGA) 12‧‧‧Programmable Gain Amplifier (PGA)

14‧‧‧類比至數位轉換器(ADC) 14‧‧‧ Analog to Digital Converter (ADC)

16‧‧‧可變數位增益之數位增益電路 16‧‧‧Digital gain circuit with variable digital gain

20‧‧‧黑階補償(BLC)電路 20‧‧‧Black Level Compensation (BLC) Circuit

22‧‧‧可程式增益放大器(PGA) 22‧‧‧Programmable Gain Amplifier (PGA)

23‧‧‧加法器 23‧‧‧Adder

24‧‧‧類比至數位轉換器(ADC) 24‧‧‧ Analog to Digital Converter (ADC)

26‧‧‧數位增益電路 26‧‧‧Digital gain circuit

30‧‧‧黑階補償(BLC)電路 30‧‧‧Black Level Compensation (BLC) Circuit

31‧‧‧加法器 31‧‧‧Adder

32‧‧‧可程式增益放大器(PGA) 32‧‧‧Programmable Gain Amplifier (PGA)

33‧‧‧類比偏移電路 33‧‧‧ analog offset circuit

330‧‧‧差值電路 330‧‧‧ difference circuit

332‧‧‧積分器/數位至類比轉換器(DAC) 332‧‧‧Integrator/Digital to Analog Converter (DAC)

34‧‧‧類比至數位轉換器(ADC) 34‧‧‧ Analog to Digital Converter (ADC)

35‧‧‧加法器 35‧‧‧Adder

36‧‧‧數位增益電路 36‧‧‧Digital gain circuit

37‧‧‧比較器/除法器 37‧‧‧ Comparator/divider

370‧‧‧比較器 370‧‧‧ comparator

372‧‧‧上數計數器 372‧‧‧Upcount counter

38‧‧‧數位偏移電路 38‧‧‧Digital offset circuit

39‧‧‧加法器 39‧‧‧Adder

40‧‧‧熱像素臨界控制次系統 40‧‧‧hot pixel critical control subsystem

400‧‧‧臨界統計邏輯 400‧‧‧ Critical statistical logic

402‧‧‧數位至類比轉換器(DAC) 402‧‧‧Digital to analog converter (DAC)

404‧‧‧迴路1中斷控制電路 404‧‧‧Circuit 1 interrupt control circuit

50‧‧‧熱像素臨界控制次系統 50‧‧‧hot pixel critical control subsystem

500‧‧‧暗像素平均濾波器 500‧‧‧Dark pixel averaging filter

502‧‧‧類比偏移電路 502‧‧‧ analog offset circuit

第一圖顯示影像感測器的信號鏈路。 The first figure shows the signal link of the image sensor.

第二圖顯示影像系統的信號鏈路。 The second figure shows the signal link of the imaging system.

第三A圖顯示本發明第一實施例之影像系統的信號鏈路。 Figure 3A shows the signal chain of the image system of the first embodiment of the present invention.

第三B圖顯示第三A圖之類比偏移電路的詳細方塊圖。 The third B diagram shows a detailed block diagram of the analog offset circuit of the third A picture.

第三C圖顯示第三A圖之比較器/除法器的詳細方塊圖。 The third C diagram shows a detailed block diagram of the comparator/divider of the third A diagram.

第四圖顯示本發明第二實施例之影像系統的信號鏈路。 The fourth figure shows the signal link of the image system of the second embodiment of the present invention.

第五圖顯示本發明第三實施例之影像系統的信號鏈路。 The fifth figure shows the signal link of the image system of the third embodiment of the present invention.

第六圖顯示本發明第四實施例之影像系統的信號鏈路。 Figure 6 is a diagram showing the signal chain of the image system of the fourth embodiment of the present invention.

第七圖顯示本發明第五實施例之影像系統的信號鏈路。 The seventh figure shows the signal link of the image system of the fifth embodiment of the present invention.

3‧‧‧影像系統 3‧‧‧Image system

30‧‧‧黑階補償(BLC)電路 30‧‧‧Black Level Compensation (BLC) Circuit

31‧‧‧加法器 31‧‧‧Adder

32‧‧‧可程式增益放大器(PGA) 32‧‧‧Programmable Gain Amplifier (PGA)

33‧‧‧類比偏移電路 33‧‧‧ analog offset circuit

34‧‧‧類比至數位轉換器(ADC) 34‧‧‧ Analog to Digital Converter (ADC)

35‧‧‧加法器 35‧‧‧Adder

36‧‧‧數位增益電路 36‧‧‧Digital gain circuit

37‧‧‧比較器/除法器 37‧‧‧ Comparator/divider

Claims (7)

一種影像系統的信號鏈路，包含：一第一級電路，包含一可程式增益放大器(PGA)及一黑階補償(BLC)電路共同形成一第一迴路，其中該可程式增益放大器(PGA)接收一黑階信號，且該黑階補償(BLC)電路補償該可程式增益放大器(PGA)；一第二級電路，連接於該第一級電路後面，該第二級電路包含一類比至數位轉換器(ADC)及一類比偏移電路共同形成一第二迴路，其產生一暗信號偏移加至該類比至數位轉換器(ADC)的一輸入；及一第三級電路，連接於該第二級電路後面，該第三級電路包含一數位增益電路及一比較器/除法器共同形成一第三迴路，用以讓該影像系統的最終輸出穩定於一目標位準，其中該比較器/除法器根據該目標位準及該數位增益電路的輸出以產生一數位增益前目標位準(before-digital-gain target level)，其值大約等於該目標位準除以該數位增益電路的數位增益；其中該類比偏移電路根據該數位增益前目標位準及該類比至數位轉換器(ADC)的輸出以產生該暗信號偏移，藉此該類比至數位轉換器(ADC)的輸出可穩定於該數位增益前目標位準；其中上述之比較器/除法器包含：一比較器，用以比較該最終輸出及該目標位準；及一上數計數器，用以產生該數位增益前目標位準，其中，當該最終輸出大於該目標位準時，則該比較器之比較 結果停止該上數計數器之計數。 A signal link of an image system, comprising: a first stage circuit comprising a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit to form a first loop, wherein the programmable gain amplifier (PGA) Receiving a black level signal, and the black level compensation (BLC) circuit compensates the programmable gain amplifier (PGA); a second stage circuit is connected behind the first stage circuit, the second stage circuit includes an analog to digital A converter (ADC) and a type of offset circuit together form a second loop that produces a dark signal offset applied to the analog input to an input of the digital converter (ADC); and a third stage circuit coupled to the After the second stage circuit, the third stage circuit includes a digital gain circuit and a comparator/divider to form a third loop for stabilizing the final output of the image system to a target level, wherein the comparator And a divider according to the target level and an output of the digital gain circuit to generate a before-digital-gain target level, the value of which is approximately equal to the target level divided by the digit of the digital gain circuit increase Wherein the analog offset circuit generates the dark signal offset based on the digital gain pre-target level and the analog to digital output of the digital converter (ADC), whereby the output of the analog-to-digital converter (ADC) is stable The digital gain pre-target level; wherein the comparator/divider comprises: a comparator for comparing the final output with the target level; and an up counter for generating the digital gain pre-target Quasi, wherein when the final output is greater than the target level, then the comparator is compared As a result, the count of the up counter is stopped. 如申請專利範圍第1項所述影像系統的信號鏈路，其中上述第一級電路的黑階補償(BLC)電路接收該可程式增益放大器(PGA)的輸出，且該黑階補償(BLC)電路的輸出及該黑階信號饋至該可程式增益放大器(PGA)的輸入。 The signal link of the image system of claim 1, wherein the black level compensation (BLC) circuit of the first stage circuit receives the output of the programmable gain amplifier (PGA), and the black level compensation (BLC) The output of the circuit and the black level signal are fed to the input of the programmable gain amplifier (PGA). 如申請專利範圍第1項所述影像系統的信號鏈路，其中上述之類比偏移電路包含：一差值電路，用以決定該類比至數位轉換器(ADC)的輸出和該數位增益前目標位準的差值；及一積分器或數位至類比轉換器(DAC)，其根據該差值以產生該暗信號偏移，用以加至該類比至數位轉換器(ADC)的輸入。 The signal link of the image system of claim 1, wherein the analog offset circuit comprises: a difference circuit for determining the analog output to the digital converter (ADC) and the digital gain pre-target The difference in level; and an integrator or digital to analog converter (DAC) that produces the dark signal offset based on the difference to add to the analog input to the digital converter (ADC). 一種影像系統的信號鏈路，包含：一第一級電路，包含一可程式增益放大器(PGA)及一黑階補償(BLC)電路共同形成一第一迴路，其中該可程式增益放大器(PGA)接收一黑階信號，且該黑階補償(BLC)電路補償該可程式增益放大器(PGA)；一第二級電路，連接於該第一級電路後面，該第二級電路包含一類比至數位轉換器(ADC)及一類比偏移電路共同形成一第二迴路，其產生一暗信號偏移加至該類比至數位轉換器(ADC)的一輸入，其中該類比偏移電路根據一數位暗平均數(digital dark mean)及該類比至數位轉換器(ADC)的輸出以產生該暗信號偏移，藉此該類比至數位轉換器(ADC)的輸出可穩定於該數位暗平均數； 一第三級電路，連接於該第二級電路後面，該第三級電路包含一數位增益電路及一數位偏移電路，其中該數位偏移電路接收一最終輸出及一目標位準，用以產生一輸出，其再加至該數位增益電路的輸出，藉此該最終輸出可穩定於該目標位準；及一熱像素臨界控制次系統，其根據該類比至數位轉換器(ADC)的輸出以決定一熱像素臨界值，並據以阻隔熱像素信號，該熱像素臨界控制次系統包含：一臨界統計邏輯，其根據該類比至數位轉換器(ADC)的輸出以決定一熱像素臨界值；一數位至類比轉換器(DAC)，用以將該熱像素臨界值自數位形式轉換為類比形式；及一中斷控制電路，當該黑階信號被決定為熱像素時，該中斷控制電路即中斷該第一迴路。 A signal link of an image system, comprising: a first stage circuit comprising a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit to form a first loop, wherein the programmable gain amplifier (PGA) Receiving a black level signal, and the black level compensation (BLC) circuit compensates the programmable gain amplifier (PGA); a second stage circuit is connected behind the first stage circuit, the second stage circuit includes an analog to digital A converter (ADC) and a type of offset circuit together form a second loop that produces a dark signal offset applied to an input of the analog to digital converter (ADC), wherein the analog offset circuit is dark according to a digit a digital dark mean and the analogy to an output of the digital converter (ADC) to produce the dark signal offset, whereby the output of the analog to digital converter (ADC) is stable to the digital dark average; a third stage circuit is connected to the second stage circuit, the third stage circuit comprises a digital gain circuit and a digital offset circuit, wherein the digital offset circuit receives a final output and a target level for Generating an output that is added to the output of the digital gain circuit, whereby the final output is stable to the target level; and a thermal pixel critical control subsystem that is based on the output of the analog to digital converter (ADC) To determine a thermal pixel threshold and to block the pixel signal, the thermal pixel critical control subsystem includes: a critical statistical logic that determines a thermal pixel threshold based on the analog to digital output of the digital converter (ADC) a digital to analog converter (DAC) for converting the thermal pixel threshold from a digital form to an analog form; and an interrupt control circuit, when the black level signal is determined to be a hot pixel, the interrupt control circuit is Interrupt the first loop. 如申請專利範圍第4項所述影像系統的信號鏈路，其中上述第一級電路的黑階補償(BLC)電路接收該可程式增益放大器(PGA)的輸出，且該黑階補償(BLC)電路的輸出及該黑階信號饋至該可程式增益放大器(PGA)的輸入。 The signal link of the image system of claim 4, wherein the black level compensation (BLC) circuit of the first stage circuit receives the output of the programmable gain amplifier (PGA), and the black level compensation (BLC) The output of the circuit and the black level signal are fed to the input of the programmable gain amplifier (PGA). 如申請專利範圍第4項所述影像系統的信號鏈路，其中上述之類比偏移電路包含：一差值電路，用以決定該類比至數位轉換器(ADC)的輸出和該數位暗平均數的差值；及一積分器或數位至類比轉換器(DAC)，其根據該差值以產生該暗信號偏移，用以加至該類比至數位轉換器(ADC)的輸入。 The signal link of the image system of claim 4, wherein the analog offset circuit comprises: a difference circuit for determining an output of the analog to digital converter (ADC) and the digital dark average And an integrator or digital to analog converter (DAC) that produces the dark signal offset based on the difference to add to the analog input to the digital converter (ADC). 一種影像系統的信號鏈路，包含：一第一級電路，包含一可程式增益放大器(PGA)及一黑階補償(BLC)電路共同形成一第一迴路，其中該可程式增益放大器(PGA)接收一黑階信號，且該黑階補償(BLC)電路補償該可程式增益放大器(PGA)；一第二級電路，連接於該第一級電路後面，該第二級電路包含一類比至數位轉換器(ADC)及一類比偏移電路共同形成一第二迴路，其產生一暗信號偏移加至該類比至數位轉換器(ADC)的一輸入，其中該類比偏移電路根據一數位暗平均數(digital dark mean)及該類比至數位轉換器(ADC)的輸出以產生該暗信號偏移，藉此該類比至數位轉換器(ADC)的輸出可穩定於該數位暗平均數；一第三級電路，連接於該第二級電路後面，該第三級電路包含一數位增益電路及一數位偏移電路，其中該數位偏移電路接收一最終輸出及一目標位準，用以產生一輸出，其再加至該數位增益電路的輸出，藉此該最終輸出可穩定於該目標位準；及一熱像素臨界控制次系統，其根據該類比至數位轉換器(ADC)的輸出以決定一熱像素臨界值，並據以阻隔熱像素信號，其中上述之熱像素臨界控制次系統包含：一暗像素平均濾波器，其於數位領域將所有該暗像素信號予以平均，但其根據一統計上的熱像素臨界值將該熱像素信號予以除外，其中該熱像素臨界值係根據該類比至數位轉換器(ADC)的輸出所決定。 A signal link of an image system, comprising: a first stage circuit comprising a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit to form a first loop, wherein the programmable gain amplifier (PGA) Receiving a black level signal, and the black level compensation (BLC) circuit compensates the programmable gain amplifier (PGA); a second stage circuit is connected behind the first stage circuit, the second stage circuit includes an analog to digital A converter (ADC) and a type of offset circuit together form a second loop that produces a dark signal offset applied to an input of the analog to digital converter (ADC), wherein the analog offset circuit is dark according to a digit a digital dark mean and an analog to an output of the digital converter (ADC) to produce the dark signal offset, whereby the output of the analog to digital converter (ADC) is stable to the digital dark average; a third stage circuit is connected to the second stage circuit, the third stage circuit includes a digital gain circuit and a digital offset circuit, wherein the digital offset circuit receives a final output and a target level for generating An output, and then Adding to the output of the digital gain circuit, whereby the final output is stable to the target level; and a thermal pixel critical control subsystem that determines the thermal pixel threshold based on the analog output to the digital converter (ADC) And a thermal pixel critical control subsystem comprising: a dark pixel averaging filter that averages all of the dark pixel signals in a digital domain, but based on a statistically hot pixel The threshold is excluded from the thermal pixel signal, wherein the thermal pixel threshold is determined based on the analog to digital converter (ADC) output.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100301A (en) * 1996-02-28 2000-08-08 Pfizer Inc Combination therapy to treat osteoporosis-polyphosphonates and estrogen agonists
US6441684B1 (en) * 1999-06-15 2002-08-27 Analog Devices, Inc. Variable gain amplifier system
US6791607B1 (en) * 1998-07-15 2004-09-14 Texas Instruments Incorporated Optical black and offset correction in CCD signal processing
TW200625054A (en) * 2005-01-14 2006-07-16 Cai-Fu Wu Power factor corrector control device for accommodating mains voltage distortion and achieving high power factor and low harmonic current
US8115835B2 (en) * 2008-05-28 2012-02-14 Mediatek Singapore Pte Ltd. Programmable digital black level calibration with feedback control

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6100301A (en) * 1996-02-28 2000-08-08 Pfizer Inc Combination therapy to treat osteoporosis-polyphosphonates and estrogen agonists
US6791607B1 (en) * 1998-07-15 2004-09-14 Texas Instruments Incorporated Optical black and offset correction in CCD signal processing
US6441684B1 (en) * 1999-06-15 2002-08-27 Analog Devices, Inc. Variable gain amplifier system
TW200625054A (en) * 2005-01-14 2006-07-16 Cai-Fu Wu Power factor corrector control device for accommodating mains voltage distortion and achieving high power factor and low harmonic current
US8115835B2 (en) * 2008-05-28 2012-02-14 Mediatek Singapore Pte Ltd. Programmable digital black level calibration with feedback control

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