201114267 六、發明說明： 【發明所屬之技術領域 [0001]本發明係有關影像感測器的信號鏈路（Signal chain) ，特別是關於〆種黑階補償（black leve 1 compensa-tion，BLC)及高增益信號鏈路的混合信號運算。 【先前技術】 [0002] 半導體影像感測器（例如電荷耦合元件（CCD)或互補金 屬氧化半導體（CM0S)感測器）普遍使用於照相機或攝 影機中，用以將可見光之影像轉換為電子信號。 Ο [0003] 由於電子電路的非完美性質，使得影像感測器在未接收 到任何光線的情形下仍然會具有漏電流。為了克服此問 題，通常係讀取多列的光遮（light-shielded)像素或 光學黑像素（optical black pixel)並取其平均作為 光學黑階參考（optical black reference)，用以進 行黑階補償（BLC)。 [0004] 第一圖顯示影像感測器的信號鏈路1，其揭露於美國專利 〇 申請第 12/477, 899號，題為” Black Level Compens〜 ation Circuit” ，其申請人同於本專利申請案的申請 人。信號鏈路1於黑階補償模式中，使用黑階補償（BLC )電路10以補償可程式增益放大器（programmable gain ampl if ier，PGA) 12 ’使得所形成的迴路1累積 偏移值（offset value)而得以匹配類比至數位轉換器 (ADC) 14的零位準。信號鏈路1還包含具可變數位增益 之數位增益電路1 6。 根據第一圖所示的信號鏈路1，數位增益電路16的最終輸 098133777 表單編號A0101 第3頁/共27頁 n<w [0005] 201114267 [0006] [0007] [0008] 098133777 出於黑階補償模式時會趨近零位準。然而，此零位準之 黑階對於人眼會顯得不真實。另外，當聚集有黑雜訊時 ，該零位準可能會造成飽和。再者，一般的類比至數位 轉換器（ADC) 14因為電路的非完美性及製程的差異性， 通常會具有電路偏移量。當高增益信號鏈路1具高增益的 可程式增益放大器（PGA) 12及高增益的數位增益電路16 時，上述的問題將會變得更難控制。 因此，亟需提出一種新穎影像感測器之信號鏈路 獲得一真實的黑階輸出。再者，此新穎信號鏈路 是高增益的信號鏈路，還能消除類比至數位轉換器（ADC )14的電路偏移量。 【發明内容】 鑑於上述，本發明實施例的目的之一在於提出一種信號 鏈路，其不受增益設定的影響，使得最終輸出的非零光 學黑階對於人眼感知顯得較為真實，且可以消除類比至 數位轉換器（ADC)的電路偏移量。 根據本發明實施例，影像系統的信號鏈路包含三級電路 。第一級電路包含可程式增益放大器（PGA)及黑階補償 (BLC)電路所形成的黑階補償迴路。第二級電路包含類 比至數位轉換器（ADC)，其中一暗信號偏移加至類比至 數位轉換器（ADC)的輸入。第三級電路包含數位增益電 路及數位迴路，用以讓影像系統的最終輸出於黑階補償 模式下可穩定於一目標位準。 根據本發明實施例之一，第三級電路的數位迴路根據目 標位準及數位增益電路的輸出以產生一數位增益前目標 表單編號A0101 第4頁/共27頁 0982057780-0 ，用以 ，特別 [0009] 201114267 [0010] [0011] ο 位準（bef0re_digitabgain target 】州），其 值大約等於目標位準除以數位增益。 八 根據本發明另—實施例，第二級電路包含類比偏移電路 ’其根據數位增益前目標位準及類比至數位轉換器（狐 的輸出以產生暗信號偏移，藉此類比至數位轉換哭（ 術）的輸出可敎於數位增妓目標位準。 根據本發明又-實_，第三級電路包含數位偏移電路 ’其接收最終輸出及目標位準，心產生-輸出’其再 加至數位增益電料㈣，藉此最終輪討敎於 位 if!。 [0012] [0013]201114267 VI. Description of the Invention: [Technical Field [0001] The present invention relates to a signal chain of an image sensor, in particular to a black leve 1 compensa-tion (BLC) And mixed signal operation of high gain signal links. [Prior Art] [0002] Semiconductor image sensors (such as charge coupled devices (CCD) or complementary metal oxide semiconductor (CMOS) sensors) are commonly used in cameras or cameras to convert visible light images into electrical signals. . Ο [0003] Due to the imperfect nature of electronic circuits, image sensors still have leakage currents without receiving any light. In order to overcome this problem, a plurality of columns of light-shielded pixels or optical black pixels are usually read and averaged as an optical black reference for black level compensation. (BLC). [0004] The first figure shows a signal link 1 of an image sensor, which is disclosed in US Patent Application Serial No. 12/477,899, entitled "Black Level Compensation Circuit", the applicant of which is the same as the present patent. Applicant for the application. In the black-end compensation mode, the signal link 1 uses a black-order compensation (BLC) circuit 10 to compensate a programmable gain ampl if ier (PGA) 12 ' such that the formed loop 1 accumulates an offset value (offset value) ) to match the analog to the zero level of the digital converter (ADC) 14. Signal link 1 also includes a digital gain circuit 16 with variable bit gain. According to the signal link 1 shown in the first figure, the final input of the digital gain circuit 16 is 098133777 Form No. A0101 Page 3 / Total 27 pages n<w [0005] 201114267 [0006] [0007] [0008] 098133777 Out of black In the order compensation mode, it will approach the zero level. However, this black level of the zero position will be unreal to the human eye. In addition, when there is black noise, the zero level may cause saturation. Moreover, the general analog-to-digital converter (ADC) 14 typically has a circuit offset due to circuit imperfections and process variations. When the high gain signal link 1 has a high gain programmable gain amplifier (PGA) 12 and a high gain digital gain circuit 16, the above problems will become more difficult to control. Therefore, it is urgent to propose a signal link of a novel image sensor to obtain a true black-order output. Moreover, the novel signal link is a high gain signal link that also eliminates the analog to digital converter (ADC) 14 circuit offset. SUMMARY OF THE INVENTION In view of the above, one of the objects of the embodiments of the present invention is to provide a signal link that is not affected by the gain setting, so that the final output of the non-zero optical black level is more realistic for human perception and can be eliminated. Analog to the circuit offset of the digital converter (ADC). According to an embodiment of the invention, the signal chain of the image system comprises a three-level circuit. The first stage circuit consists of a black level compensation loop formed by a programmable gain amplifier (PGA) and a black level compensation (BLC) circuit. The second stage circuit contains an analog to digital converter (ADC) in which a dark signal offset is added to the analog to the input of the digital converter (ADC). The third stage circuit includes a digital gain circuit and a digital loop to stabilize the final output of the image system in a black level compensation mode to a target level. According to one embodiment of the present invention, the digital loop of the third stage circuit is based on the output of the target level and the digital gain circuit to generate a digital gain before the target form number A0101, page 4 / total 27 pages 0982057780-0, for special [0009] 201114267 [0011] ο level (bef0re_digitabgain target state), its value is approximately equal to the target level divided by the digital gain. According to another embodiment of the present invention, the second stage circuit includes an analog offset circuit 'which is based on the digital gain front target level and the analog to digital converter (the output of the fox to generate a dark signal offset, thereby analog to digital conversion) The output of the crying can be at the digital target level. According to the present invention, the third stage circuit includes a digital offset circuit that receives the final output and the target level, and the heart generates an output. Add to the digital gain material (4), thereby finally turning to the position if!. [0013]
，本發明再—實施例，第二級電路包含類比偏移電路 壬其根據數㈣平馳（digitaI心、刪）及類比 ^位轉㈣WO的輸出以產生暗信號偏移，藉此類 比至數位轉換器⑽C)的輸出可穩定於數位暗平均數。 根據本發明f施狀特徵，❹熱像素臨界控制次系統 其根據類比至數位轉換5| rAnr、 得換器（ADC)的輪出以決定一熱像 素臨界值’並據錄隔鱗素信號。 【實施方式】 闺帛二圖顯㈣彡像“2的信號鏈路，其包含黑補償⑽c 電路20、可程式增益放大器（pGA) 22、類比至數位轉 換器（ADC) 24及（可變）數位増益電路26。於影像系統 2中，黑階補償（BLC)電糊、可程式增益放大器（ PGA) 22形成迴路1 ’其（自光遮像素或光學黑像素）接 收-黑階信號並可使其輪出位於零位準。為了讓影像系 098133777 表單編號A0101 第5頁/共27頁 0982057780-0 201114267 統2的最終輪出之光學黑階參考對於人眼感知較為真實， 因此在類比至數位轉換器（ADC)之前需要加入一暗信號 偏移值（dark signal offset)，例如藉由加法器23 加入，使得於黑階補償模式之最終輸出具有非零的目標 位準’其不會受到可程式增益放大器（PGA) 22和數位增 盈電路26的增益設定所影響。再者，類比至數位轉換器 (ADC)的電路偏移量也可同時被消除。上述的目標位準 具有非零值。例如’對於十位元系統的0至1023位階，可 將該目標位準設於20處。 [0015] 第二A圖顯示本發明第一實施例之影像系統3的信號鏈路 。影像系統3包含三級電路，其直接或間接地依序電性互 相連接。第一級電路包含迴路^，在本實施例中為類比黑 階補償迴路，其係將可程式增益放大器（PGA) 32的輸出 迴授至黑階補償（BLC)電路30，並將黑階補償（BLC) 電路30的輸出和（自光遮像素或光學黑像素的）黑階信 號’藉由加法器31 ’饋至可程式增益放大器（PGA) 32的 輪入。第一級電路（或迴路1)的實施可採用美國專利申 請第 12/477, 899號’題為” Black Level C〇mpensa一 tl〇n Circuit” ，其申請人同於本專利申請案的申請人 [0016] 098133777 第二級電路包含迴路2，其係由類比至數位轉換器 )34和類比偏移電路33所組成。其中，類比偏移電路” 接收類比至數位轉換器（ADC) 34及（自第三級電路）數位增盈前目標位準（before-digital-gain target level )。根據此二輸入，類比偏移電路33因而決定出類 I單碥號A0I01 第6頁/共27頁 0982057780-0 201114267 比至數位轉換②（ADG) 34之輸人，使得類比至數位轉換 益（ADC)的偏移量得以消除（或受到補償广特別的是 ’藉此传以決定出暗信號偏移值，使得最終輸出可以達 到（非零㈣：）目標位準。第三㈣顯示本實施例之類比 偏移电路33的詳細方塊圖。其中，類比偏移電路33使用 差值電路33G ’其決定二輸人之差值，藉以驅動一積分 器332或數位至類比轉換器（罐）以產生類比至數位轉 換is ( ADC) 34之輸人。所產生的輸人連同第__級電路之 Ο [0017] 輸出-併（藉由加法器35)饋至類比至數位轉換器⑽c )34 ° ❹ 第一級％路包含迴路3，其係由數位增益電路36和比較器 /除法器37所組成’其於黑幽雜式時藉㈣關〇閉合 而形成迴路3。其中’比較器/除法器37接收（自最終輸 出）目標位準和數位增益電路36的輸出。根據此二輸入 ’比較器/除法器37因而產生數位増益前目標位準，用以 決定（第二級電路）類比至數位轉換器（ADC) 34的輸出 。第三c圖顯示本實施例之比較器/除法器37的詳細方塊 圖。其中，比較器/除法器37使用一比較器37〇以比較最 終輸出及目標位準。當最終輸出大於目標位準時，比較 結果會停止上數計數器（up c〇unter) 372的計數，因 而產生數位增益前目標位準。值得注意的是，本實施例 使用上數計數器372而非數位除法器，因為後者需佔用較 大電路面積。然而，在其他實施例中，也可使用數位除 法器以取代上數計數器372。 [0018] 根據影像系統3的架構，當可程式增益放大器（PGA) 32 098133777 表單編號A0101 第7頁/共27頁 0982057780-0 201114267 的所需類比增益及數位增益電路36的數位增益設定均完 成且（平均）黑階信號已收到時，則迴路1和迴路3將可 獨立運作，甚至可同時分別決定出迴路2的輸入及輸出。 據所决疋之結果，迴路2即可累積所需偏移量以匹配目 標位準。藉此，位於最終輸出的（非零位準）光學黑參 考對於人眼的感知將會較為真實，且可同時消除類比至 數位轉換器（ADC)的電路偏移量。 [0019] [0020] 弟四圖顯示本發明第二實施例之影像系統4的信號鍵路。 實細*例的架構類似於第一實施例（第三A圖）架構，以 將說月其差異點。與前一實施例相同的方塊將以相同 夺號表π。對於第二級電路’本實施例的類比偏移電路 3係接收—數位暗平均數（似^如丨虹灶脱⑽），而 ^數位增“目標位準^該數位暗平均數可以是類比至 數位轉換器（概）34的預期輸出，其可藉由實 由使用者設定。 次 ;第~級電路’迴路3並未涵蓋數位增益電路36。本實 1!的沿路3係將取終輸出及目標位準連接至—數位偏移 =路38 ’其輪出㈣至—加法器39，其再連接至數位增 皿電路36的輸出。數位偏移電路38的實施可類似於第三β 圖所示的類比偏移電路33。 — [0021] 098133777 的禾構，所有三個迴路於黑階補償模式下 均可獨立運作，盆中„„ ，、中，開關1連接至零位準，迴路2連接 至數位暗平均數。換句話說，迴路2並不需要等待迫路3 所提供的數位增显前目標位準。於補償校正之後，第一 級電路（或迴路 的輸出接近零位準。第二級電路（戋 第8頁/共27頁 表單編號A0101 0982057780-0 201114267 迴路2)的輪出接近數位暗平均數，其相# 路33的輸出。第三級電路（或迴路3)的輸出接近^ 準，其值相當於（數位暗平均數）* (數位增益）+ (數 位偏移電路38的輪出）。相較於前-實施例（第三謂 )，本實施例的黑階補償運作速度較快，因為三個迴路 句可獨立運作。再者，本實施例的黑階補償運作可消除 里化誤差’ g為數位偏移電路38可精確匹配目標位準。 [0022] Ο [0023] Ο 第五圖顯示本發”三實_之影像线5的信號鏈路。 本實施例的架構類似於第二實施例（第四圖）架構，以 下將說明Μ異點’特別是第二級電路。與前1施例 相同的方塊將以相同符號表示。 對於第一級電路’本實施例以類比暗平均數（anal〇g 脱⑻直接饋至類比至數位轉換器（ADC) 34前的 加法器35，而非使用數位暗平均數，藉此可簡化第二級 電路。該類比暗平均數為類比至數位轉換器UDC) 34的In a second embodiment of the present invention, the second stage circuit includes an analog offset circuit 产生 which outputs a dark signal offset according to the number (4) ping (digitaI, 删) and analog 位 (4) WO, thereby analogous to digital The output of converter (10) C) can be stabilized by a digital dark average. In accordance with the present invention, the hot pixel critical control subsystem is based on analog to digital conversion 5|rAnr, the converter (ADC) is rotated to determine a thermal pixel threshold' and is recorded as a squaring signal. [Embodiment] FIG. 2 shows a signal link of "2", which includes a black compensation (10) c circuit 20, a programmable gain amplifier (pGA) 22, an analog to digital converter (ADC) 24, and (variable). Digital benefit circuit 26. In image system 2, a black-order compensation (BLC) paste, a programmable gain amplifier (PGA) 22 forms a loop 1 'which receives (from a photomask pixel or an optical black pixel) a black level signal and Let the wheel out at the zero level. In order to make the image system 098133777 Form No. A0101 Page 5 / Total 27 Page 0982057780-0 201114267 The final rounded optical black level reference of the system 2 is more realistic for the human eye, so in the analogy to The digital converter (ADC) is required to add a dark signal offset, for example by the adder 23, so that the final output of the black-order compensation mode has a non-zero target level. The gain settings of the programmable gain amplifier (PGA) 22 and the digital gain circuit 26 are affected. Furthermore, the analog-to-digital converter (ADC) circuit offset can also be eliminated at the same time. The above target level has a non-zero value For example, for the 0 to 1023 level of the tens system, the target level can be set at 20. [0015] Figure 2A shows the signal link of the image system 3 of the first embodiment of the present invention. 3 includes three stages of circuits, which are directly or indirectly electrically connected to each other. The first stage circuit includes a circuit ^, which in this embodiment is an analog black level compensation circuit, which is a programmable gain amplifier (PGA) 32 The output is fed back to the black level compensation (BLC) circuit 30, and the output of the black level compensation (BLC) circuit 30 and the black level signal 'from the photomask or optical black pixel' are fed to the adder 31' The rounding of the program gain amplifier (PGA) 32. The implementation of the first stage circuit (or circuit 1) can be performed by the US Patent Application No. 12/477,899 entitled "Black Level C〇mpensa-tl〇n Circuit". The Applicant is the same as the applicant of the present patent application [0016] 098133777 The second stage circuit comprises a loop 2 consisting of an analog to digital converter 34 and an analog offset circuit 33. The analog offset circuit Receive analog to digital converter (ADC) 34 and (since Three circuit) and increased profits digit before the target level (before-digital-gain target level). Based on the two inputs, the analog offset circuit 33 thus determines the input of the class I apostrophe A0I01 page 6 / page 27 0982057780-0 201114267 to digital conversion 2 (ADG) 34, making analog to digital conversion benefits ( The offset of the ADC) is eliminated (or compensated for the wide range of 'this pass to determine the dark signal offset value so that the final output can reach the (non-zero (four):) target level. The third (four) shows the implementation A detailed block diagram of the analog offset circuit 33. The analog offset circuit 33 uses the difference circuit 33G' to determine the difference between the two inputs, thereby driving an integrator 332 or a digital to analog converter (can). Generates an analog to digital converter is (ADC) 34. The resulting input is coupled to the __ stage circuit [0017] output - and (by adder 35) fed to analog to digital converter (10) c) 34 ° ❹ The first stage % path contains the loop 3, which is composed of the digital gain circuit 36 and the comparator/divider 37. It is closed by the (4) closed loop to form the loop 3. Where' comparator/divider 37 receives (from the final output) the target level and the output of digital gain circuit 36. Based on the two input 'comparator/divider 37, a digital pre-target level is generated to determine (second stage circuit) analogy to the output of the digital converter (ADC) 34. The third c-picture shows a detailed block diagram of the comparator/divider 37 of the present embodiment. Among them, the comparator/divider 37 uses a comparator 37 比较 to compare the final output with the target level. When the final output is greater than the target level, the comparison will stop the count of the up counter (up c〇unter) 372, thus generating the digital gain pre-target level. It is worth noting that this embodiment uses an up counter 372 instead of a digital divider because the latter takes up a large circuit area. However, in other embodiments, a digital divider can also be used in place of the upcount counter 372. [0018] According to the architecture of the image system 3, the required analog gain of the programmable gain amplifier (PGA) 32 098133777 Form No. A0101, page 7 / page 27 0982057780-0 201114267, and the digital gain setting of the digital gain circuit 36 are completed. When the (average) black-order signal has been received, loop 1 and loop 3 will operate independently, and the input and output of loop 2 can be determined simultaneously. As a result of the decision, Loop 2 can accumulate the required offset to match the target level. Thereby, the (non-zero level) optical black reference at the final output will be more realistic for the human eye and will simultaneously eliminate analog to digital converter (ADC) circuit offsets. [0020] The fourth figure shows the signal key of the image system 4 of the second embodiment of the present invention. The architecture of the real example is similar to the architecture of the first embodiment (third A diagram), so that the difference will be said. The same blocks as in the previous embodiment will have the same number π. For the second-stage circuit 'the analog offset circuit 3 of this embodiment receives the digital dark average (like ^ 丨 灶 灶 (10)), and the ^ digits increase the "target level ^ the number of dark averages can be analogy To the expected output of the digital converter 34, which can be set by the user. The first stage circuit 'loop 3 does not cover the digital gain circuit 36. The actual 3! The output and target levels are coupled to a digital offset = way 38' which rotates (4) to - adder 39, which in turn is coupled to the output of digital dish circuit 36. The implementation of digital offset circuit 38 can be similar to the third beta The analog shift circuit 33 shown in the figure. — [0021] 098133777, all three circuits can operate independently in the black level compensation mode. In the basin, the switch 1 is connected to the zero level. Loop 2 is connected to the digital dark average. In other words, loop 2 does not need to wait for the digital pre-emphasis target level provided by forced channel 3. After the compensation correction, the first-stage circuit (or the output of the loop is close to zero) Quasi-second circuit (戋第8页/Total 27 page form number A01 01 0982057780-0 201114267 The round-out of the loop 2) is close to the digital dark average, the output of the phase #路33. The output of the third-stage circuit (or loop 3) is close to the standard, and its value is equivalent to (digital dark average) * (digital gain) + (rounding of the digital offset circuit 38). Compared with the previous embodiment (third predicate), the black-order compensation of this embodiment operates faster because three circuit sentences can operate independently. Furthermore, the black-order compensation operation of this embodiment can eliminate the refinement error 'g is the digital offset circuit 38 can accurately match the target level. [0022] Ο [fifth figure shows the present issue" three real_ The signal link of the image line 5. The architecture of this embodiment is similar to the second embodiment (fourth figure) architecture, and the following will explain the difference point 'particularly the second stage circuit. The same block as the previous embodiment will be Represented by the same symbol. For the first stage circuit 'this embodiment uses the analog dark average (anal〇g off (8) directly fed to the adder 35 before the analog to digital converter (ADC) 34 instead of using the digital dark average This simplifies the second-level circuit. The analogy of the dark average is analogous to Bit converter UDC) 34 is
預期輸出，其值可大^A 了大約4於數位暗平均數。類似的情形 ’類比暗平均數可藉由實驗獲得或讀用者設定。本實 施例之黑階補償運作類似於第二實施例，亦即，三個迴 路於黑階轉料T可獨立運作。本實施 :=優於其他實施例，假設類比至數位轉換二 的偏移很小並侷限於一範圍内。 [0024] 098133777 =圖顯林發㈣⑽號鏈路。 本貫施例的架構係根基於第四圖架構再增加熱像素（h〇t 界控制次系統4〇 ’用以處理因製程非理想性所 t at像素效應。與先前實施例相同的方塊將以相同 第9頁/共27頁 表單編號A0101 0982057780-0 201114267 符號表示。 [0025] [0026] [0027] [0028] S二㈣㈣疋之後’各個暗像素信號（包含熱像 將輸入至影像系統6。臨界統計邏輯4GG (於數位領域 根據類比至數位轉換E (就）34的輸出以決定出 的（數位）熱像素臨界值。該決定之熱像素臨界值田 由數位至類比轉換器（DAC) 4。2)被轉換為類比形式： 接者此（類比）熱像素臨界值及暗像素信號被饋至 路！中斷控制電路404。當輸入之暗像素信號的位準超巧 該熱像素臨界值時，迴路1中斷控制電路404即控制開^ 以斷開迴路1，因而阻擔熱像素進入黑階補償^ 路30。 電 第七圖顯示本發明第五實施例之影像系統r的信號鏈路 本實施例的架構類似於第四實施例（第六圖）架構以 :將4明其差異點。與前_實施例相同的方塊將以相同 符號表示。 在本實施例中，熱像素臨界控制次系統Μ包含暗像素 =波H5G0，其於數位領域將所有暗像素信號予以平均 t其根據-統計上的熱像素臨界值將熱像素予以除外= 。該熱像素臨界值係根據類比至數位轉換器（觀）'、 輸出所決定。 的 熱像素臨界控m⑽還包含類比偏移電路⑽其* 似於第四圖_比偏移電路33，其根據數位暗平均數及# 類比至數位轉換器（取）34的輸出以提供輪人給類 數位轉換器（ADC) 34。相較於第六圖，本實施例的像素 098133777 表早編號A0101 第10頁/共27頁 〇982〇5??8〇. 201114267 臨界控制次系統50係運作於數位領域中。再者，本實施 例的熱像素控制不涉及可程式增益放大器（PGA) 32的增 盈設定。 [0029] 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離發明所揭示之精 神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 ❹ [0030] ❹ 【圖式簡單說明】 第一圖顯示影像感測器的信號鏈路。 第二圖顯示影像系統的信號鏈路。 第三A圖顯示本發明第一實施例之影像系統的信號鏈路。 第三B圖顯示第三A圖之類比偏移電路的詳細方塊圖。 第三C圖顯示第三A圖之比較器/除法器的詳細方塊圖。 第四圖顯示本發明第二實施例之影像系統的信號鏈路。 第五圖顯示本發明第三實施例之影像系統的信號鏈路。 第六圖顯示本發明第四實施例之影像系統的信號鏈路。 第七圖顯示本發明第五實施例之影像系統的信號鏈路。 [0031] 【主要元件符號說明】 1 信號鏈路 2 影像系統 3 影像系統 4 影像系統 5 影像系統 6 影像系統 7 影像系統 098133777 表單編號A0101 第11頁/共27頁 0982057780-0 201114267 10 黑階補償（BLC)電路 12 可程式增益放大器（PGA) 14 類比至數位轉換器（ADC) 16 可變數位增益之數位增益電路 20 黑階補償（BLC)電路 22 可程式增益放大器（PGA) 23 加法器 24 類比至數位轉換器（ADC) 26 數位增益電路 30 黑階補償（BLC)電路 31 加法器 32 可程式增益放大器（PGA) 33 類比偏移電路 330 差值電路 332 積分器/數位至類比轉換器（DAC) 34 類比至數位轉換器（ADC) 35 加法器 36 數位增益電路 37 比較器/除法器 370 比較器 372 上數計數器 38 數位偏移電路 39 加法器 40 熱像素臨界控制次系統 400 臨界統計邏輯 402 數位至類比轉換器（DAC) 098133777 表單編號A0101 第12頁/共27頁 0982057780-0 201114267 404 迴路1中斷控制電路 50 熱像素臨界控制次系統 500 暗像素平均濾波器 502 類比偏移電路 〇 098133777 表單編號A0101 第13頁/共27頁 0982057780-0The expected output, which can be as large as 4, is a dark average of 4 digits. A similar situation ‘ analog dark average can be set by experiment or by the reader. The black-order compensation operation of this embodiment is similar to that of the second embodiment, that is, three circuits can operate independently in the black-order transfer T. This implementation: = is superior to other embodiments, assuming that the offset from analog to digital conversion two is small and limited to a range. [0024] 098133777 = Figure shows Linfa (4) (10) link. The architecture of the present embodiment is based on the fourth graph architecture to add hot pixels (h〇t bound control subsystem 4〇' to handle the pixel effect due to process non-ideality. The same block as the previous embodiment will It is represented by the same page 9/total 27 page form number A0101 0982057780-0 201114267. [0025] [0028] After S (four) (four) 疋 'each dark pixel signal (including the thermal image will be input to the imaging system) 6. Critical statistical logic 4GG (in the digital domain according to the analog to digital conversion E (ie) 34 output to determine the (digital) thermal pixel threshold. The decision of the hot pixel threshold field digital to analog converter (DAC ) 4. 2) is converted to analog form: This (analog) hot pixel threshold and dark pixel signal are fed to the path! Interrupt control circuit 404. When the level of the input dark pixel signal is super-smart, the hot pixel is critical When the value is, the loop 1 interrupt control circuit 404 controls the opening to open the loop 1, thereby blocking the thermal pixel from entering the black level compensation circuit 30. The seventh figure shows the signal chain of the image system r of the fifth embodiment of the present invention. Luben embodiment The structure is similar to that of the fourth embodiment (sixth figure) in order to explain the difference. The same blocks as the previous embodiment will be denoted by the same symbols. In this embodiment, the hot pixel critical control subsystem Μ Dark pixel = wave H5G0, which averages all dark pixel signals in the digital domain. It excludes hot pixels according to the statistical hot pixel threshold. The thermal pixel threshold is based on analog to digital converter (view) The thermal pixel threshold control m(10) determined by the output also includes an analog offset circuit (10) which is similar to the fourth image-to-offset circuit 33, which is based on the digital dark average and the analogy to the digital converter (taken) 34 The output is provided to provide a digital converter (ADC) 34. Compared with the sixth figure, the pixel 098133777 of the present embodiment is numbered A0101, page 10, total 27 pages, 〇982〇5??8〇. 201114267 The critical control subsystem 50 operates in the digital domain. Furthermore, the thermal pixel control of this embodiment does not involve the gain setting of the programmable gain amplifier (PGA) 32. [0029] The above description is only preferred of the present invention. The embodiment is not used The scope of the patent application of the present invention is to be included in the scope of the following claims. ❹ [0030] ❹ [Simple Description] First The figure shows the signal link of the image sensor. The second figure shows the signal link of the image system. The third A shows the signal link of the image system of the first embodiment of the present invention. The third B shows the third A picture. A detailed block diagram of the analog offset circuit. The third C diagram shows a detailed block diagram of the comparator/divider of the third A diagram. The fourth figure shows the signal link of the image system of the second embodiment of the present invention. The fifth figure shows the signal link of the image system of the third embodiment of the present invention. Figure 6 is a diagram showing the signal chain of the image system of the fourth embodiment of the present invention. The seventh figure shows the signal link of the image system of the fifth embodiment of the present invention. [0031] [Signal Description of Main Components] 1 Signal Link 2 Image System 3 Image System 4 Image System 5 Image System 6 Image System 7 Image System 098133777 Form No. A0101 Page 11 of 27 0982057780-0 201114267 10 Black Level Compensation (BLC) Circuit 12 Programmable Gain Amplifier (PGA) 14 Analog to Digital Converter (ADC) 16 Variable Bit Gain Digital Gain Circuit 20 Black Level Compensation (BLC) Circuit 22 Programmable Gain Amplifier (PGA) 23 Adder 24 Analog to Digital Converter (ADC) 26 Digital Gain Circuit 30 Black Level Compensation (BLC) Circuit 31 Adder 32 Programmable Gain Amplifier (PGA) 33 Analog Offset Circuit 330 Difference Circuit 332 Integrator / Digital to Analog Converter ( DAC) 34 Analog to Digital Converter (ADC) 35 Adder 36 Digital Gain Circuit 37 Comparator/Divider 370 Comparator 372 Up Counter 38 Digital Offset Circuit 39 Adder 40 Thermal Pixel Critical Control Sub System 400 Critical Statistical Logic 402 Digital to Analog Converter (DAC) 098133777 Form Number A0101 Page 12 of 27 Page 0982057780-0 201114267 404 Loop 1 Interrupt Control Circuit 50 Thermal pixel critical control subsystem 500 Dark pixel averaging filter 502 Analog offset circuit 〇 098133777 Form number A0101 Page 13 of 27 0982057780-0