TWI383414B - Electrode structure and method for making same - Google Patents
Electrode structure and method for making same Download PDFInfo
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Description
本發明係關於一種電荷存儲裝置，特別係關於一種電極結構及其製備方法。 The present invention relates to a charge storage device, and more particularly to an electrode structure and a method of fabricating the same.
近年來，電子設備迅速發展，各種電子設備對於電荷存儲裝置之需求亦愈來愈大。隨著電子設備之小型化需求，對各種電子設備中常用之電容及電池等電荷存儲裝置亦提出小型化以及高電荷容量之需求。 In recent years, electronic devices have developed rapidly, and the demand for charge storage devices of various electronic devices has also increased. With the miniaturization of electronic devices, there is also a demand for miniaturization and high charge capacity for charge storage devices such as capacitors and batteries commonly used in various electronic devices.
傳統電容通常採用慣用之氧化物為材料且電極表面平坦，其電荷儲存容量非常有限。為提高電容之電荷容量，通常採用雙層或多層電容，從而於單位重量和單位體積中能比傳統電容儲存更多能量。若將電極層設置為多孔結構，則可增大電極表面積，進而增大電荷容量。惟，所述雙層或多層電容結構較為複雜，導致生產成本增加，其電極之電荷容量提高亦有限，使得電容性能受到限制。 Conventional capacitors are usually made of a conventional oxide and have a flat electrode surface, and their charge storage capacity is very limited. In order to increase the charge capacity of the capacitor, a double-layer or multi-layer capacitor is usually used, so that more energy can be stored in unit weight and unit volume than conventional capacitors. If the electrode layer is provided in a porous structure, the surface area of the electrode can be increased, thereby increasing the charge capacity. However, the double-layer or multi-layer capacitor structure is complicated, resulting in an increase in production cost, and the charge capacity of the electrode is also limited, which limits the performance of the capacitor.
另一種提高電容電荷容量之方法係將作為電容電極之金屬箔進行處理，其通過腐蝕所述金屬箔使其表面粗糙化，從而增大其表面積以提高電荷容量。惟，通過腐蝕處理以增大表面積通常需要增加蝕刻深度。因此需要用作電極之金屬箔厚度較大方能維持強度，且經常出現局部腐蝕、未腐蝕以及表面溶解等情況，表面形狀很難控制，其電荷容量之提昇並不理想。 Another method of increasing the capacitance of the capacitor is to treat the metal foil as a capacitor electrode by roughening the surface of the metal foil to increase its surface area to increase the charge capacity. However, it is often necessary to increase the etching depth by etching to increase the surface area. Therefore, the thickness of the metal foil used as the electrode is large to maintain the strength, and local corrosion, non-corrosion, and surface dissolution often occur, and the surface shape is difficult to control, and the increase in charge capacity is not satisfactory.
上述電極結構中，表面形狀不理想，電荷容量有限，不 能很好的滿足小型化以及高電荷容量之需求，不利於廣泛應用。 In the above electrode structure, the surface shape is not ideal, and the charge capacity is limited, and It can meet the needs of miniaturization and high charge capacity, which is not conducive to wide application.
有鑑於此，提供一種電荷容量高，表面具有預定形狀之電極結構實為必要。 In view of the above, it is necessary to provide an electrode structure having a high charge capacity and a predetermined shape on the surface.
以下，將以若干實施例說明一種電極結構。 Hereinafter, an electrode structure will be described in several embodiments.
以及通過這些實施例說明一種電極結構製備方法。 And an electrode structure preparation method will be described by these examples.
為實現上述內容，提供一種電極結構，其包括：一導電基板；其中，所述導電基板表面形成有複數個排列成預定圖案之微結構。所述電極結構還包括一層納米材料塗層，所述納米材料塗層覆蓋所述導電基板的微結構及所述導電基板表面。 In order to achieve the above, an electrode structure is provided, comprising: a conductive substrate; wherein the surface of the conductive substrate is formed with a plurality of microstructures arranged in a predetermined pattern. The electrode structure further includes a layer of nano material coating covering the microstructure of the conductive substrate and the surface of the conductive substrate.
所述微結構包括微小突起或微小凹陷。 The microstructures include minute protrusions or minute depressions.
優選，所述微結構直徑範圍為2~50奈米。 Preferably, the microstructure has a diameter ranging from 2 to 50 nanometers.
優選，所述微結構直徑範圍為10~40奈米。 Preferably, the microstructure has a diameter ranging from 10 to 40 nanometers.
優選，所述奈米材料塗層厚度為1~20奈米。 Preferably, the nano material coating has a thickness of 1 to 20 nm.
優選，所述奈米材料塗層厚度為2~10奈米。 Preferably, the nano material coating has a thickness of 2 to 10 nm.
以及，提供一種電極結構之製備方法，其包括下述步驟：提供一導電基板；於所述導電基板表面形成複數個排列成預定圖案之微結構。 And, a method for preparing an electrode structure, comprising the steps of: providing a conductive substrate; and forming a plurality of microstructures arranged in a predetermined pattern on the surface of the conductive substrate.
形成一層覆蓋所述導電基板的微結構及所述導電基板表面的納米材料塗層。 Forming a nano-material coating covering the microstructure of the conductive substrate and the surface of the conductive substrate.
所述微結構包括微小突起或微小凹陷。 The microstructures include minute protrusions or minute depressions.
優選，於所述導電基板表面形成複數個排列成預定圖案之微結構之方法包括奈米壓印(Nano-imprinting)及熱壓印(Hot Embossing)。 Preferably, a method of forming a plurality of microstructures arranged in a predetermined pattern on the surface of the conductive substrate comprises nano-imprinting and hot embossing.
相較於先前技術，本技術方案之電極結構表面設有複數個排列成預定圖案之微結構，其表面之預定圖案可根據需要進行設計；所述電極結構表面之微結構直徑範圍為奈米級，可大幅提高所述電極結構之表面積，且所述電極結構表面還可塗覆一層奈米材料塗層，進一步增加其表面積，從而使所述電極結構具有高電荷容量。綜上所述，本技術方案之電極結構具有電荷容量高，表面形狀可預定等優點。 Compared with the prior art, the surface of the electrode structure of the present technical solution is provided with a plurality of microstructures arranged in a predetermined pattern, and the predetermined pattern of the surface can be designed as needed; the microstructure of the surface of the electrode structure has a diameter range of nanometer. The surface area of the electrode structure can be greatly increased, and the surface of the electrode structure can also be coated with a coating of a nano material to further increase its surface area, so that the electrode structure has a high charge capacity. In summary, the electrode structure of the present technical solution has the advantages of high charge capacity, surface shape, and the like.
下面將結合附圖對本技術方案作進一步之詳細說明。 The technical solution will be further described in detail below with reference to the accompanying drawings.
請參閱第四圖，本技術方案實施例中提供一種電極結構100，其包括：一導電基板10，其中，所述導電基板10表面形成有複數個排列成預定圖案之微結構13，所述微結構13直徑範圍為2~50奈米。 Referring to the fourth embodiment, an embodiment of the present invention provides an electrode structure 100, including: a conductive substrate 10, wherein a surface of the conductive substrate 10 is formed with a plurality of microstructures 13 arranged in a predetermined pattern, the micro Structure 13 has a diameter ranging from 2 to 50 nm.
優選，所述導電基板10表面上包括一層奈米材料塗層15，所述奈米材料塗層15厚度為1~20奈米。 Preferably, the surface of the conductive substrate 10 includes a layer of nano material coating 15 having a thickness of 1 to 20 nm.
所述導電基板10之材料包括石墨或鋰、鋁、銅、銀、鎳、鎢、鉬等導電金屬及其合金，本實施例中所述導電基板10選用石墨為材料。 The material of the conductive substrate 10 includes graphite or a conductive metal such as lithium, aluminum, copper, silver, nickel, tungsten, molybdenum or the like and an alloy thereof. In the embodiment, the conductive substrate 10 is made of graphite.
所述微結構13包括微小突起或微小凹陷，本實施例中所述複數個微結構13於所述導電基板10表面形成均勻分佈之微小突起陣列。 The microstructures 13 include minute protrusions or minute depressions. In the embodiment, the plurality of microstructures 13 form an evenly distributed array of minute protrusions on the surface of the conductive substrate 10.
優選，所述微結構13直徑範圍為10~40奈米。 Preferably, the microstructure 13 has a diameter ranging from 10 to 40 nm.
所述奈米材料塗層15之材料包括碳奈米管(Carbon Nanotube)及奈米級氧化物粉體。 The material of the nano material coating 15 includes a carbon nanotube and a nano-sized oxide powder.
所述奈米級氧化物粉體材料包括氧化銦錫(ITO)、氧化鉻(CrOx)、氧化鈷(CoOx)、氧化鎳(NiOx)、氧化鐵(FeOy)、氧化鋁(Al2O3)、氧化鋅(ZnOx)、氧化矽(SiO2)、氧化鈦(TiO2)、氧化鋯(ZrOx)等等，其中，x值介於1與2之間，y值介於1與1.5之間。 The nano-sized oxide powder material includes indium tin oxide (ITO), chromium oxide (CrO x ), cobalt oxide (CoO x ), nickel oxide (NiO x ), iron oxide (FeO y ), and aluminum oxide (Al). 2 O 3 ), zinc oxide (ZnO x ), yttrium oxide (SiO 2 ), titanium oxide (TiO 2 ), zirconia (ZrO x ), etc., wherein the value of x is between 1 and 2, and the value of y is Between 1 and 1.5.
優選，所述奈米材料塗層15厚度為2~10奈米。 Preferably, the nano material coating 15 has a thickness of 2 to 10 nm.
請一併參閱第一圖至第四圖，本技術方案之實施例中還提供一種電極結構100之製備方法，其包括：提供一導電基板10；於所述導電基板10表面上形成複數個排列成預定圖案之微結構13，所述微結構13直徑範圍為2~50奈米。 Referring to the first to fourth embodiments, a method for fabricating the electrode structure 100 is further provided in the embodiment of the present invention, which includes: providing a conductive substrate 10; forming a plurality of arrangements on the surface of the conductive substrate 10. The microstructure 13 is in a predetermined pattern, and the microstructure 13 has a diameter ranging from 2 to 50 nm.
進一步，於所述導電基板10表面形成一層奈米材料塗層15，所述奈米材料塗層15厚度為1~20奈米。 Further, a layer of nano material coating 15 is formed on the surface of the conductive substrate 10, and the nano material coating layer 15 has a thickness of 1 to 20 nm.
所述導電基板10之材料包括石墨或鋰、鋁、銅、銀、鎳、鎢、鉬等導電金屬及其合金，本實施例中所述導電基板10選用石墨為材料。 The material of the conductive substrate 10 includes graphite or a conductive metal such as lithium, aluminum, copper, silver, nickel, tungsten, molybdenum or the like and an alloy thereof. In the embodiment, the conductive substrate 10 is made of graphite.
於所述導電基板10表面上形成複數個排列成預定圖案之微結構13之方法包括奈米壓印(Nano-imprinting)及熱壓印(Hot Embossing)。本實施例中採用奈米壓印方式，通過壓模11於所述導電基板10表面上壓印形成與壓模型面12形狀對應之均勻分佈之微結構13陣列。所述微結構13包括微小突起或微小凹陷，本實施例中所述微結構13為微小突起。 A method of forming a plurality of microstructures 13 arranged in a predetermined pattern on the surface of the conductive substrate 10 includes nano-imprinting and hot embossing. In this embodiment, a nano-imprinting method is adopted, and an array of uniformly distributed microstructures 13 corresponding to the shape of the pressed mold surface 12 is formed by stamping on the surface of the conductive substrate 10 by the stamper 11. The microstructure 13 includes minute protrusions or minute depressions, and the microstructures 13 in the embodiment are minute protrusions.
所述壓模11之製備可包括以下步驟：設計圖案，並製備具有該圖案之掩模，該圖案及圖案尺寸與所述導電基板10表面所需形成之微結構13對應；提供一矽基片，於該矽基片上塗覆一光阻層；採用上述掩模覆蓋於該矽基片上曝光顯影，所述矽基片上即形成預定圖案；於所述矽基片上通過電鑄鎳或磷化鎳；用氫氧化鉀等鹼液溶解去除矽；再用反應性離子蝕刻方法去除殘留之光阻層，得到壓模型面12與預定圖案相對應之壓模11。 The preparation of the stamper 11 may include the steps of: designing a pattern, and preparing a mask having the pattern corresponding to the microstructure 13 to be formed on the surface of the conductive substrate 10; providing a germanium substrate Applying a photoresist layer on the ruthenium substrate; exposing and developing the ruthenium substrate by using the mask, the predetermined pattern is formed on the ruthenium substrate; electroforming nickel or nickel phosphide on the ruthenium substrate The cerium is dissolved and removed by an alkali solution such as potassium hydroxide; and the residual photoresist layer is removed by a reactive ion etching method to obtain a stamper 11 having a pressed mold surface 12 corresponding to a predetermined pattern.
優選，所述微結構13直徑範圍為10~40奈米。 Preferably, the microstructure 13 has a diameter ranging from 10 to 40 nm.
於所、述導電基板10表面形成一層奈米材料塗層15之方法包括化學氣相沈積法(Chemical Vapour Deposition)、濺射法(Sputtering)及蒸鍍法(Evaporation)。 A method of forming a layer of nano-material coating 15 on the surface of the conductive substrate 10 includes chemical vapor deposition, sputtering, and evaporation.
所述奈米材料塗層15之材料包括碳奈米管(Carbon Nanotube)及奈米級氧化物粉體。 The material of the nano material coating 15 includes a carbon nanotube and a nano-sized oxide powder.
所述奈米級氧化物粉體包括氧化銦錫(ITO)、氧化鉻(CrOx)、氧化鈷(CoOx)、氧化鎳(NiOx)、氧化鐵(FeOy)、氧化鋁(Al2O3)、氧化鋅(ZnOx)、氧化矽(SiO2)、氧化鈦(TiO2)、氧化鋯(ZrOx)等等，其中x值介於1與2之間，y值介於1與1.5之間。 The nano-sized oxide powder includes indium tin oxide (ITO), chromium oxide (CrO x ), cobalt oxide (CoO x ), nickel oxide (NiO x ), iron oxide (FeO y ), and aluminum oxide (Al 2 ). O 3 ), zinc oxide (ZnO x ), yttrium oxide (SiO 2 ), titanium oxide (TiO 2 ), zirconia (ZrO x ), etc., wherein x is between 1 and 2, and y is between 1 Between 1.5 and 1.5.
優選，所述奈米材料塗層15厚度為2~10奈米。 Preferably, the nano material coating 15 has a thickness of 2 to 10 nm.
當然，本技術方案提供之電極結構不僅可用於電容，亦可應用於其他電荷存儲裝置，如作為鋰電池之電極。 Of course, the electrode structure provided by the technical solution can be used not only for a capacitor but also for other charge storage devices, such as an electrode of a lithium battery.
相較於先前技術，本技術方案之電極結構表面設有複數個排列成預定圖案之微結構，其表面之預定圖案可根據需要進行設計；所述電極結構表面之微結構直徑範圍為奈米級，可通過所述微結構尺寸大小調整所述電極結構之表面積，且所述電極結構表面還可塗覆一層奈米材料塗層，進一步增加其表面積，從而使所述電極結構達到所需之高電荷容量。綜上所述，本技術方案之電極結構具有電荷容量高，表面形狀可預定等優點。 Compared with the prior art, the surface of the electrode structure of the present technical solution is provided with a plurality of microstructures arranged in a predetermined pattern, and the predetermined pattern of the surface can be designed as needed; the microstructure of the surface of the electrode structure has a diameter range of nanometer. The surface area of the electrode structure can be adjusted by the microstructure size, and the surface of the electrode structure can also be coated with a coating of a nano material to further increase the surface area thereof, so that the electrode structure reaches a desired height. Charge capacity. In summary, the electrode structure of the present technical solution has the advantages of high charge capacity, surface shape, and the like.
綜上所述，本發明確已符合發明專利之要件，遂依法提出專利申請。惟，以上所述者僅為本發明之較佳實施方式，自不能以此限制本案之申請專利範圍。舉凡熟悉本案技藝之人士援依本發明之精神所作之等效修飾或變化，皆應涵蓋於以下申請專利範圍內。 In summary, the present invention has indeed met the requirements of the invention patent, and has filed a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and it is not possible to limit the scope of the patent application of the present invention. Equivalent modifications or variations made by persons skilled in the art in light of the spirit of the invention are intended to be included within the scope of the following claims.
100‧‧‧電極結構 100‧‧‧electrode structure
10‧‧‧導電基板 10‧‧‧Electrical substrate
11‧‧‧壓模 11‧‧‧Molding
12‧‧‧壓模型面 12‧‧‧ Pressure model surface
13‧‧‧微結構 13‧‧‧Microstructure
15‧‧‧奈米材料塗層 15‧‧‧Nano material coating
第一圖係本技術方案實施例導電基板壓印前之示意圖。 The first figure is a schematic diagram of the conductive substrate before the imprinting of the embodiment of the present technical solution.
第二圖係本技術方案實施例導電基板壓印示意圖。 The second figure is a schematic diagram of the imprinting of the conductive substrate in the embodiment of the present technical solution.
第三圖係本技術方案實施例導電基板壓印後之示意圖。 The third figure is a schematic view of the conductive substrate after the embossing of the conductive substrate of the embodiment of the present technical solution.
第四圖係本技術方案實施例導電基板塗覆奈米材料塗層後之示意圖。 The fourth figure is a schematic diagram of the conductive substrate coated with the nano material coating in the embodiment of the present technical solution.
100‧‧‧電極結構 100‧‧‧electrode structure
10‧‧‧導電基板 10‧‧‧Electrical substrate
13‧‧‧微結構 13‧‧‧Microstructure
15‧‧‧奈米材料塗層 15‧‧‧Nano material coating
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| US20050224779A1 (en) * | 2003-12-11 | 2005-10-13 | Wang Zhong L | Large scale patterned growth of aligned one-dimensional nanostructures |
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