TWI382420B - Storage device using multi-level flash memory as single flash memory and method for the same - Google Patents
Storage device using multi-level flash memory as single flash memory and method for the same Download PDFInfo
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- G—PHYSICS
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
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- G—PHYSICS
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- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
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- G11C2211/5641—Multilevel memory having cells with different number of storage levels
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Description
本發明係有關一種增加快閃記憶體壽命之儲存裝置以及方法，更具體來說，係關於一種利用多值式快閃記憶體實施單值式快閃記憶體功能之儲存裝置以及方法。The present invention relates to a storage device and method for increasing the life of a flash memory, and more particularly to a storage device and method for implementing a single-valued flash memory function using multi-valued flash memory.
快閃記憶體(Flash Memory)為一非揮發性(non－volatile)之記憶體，在電源關閉時仍可保存先前寫入的資料。與其他儲存媒體(如硬碟、軟碟或磁帶等)比較，快閃記憶體有體積小、重量輕、防震動、存取時無機械動作延遲與低耗電等特性。由於快閃記憶體的這些特性，因此近年來消費性電子產品、嵌入式系統或可攜式電腦等資料儲存媒體皆大量採用。Flash Memory is a non-volatile memory that retains previously written data when the power is turned off. Compared with other storage media (such as hard disk, floppy disk or tape), the flash memory has the characteristics of small size, light weight, anti-vibration, no mechanical action delay and low power consumption during access. Due to these characteristics of flash memory, in recent years, data storage media such as consumer electronics, embedded systems or portable computers have been widely adopted.
快閃記憶體主要可分兩種：NOR型快閃記憶體與NAND型快閃記憶體。NOR型快閃記憶體的優點為低電壓、存取快且穩定性高，因此已被大量應用於可攜式電子裝置及電子通訊裝置，諸如個人電腦(Personal Computer，PC)、行動電話、個人數位助理(Personal Digital Assistance，PDA)以及轉頻器(Set－top Box，STB)等。NAND型快閃記憶體是專門為資料儲存用途而設計之快閃記憶體，通常應用於儲存並保存大量的資料的儲存媒介，如可攜式記憶卡(SD Memory Card，Compact Flash Card，Memory Stick等等)。當快閃記憶體在執行寫入(Write)、抹除(Erase)及讀取(Read)運作時，可透過內部的電容耦合(Coupling)有效地控制漂浮閘(Floating Gate)上電荷 的移動，進而使得該漂浮閘可根據該電荷的移動而決定下層電晶體的閥值電壓。換言之，當負電子注入該漂浮閘時，該漂浮閘的儲存狀態便會從1變成0；而當負電子從該漂浮閘移走後，該漂浮閘的儲存狀態便會從0變成1。There are two main types of flash memory: NOR flash memory and NAND flash memory. NOR-type flash memory has the advantages of low voltage, fast access and high stability, so it has been widely used in portable electronic devices and electronic communication devices, such as personal computers (PCs), mobile phones, and individuals. Personal Digital Assistance (PDA) and Set-top Box (STB). NAND flash memory is a flash memory designed for data storage. It is usually used as a storage medium for storing and storing large amounts of data, such as a portable memory card (SD Memory Card, Compact Flash Card, Memory Stick). and many more). When the flash memory performs Write, Erase, and Read operations, it can effectively control the charge on the Floating Gate through internal capacitive coupling (Coupling). The movement, in turn, allows the floating gate to determine the threshold voltage of the lower transistor based on the movement of the charge. In other words, when negative electrons are injected into the floating gate, the storage state of the floating gate will change from 1 to 0; and when the negative electrons are removed from the floating gate, the storage state of the floating gate will change from 0 to 1.
NAND快閃記憶體內部由複數個區塊(block)所組成。每一區塊包含複數個頁(page)，每一頁則可分為資料儲存區(data area)以及備用區(spare area)，資料儲存區的資料容量可為512個位元組，用來儲存使用資料，備用區的資料容量可為64個位元組，用來儲存錯誤修正碼(Error Correction Code,ECC)。與NOR型快閃記憶體不同，NAND型快閃記憶體之讀取與寫入單位皆為一個頁，資料讀寫的動作必須先向晶片發出讀取或寫入指令後才可進行。The NAND flash memory is composed of a plurality of blocks. Each block contains a plurality of pages, each of which can be divided into a data area and a spare area. The data storage area can have a data capacity of 512 bytes. The usage data is stored, and the data capacity of the spare area can be 64 bytes for storing the Error Correction Code (ECC). Unlike the NOR flash memory, the read and write units of the NAND flash memory are all one page, and the data read and write operations must be performed after a read or write command is issued to the wafer.
NAND快閃記憶體有可分為兩種：一種是多值式(Multi－level cell，MLC)快閃記憶體，另一種則是單值式(Single－level cell，SLC)快閃記憶體。請參閱第1圖以及第2圖，第1圖係NAND快閃記憶體之實體記憶單元之結構圖。第2圖係單值式快閃記憶體之實體記憶單元之臨界電壓與浮動閘極電荷分布之示意圖。NAND快閃記憶體實體記憶單元54包含一浮動閘極(Floating Gate)542、一源極544、一汲極546以及一閘極548。當電荷由源極544流入實體記憶單元54時，浮動閘極542儲存不同電位(Level)的電荷而使得實體記憶單元54的臨界電壓(threshold voltage)Vt變動，以呈現出不同的存儲狀態。如第2圖所示，舉例來說，單值式快閃記憶體之實體記憶單元54的臨界電壓大致上以4伏特為準，4伏特以上表示該實體記憶單 元54即判定為邏輯值為”0”，4伏特以下即判定為邏輯值為”1”。NAND flash memory can be divided into two types: one is multi-level cell (MLC) flash memory, and the other is single-level cell (SLC) flash memory. Please refer to FIG. 1 and FIG. 2, which is a structural diagram of a physical memory unit of a NAND flash memory. Figure 2 is a schematic diagram of the threshold voltage and floating gate charge distribution of a physical memory cell of a single-valued flash memory. The NAND flash memory physical memory unit 54 includes a floating gate 542, a source 544, a drain 546, and a gate 548. When charge flows from the source 544 into the physical memory unit 54, the floating gate 542 stores different levels of charge such that the threshold voltage Vt of the physical memory unit 54 varies to exhibit different storage states. As shown in FIG. 2, for example, the threshold voltage of the physical memory unit 54 of the single-valued flash memory is substantially 4 volts, and the physical memory list is represented by 4 volts or more. The element 54 determines that the logical value is "0", and if it is 4 volts or less, it is determined that the logical value is "1".
請參閱第3圖，第3圖係多值式快閃記憶體之實體記憶單元之臨界電壓Vt與浮動閘極電荷分布之示意圖。多值式快閃記憶體之實體記憶單元54的臨界電壓則大致上3.5伏特以下判定為邏輯值為”11”、3.5伏特~4伏特判定為邏輯值為”10”、4伏特~5.5伏特判定為邏輯值為”01”，5.5伏特以上即判定為邏輯值為”00”。多值式快閃記憶體的實體記憶單元資料密度比較大，且多值式NAND快閃記憶體連續存取速度(Access Time)是要比單值式NAND快閃記憶體快。此外，單值式NAND快閃記憶體架構可以存取10萬次，而多值式NAND快閃記憶體架構只能承受約1萬次的存取，所以多值式NAND快閃記憶體的使用壽命較短。再者，多值式NAND快閃記憶體能耗比單值式NAND快閃記憶體高約15%左右的電流消耗。Please refer to FIG. 3, which is a schematic diagram of the threshold voltage Vt and the floating gate charge distribution of the physical memory unit of the multi-valued flash memory. The threshold voltage of the physical memory unit 54 of the multi-valued flash memory is determined to be a logical value of "11" substantially below 3.5 volts, and a logical value of "10" and 4 volts to 5.5 volts is determined as 3.5 volts to 4 volts. The logical value is "01", and it is determined that the logical value is "00" above 5.5 volts. The multi-value flash memory has a relatively large data density of the physical memory unit, and the multi-value NAND flash memory access speed (Access Time) is faster than the single-valued NAND flash memory. In addition, the single-value NAND flash memory architecture can access 100,000 times, while the multi-value NAND flash memory architecture can only withstand about 10,000 accesses, so the use of multi-valued NAND flash memory Short life. Furthermore, the multi-value NAND flash memory consumes about 15% more current than the single-value NAND flash memory.
但是單值式NAND快閃記憶體的價格較多值式NAND快閃記憶體高，舉例來說，2G容量大小的單值式NAND快閃記憶體比4G容量大小的多值式NAND快閃記憶體貴，所以在價格上來說，多值式快閃記憶體NAND仍有其使用上的優勢。However, the price of single-valued NAND flash memory is higher than that of NAND flash memory. For example, single-value NAND flash memory with 2G capacity is more than 4G capacity multi-value NAND flash memory. It is expensive, so in terms of price, multi-value flash memory NAND still has its advantages in use.
本發明之目的係利用多值式NAND快閃記憶體來模擬單值式NAND快閃記憶體，以達到成本上的優勢。The object of the present invention is to use a multi-valued NAND flash memory to simulate a single-valued NAND flash memory to achieve cost advantages.
本發明提供一種快閃記憶體儲存裝置，其包含一多值式快閃記憶體、一讀取控制單元以及一寫入控制單元。該多值式快閃記憶體包含複數 個實體記憶單元，該複數個實體記憶單元形成一第一頁面以及一第二頁面。該寫入控制單元用來於接收一第一請求將一第一資料寫入該第一頁面時，將該第一資料寫入該第一頁面並將該第一資料複製為一第二資料，再將該第二資料寫入該第二頁面。每一實體記憶單元的臨界電壓範圍包含四個電壓區間，每一電壓區間用來表示二位元資料，當該二位元資料儲存於該等實體記憶單元之一第一實體記憶單元，使得該第一實體記憶單元之臨界電壓介於一第一電壓區間以及一第二電壓區之間時，判定該二位元資料符合一第一邏輯值，當該二位元資料儲存於該等實體記憶單元之一第二實體記憶單元，使得該第二實體記憶單元之臨界電壓介於一第三電壓區間以及一第四電壓區之間時，判定該二位元資料符合一第二邏輯值。The invention provides a flash memory storage device comprising a multi-value flash memory, a read control unit and a write control unit. The multi-valued flash memory includes a plurality of The physical memory unit, the plurality of physical memory units form a first page and a second page. The write control unit is configured to: when receiving a first request, write a first data to the first page, write the first data to the first page, and copy the first data into a second data, The second data is then written to the second page. The threshold voltage range of each physical memory unit includes four voltage intervals, each voltage interval is used to represent two-bit data, and when the two-bit data is stored in one of the first physical memory units of the physical memory unit, When the threshold voltage of the first physical memory unit is between a first voltage interval and a second voltage region, determining that the binary data meets a first logic value, and when the binary data is stored in the physical memory And a second physical memory unit, wherein when the threshold voltage of the second physical memory unit is between a third voltage interval and a fourth voltage region, determining that the binary data conforms to a second logic value.
本發明另提供一種利用多值式快閃記憶體實施單值式快閃記憶體功能之方法，其包含下列步驟：(a)提供一多值式快閃記憶體，其包含複數個實體記憶單元，每一實體記憶單元包含一第一記憶區以及一第二記憶區，該第一記憶區以及該第二記憶區係用來儲存一位元之資料，該複數個實體記憶單元之每一第一記憶區形成一第一頁面，該複數個實體記憶單元之每一第二記憶區形成一第二頁面；(b)當接收一第一請求將一第一資料寫入該第一頁面時，將該第一資料寫入該第一頁面並將該第一資料複製為一第二資料，再將該第二資料寫入該第二頁面；以及(c)當接收一第二請求以自該第一頁面讀取該第一資料時，偵測該第一 頁面所儲存之該第一資料以及該第二頁面所儲存之該第二資料，以讀取該第一資料。The present invention further provides a method for implementing a single-valued flash memory function using multi-valued flash memory, comprising the steps of: (a) providing a multi-valued flash memory comprising a plurality of physical memory cells Each physical memory unit includes a first memory area and a second memory area, wherein the first memory area and the second memory area are used to store data of one bit, each of the plurality of physical memory units a memory area forms a first page, each second memory area of the plurality of physical memory units forms a second page; (b) when receiving a first request to write a first data to the first page, Writing the first data to the first page and copying the first data into a second data, and then writing the second data to the second page; and (c) receiving a second request from the The first page detects the first data, and detects the first The first data stored in the page and the second data stored in the second page are used to read the first data.
依據本發明之方法，該第一資料包含一第一位元，該第二資料包含一第二位元，步驟(c)另包含：當該第一位元為一第一邏輯值且該第二位元為一第二邏輯值時，將該第一資料判讀為該第一邏輯值；當該第一位元為該第一邏輯值且該第二位元為該第一邏輯值時，將該第一資料判讀為該第一邏輯值；當該第一位元為該第二邏輯值且該第二位元為該第一邏輯值時，將該第一資料判讀為該第二邏輯值；以及當該第一位元為該第二邏輯值且該第二位元為該第二邏輯值時，將該第一資料判讀為該第二邏輯值。According to the method of the present invention, the first data includes a first bit, the second data includes a second bit, and the step (c) further includes: when the first bit is a first logical value and the first When the binary bit is a second logical value, the first data is interpreted as the first logical value; when the first bit is the first logical value and the second bit is the first logical value, Determining the first data as the first logic value; when the first bit is the second logic value and the second bit is the first logic value, the first data is interpreted as the second logic a value; and when the first bit is the second logical value and the second bit is the second logical value, the first data is interpreted as the second logical value.
請參閱第4圖，第4圖係本發明之儲存裝置10以及主機5之功能方塊圖。儲存裝置10包含一快閃記憶體20、一存取介面30以及一寫入控制單元40以及一讀取控制單元50。快閃記憶體20可為一多值式NAND快閃記憶體，其包含複數個頁面22，用來儲存資料。Please refer to FIG. 4, which is a functional block diagram of the storage device 10 and the host 5 of the present invention. The storage device 10 includes a flash memory 20, an access interface 30, a write control unit 40, and a read control unit 50. The flash memory 20 can be a multi-valued NAND flash memory that includes a plurality of pages 22 for storing data.
請一併參閱第4圖、第5圖以及第6圖，第5圖係本發明之利用多值式快閃記憶體實施單值式快閃記憶體功能之方法流程圖。第6圖係第4圖之快閃記憶體20之頁面存取資料時之示意圖。本發明之方法步驟如下： 步驟500：提供一多值式快閃記憶體，其包含複數個實體記憶單元，該複數個實體記憶單元形成一第一頁面與一第二頁面，每一實體記憶單元的臨界電壓範圍包含四個電壓區間，每一電壓區間用來表示二位元資料。Please refer to FIG. 4, FIG. 5 and FIG. 6 together. FIG. 5 is a flow chart of a method for implementing a single-valued flash memory function using multi-valued flash memory according to the present invention. Fig. 6 is a view showing the page access data of the flash memory 20 of Fig. 4. The steps of the method of the present invention are as follows: Step 500: Providing a multi-valued flash memory, comprising a plurality of physical memory units, the plurality of physical memory units forming a first page and a second page, each of the physical memory cells having a threshold voltage range of four Voltage interval, each voltage interval is used to represent two-bit data.
步驟502：當接收一第一請求將一第一資料寫入該第一頁面時，將該第一資料寫入該第一頁面並將該第一資料複製為一第二資料，再將該第二資料寫入該第二頁面。Step 502: When receiving a first request to write a first data to the first page, writing the first data to the first page and copying the first data into a second data, and then Two data is written to the second page.
步驟504：當接收一第二請求以自該第一頁面讀取該第一資料時，偵測該第一頁面所儲存之該第一資料以及該第二頁面所儲存之該第二資料，以讀取該第一資料。Step 504: When receiving a second request to read the first data from the first page, detecting the first data stored in the first page and the second data stored in the second page, Read the first data.
步驟506：當該第一位元為一第一邏輯值且該第二位元為一第二邏輯值時，將該第一資料判讀為該第一邏輯值。Step 506: When the first bit is a first logic value and the second bit is a second logic value, the first data is interpreted as the first logic value.
步驟508：當該第一位元為該第一邏輯值且該第二位元為該第一邏輯值時，將該第一資料判讀為該第一邏輯值。Step 508: When the first bit is the first logic value and the second bit is the first logic value, the first data is interpreted as the first logic value.
步驟510：當該第一位元為該第二邏輯值且該第二位元為該第一邏輯值時，將該第一資料判讀為該第二邏輯值。Step 510: When the first bit is the second logic value and the second bit is the first logic value, the first data is interpreted as the second logic value.
步驟512：當該第一位元為該第二邏輯值且該第二位元為該第二邏輯值時，將該第一資料判讀為該第二邏輯值。Step 512: When the first bit is the second logic value and the second bit is the second logic value, the first data is interpreted as the second logic value.
快閃記憶體儲存裝置10內的多值式快閃記憶體20包含一第一頁面22a以及一第二頁面22b(步驟500)。實體上，多值式快閃記憶體20包含複數個實體記憶單元(cell)C，複數個實體記憶單元C形成一第一頁面22a和一第二 頁面22b。快閃記憶體儲存裝置10連結到主機5時，使用者可以透過主機5下達指令以存取快閃記憶體儲存裝置10。當使用者下達寫入指令後，存取介面30會對快閃記憶體儲存裝置10發送一寫入請求，以將第一資料寫入至快閃記憶體儲存裝置10內(步驟502)。寫入控制單元40會依據該寫入請求將該第一資料寫入指定的頁面22，例如第一頁面22a。同時寫入控制單元40會將該第一資料複製為一第二資料，再將該第二資料寫入第二頁面22b。The multi-valued flash memory 20 in the flash memory storage device 10 includes a first page 22a and a second page 22b (step 500). Physically, the multi-valued flash memory 20 includes a plurality of physical memory cells C, and the plurality of physical memory cells C form a first page 22a and a second Page 22b. When the flash memory storage device 10 is connected to the host 5, the user can issue an instruction through the host 5 to access the flash memory storage device 10. After the user issues the write command, the access interface 30 sends a write request to the flash memory storage device 10 to write the first data into the flash memory storage device 10 (step 502). The write control unit 40 writes the first material to the specified page 22, such as the first page 22a, in accordance with the write request. At the same time, the write control unit 40 copies the first data into a second data, and writes the second data to the second page 22b.
請一併參閱第3圖至第6圖。當使用者下達讀取指令以讀取該第一資料時，存取介面30會對快閃記憶體儲存裝置10發送一讀取請求，以自第一頁面22a讀取該第一資料，此時讀取控制單元50會偵測第一頁面22a所儲存之該第一資料以及第二頁面22b所儲存之該第二資料(步驟504)。依據第3圖以及第5圖所示，第一頁面22a的第一資料的第一位元DA1，與第二頁面22b的第二資料的第二位元DB1在實體上皆屬於同一實體記憶單元C1，同理，第一頁面22a的第一資料的第n位元DAn，與第二頁面22b的第二資料的第n位元DBn在實體上亦屬於同一實體記憶單元Cn，為便於說明，本實施例n＝9。所以讀取控制單元50在判讀實體記憶單元C1的資料內容時，是依據實體記憶單元的臨界電壓值來決定所儲存資料的邏輯值。一般情形下，實體記憶單元C1的臨界電壓會大於5.5V(亦即電壓區間d)，使其儲存的資料可判讀為邏輯值”00”；實體記憶單元C2的臨界電壓會小於2.5V(亦即電壓區間a)，使其儲存的資料可判讀為邏輯值”11”。之後，讀取控制單元50會分別把實體記憶單元C1、C2的資料輸出為邏輯值”0”和”1” (步驟508、512)。但是倘若實體記憶單元C3的臨界電壓稍微偏高，使得對應到邏輯值”00”的臨界電壓略低於5.5V(參考第3圖所示電壓區間c)，此時，讀取控制單元50會把其儲存的資料判讀為邏輯值”01”，但是把實體記憶單元C3的資料輸出為邏輯值”0”(步驟506)。倘若實體記憶單元C5的臨界電壓稍微偏低，使得對應到邏輯值”11”的臨界電壓略高於2.5V(參考第3圖所示電壓區間b)，此時，讀取控制單元50會把其儲存的資料判讀為邏輯值”10”，但是把實體記憶單元C5的資料輸出為邏輯值”1”(步驟510)。換言之，邏輯值”1”的臨界電壓範圍保持在4伏特以下，而邏輯值”0”的臨界電壓範圍保持在4伏特以上。除此之外，以第3圖為例，原先的第一資料的內容為”010010100”，即使實體記憶單元(例如C3、C5)的臨界電壓出現些微的增加或減少，第一資料的輸出還是保持”010010100”，而不會出現錯誤的輸出。Please refer to Figures 3 to 6 together. When the user issues a read command to read the first data, the access interface 30 sends a read request to the flash memory storage device 10 to read the first data from the first page 22a. The read control unit 50 detects the first data stored in the first page 22a and the second data stored in the second page 22b (step 504). According to FIG. 3 and FIG. 5, the first bit DA1 of the first material of the first page 22a and the second bit DB1 of the second material of the second page 22b are physically belonging to the same physical memory unit. C1. Similarly, the nth bit DAn of the first material of the first page 22a and the nth bit DBn of the second material of the second page 22b also belong to the same physical memory unit Cn, for convenience of explanation. This embodiment n=9. Therefore, when reading the data content of the physical memory unit C1, the read control unit 50 determines the logical value of the stored data according to the threshold voltage value of the physical memory unit. Under normal circumstances, the threshold voltage of the physical memory unit C1 will be greater than 5.5V (that is, the voltage interval d), so that the stored data can be interpreted as a logic value "00"; the threshold voltage of the physical memory unit C2 will be less than 2.5V (also That is, the voltage interval a) can be interpreted as a logical value "11". Thereafter, the read control unit 50 outputs the data of the physical memory cells C1 and C2 to logical values "0" and "1", respectively. (Steps 508, 512). However, if the threshold voltage of the physical memory cell C3 is slightly higher, so that the threshold voltage corresponding to the logic value "00" is slightly lower than 5.5V (refer to the voltage interval c shown in FIG. 3), at this time, the read control unit 50 will The stored data is interpreted as a logical value "01", but the data of the physical memory unit C3 is output as a logical value of "0" (step 506). If the threshold voltage of the physical memory cell C5 is slightly lower, so that the threshold voltage corresponding to the logic value "11" is slightly higher than 2.5V (refer to the voltage interval b shown in FIG. 3), at this time, the read control unit 50 will The stored data is interpreted as a logical value "10", but the data of the physical memory unit C5 is output as a logical value "1" (step 510). In other words, the threshold voltage range of the logic value "1" is kept below 4 volts, and the threshold voltage range of the logic value "0" is kept above 4 volts. In addition, taking Figure 3 as an example, the content of the original first data is “010010100”, even if the threshold voltage of the physical memory unit (such as C3, C5) slightly increases or decreases, the output of the first data is still Keep "010010100" without erroneous output.
綜上所述，在每一次資料寫入過程中，一筆資料除了寫入至第一頁面外，還會再將同一筆資料再寫入第二頁面。而在讀取這筆資料時，則會依據分別儲存在第一以及第二頁面的這兩筆資料來決定該資料值。所以本發明是利用多值式快閃記憶體來模擬實施單值式快閃記憶體功能。這樣一來，可以降低生產快閃記憶體儲存裝置之成本。In summary, in each data writing process, in addition to writing a piece of data to the first page, the same data will be written to the second page. When the data is read, the data values are determined based on the two data stored on the first and second pages, respectively. Therefore, the present invention utilizes multi-valued flash memory to simulate the implementation of a single-valued flash memory function. In this way, the cost of producing a flash memory storage device can be reduced.
綜合以上所述，雖然本發明已較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作各種更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。In view of the above, the preferred embodiments of the present invention are disclosed above, but are not intended to limit the present invention, and various modifications and refinements can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
10‧‧‧儲存裝置10‧‧‧Storage device
20‧‧‧快閃記憶體20‧‧‧Flash memory
30‧‧‧存取介面30‧‧‧Access interface
40‧‧‧寫入控制單元40‧‧‧Write control unit
50‧‧‧讀取控制單元50‧‧‧Read control unit
22‧‧‧頁面22‧‧‧ page
542‧‧‧浮動閘極542‧‧‧Floating gate
544‧‧‧源極544‧‧‧ source
545‧‧‧氧化薄膜545‧‧‧Oxide film
546‧‧‧汲極546‧‧‧汲polar
548‧‧‧閘極548‧‧‧ gate
22a‧‧‧第一頁面22a‧‧‧ first page
22b‧‧‧第二頁面22b‧‧‧ second page
24a‧‧‧第一記憶區24a‧‧‧First Memory Area
24b‧‧‧第二記憶區24b‧‧‧Second memory area
C、C1－C9‧‧‧實體記憶單元C, C1-C9‧‧‧ physical memory unit
第1圖係NAND快閃記憶體之實體記憶單元之結構圖。Figure 1 is a block diagram of a physical memory unit of a NAND flash memory.
第2圖係單值式快閃記憶體之實體記憶單元之臨界電壓與浮動閘極電荷分布之示意圖。Figure 2 is a schematic diagram of the threshold voltage and floating gate charge distribution of a physical memory cell of a single-valued flash memory.
第3圖係多值式快閃記憶體之實體記憶單元之臨界電壓與浮動閘極電荷分布之示意圖。Figure 3 is a schematic diagram of the threshold voltage and floating gate charge distribution of a physical memory cell of a multi-valued flash memory.
第4圖係本發明之儲存裝置之功能方塊圖。Figure 4 is a functional block diagram of the storage device of the present invention.
第5圖係本發明之利用多值式快閃記憶體實施單值式快閃記憶體功能之方法流程圖。Figure 5 is a flow chart of a method for implementing a single-valued flash memory function using multi-valued flash memory according to the present invention.
第6圖係第4圖之快閃記憶體之頁面存取資料時之示意圖。Figure 6 is a schematic diagram of the page access data of the flash memory of Figure 4.
22a‧‧‧第一頁面22a‧‧‧ first page
22b‧‧‧第二頁面22b‧‧‧ second page
C、C1－C9‧‧‧實體記憶單元C, C1-C9‧‧‧ physical memory unit
Claims (4)
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| US12/276,489 US20100049904A1 (en) | 2008-08-22 | 2008-11-24 | Storage device using a multi-level flash memory as a single flash memory and method for the same |
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| JP5364807B2 (en) * | 2011-06-08 | 2013-12-11 | パナソニック株式会社 | MEMORY CONTROLLER AND NONVOLATILE MEMORY DEVICE |
| US9543019B2 (en) * | 2012-12-11 | 2017-01-10 | Intel Corporation | Error corrected pre-read for upper page write in a multi-level cell memory |
| CN103927262A (en) * | 2014-03-21 | 2014-07-16 | 深圳市硅格半导体有限公司 | Flash memory physical block control method and flash memory physical block control device |
| US11966626B2 (en) * | 2022-05-13 | 2024-04-23 | Western Digital Technologies, Inc. | Hybrid terabytes written (TBW) storage systems |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200963A (en) * | 1990-06-26 | 1993-04-06 | The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration | Self-checking on-line testable static ram |
| US5515317A (en) * | 1994-06-02 | 1996-05-07 | Intel Corporation | Addressing modes for a dynamic single bit per cell to multiple bit per cell memory |
| US6122193A (en) * | 1998-06-01 | 2000-09-19 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory capable of storing 1-bit data or multi-bit data |
| TWI224792B (en) * | 2001-05-22 | 2004-12-01 | Hitachi Ltd | Non volatile data storage system and data storaging method |
| TW200929224A (en) * | 2007-12-31 | 2009-07-01 | Phison Electronics Corp | Data writing method for flash memory and controller thereof |
-
2008
- 2008-08-22 TW TW097132295A patent/TWI382420B/en active
- 2008-11-24 US US12/276,489 patent/US20100049904A1/en not_active Abandoned
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5200963A (en) * | 1990-06-26 | 1993-04-06 | The United States Of America As Represented By The Administrator, National Aeronautics And Space Administration | Self-checking on-line testable static ram |
| US5515317A (en) * | 1994-06-02 | 1996-05-07 | Intel Corporation | Addressing modes for a dynamic single bit per cell to multiple bit per cell memory |
| US6122193A (en) * | 1998-06-01 | 2000-09-19 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory capable of storing 1-bit data or multi-bit data |
| TWI224792B (en) * | 2001-05-22 | 2004-12-01 | Hitachi Ltd | Non volatile data storage system and data storaging method |
| TW200929224A (en) * | 2007-12-31 | 2009-07-01 | Phison Electronics Corp | Data writing method for flash memory and controller thereof |
| US20090172256A1 (en) * | 2007-12-31 | 2009-07-02 | Phison Electronics Corp. | Data writing method for flash memory, and flash memory controller and storage device thereof |
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