TWI377655B - Method for manufacturing coreless package substrate - Google Patents
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- TWI377655B TWI377655B TW98101691A TW98101691A TWI377655B TW I377655 B TWI377655 B TW I377655B TW 98101691 A TW98101691 A TW 98101691A TW 98101691 A TW98101691 A TW 98101691A TW I377655 B TWI377655 B TW I377655B
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1377655 六、發明說明： 【發明所屬之技術領域】 於一 除式臨時核心層進行增層ί程:無 本發明侧於-種無核心輯基板的製造， -種利用可移 · 基板的製造方法 【先前技術】 現今半導體封裝產業為了滿足各種高密度封裝之 逐漸發展出各種不同型式之封裝構造，其中常見 ^ ^ubstrateK封裝構造包含球格陣酸裝構造_ _、抓ς， 封裝構^in _啊，PGA)、接點陣列封 ^構造(land gnd array，LGA)或基板上晶片封裝構造加㈣⑽ ^1^0心在上雜裝構造+ ’職板之—上表面承載有 ^ 了晶片並經由打線b〇nding)或凸塊(bumPing)製程 個接墊電性連接至該基板之上表面的數個焊 ，’該基板之-下表面亦必需提供大量的焊塾，以焊接數個輪 出端。通常，該基板係-多層電路板，其除了在上、下表面 供表面電路層以形成所需焊墊之外，其内部亦具有 路層及數辦通孔，以重新安排上、下表面的焊墊之連接】 。因此，如何製造具有多層之職絲板， 業之一重要關鍵技術。 舉例而言’請參照第1圖所示，其揭示—種習用封裝 10之構造，其令該封裝基板10係以一核心層(c〇re iayer)n為 中心’並藉由增層法(build-up)在該核心層11之兩侧分別向外 依序形成一第一電路層12、一第一介電層13、一第二電路層 14、一第一介電層15、一表面電路層π及一防焊層I?。再者， 在增層期間’該核心層11另可能形成數個電鍍通孔 through hole)lll貫穿其間，以電性連接兩侧之該第一電路層 12。該第一介電層13可能形成數個導通孔(c〇nductive via)i3i 3 1377655 貫穿其間，以電性連接該第一及第二電路層12、i4。 彡紐個導通孔151貫輪電性 個Η 口 161 曰及表面電路層16。最後’該防焊層16形成數 塾it円號^裸露一部分的該表面電路層16，以提供數個烊 接示)位置），以便結合金屬線、凸塊或錫球等電性連1377655 VI. Description of the Invention: [Technical Field of the Invention] The layering process is performed on a temporary core layer of the present invention: no manufacturing of the substrate without the core of the invention, and a method for manufacturing the substrate using the removable substrate [Prior Art] Nowadays, the semiconductor packaging industry has gradually developed various types of package structures in order to meet various high-density packages. Among them, the common ^^ubstrateK package structure includes a ball grid array structure _ _, grab ς, package structure ^in _ Ah, PGA), land array array structure (LGA) or chip package structure on the substrate (4) (10) ^1^0 heart on the top miscellaneous structure + 'the board's top surface carries the wafer and A plurality of solders are electrically connected to the upper surface of the substrate via a wire bonding or bumping process, and the bottom surface of the substrate must also provide a large number of soldering pads to solder several rounds. Out. Generally, the substrate is a multi-layer circuit board which has a surface circuit layer on the upper and lower surfaces to form a desired pad, and has a road layer and a plurality of through holes therein to rearrange the upper and lower surfaces. Bond pad connection]. Therefore, how to manufacture a multi-layered wire board is one of the key technologies. For example, please refer to FIG. 1 , which discloses a configuration of a conventional package 10, which is such that the package substrate 10 is centered on a core layer and is formed by a build-up method ( Build-up) sequentially forming a first circuit layer 12, a first dielectric layer 13, a second circuit layer 14, a first dielectric layer 15, and a surface on the two sides of the core layer 11 Circuit layer π and a solder mask I?. Furthermore, during the build-up period, the core layer 11 may further form a plurality of plated through holes 111 therebetween to electrically connect the first circuit layers 12 on both sides. The first dielectric layer 13 may form a plurality of vias i3i 3 1377655 extending therebetween to electrically connect the first and second circuit layers 12, i4.彡 New vias 151 are electrically connected to the surface of the circuit layer 16 and the surface circuit layer 16. Finally, the solder mask layer 16 forms a portion of the surface circuit layer 16 that is exposed to a portion of the surface circuit layer 16 to provide electrical connections such as metal lines, bumps or solder balls.
上述制封裝基板1G大量應用在目前之半雜封 ^然而’為了符合半導體封裝之小型化需求，因此有^要進 一步設法減少該封裝基板10的整體厚度。然而，該封 =在增層期間不可避免的必需使用具有足夠厚度的該核ς層 ，，確絲提供;支職度，及防止因熱應力(此』 stress)不均勻所發生的魅曲等(warpage)缺陷。但是，使用該核 心層11卻也會佔用過多厚度空間，導致不利於降低該封 板10的整體厚度。另一方面，當整體厚度不變時，也難以g 由減少該核心層11之厚度’以將省下來的厚度空_來增力: 電路層的_數’因此使贱核心層11亦不利於提高電路集 成度。 〃 故，有必要提供一種封裝基板的製造方法，以解決習知技 術所存在的問題。The above-mentioned package substrate 1G is widely used in the current half-package. However, in order to meet the miniaturization requirements of the semiconductor package, it is necessary to further reduce the overall thickness of the package substrate 10. However, the seal = it is inevitable to use the core layer having a sufficient thickness during the layering, which is provided by the wire; the degree of support, and the temptation to prevent the unevenness of the thermal stress (the stress) (warpage) defect. However, the use of the core layer 11 also takes up too much thickness space, which is disadvantageous in reducing the overall thickness of the sealing plate 10. On the other hand, when the overall thickness is constant, it is also difficult to increase the thickness of the core layer 11 to increase the thickness of the remaining layer: the number of circuit layers is such that the core layer 11 is also disadvantageous. Improve circuit integration. Therefore, it is necessary to provide a method of manufacturing a package substrate to solve the problems of the prior art.
【發明内容】 本發明之主要目的在於提供一種無核心封裝基板的製造方 法，其係利用臨時核心層在增層期間提供足夠支撐強度，並可 在增層後移除臨時核心層，進而有利於降低基板厚度及提高電 路集成度。 本發明之次要目的在於提供一種無核心封裝基板的製造方 法，其係利用臨時核心層進行增層，以同時在其兩側製做二組 無核心封裝基板，進而提高生產速度、降低製造成本及確保增 層良率。 本發明之另一目的在於提供一種無核心封裝基板的製造方 4 1377655 t其係利用臨時核心層進行增層，臨時核心厚沾本品目士 金屬箱層，可直接轉用做為無核心封==== 層，進而簡化增層製程、提高增層效率及mm面電路 方二本臨發 別依序堆疊-第一金屬夢二一八^時核心層之二侧分 其中該第-金Ui有平及第二金侧， 面朝向該臨時核心声，及#粗糙表面，該平坦表 每案化，以分別形成—第二電路層;: 母—該無核心_基板至少包含該第 士自層、第-介電層、第二電闕及至少多。 哕iif批—實關巾’在提供該臨時如層之^驟中， 該臨時核心層係為含；^階段熱隨樹脂之核心層。 - 3^發爲明λ一實施例中，在提供該臨時核心層及壓合該第 表ΐ 中’該臨時核心層之每一側具有一臨時黏性 表面以結合於該第一金屬箔層之平坦表面。 雷實補巾’在堆疊該第—金屬紐、第一介 層之步驟後’進行加熱處理，以永久性去除 琢臨時核心層之臨時黏性表面的黏性。 一明之一實施例中，在提供該臨時核心層及壓合該第 一金屬箔層之步驟中’該臨時核心層之每一側具有一金屬支撐 層’該金屬支魏具有—粗糙表面及-平坦表面，該金屬支樓 ，之粗糙表面結合於該臨時核心層之表面，及該金屬支撐層之 平坦表面結合於該第一金屬箔層之平坦表面。 在本發明之一實施例中，該臨時核心層之金屬支撐層的厚 度大於該第一金屬箔層之厚度。 在本發明之一實施例中’在堆疊該增層結構之步驟後及移 除該臨時核心層之步驟前，另對該增層結構之增層介電層及增 5 1377655 層金屬箔層進行鑽札、填孔及圖案化，以形成數個導 增層電路層。 久— 在本發明之一實施例中，在得到該無核心封裝基板之步 後，另對該無核心封裝基板之第一金屬箔層及第一介電層進疒 鑽孔、填孔及圖案化，以形成一第一電路層及數個導通^。仃 在本發明之一實施例中，在形成該第一電路層之步驟後， 在該第一電路層上形成一防焊層(s〇lder mask)，並對該防焊声 進行圖案化，以形成數個開口，裸露一部分的該第一電路；曰， 以提供數個焊墊。 曰SUMMARY OF THE INVENTION The main object of the present invention is to provide a method for manufacturing a coreless package substrate, which utilizes a temporary core layer to provide sufficient support strength during layer buildup, and which can remove the temporary core layer after layer buildup, thereby facilitating Reduce substrate thickness and increase circuit integration. A secondary object of the present invention is to provide a method for manufacturing a coreless package substrate, which utilizes a temporary core layer for layering to simultaneously form two sets of coreless package substrates on both sides thereof, thereby improving production speed and manufacturing cost. And to ensure the increase in yield. Another object of the present invention is to provide a coreless package substrate manufacturing method 4 1377655 t which utilizes a temporary core layer for layering, and the temporary core layer is thickened with the metal layer of the product, which can be directly used as a coreless seal = === Layer, which simplifies the layer-adding process, improves the layer-adding efficiency, and stacks the mm-face circuit. The second metal dream is stacked in sequence. The first metal dream is the second side of the core layer. The first-gold Ui The second gold side is flat, the surface faces the temporary core sound, and the #rough surface, the flat table is formed separately to form a second circuit layer; the mother-the core-free substrate includes at least the first The layer, the first dielectric layer, the second electrical layer, and at least more. The 哕iif batch-solid cover towel is provided in the temporary layer, the temporary core layer is contained; the stage heat is accompanied by the core layer of the resin. In the embodiment, the temporary core layer is provided and the temporary surface of the temporary core layer is provided with a temporary adhesive surface to be bonded to the first metal foil layer. Flat surface. The Raytheon patch is heat treated after the step of stacking the first metal and the first layer to permanently remove the viscosity of the temporary adhesive surface of the temporary core layer. In one embodiment, in the step of providing the temporary core layer and pressing the first metal foil layer, 'the temporary core layer has a metal support layer on each side of the temporary core layer'. The metal support has a rough surface and a flat surface, the metal surface, the rough surface is bonded to the surface of the temporary core layer, and the flat surface of the metal support layer is bonded to the flat surface of the first metal foil layer. In one embodiment of the invention, the metal support layer of the temporary core layer has a thickness greater than the thickness of the first metal foil layer. In an embodiment of the present invention, after the step of stacking the build-up structure and before the step of removing the temporary core layer, the build-up dielectric layer of the build-up structure and the metal foil layer of 5,377,655 layers are added. Drilling, filling and patterning to form a plurality of conductive layer circuit layers. For a long time, in an embodiment of the present invention, after the step of obtaining the coreless package substrate, the first metal foil layer and the first dielectric layer of the coreless package substrate are drilled, filled, and patterned. To form a first circuit layer and a plurality of conductions. In an embodiment of the present invention, after the step of forming the first circuit layer, a solder mask is formed on the first circuit layer, and the solder resist is patterned. To form a plurality of openings, a portion of the first circuit is exposed; 曰 to provide a plurality of pads.曰
在本發明之一實施例中，在得到該無核心封裝基板之步驟 後，另對該增層結構之增層介電層及增層金屬箔層進行鑽孔、 填孔及圖案化，以形成數個導通孔及一增層電路層。 在本發明之一實施例中，在形成該增層電路層之步驟後， 在該增層電路層上形成一防焊層，並對該防焊層進行圖案化， 以形成數個開口，裸露一部分的該增層電路層，以提供數個焊 塾。 在本發明之一實施例中，在形成該防焊層及焊墊之步驟 後，在該焊墊之表面形成一助焊層。In an embodiment of the present invention, after the step of obtaining the coreless package substrate, the build-up dielectric layer and the build-up metal foil layer of the build-up structure are further drilled, filled, and patterned to form A plurality of vias and a build-up circuit layer. In an embodiment of the present invention, after the step of forming the build-up circuit layer, a solder resist layer is formed on the build-up circuit layer, and the solder resist layer is patterned to form a plurality of openings, exposed A portion of the build-up circuit layer provides a plurality of solder bumps. In an embodiment of the invention, after the step of forming the solder resist layer and the pad, a solder layer is formed on the surface of the pad.
在本發明之一實施例中，該助焊層選自電鍍鎳層、電鍍金 層、無電鍍鎳化金層(electroless Ni/Au)、浸鍍銀（immersion silver)、浸鍍錫（immersi〇n tin )或有機保護膜(哪妨^ solderability preservatives，OSP)。 在本發明之一實施例中，該第一金屬箔層、第二金屬箔層 及增層金屬箔層之厚度實質介於10至35微米之間。 在本發明之一實施例中，該第一介電層及增層介電層之厚 度實質介於30至55微米之間。 【實施方式】 *為了讓本發明之上述及其他目的、特徵、優點能更明顯易 懂’下文將待舉本發明較佳實施例，並配合所附圖式，作詳細 6 1377655 說明如下。 姑參照f2A至2H圖所示’本發明第—實施例之無核心封 裝基板的製造綠主要包含下列步驟：提供—臨時核心層20; 在該臨時核心層2〇之二側分職序堆疊—第-金屬· 21、 -第-介電層22及第二金屬羯層23’其中該第一金屬羯層21 具有一平坦表面211及一粗糙表面212，該平扫 向 該臨時核心層2〇，及該祕表面212朝㈣第—f介 f2 ; 對每一該第二金屬箔層23進行圖案化，以分別形成一第二電 路層230;在每一該第二電路層23〇外堆疊至少一增層结構 30 ’該增層結構3G包含-增層介電層31及―增層金^層 32 ;以及，移除該臨時核心層2〇 ’以得到二無核心封裝基板 200，每一該無核心封裝基板2〇〇至少包含該第一金屬箔層 21、第一 w電層22、第二電路層230及至少一增層結構3〇。 請參照帛2A圖所示’本發明第一實施例之無核心封裝基 板的製造方法第一步驟係：提供一臨時核心層2(^在本步驟 中，該臨時核心層20較佳係選自含有B階段熱固性樹脂 (B-stage thermosetting resin)之核心層，例如含有b階段環氧樹 脂之核心層，另外亦可能含有雙順丁烯二酸醯亞胺三氮樹脂 (bismaleimide triazine，BT)等熱固性樹脂。上述含有B階段埶 固性樹脂之核心層係藉由將玻璃纖維(glass fiber)布等填充g 料預浸在生漆(varnish)狀態的A階段熱固性樹脂半乾後並經加 熱軟化所製成。因此，該臨時核心層2〇之每一側皆具有一臨 時黏性表面201、202，以提供一預定程度之臨時黏^。在本 實施例中，該臨時核心層20可選自玻纖布基材環氧樹脂銅箔 基板，例如FR-4或FR-5等，但並不限於此.該臨時核心層 20用以提供增層製程所需之足夠支撐強度，因此必需具備足 夠厚度，但在具備足夠支撐強度的前題下，本發明並不限制該 臨時核心層20之厚度範圍。 清再參照第2Α圖所示，本發明第一實施例之無核心封裝 基板的製造方法第二步驟係：在該臨時核心層2〇之二側分別 7 1377655In an embodiment of the invention, the soldering layer is selected from the group consisting of an electroplated nickel layer, an electroplated gold layer, an electroless Ni/Au, an immersion silver, and an immersi tin. n tin ) or organic protective film (how to ^ solderability preservatives, OSP). In one embodiment of the invention, the thickness of the first metal foil layer, the second metal foil layer, and the build-up metal foil layer is substantially between 10 and 35 microns. In one embodiment of the invention, the thickness of the first dielectric layer and the build-up dielectric layer is substantially between 30 and 55 microns. The above and other objects, features, and advantages of the present invention will become more apparent and understood <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Referring to the f2A to 2H diagram, the manufacturing green of the coreless package substrate of the first embodiment of the present invention mainly comprises the following steps: providing a temporary core layer 20; and stacking the jobs on the two sides of the temporary core layer 2 a first metal 21, a first dielectric layer 22 and a second metal germanium layer 23', wherein the first metal germanium layer 21 has a flat surface 211 and a rough surface 212, and the flat scan is directed to the temporary core layer 2 And the surface 212 facing the (4)th f-f; each of the second metal foil layers 23 is patterned to form a second circuit layer 230; respectively, stacked on each of the second circuit layers 23 At least one build-up structure 30' includes a build-up dielectric layer 31 and a build-up layer 32; and remove the temporary core layer 2' to obtain a second coreless package substrate 200, each The coreless package substrate 2 includes at least the first metal foil layer 21, the first w electrical layer 22, the second circuit layer 230, and at least one buildup structure 3A. Referring to FIG. 2A, a first step of the manufacturing method of the coreless package substrate according to the first embodiment of the present invention is to provide a temporary core layer 2 (in this step, the temporary core layer 20 is preferably selected from the group consisting of A core layer containing a B-stage thermosetting resin, for example, a core layer containing a b-stage epoxy resin, and may also contain a bismaleimide triazine (BT), etc. The thermosetting resin. The core layer containing the B-stage tamping resin is pre-impregnated with a glass fiber cloth, such as a glass fiber cloth, in a varnish state, and the A-stage thermosetting resin is semi-dried and softened by heating. Thus, each of the temporary core layers 2 has a temporary adhesive surface 201, 202 to provide a predetermined degree of temporary adhesion. In this embodiment, the temporary core layer 20 can be selected from A fiberglass cloth substrate epoxy resin copper foil substrate, such as FR-4 or FR-5, etc., but is not limited thereto. The temporary core layer 20 is used to provide sufficient support strength for the build-up process, so it is necessary to have sufficient Thickness, but in possession The invention is not limited to the thickness range of the temporary core layer 20. The second step of the method for manufacturing the coreless package substrate according to the first embodiment of the present invention is as follows: On the two sides of the temporary core layer 2, respectively, 1 1377655
一第一金屬箱層2卜-第-介電層22及第二金屬箔 U产本步驟中’該第一金屬箱層21及第二金屬羯層23 二預J藉由電鍍法(electroplating)或輾軋法⑽_加以製成 =加其中至少該第-金賴層21必需具有—平坦表面211 表面212 ’該平坦表面211朝向該臨時核心層20，及 212朝向該第一介電層22。上述堆疊排列關係之 笛-厶m2下文加以詳細說明。再者，該第一金屬箔層21及 但取材自銅、18、錄、金、銀等金屬或合金， if去眘哲义必°。第一金屬荡層21及第二金屬落層23之厚度 ίί 35微权間。值躲4的是，當該臨時核 時臨_ _ VR-5等玻纖布紐魏樹賴箔基板 i t 母—側的臨時黏性表面2G1、202已預先 :朝:之金屬箱層，其可直接用以做為該第- ί _有利於減少備料成本或簡化堆疊步驟。該 第-;I電層22實質包含具備臨時黏性之 g ==如B階段之環氧樹脂或雙順丁烯 ί電層二亦可加入玻璃纖維布等填充材料。該a first metal box layer 2, a first dielectric layer 22 and a second metal foil U, in the present step, 'the first metal box layer 21 and the second metal layer 23 are pre-J by electroplating Or rolling method (10) _ is made = plus at least the first - gold layer 21 must have - flat surface 211 surface 212 'the flat surface 211 faces the temporary core layer 20, and 212 toward the first dielectric layer 22 . The above-described stacking arrangement of the flute-厶m2 will be described in detail below. Furthermore, the first metal foil layer 21 and the material are obtained from copper, 18, metal, or alloy such as gold, silver, and the like. The thickness of the first metal verting layer 21 and the second metal falling layer 23 is ίί 35 micro-weight. The value of hiding 4 is that when the temporary core is _ _ VR-5 and other fiberglass cloth New Zealand lai Lai foil substrate it mother-side temporary adhesive surface 2G1, 202 has been: toward: the metal box layer, its Can be used directly as the first - _ _ to reduce the cost of preparation or simplify the stacking steps. The first-electrode layer 22 substantially includes a temporary adhesive viscous g == such as a B-stage epoxy resin or a bi-butylene electrical layer 2 may also be added to a filler such as a glass fiber cloth. The
行本發明冑二步騎，可在絲堆疊之後，it行^處理f 該臨時核心層20之臨時黏性表面2〇1 二、 吏 性。此時，該臨時黏性表面久去除其黏 -金屬細之 表面2i2將會永久性結合於該第一介22屬同曰 屬箱層23亦會永久性結合於該第一介電層22。第-金 請參照第2B圖所示，本發明第一實施例之師 ίΐ银電路層230。在本步驟中，本發明可 藉由現有时佈光阻、光罩曝光及顯影 =了 23，因而形成該第二電路層23〇。必要時，本發 8 1377655 =之前(或之後）’選擇進行鑽孔及填孔的製程，以在該第 中形成數個導通孔(未繪示），該鑽孔製程可選自雷射 ，機械鑽孔’而該填孔製程係藉由電鑛方式加以完成。惟，= ϋ施例卜本發_在第五步驟之後，才在該第一声 22中形成數個導通孔功(如第Μ圖所示}。上述導通: 成時機並非用以限制本發明。 的屯 、、二耷參照第2C、2D及2E @所示’本發明第—實施例之無核 ^封裝基板的製造方法第四步驟係：在每—該第二電路層23〇 夕，疊至4-增層結構3G、4G。在本實施例中，本發明係設 置二組該增層結，3G、4G，但其數量並不限於此，其亦可:曼 置一組、三組或三組以上。該增層結構3〇包含一增層介電^ 31及-增層金屬羯層32。該增層介電層31實質相同於二 =電層22 ’同樣實質包含具備臨時黏性之B階段油性樹脂 等絕緣材料’及其厚度較佳實質介於3〇至55微米之間。該辦 層金屬箔層32實質相同於該第二金屬箔層23，同樣可取材自曰 銅、鋁、鎳、金、銀等金屬或合金，及其厚度較佳實質介於 10至35微米之間。在本實施例中，如第2C圖所示，本發明 先在每一該第二電路層23〇外堆疊該增層結構3〇，並適當加 熱處理’以使該增層介電層31結合於該第二電路層23〇 了並 使該增層金屬箔層32朝向外侧。接著，如第2D圖所示，對 該增層結構30之增層介電層31及增層金屬箔層％進行鑽 孔、填孔及圖案化等處理，以形成數個導通孔311及一增層電 路層320。再者，如第2E圖所示，以類似第2C圖的做法，進 一步在每一該增層電路層32〇外再堆疊另一該增層結構4〇， 該增層結構40包含一增層介電層41及一增層金屬箔層42， 其實質相同於該增層介電層31及增層金屬箔層32。必要時， 本發明亦可在對該增層介電層41及增層金屬箔層42選擇進行 鑽孔、填孔及圖案化的製程，以形成數個導通孔(未繪示)及另 一增層電路層(未繪示）。惟，在本實施例中，為了使堆疊結構 具有對稱性以防止熱應力(thermal stress)不均勻造成輕曲 9 1377655 (warpage)缺陷，本發明係在第五步驟之後，才使該增層介電層 41及增層金屬箱層c形成數個導通孔411及另一增層電路層 420(如第2G圖所示）。 請參照第2F、2G及圖所示，本發明第一實施例之無核 心^裝基板的製造方法第五步驟係：移除該臨雜心層2〇， 以得到二無核心封裝基板2〇0。在本實施例中，該臨時核心層 20之臨時黏性表面2(U、202已在上述數次堆疊加熱過程中永 久性去y其黏性。此時’該平坦表面211與臨時黏性表面2〇1、 202的最終結合強度將明顯小於該粗縫表面212與第一介電層 22之最終結合強度。因此，如第2F圖所示，本發明可輕易藉 由人工或簡易機具移除該臨時核心層2〇,並留下二組該無核 心封裝基板200，其中每一該無核心封裝基板2〇〇至少包含該 第一金屬箔層21、第一介電層22、第二電路層230及至少一 增層結構30、40。在本實施例中，每一該無核心封裝基板2〇〇 包含二組該增層結構3〇、40 ’但並不限於此。接著，如第2g 圖所示，在移除該臨時核心層20之後，可對每一該無核心封 裝基板200之第一金屬箔層21及第一介電層22進行鑽孔、填 孔及圖案化，以形成一第一電路層21〇及數個導通孔221。同 時，對該增層結構40之增層介電層41及增層金屬箔層42進 行鑽孔、填扎及圖案化，以形成數個導通孔411及一增層電路 層420。隨後’如第2H圖所示，則可在該第一電路層21〇上 形成一防焊層(solder mask)50，並對該防焊層50進行圖案化， 以形成數個開口 51 ’裸露一部分的該第一電路層21〇，以提供 數個焊墊(未標示）。同時，在該增層電路層420上形成另一防 谭層50 ’並對該防焊層50進行圖案化，以形成數個開口 51， 裸露一部分的該增層電路層420，以提供數個焊墊(未標示）。 最後，依產品需求’選擇性的在該第一電路層21〇(或增層電路 層420)之焊墊的表面形成一助焊層60,該助焊層6〇係^選自 電鍍鎳層〜電鍍金層’無電鍍鎳化金層㈨沈加丨挪洲/如^浸 鐘銀（immersion silver)、浸鍍錫（immersion tin)或有機保護 膜(organic solderability preservatives，OSP)。 藉由上述第一至第五步驟，本發明第一實施例即可利用該 臨時核心層20提供足夠支撐強度，以便順利進行增層製程， 並可在增層後移除該臨時核心層20，故有利於降低該無核心 封裝基板200的整體厚度及提高該無核心封裝基板2〇〇的電路 集成度。由於可同時在該臨時核心層20的兩侧製做二組無核 心封裝基板200 ’因此不但可相對提高生產速度及降低製造成 本’亦可藉由二側對稱進行增層，以確實防止熱應力不均勻所 造成的龜曲缺陷，進而確保增層良率。 請參照第3圖所示，本發明第二實施例之無核心封裝基板 的製造方法係相似於本發明第一實施例’但該第二實施例使用 之臨時核心層70不同於該第一實施例之臨時核心層2〇。在第 二實施例中’在預先製備該臨時核心層70時，該臨時核心層 70之每一侧已具有一金屬支撐層71及一第一金屬箔層72。例 如’該臨時核心層70可選用特殊之FR-4或FR-5等玻纖布基 材環氧樹脂銅箔基板’亦即該臨時核心層70每一侧的表面已 預先依序黏附有該金屬支撐層71及第一金屬箔層72，因而有 利於減少備料成本或簡化堆疊步驟。更詳言之，該金屬支撐層 71具有一粗糙表面711及一平坦表面712,同時該第一金屬箔 層72具有一平坦表面721及一粗糙表面722。在本發明中， 該金屬支撐層71之粗糙表面711結合於該臨時核心層"7〇，其 中該臨時核心層70可具有臨時黏性表面(未標示），;亦可 具有臨時黏性表面。再者，該金屬支撐層71之平坦表面712 結合於該第一金屬箔層72之平坦表面721 ’該第一金屬箔層 72之粗糙表面722則用以依序堆疊結合一第一介層電73^一 第二金屬領層74。因此，該金屬支㈣71與臨時核心層7〇 之最終結合強度會大於該金屬支撐層7丨與第一金屬箔層72之 最終結合織。當第三實_完成職並欲鑛馳時核心層 7〇時’該臨時核心層70將連同該金屬支撐層71 一 僅由該第-金射㈣72、第—介層電Μ、第二金屬歸％及 1377655According to the second step of the present invention, after the wire is stacked, the temporary adhesive surface of the temporary core layer 20 is treated. At this time, the temporary adhesive surface is permanently removed from the adhesive-metal thin surface 2i2 and will be permanently bonded to the first dielectric layer 23 and will be permanently bonded to the first dielectric layer 22. First - Gold Referring to Figure 2B, the first embodiment of the present invention is a silver circuit layer 230. In this step, the present invention can form the second circuit layer 23 by the prior art photoresist, mask exposure, and development = 23. If necessary, the present invention 8 1377655 = before (or after) 'selects the drilling and filling process to form a plurality of via holes (not shown) in the middle, the drilling process may be selected from lasers, Mechanical drilling 'and the hole filling process is done by electric mining. However, after the fifth step, a plurality of via functions are formed in the first sound 22 (as shown in the figure). The above-mentioned conduction: the timing is not intended to limit the present invention. The second step of the manufacturing method of the coreless package substrate according to the second embodiment of the present invention is as follows: 每, 耷, 耷, and the second step of the second circuit layer 23 4-layered structure 3G, 4G. In the present embodiment, the present invention provides two sets of the build-up junctions, 3G, 4G, but the number is not limited thereto, and it may also be: one set, three sets or More than three sets. The build-up structure 3〇 includes a build-up dielectric ^ 31 and a build-up metal tantalum layer 32. The build-up dielectric layer 31 is substantially the same as the second = electrical layer 22' and substantially contains temporary adhesion. The insulating material such as the B-stage oil-based resin and the thickness thereof are preferably substantially between 3 Å and 55 μm. The metal foil layer 32 is substantially the same as the second metal foil layer 23, and is also available from beryllium copper, A metal or an alloy such as aluminum, nickel, gold or silver, and a thickness thereof is preferably substantially between 10 and 35 μm. In this embodiment, as shown in Fig. 2C The present invention firstly stacks the build-up structure 3〇 on each of the second circuit layers 23 and heats it appropriately so that the build-up dielectric layer 31 is bonded to the second circuit layer 23 and The build-up metal foil layer 32 faces outward. Next, as shown in FIG. 2D, the build-up dielectric layer 31 and the build-up metal foil layer % of the build-up structure 30 are drilled, filled, and patterned. a plurality of via holes 311 and a build-up circuit layer 320 are formed. Further, as shown in FIG. 2E, another layer of the build-up circuit layer 32 is further stacked in another manner similar to FIG. 2C. The build-up structure 40 includes a build-up dielectric layer 41 and a build-up metal foil layer 42 which are substantially identical to the build-up dielectric layer 31 and the build-up metal foil layer 32. The present invention may also select a process of drilling, filling, and patterning the build-up dielectric layer 41 and the build-up metal foil layer 42 to form a plurality of vias (not shown) and another build-up layer. Circuit layer (not shown). However, in the present embodiment, in order to make the stack structure have symmetry to prevent uneven thermal stress A defect of 9 1377655 (warpage) is caused. In the present invention, after the fifth step, the build-up dielectric layer 41 and the build-up metal case layer c are formed into a plurality of via holes 411 and another build-up circuit layer 420 ( As shown in FIG. 2G and FIG. 2G, the fifth step of the method for manufacturing the coreless substrate according to the first embodiment of the present invention is as follows: removing the adjacent layer 2, The second core package substrate 2 〇 0 is obtained. In this embodiment, the temporary viscous surface 2 of the temporary core layer 20 (U, 202 has been permanently y viscous during the above-mentioned several stack heating processes. The final bond strength of the flat surface 211 to the temporary adhesive surface 2〇1, 202 will be significantly less than the final bond strength of the rough surface 212 and the first dielectric layer 22. Therefore, as shown in FIG. 2F, the present invention can easily remove the temporary core layer 2 by manual or simple implements, and leave two sets of the coreless package substrate 200, wherein each of the coreless package substrates 2〇 The crucible includes at least the first metal foil layer 21, the first dielectric layer 22, the second circuit layer 230, and the at least one buildup structure 30, 40. In this embodiment, each of the coreless package substrates 2A includes two sets of the buildup structures 3, 40' but is not limited thereto. Then, as shown in FIG. 2g, after the temporary core layer 20 is removed, the first metal foil layer 21 and the first dielectric layer 22 of each of the coreless package substrates 200 may be drilled, filled, and filled. Patterning to form a first circuit layer 21 and a plurality of vias 221. At the same time, the build-up dielectric layer 41 and the build-up metal foil layer 42 of the build-up structure 40 are drilled, filled and patterned to form a plurality of vias 411 and a build-up circuit layer 420. Then, as shown in FIG. 2H, a solder mask 50 may be formed on the first circuit layer 21, and the solder resist layer 50 is patterned to form a plurality of openings 51' bare. A portion of the first circuit layer 21 is provided to provide a plurality of pads (not labeled). At the same time, another anti-solder layer 50' is formed on the build-up circuit layer 420 and the solder resist layer 50 is patterned to form a plurality of openings 51, and a portion of the build-up circuit layer 420 is exposed to provide a plurality of Solder pad (not shown). Finally, a solder layer 60 is selectively formed on the surface of the pad of the first circuit layer 21 (or the build-up circuit layer 420) according to product requirements, and the solder layer 6 is selected from the electroplated nickel layer. Electroplated gold layer 'electroless nickel plating gold layer (9) sinking 丨 洲 / / / immersion silver (immersion silver), immersion tin (immersion tin) or organic protective film (organic solderability preservatives (OSP). With the first to fifth steps described above, the first embodiment of the present invention can utilize the temporary core layer 20 to provide sufficient support strength for smoothing the build-up process, and the temporary core layer 20 can be removed after layering. Therefore, it is advantageous to reduce the overall thickness of the coreless package substrate 200 and improve the circuit integration of the coreless package substrate 2 . Since two sets of coreless package substrates 200' can be fabricated on both sides of the temporary core layer 20 at the same time, the production speed and the manufacturing cost can be relatively increased, and the layers can be layered by two sides to ensure thermal stress. The tortuosity defect caused by unevenness ensures the formation yield. Referring to FIG. 3, the manufacturing method of the coreless package substrate according to the second embodiment of the present invention is similar to the first embodiment of the present invention, but the temporary core layer 70 used in the second embodiment is different from the first embodiment. The temporary core layer of the example is 2〇. In the second embodiment, when the temporary core layer 70 is prepared in advance, each side of the temporary core layer 70 has a metal supporting layer 71 and a first metal foil layer 72. For example, the temporary core layer 70 may be a special fiberglass cloth substrate epoxy resin foil substrate such as FR-4 or FR-5, that is, the surface of each side of the temporary core layer 70 is adhered in advance. The metal support layer 71 and the first metal foil layer 72 are thus advantageous in reducing the cost of stock preparation or simplifying the stacking step. More specifically, the metal support layer 71 has a rough surface 711 and a flat surface 712, while the first metal foil layer 72 has a flat surface 721 and a rough surface 722. In the present invention, the rough surface 711 of the metal supporting layer 71 is bonded to the temporary core layer "7〇, wherein the temporary core layer 70 may have a temporary adhesive surface (not labeled); and may also have a temporary adhesive surface . Furthermore, the flat surface 712 of the metal supporting layer 71 is bonded to the flat surface 721 of the first metal foil layer 72. The rough surface 722 of the first metal foil layer 72 is used to sequentially stack and bond a first interlayer. 73^ a second metal collar 74. Therefore, the final bonding strength of the metal branch (71) 71 to the temporary core layer 7〇 is greater than the final bonding strength of the metal supporting layer 7丨 and the first metal foil layer 72. When the third layer is completed and is to be mined, the core layer 70 will be combined with the metal support layer 71, and only the first-gold (four) 72, the first layer, and the second metal.归% and 1377655
至少增層^構(未繪示)構成二組無核心封裝基板(未繪示）。 值得注意的是，由於該臨時核心層70之金屬支標層71僅 用以提供支撐作用，因此本發明並不限制該金屬支撐^ 71之 厚度丄但其厚度較佳大於該第一金屬箔層72之厚度。該第一 金屬箱層72之厚度較佳實質介於10至35微米之間。除了該 臨時核心層70的構造不同之外，該第二實施例之無核心:封g 基板的製造方法係實質相同於該第一實施例，故本發明不再< 予詳細說明該第二實施例之各個步驟。 如上所述，相較於第1圖之習用封裝基板10在增層時使用 該核心層11，導致不利於降低整體厚度或提高電路集成 缺點第2A至2H及3圖之本發明利用該臨時核心層2〇在择 層期間提供㈣支#強度，並可在增層後移除該臨時核心層曰 20’因而有利於降低該無核心封裝基 該無核心職基板的減度。再者，At least the build-up layer (not shown) constitutes two sets of coreless package substrates (not shown). It should be noted that since the metal support layer 71 of the temporary core layer 70 is only used to provide support, the present invention does not limit the thickness of the metal support 71, but the thickness thereof is preferably larger than the first metal foil layer. 72 thickness. The thickness of the first metal box layer 72 is preferably substantially between 10 and 35 microns. Except for the difference in the configuration of the temporary core layer 70, the coreless method of manufacturing the second embodiment is substantially the same as the first embodiment, and the present invention is no longer described in detail. The various steps of the examples. As described above, the use of the core layer 11 in the build-up of the conventional package substrate 10 of FIG. 1 results in a disadvantage of reducing the overall thickness or improving circuit integration defects. The present invention utilizes the temporary core in FIGS. 2A to 2H and 3 The layer 2 提供 provides (4) branch strength during the layer selection, and may remove the temporary core layer 曰 20 ′ after the layer is added, thereby facilitating reducing the reduction of the coreless substrate of the coreless package. Furthermore,
臨時核心層20的兩側製做二組無核心封裝基板綱，因此不 仁了相對友尚生產速度及降低製造成本，亦可藉由二側對稱進 行增層，鱗實防止熱應力不均勻所造成的編舰，進而禮 保增層良率。此外’如第3圖所示，當該臨時核心層7〇的表 面具有可撕除之第一金屬箔層72時，該第一金屬箔層72可直 接轉用做為後續無核心封裝基板的表面電路層，因此能簡 層製程、提高增層效率及降低備料成本。 ^ 雖然本發明已IX較佳實施例揭露’然其並_以限制本發 明Μ壬何熟習此項技藝之人士，在不脫離本發明之精神和範圍 内，當可作各種絲與修飾’因此本發明之賴麵當視後附 之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖：習用封裝基板之示意圖。 f、2A至2Η圖.本發明第一實施例之無核心封裝基板的製造 方法之流程示意圖。 12 1377655 第3圖：本發明第二實施例之無核心封裝基板的製造方法之示 意圖。 【主要元件符號說明】 10封裝基板 111電鍍通孔 13第一介電層 14 第二電路層 151導通孔 161 開口 20臨時核心層 201臨時黏性表面 21第一金屬箔層 211平坦表面 22第一介電層 23第二金屬箔層 30增層結構 311導通孔 320增層電路層 41增層介電層 42增層金屬箱層 50防焊層 60助焊層 71金屬支撐層 712平坦表面 721平坦表面 73第一介層電 11核心層 12第一電路層 131導通孔 15第二介電層 16表面電路層 17防焊層 200無核心封裝基板 202臨時黏性表面 210第一電路層 212粗糖表面 221導通孔 230第二電路層 31增層介電層 32增層金屬猪層 40增層結構 411導通孔 420增層電路層 51開口 70 臨時核心層 711粗糖表面 72第一金屬箔層 722粗链;表面 74第二金屬箔層 13The two sides of the temporary core layer 20 are made of two sets of coreless package substrates, so the relative production speed and manufacturing cost are reduced, and the layers can be layered by two sides to prevent uneven thermal stress. The packaged ship, and then the gift protection increased the yield. In addition, as shown in FIG. 3, when the surface of the temporary core layer 7 has a peelable first metal foil layer 72, the first metal foil layer 72 can be directly transferred to be used as a subsequent coreless package substrate. The surface circuit layer can therefore simplify the layer process, increase the layering efficiency and reduce the cost of stock preparation. Although the present invention has been disclosed in the preferred embodiments of the present invention, it is intended that those skilled in the art will be able to make various filaments and modifications without departing from the spirit and scope of the present invention. The scope of the present invention is defined by the scope of the patent application. [Simple description of the drawing] Fig. 1: Schematic diagram of a conventional package substrate. f, 2A to 2D. A schematic flow chart of a method of manufacturing a coreless package substrate according to a first embodiment of the present invention. 12 1377655 Fig. 3 is a schematic view showing a method of manufacturing a coreless package substrate according to a second embodiment of the present invention. [Main component symbol description] 10 package substrate 111 plated through hole 13 first dielectric layer 14 second circuit layer 151 via hole 161 opening 20 temporary core layer 201 temporary adhesive surface 21 first metal foil layer 211 flat surface 22 first Dielectric layer 23 second metal foil layer 30 build-up structure 311 via hole 320 build-up circuit layer 41 build-up dielectric layer 42 build-up metal box layer 50 solder mask layer 60 solder layer 71 metal support layer 712 flat surface 721 flat Surface 73 first interlayer 11 core layer 12 first circuit layer 131 via 15 second dielectric layer 16 surface circuit layer 17 solder mask 200 without core package substrate 202 temporary adhesive surface 210 first circuit layer 212 raw sugar surface 221 via 230 second circuit layer 31 build-up dielectric layer 32 build-up metal pig layer 40 build-up structure 411 via 420 build-up circuit layer 51 opening 70 temporary core layer 711 raw sugar surface 72 first metal foil layer 722 thick chain ; surface 74 second metal foil layer 13
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| TW98101691A TWI377655B (en) | 2009-01-16 | 2009-01-16 | Method for manufacturing coreless package substrate |
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| TW98101691A TWI377655B (en) | 2009-01-16 | 2009-01-16 | Method for manufacturing coreless package substrate |
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| TWI377655B true TWI377655B (en) | 2012-11-21 |
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| CN103066049B (en) * | 2011-10-24 | 2015-09-02 | 联致科技股份有限公司 | Base plate for packaging and method for making thereof |
| TWI458402B (en) * | 2012-08-01 | 2014-10-21 | Zhen Ding Technology Co Ltd | Package substrate, and method for manufacturing same, package structure, and method for manufacturing chip package |
| CN103579009A (en) * | 2012-08-02 | 2014-02-12 | 富葵精密组件(深圳)有限公司 | Package substrate, manufacturing method of the package substrate, chip packaging structure and manufacturing method of the chip packaging body |
| CN103779233A (en) * | 2012-10-17 | 2014-05-07 | 宏启胜精密电子(秦皇岛)有限公司 | Bearing plate manufacturing method |
| CN103857204B (en) * | 2012-11-28 | 2017-10-27 | 碁鼎科技秦皇岛有限公司 | Loading plate and preparation method thereof |
| TWI563602B (en) * | 2016-04-15 | 2016-12-21 | Phoenix Pioneer Technology Co Ltd | Method of fabricating a package substrate |
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