1.376879 2012/6/11無劃線替換頁 六、發明說明： 【發明所屬之技術領域】 本發明係關於延遲鎖定迴路，特別是關於一種全數位 快速鎖定自我校正多相位延遲鎖定迴路。 【先前技術】 隨著積體電路（1C)的進步與發展，積體電路之執行效 #能已經過大幅改善而電路之複雜度亦隨之提昇，各方面之 應用’包括資訊，通訊，消費性電子產品及微處理器均朝 向單晶片系統（system on a chip, SoC)發展。然而，上述系 統通常包含許多不同元件，而各元件對於同一參考時脈將 產生不同的延遲，因而需要在系統中加入鎖相迴路（phase locked loop，PLL)或延遲鎖定迴路（delay_i〇cked 1〇〇p，Dll) 以進行時脈之校正並維持系統的同步。 • 一般而言’鎖相迴路内包含一電壓控制振盪器 controlled oscillator)，而此電壓控制振盪器常會無法避免 的累積抖動（jitter)，進而使得鎖相迴路之雜訊抗擾性（η〇ίπ immunity)低於延遲鎖定迴路。除了低成本與較良 表現之外，延遲鎖定迴路之穩定性與快速鎖定之特性亦使 其較常被採用。另一方面，鎖相迴路通常係採用類比電路 或與數位電路混合的設計，其可鎖定之範圍雖較大（斑全數 位之延遲鎖定迴路相比），但其功率之損耗卻比全數位式的 设計向出許多。 3 1,376879 方法美；專利第™號揭露了-種自 =用於校正環狀振盪器的輸出波形（Qutput物咖叫 路：“Γ:Γ: °ffset)。此方法係於多相位鎖相迴 ::僂:玫 出訊號之間由於製程上的變動或 虎 '遞路徑的不同所造成之延遲誤差(de〗ay1.376879 2012/6/11 Unlined Replacement Page VI. Description of the Invention: [Technical Field] The present invention relates to a delay locked loop, and more particularly to a full digit fast lock self-correcting multi-phase delay locked loop. [Prior Art] With the advancement and development of the integrated circuit (1C), the implementation efficiency of the integrated circuit can be greatly improved and the complexity of the circuit is also improved. The application of various aspects includes information, communication, and consumption. Both sex electronics and microprocessors are moving toward system on a chip (SoC). However, the above system usually contains many different components, and each component will have different delays for the same reference clock. Therefore, a phase locked loop (PLL) or a delay locked loop (delay_i〇cked 1〇) needs to be added to the system. 〇p, Dll) to correct the clock and maintain synchronization of the system. • In general, the 'phase-locked loop contains a controlled oscillator), and this voltage-controlled oscillator often avoids the accumulation of jitter, which in turn makes the noise immunity of the phase-locked loop (η〇ίπ Immunity) is below the delay locked loop. In addition to low cost and better performance, the stability and fast locking characteristics of the delay locked loop make it more common. On the other hand, the phase-locked loop is usually a analog circuit or a design mixed with a digital circuit. The lockable range is large (compared to the delay-locked loop of the full-numbered bit), but the power loss is better than the full digital The design is a lot more. 3 1,376879 Method Beauty; Patent No. TM exposes - the output waveform used to correct the ring oscillator (Qutput is called "路: Γ: °ffset". This method is based on multi-phase lock Phase back::偻: Delay error between the signal due to process changes or tiger's different path (de〗
)°假設其具有8個多相位之輪出，其補償原理係 用鎖相迴路之鎖定機制而將原本之鎖定參考時脈盘除M Γ=鎖定參考時脈與除(Μ+ι/8)頻訊號。藉由二述改 4，仙機制可漸進改變多相位之間的相位差，使直最欲 等的。新式之除（M+1/8)頻訊號之除頻器係依序利用 兩。^遗所產生’其控制訊號則係由有限狀態機（finite ne，FSM)實施。上述專利所揭露之裝置與方法 係^訊號的設計，其中鎖相迴路與自我校正之機制皆係 =類比方式實施’而除頻電路與其控制訊號則係以數位方 式實施。由於上述專利之裝置與方法係以混合訊號之多相 位鎖相迴路架構所建立，因而具有不易隨著製程移植，較 不適用於先進製程及擁有較低抗雜訊能力等缺點。 另卜2006年Η. H. Chang等人發表於IEEE jIt is assumed that it has 8 multi-phase rounds, and the compensation principle is to use the locking mechanism of the phase-locked loop to lock the original reference clock to M Γ=lock reference clock and divide (Μ+ι/8) Frequency signal. By changing the second, the immortal mechanism can gradually change the phase difference between the multiple phases, so that the direct and the most desired. The new type of divider (M+1/8) frequency signal is used in sequence. ^The legacy generated' its control signal is implemented by a finite state machine (FSN). The apparatus and method disclosed in the above patents are designed for the signal, wherein the phase-locked loop and the self-correcting mechanism are both implemented in analogy mode, and the frequency-dividing circuit and its control signal are implemented in a digital manner. Since the devices and methods of the above patents are established by a multi-phase phase-locked loop architecture of mixed signals, they are not easy to be transplanted with the process, are not suitable for advanced processes, and have low anti-noise capability. In addition, 2006. H. Chang et al. published in IEEE j
Solid State Circuits 第 41 卷第 5 期第 1051-1061 頁之文獻 ( GHz Self-Calibration Multiphase Delay-Locked L〇〇P) ’提出了-種利用數位校正電路降低多相位時脈之間 不匹配所引起之時序誤差timing )的方法。此方法係於多相位延遲鎖定迴路之架構下， 根據所應用之自我杈正演算法以數位式調整輸出緩衝器 4 1,376879 2012/6/" &劃線巷抱百 (⑽buffer)的方式調整各級輸出訊號間之相位差，f用 時序控制電路（timing c〇iuroI circuit)於一參考時脈週期 (reference cyc丨e)内選擇需調整之輸出訊號，藉由一次調整 一級的輸出補償延遲誤差，最終使多相位輸出訊號之間的 相位差均能相同。由於此方法需要額外的時序控制電路， 因此在設計上較為複雜，且其一次只能調整一級的輸出訊 號’故將延長鎖定之速度。 另一方面，2000年G. K. Dehng等人發表於IEEE j 攀 Solid-State Circuits 第 35 卷第 8 期第 1128_1136 頁之文獻 (Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop)，提出了 一種全數位延遲鎖定迴路， 其鎖疋機制係以二元搜尋（binary search)之方式進行。此方 法之缺點在於其鎖定範圍較大（widerange)時可能會有諧 波鎖定（harmonic lock)的問題。 有鑑於上述，本發明提出一種以全數位方式實施之自 #我校正多相位延遲鎖定迴路，其具有易於隨著製程移植， 適合應用於先進製程，擁有較佳的抗雜訊能力與良好鎖定 速度，電路设計簡單並能有效增加鎖定範圍等特徵，以達 到維持系統中各元件之同步的效果。 【發明内容】 本發明之一目的係在於提供一種快速自我校正“apW calibration, RSC)之演算法，以於多相位延遲鎖定迴路 之各個相位差不相同時，判斷應當如何自我校正。 本發明之-目的係在於提供一種非平衡式二元搜尋演 5 1^76879 算法，適用於全數位式延遲 2=無_換頁 圍（I〇ckrange)。 以增加可鎖定之範 本發明之又一目的係在於根據上述 法及非平衡式二元搜尋演算法提供一種=正决鼻 位延遲鎖定迴路竿構，自我校正之多相 路架構此架構可讓所設計的延ϋ鎖定迴跋 之多項延遲鎖定的輸出補償因延遲誤鎖疋沿路 ⑽阶叫，並有效增加敎範圍。所^之相位誤差 本發明提出-種自我校正機制及鎖定機制， 各種多相位輸出之數位延遲鎖定電路。上述校制 =:調整各級輸出相位之間的相位差，以消除= 遲决差所造成之相位誤差，使得在各種頻率下，多相位輸 出均能有相同的相位差輸出。而上述鎖定機制則可： 鎖定之範圍。 θ ι 本發明揭露了-種全數位自我校正多相位延遲鎖定迴 路’其包含四個主要的區塊’分別為：一組數位式控制延 修遲線，一相位彳貞測器，一鎖定單元，及一自我校正單元。 數位式控制延遲線係由κ個相同之延遲級串連所形成，而 所有的延遲級均係透過兩組控制訊號C[M:0]與所 控制。C[M:0]係由採用非平衡式二元搜尋演算法之鎖定單 元所產生。當延遲鎖定迴路鎖定時，自我校正單元將產生 Bi[N:〇]以調整各級輸出訊號之間的相位差。 本發明之鎖定機制係由比對參考時脈（reference elaek> 與第K級的輸出sfl號之間的相位差啟動，此時自我校正單 元為無作用狀態（disabled) ’鎖定單元將根據非平衡式二元 6 1376879 2012/6/11無劃線替換頁 搜尋演算法調整控制字組C[M:0]，當完成鎖定之後數位式 控制延遲線所提供之延遲時間將會等同於一參考時脈週 期，訊號LOCKED將拉起，進而啟動自我校正單元。自我 校正單元將藉甴改變控制字組Bi[N:0]實施輸出訊號相位 之自我校正功能，而控制字組C[M:0]係固定的，以讓延遲 鎖定迴路維持鎖定的狀態。 【實施方式】 本發明將配合其較佳實施例與隨附之圖示詳述於下。 #應可理解者為本發明中所有之較佳實施例僅為例示之用， 並非用以限制。因此除文中之較佳實施例外，本發明亦可 廣泛地應用在其他實施例中。且本發明並不受限於任何實 施例，應以隨附之申請專利範圍及其同等領域而定。 參照第 圖Solid State Circuits, Vol. 41 No. 5, No. 1051-1061 ( GHz Self-Calibration Multiphase Delay-Locked L〇〇P) 'Proposed a kind of digital correction circuit to reduce the mismatch between multi-phase clocks Timing error timing method. This method is based on the architecture of the multi-phase delay-locked loop. The output buffer is digitally adjusted according to the applied self-derivation algorithm. 1,376879 2012/6/"& scribing lanes ((10) buffer) The mode adjusts the phase difference between the output signals of each level, and f uses a timing control circuit (timing c〇iuroI circuit) to select an output signal to be adjusted in a reference clock cycle (reference cyc丨e), by adjusting the output of one level at a time. The delay error is compensated, and finally the phase difference between the multi-phase output signals can be the same. Since this method requires an additional timing control circuit, it is complicated in design, and it can only adjust the output signal of one stage at a time, thus extending the locking speed. On the other hand, in 2000, GK Dehng et al. published in the IEEE-Chen-Solid-State Circuits, Vol. 35, No. 8, No. 1128_1136 (Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop) The digital delay lock loop, whose lock mechanism is performed in the form of binary search. The disadvantage of this method is that it may have a harmonic lock when it has a wide range of locks. In view of the above, the present invention proposes a self-correcting multi-phase delay locking loop implemented in a full digital manner, which has an easy migration with a process, is suitable for use in an advanced process, and has better anti-noise capability and good locking speed. The circuit design is simple and can effectively increase the locking range and other features to achieve the synchronization effect of maintaining various components in the system. SUMMARY OF THE INVENTION One object of the present invention is to provide a fast self-correcting "apW calibration, RSC" algorithm for judging how self-correction should be performed when the phase differences of the multi-phase delay locked loop are different. - The purpose is to provide an unbalanced binary search algorithm 5 1^76879, which is suitable for full digital delay 2 = no _ page squaring. To add a lockable model, another object of the invention is According to the above method and the unbalanced binary search algorithm, a = positive-negative delay-locked loop structure is provided, and the self-correcting multi-phase architecture can be designed to allow the delayed delay of the designed delay-locked output. The compensation is delayed due to the delay of the lock (10) step, and effectively increases the range of the 。. The phase error of the present invention proposes a self-correction mechanism and a locking mechanism, various multi-phase output digital delay locking circuits. The above school system =: adjustment The phase difference between the output phases of each stage to eliminate the phase error caused by the delay of the delay, so that the multi-phase output can be the same at various frequencies. The phase difference output can be: The above locking mechanism can be: the range of the lock. θ ι The present invention discloses a full-digit self-correcting multi-phase delay locked loop 'which includes four main blocks' respectively: a set of digital Control delay delay line, a phase detector, a locking unit, and a self-correcting unit. The digital control delay line is formed by cascading the same delay stages in series, and all delay stages are transmitted through two The group control signal C[M:0] and the control. C[M:0] are generated by a locking unit using an unbalanced binary search algorithm. When the delay locked loop is locked, the self-correcting unit will generate Bi [ N: 〇] to adjust the phase difference between the output signals of the stages. The locking mechanism of the present invention is initiated by comparing the phase difference between the reference reference clock (reference elaek> and the output sfl number of the Kth stage, at this time self-correcting The unit is disabled (the disabled unit will adjust the control block C[M:0] according to the unbalanced binary 6 1376879 2012/6/11 no-line replacement page search algorithm, when the lock is completed Control delay line The delay time will be equivalent to a reference clock cycle, the signal LOCKED will be pulled up, and then the self-correction unit will be activated. The self-correction unit will implement the self-correction function of the output signal phase by changing the control block Bi[N:0]. And the control block C[M:0] is fixed so that the delay locked loop maintains the locked state. [Embodiment] The present invention will be described in detail with the preferred embodiment and the accompanying drawings. It should be understood that the preferred embodiments of the present invention are intended to be illustrative only and not limiting. Therefore, the present invention may be applied to other embodiments in addition to the preferred embodiments. It is not limited to any embodiment, and should be determined by the scope of the accompanying patent application and its equivalent. Refer to the figure
其係本發明之全數位自我校正多相位延 遲鎖定迴路之較佳實施例的示意圖。如圖所示，全數位自 我校正多相位延遲鎖定迴路100包含四個主要區塊，分別 為：一組數位式控制延遲線（digita„yc〇ntr〇Ueddeiayiine， DCDL)l〇2，-第-相位⑽器（phase detect〇r，pD)i〇4，一’ ，定單元Η)6’及-自我校正單元⑽。在數位式控制延遲 中為Κ個相同之延遲級。所有延遲級皆係經由控制 及卵增制。㈣社c陶係藉由採用 料衡式二元料演算法之較單元⑽絲得 ^组叫Ν··_係由自我校正單元灌所提供，且 1 遲鎖定迴路100鎖定後謹恒％敕 、' κ 貝疋傻運滇凋整各個輸出訊號之 差4代表第i個延遲級之多相 相位 夕相位延遲鎖定迴路的輸出訊 7 U76879 # 〇 & /0 · en ,1，* π 2012/6/11 無劃線替換頁 號。而Θ，代表第！個延遲級及第（Μ)個延遲級之間的相 位差。 鎖疋機制係由比對參考時脈㈣⑽⑽d。⑻盘抑之 間^目位差啟動。此時自我校正單元1〇8為無作用狀態， 鎖定早70 106將根據非平衡式二元搜尋演算法調整控制字 組C[M:〇]。當完成二元搜尋演算法之後，數位式控制延遲 線H)2所提供之延遲時間將會等同於一參考時 符合（1)時， ^ 1 + Θ2 + ... + ΘΚ-1 + ΘΚ = 360° (1) 則插^訊號locked，進而啟動自我校正單元1〇8。 自我权正早兀⑽將藉由改變控制字組叫N叫執行輸出 =之相位的自我校正功能，而控制字組c [ M: G ]係固定的 以讓延遲鎖定迴路維持鎖定的狀態。 本發明提出了-種快速自我校正演算法，其可在 額外電路之情泥下縮短校正週期。第二圖顯示出本發明之 陕速自我校正演算法之一較佳實施例(κ=5時)。此快速自 我校正演算法首先將考慮三個訊號；即參考時脈，Pi，及 P2。-數位相對式相位偵；則器（digitaliy reiative忡咖 mctor，DRPD)將藉由改變控制字組叫㈣]而將Θ丨調整 1+θ2)/2。同樣的’其將考慮後續之三個訊號；㈣， 2+=二並藉由改變控制字組B2[N:G]而將…調整為（Θ 。由於經過修改之將不會影響02，故可在同 ^考時脈週期内連續進行調整。最後，將根據！>5及1 考時脈而對θ5進行調整使其符合⑴，以保證整個延遲鎖 8 1376879 2012/6/1] fee,, 定迴路將可維持鎖定之狀態。在枝τ、a p Λ 線替換离 此過程甲，控岳丨 C[M:0]將保持不變以確保快速自哉校正之方去。刺字級 作。因此’各個延遲級之最終輸出^立差將為參:成士功運 期的五分之一。 4脤遮 由於上述校正電路係於數位、dQ^ 行，其目標將根據單位步階（unit sten、/τ工由 1η)中執 eP)」T而處理。秋 量化誤差（quantization error) qe 係叙 *、、、、而， 吨法避免的。第二 傳統校正演算法與本發明之快速自我 狄 < 圖為It is a schematic diagram of a preferred embodiment of the full digital self-correcting multi-phase delay locked loop of the present invention. As shown, the full-digit self-correcting multi-phase delay locked loop 100 includes four main blocks, namely: a set of digital control delay lines (digita„yc〇ntr〇Ueddeiayiine, DCDL) l〇2,-第- Phase detector (p) i〇4, a ', fixed cell Η) 6' and - self-correction unit (10). The same delay level in the digital control delay. All delay stages are Through control and egg production. (4) The community c pottery system is provided by the self-correcting unit irrigation unit by using the material-balanced binary material algorithm (10), which is provided by the self-correcting unit irrigation, and 1 late locking circuit. 100 locks after constant %敕, ' κ 疋 疋 疋 滇 滇 各个 各个 各个 各个 各个 各个 各个 各个 各个 各个 各个 各个 各个 各个 各个 代表 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U En ,1,* π 2012/6/11 There is no line to replace the page number. Θ, represents the phase difference between the first delay stage and the (Μ)th delay stage. The lock mechanism is used to compare the reference clock. (4) (10)(10)d. (8) The position difference between the discs is activated. At this time, the self-correcting unit 1〇8 is inactive, the lock As early as 70 106, the control block C[M:〇] will be adjusted according to the unbalanced binary search algorithm. When the binary search algorithm is completed, the delay time provided by the digital control delay line H)2 will be equivalent to When one reference corresponds to (1), ^ 1 + Θ2 + ... + ΘΚ-1 + ΘΚ = 360° (1) Then insert the signal signal locked, and then start the self-correction unit 1〇8. Self-right is early (10) The control block c [ M: G ] is fixed by changing the control block called N to perform the self-correction function of the output = phase. The present invention proposes a fast A self-correcting algorithm that shortens the correction period in the case of an additional circuit. The second figure shows a preferred embodiment of the Shaanxi speed self-correction algorithm of the present invention (κ = 5 o'clock). This fast self-correcting algorithm The method will first consider three signals; that is, the reference clock, Pi, and P2. - Digital relative phase detection; the digitaliy reiative mctor (DRPD) will be changed by changing the control block called (4)] Adjust 1+θ2)/2. The same 'will consider the next three signals; (4), 2+ =2 and by adjusting the control block B2[N:G], adjust ... to (Θ. Since the modified will not affect 02, it can be continuously adjusted during the same test clock cycle. Finally, According to the !>5 and 1 test clocks, θ5 is adjusted to conform to (1) to ensure that the entire delay lock can maintain the locked state. In the branch τ, ap Λ Line replacement is away from this process, and the control Yuelu C[M:0] will remain unchanged to ensure fast self-correction. Tattoo level. Therefore, the final output of each delay stage will be the reference: one-fifth of the period of the Chengshi power. 4 脤 由于 Because the above correction circuit is in the digit, dQ^ line, the target will be processed according to the unit step (unit sten, /τ work by 1η) in the eP)"T. Autumn quantization error qe is described by *, ,, and, and is avoided by the tonne method. The second conventional correction algorithm and the fast self of the present invention
正週期一隨機延遲誤差之結果的比_ 盆戸 贵間技 人 LJ is K=5，而單位步階及量化誤差均為h / a 、 a弋為 (皮秒）。如圖 本發明所提出之快速自我校正演算法^ ^示， 令較之傳統校正、、 所需之速度縮短了 4.17倍。 喷戽法 A 了射詩# + 多彳目位延遲 的情況下將鎖定其延遲，使其努„ . 瘦格在 較佳的情況下將鎖定其延遲’使其等同於一個時脈 况發生，多相位延 為了避免錯誤鎖定（false lock)的情 定迴路應維持在下列延遲範圍中操# , 0.5 X TREF < TDCDL < 1.5 X 作奸⑺ 其中TREF代表參考時脈週期，而tdcDl 位式控制延遲線之延遲時間。另外，#斤人μ、” 應付合（3)所矛 係’其中TINmAL為延遲鎖定⑼之㈣延遲^門 統二元搜尋機制之鎖定範圍係受（3)所p艮命j。 題期 遲颂 則代表數The ratio of the result of the positive period-random delay error is _ 戸 戸 贵 L L L = = = = = = = = = = = = = = = = 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位 单位As shown in the present invention, the fast self-correction algorithm shows that the required speed is shortened by 4.17 times compared with the conventional correction. Sneeze method A. When the poems are delayed, the delay will be locked, so that the thin grid will lock the delay in the better case, making it equivalent to a clock condition. Multi-phase delay In order to avoid false locks, the loop should be maintained in the following delay range. # 0.5 X TREF < TDCDL < 1.5 X (7) where TREF represents the reference clock period and the tdcDl position Control the delay time of the delay line. In addition, #斤人μ, " cope with (3) spears" where TINmAL is the delay lock (9) (4) delay ^ gate system binary search mechanism lock range is subject to (3) p Commandment j. The title period is late, it represents the number
Max(TDCDL_MIN, 2/3 x TINITIAL) < TREF <MIN(TDCDL_MAX, 2 x TINITIAL) (3) 本發明所提供之非平衡式二元搜尋演算法將選擇一合 9 )0/y ig ^ ΤΤΧΓΤττ Λ T 2012/6/11 無劃線替換頁 ^ 而非選擇數位式控制延遲線路之中間點。 第四圖係本發明之1 __ 位7L非平衡式二元搜尋法之流程圖。 根據此流程圖將可找出-適當的TmmAL數值。 在較佳實施例中，一多相位延遲鎖定迴路包含一组 多相位輸出之延遲線’一相位偵測器，一組階段控制器 ⑻叩controller)及一組二元控制器㈣町⑽的㈣。在此 實^例中 > 夕相位輸出延遲線係由多個延遲級所串連而 成上述每一個延遲級均係由兩個延遲單元（和1叮⑶⑴所 :且f其中一延遲單元係由二元控制器所控制，而另-延 遲單元則係由可上下數計時器（up/d。·⑶捕以)控制。 在車乂佳實施例中’鎖定單元包含一階段控制器5〇〇 及-元控制器600，分別顯示於第五圖及第六圖中。階 段控制H將顯示出目前進人鎖定單元之階段，而二元控制 器將執行:專統二元搜尋之運作，其中各個控制位元係由單 位元產生器（single_bit generat〇r)所提供。 如第五圖所*，其係、一用來產生控制二元控制器之控 制汛號的又控制器5〇〇，其包含一組平移暫存器㈣出 regBter)，用以產生二元控制器之控制訊號；一 d型觸發 器（flip flop) ’用以判斷參考時脈與輸出訊號之間的關係， 其輸入為參考時脈，而其觸發訊號係延遲線最後—級之輸 出訊號；及二組多工器，其選擇訊號係根據D型觸發器之 結果產生平移暫存器之控制訊號。 參照第六圖，其係由數個單位元產±器串連而成之二 兀控制器600，其包含一 D型觸發器，兩組多工器，一組 1376879 2(Η2/6/11無劃線替換頁 邏輯或閉（OR gate)及一組邏輯及閘（AND gate)。此二元控 制器將根據階段控制器及相位偵測器之控制訊號而產生多 相位輸出延遲線之控制訊號。 在一較佳實施例中，其係於初始之際將P5重設為最 知之延遲時間^ D型觸發器將可判斷TDCDL_MIN是否大 於TREF之兩倍以決定所欲之階段以及該輸入哪一階段來 決定TINITIAL。而後續階段之操作則係根據二元搜尋演算 法執行。透過鎖定單元可避免錯誤鎖定之發生並將鎖定範 鲁圍延長至(4)。 TDCDL MIN < TREF < TDCDL—MAX (4) 另一方面，由於TDCDL·將符合（2)，因此可將除頻器 比率（divider ratio)設為2以達到最快的鎖定時間。根據非 平衡式二元搜尋演算法完成一延遲鎖定電路之鎖定所需的 整體週期將不會多於14個（7X2)參考時脈週期。 在一較佳實施例中，當訊號locked被***後將啟動 •自我校正單元，其將補償因製程變動所引起之相位差（不匹 配=第七圖係本發明之較佳實施例的自我校正單元7〇〇之 示，圖。如圖所示，自我校正單元7〇〇包含一第二相位偵 測器702 ’用以判斷最後一級輸出訊號與參考時脈之間的 相位差，四個數位相對式相位偵測器（7〇4 、706、708、710)， 心㈣輸出訊號與前-級輸出訊號之相位差和輸出訊號 與後一級輸出訊號之相位差，兩者相位差之間的關係（大 ^及五個可上下數计時器⑺2、7〗4 ^6 ^8、72…， 别用以控制多相位輸出延遲線各級輸出訊號之延遲時 1376879 間，以在第i個延遲級控制 加細丨無劃線替換頁 白冼栌τ时 母1固早控制字組Bi[2:0]。 多相位==;内^ ―級輸=第二:第 數位相對式相位偵測器之輪出 益之上數訊遗係由 H 訊號（1為整數）。舉例來說，數位相對式 =;第(第二級)的輸入為多相位輸出延遲線之第 :0>”、第二級(P2)、第三級⑽輸 汁時器714之上數訊號係由數 下數 耠 對式相位偵測器708之 輸出《產生’其觸發訊號為第五級（p5)輸出訊號。 卜相位偵測器702之輸入為多相位輸出延遲線之 及（P5)輸出訊號與參考時脈，而可上下數計時器720 =上數訊號係由該第：相位偵測器7G2之輸出訊號產生， ”觸發訊號為第三級（P3)輸出訊號。 自我杈正單元700將持續校正相位之不匹配直到相對 相位誤差小於數位相對式相位债測器之量化誤差為止。去 上述情形發生時，訊號L〇CKUf被拉起，且將決定第 控制字組Bi[2:〇]之數值。 、在一較佳實施例中，上述自我校正可在同一參考時脈 週期内連續校正所有的（五個）控制字組Bi[2:〇卜於第一來 考訊號之下一個正緣（positive edge)之前，校正後之運作應 為穩定的。上述需求係透過將遠遠相隔的多相位輸出作^ 觸發時脈（trigger clock)達成，而不需額外的時序控制電 路。當所有的訊號LOCKi皆為低訊號（i〇w signal)時，即代 12 1376879 2012/6/11無劃線替換頁 表每個延遲級内之相對相位誤差係小於量化誤差。其將插 入訊號FINISH以停止上下計時器的使用，而控制字組 Βι[2:0]將為固定的。當某個階段之相對相位誤差大於數位 相對式相位偵測器之量化誤差時，自我校正單元將重新啟 動。上述相位維持之運作係即時且持續的。 在一較佳實施例中，其模擬環境係採用台灣積體電路 公司（TSMC)之1.2V 130nm CMOS技術模型所建立。其操 作頻率範圍為333MHZ-1GHz。高於5〇〇MHz及低於 500MHz之鎖疋私序分別需要丨2及14個參考時脈週期。 本發明所提出之延遲鎖定訊號將提供8位元的解析度’，而 其最低有效位元（l〇west significant bit，LSB)之解析度為8 PS°其整體功率消耗在333MHz時為2 7讀，而在iGHz 時則為5.2mW。其製程不匹配（pr〇cess mismatch)的問題可 由L遲7G件内之電容應付。第八圖顯示出當操作頻率為 500MHz時，各個延遲級之相位誤差。如圖所示，採用本 發明之快速自我校正演算法後可有效縮減各個延遲級之相 位誤差。舉例來說’原本在p2_p3之延遲級所發生之最大 ^目位誤差為27ps (24.3。），而在採用快速自我校正演算法 後，可將上述最大相位誤差縮減至9ps (8 ι(>)。 綜上所述，本發明之快速自我校正演算法可來 内同時調整所有輪出訊號之相位，以使任意前後兩 號之間的相位差均相同，進而達到快速自我校正 力用。而本發明之非平衡式二元搜尋 適當的數位式控制延料之選擇 13 定’進而增加可鎖定之範圍。 2012/6/11無劃線替換頁 上述敘述係本發明之較佳實施例。此領域之技蓺者應 得:領會其係用以說明本發明而非用以以本發明所主張 之專利_範1其專利保護範圍當視後附之申請專利範 圍及其等同領域而定。凡孰籴 ^ φ ^ "、、，'"此領域之技藝者，在不脫離 本專利精神或範_，所作之更動或潤飾，均屬於本發明 所揭f精神下所完成之等效改變或設計，且應包含在下述 之申凊專利範圍内。 【圖式簡單說明】 本發明可藉由說明書中若干較佳實施例及詳細敘述以 及後附圖式得以瞭解。然而，此領域之技藝者應得以領會 所有本發明之較佳實施例係用以說明而非用以限制本發明 之申清專利範圍，其中： 第-圖係本發明之全數位自我校正多相位延遲鎖定迴 路之較佳實施例的示意圖； • 帛二圖顯示出本發明之快速自我校正演算法之一較佳 實施例（Κ=5時）； 〃第三圖為傳統校正演算法與本發明之快速自我校正演 算法兩者間校正週期-隨機延遲誤差之結果的比較圖； 圖； 第四圖係本發明之3位元非平衡式二元搜尋之流程 第五圖係本發明之較佳實施例的階段控制器之示意 第六圖係本發明之較佳實施例的二元控制器之示意 1376879 2012/6/11無劃線麵頁 圖； 第七圖係本發明之較佳實施例的自我校正單元之示意 圆， 士第八圖係本發明之較佳實施例（當操作頻率為500MHZ 時）的各個延遲級之相位誤差的示意圖。 【主要元件符號說明】 100全數位自我校正多相位延遲鎖定迴路 102數位式控制延遲線 ® 104第-相位偵測器 106鎖定單元 1〇8自我校正單元 500階段控制器 600二元控制器 7〇〇自我校正單元 702第二相位彳貞測器 • 7〇4數位相對式相位偵測器 706數位相對式相位偵測器 708數位相對式相位偵測器 710數位相對式相位偵測器 712可上下數計時器 714可上下數計時器 716可上下數計時器 718可上下數計時器 720可上下數計時器 1376879 2012/6/11無劃線替換頁Max(TDCDL_MIN, 2/3 x TINITIAL) < TREF <MIN(TDCDL_MAX, 2 x TINITIAL) (3) The unbalanced binary search algorithm provided by the present invention will select a combination of 9)0/y ig ^ ΤΤΧΓΤττ Λ T 2012/6/11 No scribe line replacement page ^ Instead of selecting the midpoint of the digital control delay line. The fourth figure is a flow chart of the 1__bit 7L unbalanced binary search method of the present invention. According to this flow chart, the appropriate TmmAL value can be found. In a preferred embodiment, a multi-phase delay locked loop includes a set of multi-phase output delay lines 'a phase detector, a set of stage controllers (8) 叩 controller) and a set of binary controllers (four) (10) (4) . In this embodiment, the ei-phase output delay line is connected in series by a plurality of delay stages, each of which is composed of two delay units (and 1 叮 (3) (1): and f one of the delay units It is controlled by the binary controller, and the other-delay unit is controlled by the up/down timer (up/d.·(3) capture). In the embodiment of the vehicle, the lock unit includes a one-stage controller. The 〇 and _ controller 600 are respectively shown in the fifth and sixth figures. The phase control H will display the stage of the current entry lock unit, and the binary controller will perform: the operation of the exclusive binary search, Each of the control bits is provided by a single element generator (single_bit generat〇r). As shown in the fifth figure, the controller is used to generate a control nickname for controlling the binary controller. , comprising a set of translation registers (4) out regBter) for generating a control signal of the binary controller; a d-type flip-flop (flip flop) is used to determine the relationship between the reference clock and the output signal, The input is the reference clock, and its trigger signal is the delay line last-level The output signal; and the two sets of multiplexers, the selection signal is based on the result of the D-type flip-flop to generate the control signal of the translation register. Referring to the sixth figure, it is a two-way controller 600 which is connected by a plurality of unit cells and includes a D-type flip-flop, two sets of multiplexers, and a group of 1376879 2 (Η2/6/11). The non-line replaces the page logic or OR gate and a set of logic and gates. The binary controller will generate multi-phase output delay line control according to the control signals of the phase controller and the phase detector. In a preferred embodiment, it is reset to the most known delay time at the initial stage. The D-type flip-flop will determine if TDCDL_MIN is greater than twice the TREF to determine the desired phase and which input. The TINITIAL is determined in one stage, and the subsequent operations are performed according to the binary search algorithm. The locking unit can avoid the occurrence of false locking and extend the locking range to (4). TDCDL MIN < TREF < TDCDL —MAX (4) On the other hand, since TDCDL· will conform to (2), the divider ratio can be set to 2 to achieve the fastest lock time. According to the unbalanced binary search algorithm. The overall required for a lock of the delay lock circuit The period will not be more than 14 (7X2) reference clock cycles. In a preferred embodiment, when the signal locked is inserted, the self-correction unit will be activated, which will compensate for the phase difference caused by the process variation (not Matching = seventh diagram is a self-correcting unit 7 of the preferred embodiment of the present invention. As shown, the self-correcting unit 7A includes a second phase detector 702' for determining the final Phase difference between the primary output signal and the reference clock, four digital relative phase detectors (7〇4, 706, 708, 710), the phase difference between the heart (four) output signal and the pre-stage output signal and the output signal The phase difference between the output signal and the output signal of the latter stage, the relationship between the two phase differences (large ^ and five countable up and down timers (7) 2, 7〗 4 ^6 ^8, 72..., not used to control the multi-phase output delay The delay of the output signal of each line of the line is 1376879, in order to control the page 冼栌τ when the ith delay stage is controlled by the fine line without the scribe line, the parent 1 is early control group Bi[2:0]. Multiphase == ; inside ^ ― level input = second: the number of relative phase detectors By H signal (1 is an integer). For example, the digital relative expression =; the (second level) input is the multi-phase output delay line: 0; gt;", second level (P2), third level (10) The number signal on the juicer 714 is outputted by the number of pairs of phase detectors 708, and the trigger signal is the fifth level (p5) output signal. The input of the phase detector 702 is The phase output delay line sums (P5) the output signal and the reference clock, and the up and down timer 720 = the upper signal is generated by the output signal of the phase detector 7G2, "the trigger signal is the third level ( P3) Output signal. The self-correcting unit 700 will continuously correct the phase mismatch until the relative phase error is less than the quantization error of the digital relative phase detector. When the above situation occurs, the signal L〇CKUf is pulled up and the value of the control word group Bi[2:〇] will be determined. In a preferred embodiment, the self-correction can continuously correct all (five) control blocks Bi[2 in the same reference clock cycle. [2: a positive edge under the first reference signal (positive) Before the correction, the corrected operation should be stable. The above requirements are achieved by using a far apart multi-phase output as the trigger clock without additional timing control circuitry. When all the signals LOCKi are low signal (i〇w signal), that is, 12 1376879 2012/6/11 no-line replacement page The relative phase error in each delay stage is smaller than the quantization error. It will insert the signal FINISH to stop the use of the up and down timers, while the control block Βι[2:0] will be fixed. When the relative phase error of a certain phase is greater than the quantization error of the digital relative phase detector, the self-correction unit will restart. The operation of the above phase maintenance is immediate and continuous. In a preferred embodiment, the simulation environment is established using a 1.2V 130nm CMOS technology model from Taiwan Semiconductor Manufacturing Corporation (TSMC). Its operating frequency range is 333MHZ-1GHz. Locked private sequences above 5 〇〇 MHz and below 500 MHz require 丨 2 and 14 reference clock cycles, respectively. The delay locked signal proposed by the present invention will provide an 8-bit resolution', and the resolution of the least significant bit (LSB) is 8 PS. The overall power consumption is 2 7 at 333 MHz. Read, but at 5.2mW at iGHz. The problem of pr〇cess mismatch can be dealt with by the capacitance in L7G. The eighth graph shows the phase error of each delay stage when the operating frequency is 500 MHz. As shown, the phase error of each delay stage can be effectively reduced by using the fast self-correction algorithm of the present invention. For example, the maximum error that occurred in the delay stage of p2_p3 is 27ps (24.3.), and after using the fast self-correction algorithm, the maximum phase error can be reduced to 9ps (8 ι(> In summary, the fast self-correction algorithm of the present invention can adjust the phase of all the round-trip signals simultaneously, so that the phase difference between any two front and the rear is the same, thereby achieving rapid self-correction. The unbalanced binary search of the present invention selects the appropriate digital control of the extension of the material and then increases the range of lockable. 2012/6/11 No scribe replacement page. The above description is a preferred embodiment of the present invention. Those skilled in the art should understand that the patents are intended to be illustrative of the invention and are not intended to be claimed by the invention. The scope of patent protection is determined by the scope of the patent application and its equivalents.孰籴^ φ ^ ",,,'" The skilled person in this field, without departing from the spirit or scope of this patent, makes any changes or refinements that are made under the spirit of the invention. Or design and should contain BRIEF DESCRIPTION OF THE DRAWINGS [Brief Description of the Drawings] The present invention can be understood by a number of preferred embodiments and detailed descriptions and the following figures in the specification. However, those skilled in the art should be able to understand all of them. The preferred embodiments of the invention are intended to be illustrative, and not to limit the scope of the claimed invention, in which: FIG. 1 is a schematic diagram of a preferred embodiment of the full digital self-correcting multi-phase delay locked loop of the present invention; Figure 2 shows a preferred embodiment of the fast self-correction algorithm of the present invention (Κ = 5 o'clock); 〃 The third figure shows the correction period between the conventional correction algorithm and the fast self-correction algorithm of the present invention - A comparison diagram of the results of the random delay error; Fig. 4 is a flow chart of the 3-bit unbalanced binary search of the present invention. The fifth diagram is a schematic diagram of the stage controller of the preferred embodiment of the present invention. The schematic diagram of the binary controller of the preferred embodiment of the present invention is 1376879 2012/6/11 without a lined page; the seventh figure is a schematic circle of the self-correcting unit of the preferred embodiment of the present invention, the eighth A schematic diagram of the phase error of each delay stage of the preferred embodiment of the present invention (when the operating frequency is 500 MHz). [Main Element Symbol Description] 100 Full Digit Self-Correcting Multi-Phase Delay Locking Loop 102 Digital Control Delay Line® 104 Phase-phase detector 106 lock unit 1〇8 self-correction unit 500 stage controller 600 binary controller 7〇〇 self-correction unit 702 second phase detector • 7〇4 digital relative phase detector 706 Digital relative phase detector 708 digital relative phase detector 710 digital relative phase detector 712 can be up and down timer 714 can be up and down timer 716 can be up and down timer 718 can be up and down timer 720 can be up and down Number timer 1376879 2012/6/11 no line replacement page
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