201014187 六、發明說明： 【發明所屬之技術領域】 本發明係關於延遲鎖定迴路，特別是關於一種全數位 快速鎖定自我校正多相位延遲鎖定迴路。 【先前技術】 隨著積體電路（ic)的進步與發展，積體電路之執行效 能已經過大幅改善而電路之複雜度亦隨之提昇，各方面之 ©應用，包括資訊，通訊，消費性電子產品及微處理器均朝 向單晶片系統（system on a Chip，s〇C)發展。然而，上述系 統通常包含許多不同元件，而各元件對於同一參考時脈將 產生不同的延遲，因而需要在系統中加入鎖相迴路 locked loop，PLL)或延遲鎖定迴路（delay_1〇cked 1〇〇p，dll) 以進行時脈之校正並維持系統的同步。 一般而言，鎖相迴路内包含一電壓控制振盪器（v〇ltage controlled 〇scillator)，而此電壓控制振盪器常會無法避免 的累積抖動（jitter) ’進而使得鎖相迴路之雜訊抗擾性（n〇ise immunity)低於延遲鎖定迴路。除了低成本與較良好之抖動 表現之外，延遲鎖定迴路之穩定性與快速鎖定之特性亦使 其較常被採用。另-方面，鎖相迴路通常係採用類比電路 或與數位電路混合的設計，其可鎖定之範圍雖較大（與全數 位之延遲鎖定迴路相比）’但其功率之損耗卻比全數位式的 設計高出許多。 美國專利第6,501，336號揭露了 一種自我校正裝置與 201014187 方法，用於校正環狀振盪器的輸出波形（outPut waveform) 之間的相位偏移（phase offset)。此方法係於多相位鎖相迴 路之架構下，補償各輸出訊號之間由於製程上的變動或訊 號傳遞路徑的不同所造成之延遲誤差（delaymismatch)。假 設其具有8個多相位之輸出，其補償原理係利用鎖相迴路 之鎖定機制而將原本之鎖定參考時脈與除Μ頻说號改為 鎖定參考時脈與除（Μ+1/8)頻訊號。藉由上述改變’補償機 制可漸進改變多相位之間的相位差，使其最終變為相等201014187 VI. Description of the Invention: [Technical Field] The present invention relates to a delay locked loop, and more particularly to a full digital fast lock self-correcting multi-phase delay locked loop. [Prior Art] With the advancement and development of integrated circuits (ic), the performance of integrated circuits has been greatly improved and the complexity of circuits has increased. Applications in all aspects, including information, communication, and consumerism. Both electronic products and microprocessors are moving toward system on a chip (s〇C). However, the above system usually contains many different components, and each component will have different delays for the same reference clock. Therefore, a phase-locked loop (PLL) or a delay-locked loop (delay_1〇cked 1〇〇p) needs to be added to the system. , dll) to make clock corrections and maintain system synchronization. In general, the phase-locked loop contains a voltage-controlled oscillator (v〇ltage controlled 〇 scillator), and this voltage-controlled oscillator often avoids the accumulation of jitter (jitter), which in turn makes the noise immunity of the phase-locked loop (n〇ise immunity) is lower than the delay lock loop. In addition to low cost and better jitter performance, the stability and fast locking characteristics of the delay-locked loop make it more common. On the other hand, the phase-locked loop is usually a analog circuit or a design mixed with a digital circuit. The lockable range is large (compared to the full-digit delay locked loop), but its power loss is better than the full digital The design is much higher. U.S. Patent No. 6,501,336 discloses a self-correcting device and a method of 201014187 for correcting the phase offset between the outPut waveforms of a ring oscillator. This method is based on the architecture of the multi-phase phase-locked loop, and compensates for delay errors caused by variations in the process or signal transmission paths between the output signals. Assume that it has 8 multi-phase outputs, the compensation principle is to use the locking mechanism of the phase-locked loop to change the original locked reference clock and the frequency-defining frequency to the locked reference clock and divide (Μ+1/8). Frequency signal. By the above-mentioned change, the compensation mechanism can gradually change the phase difference between the multi-phases to make them eventually equal.
A 的。新式之除（M+1/8)頻訊號之除頻器係依序利用輸出訊號 所產生，其控制訊號則係由有限狀態機（finite state machine， FSM)實施。上述專利所揭露之裝置與方法係混合訊號的設 計，其中鎖相迴路與自我校正之機制皆係以類比方式實 施，而除頻電路與其控制訊號則係以數位方式實施。由於 上述專利之裝置與方法係以混合訊號之多相位鎖相迴路架 構所建立，因而具有不易隨著製程移植，較不適用於先進 ❿製程及擁有較低抗雜訊能力等缺點。 另外，2006年Η. H. Chang等人發表於IEEE J. Solid-State Circuits 第 41 卷第 5 期第 1051-1061 頁之文獻 (A 0.7-2GHz Self-Calibration Multiphase Delay-Locked Loop)，提出了一種利用數位校正電路降低多相位時脈之間 因不匹配所引起之時序誤差（mismatch_induced timing error)的方法。此方法係於多相位延遲鎖定迴路之架構下， 根據所應用之自我校正演算法以數位式調整輸出緩衝器 (output buffer)的方式調整各輸出訊號間之相位差，使用時 4 201014187 序控制電路（timing control circuit)於一 I 土丄 号時脈週湘 (reference cycle)内選擇需調整之輸出訊號，藉由一 a 邱 一級的輸出補償延遲誤差，最終使多相位輪出 _人調整 相位差均能相同。由於此方法需要額外的時序控制 因此在設計上較為複雜，且其一次只能調整_ 趿的輸出訊 號，故將延長鎖定之速度。 另一方面，2000年G. K. Dehng等人發表於IEEE j Solid-State Circuits 第 35 卷第 8 期第 1128-1136 頁之文獻 ❹ (Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop)，提出了 一種全數位延遲鎖定迴路， 其鎖定機制係以二元搜尋（binary search)之方式進行。此方 法之缺點在於其鎖定範圍較大（wide range)時，可能會有稭 波鎖定（harmonic lock)的問題。 有鑑於上述，本發明提出一種以全數位方式實施之自 我校正多相位延遲鎖定迴路，其具有易於隨著製程移植， ❹適合應用於先進製程，擁有較佳的抗雜訊能力與良好鎖定 速度，電路設計簡單並能有效增加鎖定範圍等特徵，以達 到維持系統中各元件之同步的效果。 【發明内容】 本發明之一目的係在於提供一種快速自我校正（rapid self-calibration，RSC)之演算法，以於多相位延遲鎖定迴路 之各個相位差不相同時，判斷應當如何自我校正。 本發明之一目的係在於提供一種非平衡式二元搜尋演 算法，適用於全數位式延遲鎖定迴路，以增加可鎖定之範 5 201014187 圍（lock range)。 本發明之又-目的係在於根據上述快速自我校 f及非平衡式二元搜尋演算法提供—種具自我校正之^ ^遲敎㈣㈣’此㈣可軸設計岐遲鎖 之多項延遲鎖定的輸出補償因延遲誤差所造成 (phaSeerror)，並有效增加鎖定範圍。 位誤差 ❹ 本發明提出-種自我校正機制及鎖定機制 各種多相位輸itj之數錢遲鎖定電路4述自我校正制 之目的在於調整各輸出相位之間的相位差 駐所造成之妹縣，使得在各種㈣下，多 2能有相同的相位差輸出。而上述鎖定機制則可增加能鎖 定之範圍。 本發明揭露了-種全數位自我校正多相位延遲鎖定迴 路，其包含四個主要的區塊，分別為：一組數位 遲線，一相位積測器，一鎖定單元，及一校正單元。數^ © 式控制延遲線係由K個相同之延遲階段_連所形成，而所 有的延遲階段均係透過兩組控制訊號卩馗:…與Bi[N 所 控制。C[M:0]係由採用非平衡式二元搜尋演算法之鎖定單 元所產生。當延遲鎖定迴路鎖定時，校正單元將產生Bi[N:〇] 以調整各輸出訊號之間的相位差。 本發明之鎖定機制係由比對參考時脈（referenee el()ek) 與第K級的輸出訊號之間的相位差啟動，此時校正單元為 無作用狀態（disabled)，鎖定單元將根據非平衡式二元搜尋 演算法調整控制字組C[M:0]，當完成鎖定之後數位式控制 6 201014187 延遲線所提供之延遲時間將會等同於一參考時脈週期，訊 號LOCKED將拉起，進而啟動校正單元。校正單元將藉由 改變控制字組Bi[N:0]實施輸出訊號相位之自我校正功 能，而控制字組C[M:0]係固定的，以讓延遲鎖定迴路維 鎖定的狀態。 ' ' 【實施方式】 本發明將配合其較佳實施例與隨附之圖示詳述於下。 應可理解者為本發明中所有之較佳實施例僅為例示之用， 並非用以限制。因此除文中之較佳實施例外，本發明亦可 廣泛地應用在其他實施例中。且本發明並不受限於任何實 施例，應以隨附之申請專利範圍及其同等領域而定。 參照第一圖，其係本發明之全數位自我校正多相位延 遲鎖定迴路之較佳實施例的示意圖。如圖所示，全數位自 我校正多相位延遲鎖定迴路1〇〇包含四個主要區塊，分別 為：一組數位式控制延遲線⑻的御㈣⑽㈣制…⑻， ❹ DCDL) 102，一相位偵測器（phase detect〇r，pD) i 〇4，一 鎖定 單元106，及一权正單元1〇8。在數位式控制延遲線Μ〕 中為K個相同之延遲階段。所有延遲階段皆係經由控制字 組,C[M:0]及Bi[N:0]控制。控制字組c[M:〇]係藉由採用非 平衡式二元搜尋演算法之鎖定單元106所取得。而控制字 組Τ[Ν:0]則係由自我校正單元1〇8所提供，且其將於延遲 鎖疋迴路1 〇〇鎖疋後謹慎調整各個輸出訊號之間的相位 差。Pi代表第i個延遲階段之多相位延遲鎖定迴路的輸 出。而θί則代表第；個延遲階段及第（ί_υ個延遲階段之間 201014187 的相位差。 鎖定機制係由比對參考時脈（reference clock)與Pk之 間的相位差啟動。此時校正單元108為無作用狀態，鎖定 單元106將根據非平衡式二元搜尋演算法調整控制字組 C[M:0]。當完成二元搜尋演算法之後，數位式控制延遲線 1〇2所提供之延遲時間將會等同於一參考時脈週期。當符 合（1)時， ❹ ❹ 則***訊號LOCKED，進而啟動校正單元1〇8。校正 單元108將藉由改變控制字組Bi[N:〇]執行輸出訊號之相 位的自我校正功能，而控制字組c[M:〇]係固定的以讓延遲 鎖定迴路維持鎖定的狀態。 本發明提出了一種快速自我校正演算法，其可在不需 額外電路之情況下縮短校正週期。第二圖顯示出本發明之 ::自我校正演算法之一較佳實施例(κ=5時)。此快速自 校正演算法首先將考慮三個訊號；即參考時脈，Η，及 d t ° 一數位相對式相位偵測器⑷gitally relati hase 1 (Γ；Ι；Γ^ ^ ^ . Β! [Ν:0] , , ^ Ρ2’及Ρ3 #茲同樣的其將考慮後續之三個訊號：即卩卜 改變控制字組聊:G]而將^調整為（Θ -參考時财心經過修改之Μ將不會影響。，故可在同 麥亏時脈週期内連續 曰& ^ 考時脈而對Μ進行調整合=以=广及參 ⑼路將可維持鎖定之狀態。在整= 201014187 C[M:0]將保持不變以確保快速自我校正之方法可成功運 作。因此，各個延遲階段之最終輸出相位差將為參考時脈 週期的五分之一。 由於上述校正電路係於數位領域（digital d〇main)中執 行’其目標將根據單位步階（unit step) zl T而處理。然而， 量化誤差（quantization error) qe係無法避免的。第三圖為 傳統校正演算法與本發明之快速自我校正演算法兩者間校 正週期一隨機延遲誤差之結果的比較圖。其環境設定為 K=5 ’而單位步階及量化誤差均為5ps (皮秒）。如圖所示， 本發明所提出之快速自我校正演算法較之傳統校正演算法 所需之速度縮短了 4.17倍。 為了使有效取樣率達到最大’多相位延遲鎖定迴路在 較佳的情況下將鎖定其延遲，使其等同於一個時脈週期。 為了避免錯誤鎖定（false lock)的情況發生，多相仅延 ， 定迴路應維持在下列延遲範圍甲操作： 鎖 ❹ 0.5 X TREF < TDCDL < 1.5 x TREF (2) 傳 其中TREF代表參考時脈週期，而tdcDL則、 位式控制延遲線之延遲時間。另外，應符合（3)所_、表數 係，其中TINITIAL為延遲鎖定電路之起始延遲時=之關 統二元搜尋機制之鎖定範圍係受（3)所限制。 ^A's. The new type of (M+1/8) frequency signal divider is generated by the output signal in sequence, and the control signal is implemented by a finite state machine (FSM). The apparatus and method disclosed in the above patents are mixed signal designs in which the phase-locked loop and the self-correcting mechanism are implemented in an analogous manner, and the frequency-dividing circuit and its control signal are implemented in a digital manner. Since the devices and methods of the above patents are established by a multi-phase phase-locked loop architecture of mixed signals, they are not easy to be transplanted with the process, are not suitable for advanced processes, and have low anti-noise capability. In addition, in 2006, H. Chang et al. published in IEEE J. Solid-State Circuits, Vol. 41, No. 5, pp. 1051-1061 (A 0.7-2 GHz Self-Calibration Multiphase Delay-Locked Loop), A method for reducing a timing error (mismatch_induced timing error) caused by a mismatch between multi-phase clocks by using a digital correction circuit. The method is based on the multi-phase delay locked loop architecture, and adjusts the phase difference between the output signals according to the applied self-correction algorithm by digitally adjusting the output buffer. When used, the 4 201014187 sequence control circuit is used. (timing control circuit) selects the output signal to be adjusted in the reference cycle of the I-I number, and compensates the delay error by the output of a qi level, and finally adjusts the phase difference by multi-phase rotation All can be the same. Since this method requires additional timing control, it is more complicated in design, and it can only adjust the output signal of _ 一次 at a time, so the speed of locking will be prolonged. On the other hand, in 2000, GK Dehng et al. published in IEEE j Solid-State Circuits, Vol. 35, No. 8, No. 1128-1136 (Clock-Deskew Buffer Using a SAR-Controlled Delay-Locked Loop) An all-digital delay locked loop whose locking mechanism is implemented in a binary search. The disadvantage of this method is that there may be a problem with the harmonic lock when it has a wide range. In view of the above, the present invention provides a self-correcting multi-phase delay locking loop implemented in a full digital manner, which is easy to be transplanted with a process, is suitable for use in advanced processes, has better anti-noise capability and good locking speed. The circuit design is simple and can effectively increase the locking range and other characteristics to achieve the synchronization effect of each component in the system. SUMMARY OF THE INVENTION One object of the present invention is to provide a fast self-calibration (RSC) algorithm for judging how self-correction should be performed when the phase differences of the multi-phase delay locked loop are different. It is an object of the present invention to provide an unbalanced binary search algorithm that is suitable for a full digital delay locked loop to increase the lockable range of the 2010 14187 lock range. The purpose of the present invention is to provide a self-correcting ^ ^ 敎 (4) (4) according to the above-mentioned fast self-calibration and non-balanced binary search algorithm. The compensation is caused by the delay error (phaSeerror) and effectively increases the locking range. Bit error ❹ The present invention proposes a self-correction mechanism and a locking mechanism for various multi-phase input itj. The self-correction system is designed to adjust the phase difference between the output phases to cause the sister county, so that Under various (four), more than 2 can have the same phase difference output. The above locking mechanism can increase the range that can be locked. The present invention discloses an all-digital self-correcting multi-phase delay locked loop comprising four main blocks, namely: a set of digit delay lines, a phase accumulator, a locking unit, and a correction unit. The number of control-delay lines is formed by K identical delay stages, and all delay stages are controlled by two sets of control signals ...:... and Bi[N. C[M:0] is generated by a locking unit using an unbalanced binary search algorithm. When the delay lock loop is locked, the correction unit will generate Bi[N:〇] to adjust the phase difference between the output signals. The locking mechanism of the present invention is initiated by comparing the phase difference between the reference signal (referenee el() ek) and the output signal of the Kth stage, at which time the correction unit is disabled, and the locking unit will be based on non-equilibrium. The binary search algorithm adjusts the control block C[M:0]. When the lock is completed, the delay time provided by the digital line 6 201014187 delay line will be equivalent to a reference clock cycle, and the signal LOCKED will be pulled up. Start the correction unit. The correction unit will implement the self-correction function of the output signal phase by changing the control block Bi[N:0], and the control block C[M:0] is fixed so that the delay lock loop is locked. [Embodiment] The present invention will be described in detail with reference to the preferred embodiments thereof and the accompanying drawings. It should be understood that all of the preferred embodiments of the present invention are intended to be illustrative only and not limiting. Therefore, the invention may be applied to other embodiments in addition to the preferred embodiments described herein. The present invention is not limited to any embodiment, and should be determined by the scope of the appended claims and their equivalents. Referring to the first figure, a schematic diagram of a preferred embodiment of the full digital self-correcting multi-phase delay locked loop of the present invention. As shown, the full digital self-correcting multi-phase delay locked loop 1〇〇 contains four main blocks, namely: a set of digital control delay lines (8) of the Royal (four) (10) (four) system... (8), ❹ DCDL) 102, a phase detection A phase detector (pD) i 〇 4, a locking unit 106, and a righting unit 1 〇 8. In the digital control delay line Μ] are K identical delay stages. All delay phases are controlled via the control block, C[M:0] and Bi[N:0]. The control block c[M:〇] is obtained by the locking unit 106 using the unbalanced binary search algorithm. The control word group Ν[Ν:0] is provided by the self-correction unit 1〇8, and it will carefully adjust the phase difference between the output signals after delaying the lock loop 1 〇〇 lock. Pi represents the output of the multi-phase delay locked loop of the ith delay phase. And θί represents the phase difference between the first delay phase and the (ί_υ delay phase 201014187. The locking mechanism is initiated by comparing the phase difference between the reference clock and Pk. At this time, the correction unit 108 is Inactive state, the locking unit 106 will adjust the control block C[M:0] according to the unbalanced binary search algorithm. After completing the binary search algorithm, the digital control delay line 1〇2 provides the delay time It will be equivalent to a reference clock cycle. When (1) is met, ❹ ❹ inserts the signal LOCKED, which in turn activates the correction unit 1〇 8. The correction unit 108 will perform the output by changing the control block Bi[N:〇]. The self-correcting function of the phase of the signal, and the control block c[M:〇] is fixed to maintain the locked lock loop in a locked state. The present invention proposes a fast self-correction algorithm that can be used without additional circuitry. The correction period is shortened. The second figure shows the preferred embodiment of the present invention: self-correction algorithm (κ = 5). This fast self-correction algorithm will first consider three signals; , Η, and dt ° a digital relative phase detector (4) gitally relati hase 1 (Γ;Ι;Γ^ ^ ^ . Β! [Ν:0] , , ^ Ρ2' and Ρ3 #z Three signals: that is, change the control word group chat: G] and adjust ^ to (Θ - when the reference is changed, the financial will not be affected. Therefore, it can be continuously 曰 & in the same period of the wheat deficit clock cycle. ^ ^ Test the clock and adjust the 合 = = = 广 and 参 (9) road will maintain the locked state. In the whole = 201014187 C[M:0] will remain unchanged to ensure that the method of rapid self-correction can be successfully operated Therefore, the final output phase difference for each delay phase will be one-fifth of the reference clock period. Since the above correction circuit is implemented in the digital domain (digital d〇main), its target will be based on the unit step. Zl T is processed. However, the quantization error qe is unavoidable. The third figure is the comparison between the correction period and the random delay error between the traditional correction algorithm and the fast self-correction algorithm of the present invention. Figure. The environment is set to K=5' and the unit step and The error is 5 ps (picoseconds). As shown in the figure, the fast self-correction algorithm proposed by the present invention is shortened by 4.17 times compared with the conventional correction algorithm. In order to maximize the effective sampling rate The delay-locked loop will, in the best case, lock its delay to equal one clock cycle. To avoid false locks, the polyphase is only extended and the loop should be maintained in the following delay range. : Lock ❹ 0.5 X TREF < TDCDL < 1.5 x TREF (2) where TREF represents the reference clock period, and tdcDL, the delay time of the bit control delay line. In addition, it should comply with (3) _, the number of tables, where TINITIAL is the initial delay of the delay-locked circuit = the locking range of the binary search mechanism is limited by (3). ^
Max(TDCDL_MIN，2/3 X TINITIAL) < TREF <MIN(TDCDL_MAX, 2 χ TINITIAL)Max(TDCDL_MIN,2/3 X TINITIAL) < TREF <MIN(TDCDL_MAX, 2 χ TINITIAL)
本發明所提供之非平衡式二元搜尋演算法將選揮〜^ 適之TINITIAL而非選擇數位式控制延遲線路之中間點S 201014187 第四圖係本發明之3位元非平衡式二元搜尋法之流程圖。 根據此流程圖將可找出一適當的TmmAL數值。 在-較佳實施例中，—多相位延遲鎖定迴路包含一組 多相位輸出之延遲線，一相位偵測器，一組階段控制器 (step controller)及一組一元控制器（binary ^时〇11打）。在此 實施例中，多相位輸出延遲線係由多個延遲階段所串連而 成。上述每一個延遲階段均係由兩個延遲細胞（deiay 所組成，其中一延遲細胞係由二元控制器所控制，而另一 延遲細胞則係*可上下數計數器（up/d。⑶仙㈣控制。 在一較佳實施例中，鎖定單元包含一階段控制器5〇〇 及一二元控制器000,分別顯示於第五圖及第六圖中。階 段控制器將顯示出目前進入鎖定單元之階段，而二元控制 器將執行傳統二元搜尋之運作，其中各個控制位元係由單 位元產生器（single-bit generator)所提供。 如第五圖所示’其係一用來產生控制二元控制器之控 制afl號的階段控制器500 ’其包含一組平移暫存器（shift register) ’用以產生二元控制器之控制訊號；一 D型觸發 器（flip flop) ’用以判斷參考時脈與輸出訊號之間的關係， 其輸入為參考時脈，而其觸發訊號係延遲線最後一級之輸 出訊號；及二組多工器，其選擇訊號係根據D型觸發器之 結果產生平移暫存器之控制訊號。 參照第六圖’其係由數個單位元產生器串連而成之二 元控制器600，其包含一 D型觸發器，兩組多工器，一組 邏輯或閘（OR gate)及一組邏輯及閘（And gate)。此二元控 201014187 制器將根據階段控制器及相位偵測器之控制訊號而產生多 相位輸出延遲線之控制訊號。 在一較佳實施例中，其係於初始之際將p5重設為最 紐之延遲時間。D型觸發器將可判斷TDCDL MIN是否大 於TREF之兩倍以決定所欲之階段以及該輸入哪一階段來 決定TINITIAL。而後續階段之操作則係根據二元搜尋演算 法執行。透過鎖定單元可避免錯誤鎖定之發生並將鎖定範 ❹圍延長至（4)。 TDCDL一MIN < TREF < TDCDL MAX (4) 另一方面，由於TDCDL·將符合（2)，因此可將除頻器 比率（divider ratio)設為2以達到最快的鎖定時間。根據非 平衡式一元搜尋演算法完成一延遲鎖定電路之鎖定所需的 整體週期將不會多於14個（7x2)參考時脈週期。 ^在一較佳實施例中，當訊號LOCKED被***後將啟動 权正單元，其將補償因製程變動所引起之相位差（不匹 ©配）。第七圖係本發明之較佳實施例的校正單元7〇〇之示意 圖如圖所示，校正單元包含一相位偵測器7⑽用 以判斷最後一級輸出訊號與參考時脈之間的相位差；四個 數位相對式相位偵測器（7〇4、7〇6、7〇8、71〇)，用以判斷 輸出訊號與前一級輸出訊號之相位差和輸出訊號與後一級 輪出訊號之相位差，兩者相位差之間的關係（大小）；及五 個可上下數計時器（712、714、716、718、72〇)，分別用以 控制多相位輸出延遲線各輪出訊號之延遲時間，以在第i 個延遲階段控制每個單一控制字組Bi[2:0]。 Π 201014187 ❹The unbalanced binary search algorithm provided by the present invention selects the appropriate TINITIAL instead of selecting the intermediate point of the digital control delay line. S 201014187 The fourth picture is the 3-bit unbalanced binary search of the present invention. Flow chart of the law. According to this flow chart, an appropriate TmmAL value can be found. In a preferred embodiment, the multi-phase delay locked loop includes a set of multi-phase output delay lines, a phase detector, a set of stage controllers and a set of unary controllers (binary ^ time 〇 11 dozen). In this embodiment, the multi-phase output delay line is connected in series by a plurality of delay stages. Each of the above delay stages consists of two delayed cells (deiay, one of which is controlled by a binary controller, and the other delayed cell is *upper and lower counters (up/d. (3) cents (four) In a preferred embodiment, the locking unit comprises a phase controller 5A and a binary controller 000, respectively shown in the fifth and sixth figures. The phase controller will display the current entry locking unit. At the stage, the binary controller will perform the operation of the traditional binary search, where each control bit is provided by a single-bit generator. As shown in the fifth figure, A stage controller 500 that controls the binary controller's control afl number, which includes a set of shift register 's used to generate a binary controller control signal; a D-type flip flop' To determine the relationship between the reference clock and the output signal, the input is the reference clock, and the trigger signal is the output signal of the last stage of the delay line; and the two sets of multiplexers are selected according to the D-type flip-flop. The control signal of the translation register is generated. Referring to the sixth figure, the binary controller 600 is a series of a plurality of unit generators, which includes a D-type flip-flop, two sets of multiplexers, and one A group logic OR gate and a set of logic gates (And gates). The binary controller 201014187 will generate control signals for the multi-phase output delay lines based on the control signals of the phase controller and the phase detector. In a preferred embodiment, it is the initial time to reset p5 to the maximum delay time. The D-type flip-flop will determine if TDCDL MIN is greater than twice the TREF to determine the desired phase and which input. The TINITIAL is determined in one stage, and the subsequent operations are performed according to the binary search algorithm. Through the locking unit, the occurrence of erroneous locking can be avoided and the locking range can be extended to (4). TDCDL-MIN < TREF < TDCDL MAX (4) On the other hand, since TDCDL· will conform to (2), the divider ratio can be set to 2 to achieve the fastest lock time. Complete one according to the unbalanced unary search algorithm. Delay locked circuit The overall period required will not exceed 14 (7x2) reference clock cycles. ^ In a preferred embodiment, when the signal LOCKED is inserted, the right unit will be activated, which will compensate for the process variation. The seventh embodiment is a schematic diagram of the correction unit 7 of the preferred embodiment of the present invention. The correction unit includes a phase detector 7 (10) for determining the final output signal. The phase difference between the reference clock and the reference clock; four digital relative phase detectors (7〇4, 7〇6, 7〇8, 71〇) are used to determine the phase difference between the output signal and the output signal of the previous stage. The phase difference between the output signal and the subsequent stage of the signal, the relationship between the two phase differences (size); and five countable up and down timers (712, 714, 716, 718, 72〇), respectively The phase output delay line delays the time of each round of signals to control each single control block Bi[2:0] during the ith delay phase. Π 201014187 ❹
校正單元7 0 0内數位相對式相位偵測器的輸入為多相 立勒出延遲線之第職^㈣級、第瓜祕⑴級第则师+1) 出訊號’而可上下數計數器之上數訊號係由數位相對 式相位债測器之輸出訊號產生，其觸發訊號為第则柳, 3出訊號(i為整數）。舉例來說，數位相對式相位積測器 (第二級)的輸入為多相位輸出延遲線之第一級(ρι)、第 二級㈣、第三級（P3)輸出訊號，而可上下數計數器714 ^上數訊號係由數位相對式相位偵· 之輸出訊號產 生，其觸發訊號為第五級（P5)輸出訊號。 線之 720 觸發 另外，相位债測器702之輸入為多相位輸出延遲 第五級（P5)輸出訊號與參考時脈，而可上下數計數器 之上數訊號係由相位偵測器7〇2之輸出訊號產生，其 訊號為第三級（P3)輸出訊號。 、 。校正單it 700將持續校正相位之不匹配直到相對相位 誤差小於數位相對式相位偵測器之量化誤差為止。當上述 ㈣發生時，訊號L〇CKi將被拉起，且將決定第i個控制 予組Bi[2:0]之數值。 、在-較佳實施例中，上述自我校正可在同—參考時脈 週期内連續校正所有的（五個）控财組叩q]。於第一參 考訊號之下-個正緣(pGsitiveedge)之前，校正後之運作應 為穩定的。上述需求係透過將遠遠相隔的多相位輸出作為 觸發時脈〇dgger c】ock)達《，而不需額外的時序控制電 路。當所有的訊號LOCKi皆為低訊號（1。w咖丨）時，即代 表每個延遲階段内之相對相位㈣係小於量化誤差。其將 12 201014187 ***訊號FINISH以停止上下計數器的使用，而控制字組 Bi[2:0]將為固定的。當某個階段之相對相位誤差大於數位 相對式相位偵測器之量化誤差時，校正單元將重新啟動。 上述相位維持之運作係即時且持續的。 在一較佳實施例中，其模擬環境係採用台灣積體電路 公司（TSMC)之1.2V 130nm CMOS技術模型所建立。其操 作頻率範圍為333MHZ—1GHZ。高於500MHz及低於 500MHz之鎖定程序分別需要12及14個參考時脈週期。 本發明所提出之延遲鎖定訊號將提供8位元的解析度，而 其最低有效位元（lowest significant bit，LSB)之解析度為8 ps。其整體功率消耗在333MHz時為2.7mW，而在lGHz 時則為5.2mW。其製程不匹配（process mismatch)的問題可 由延遲元件内之電容應付。第八圖顯示出當操作頻率為 500MHz時，各個延遲階段之相位誤差。如圖所示，採用 本發明之快速自我校正演算法後可有效縮減各個延遲階段 ❹之相位誤差。舉例來說，原本在P2-P3之延遲階段所發生 之最大相位誤差為27ps (24.3。），而在採用快速自我校正演 算法後，可將上述最大相位誤差縮減至9ps (8.1。）。 綜上所述’本發明之快速自我校正演算法可於同一參 考週期内同時調整所有輪出訊號之相位，以使任意前後兩 級輸出訊號之間的相位差均相同，進而達到快速自我校正 之功用。而本發明之非平衡式二元搜尋演算法係藉由選擇 適當的數位式控制延遲線之初始延遲時間，以避免錯誤鎖 定’進而增加可鎖定之範圍。 13 201014187 上述敘述係本發明之較佳實施例。此領域之技藝者應 得以領會其係用以說明本發明而非用以限定本發明所主張 之專利權利範圍。其專利保護範圍當視後附之中請專利範 圍及其等同領域而定。凡熟悉此領域之技藝者，在不脫離 本專利精神或範圍内，所作之更動或潤飾，均屬於本發明 所揭示精神下所完成之等效改變或設計，且應包含在下述 之申凊專利範圍内。The input of the digital relative phase detector in the correction unit is the first (^) level of the multi-phase pull-out delay line, the first division of the first-class division (1), the quotation number 'the upper and lower number counters The upper signal is generated by the output signal of the digital relative phase debt detector, and the trigger signal is the first signal and the third signal (i is an integer). For example, the input of the digital relative phase product detector (second stage) is the first stage (ρι), the second level (four), and the third stage (P3) output signal of the multi-phase output delay line, and can be up and down The counter 714^upper signal is generated by the output signal of the digital relative phase detection, and the trigger signal is the fifth level (P5) output signal. In addition, the input of the phase debt detector 702 is a multi-phase output delay of the fifth stage (P5) output signal and the reference clock, and the upper and lower number counters are connected by the phase detector 7〇2. The output signal is generated, and the signal is the third level (P3) output signal. , . The calibration unit it 700 will continuously correct the phase mismatch until the relative phase error is less than the quantization error of the digital relative phase detector. When the above (4) occurs, the signal L〇CKi will be pulled up and the value of the i-th control to the group Bi[2:0] will be determined. In the preferred embodiment, the self-correction described above can continuously correct all (five) money control groups 叩q] during the same-reference clock cycle. Prior to the first reference signal - a positive edge (pGsitiveedge), the corrected operation should be stable. The above requirements are achieved by using a far-separated multi-phase output as the trigger clock, without additional timing control circuitry. When all the signals LOCKi are low signals (1. w), the relative phase (4) in each delay phase is less than the quantization error. It inserts 12 201014187 into the signal FINISH to stop the use of the up and down counters, while the control block Bi[2:0] will be fixed. When the relative phase error of a certain phase is greater than the quantization error of the digital relative phase detector, the correction unit will restart. The operation of the above phase maintenance is immediate and continuous. In a preferred embodiment, the simulation environment is established using a 1.2V 130nm CMOS technology model from Taiwan Semiconductor Manufacturing Corporation (TSMC). Its operating frequency range is 333MHZ-1GHZ. Locking procedures above 500 MHz and below 500 MHz require 12 and 14 reference clock cycles, respectively. The delay locked signal proposed by the present invention will provide an 8-bit resolution with a resolution of 8 ps for the lowest significant bit (LSB). Its overall power consumption is 2.7mW at 333MHz and 5.2mW at 1GHz. The problem of process mismatch can be handled by the capacitance in the delay element. The eighth graph shows the phase error for each delay phase when the operating frequency is 500 MHz. As shown in the figure, the phase error of each delay phase can be effectively reduced by using the fast self-correction algorithm of the present invention. For example, the maximum phase error that would otherwise occur during the delay phase of P2-P3 is 27 ps (24.3.), and the maximum phase error can be reduced to 9 ps (8.1) after the fast self-correction algorithm. In summary, the fast self-correction algorithm of the present invention can adjust the phase of all the round-trip signals simultaneously in the same reference period, so that the phase difference between any two levels of output signals is the same, thereby achieving fast self-correction. function. The unbalanced binary search algorithm of the present invention controls the initial delay time of the delay line by selecting an appropriate digital type to avoid erroneous lockout, thereby increasing the lockable range. 13 201014187 The above description is a preferred embodiment of the present invention. Those skilled in the art should be able to understand the invention and not to limit the scope of the patent claims claimed herein. The scope of patent protection depends on the patent scope and its equivalent fields. Any modification or refinement made by those skilled in the art without departing from the spirit or scope of this patent belongs to the equivalent changes or designs made under the spirit of the present invention and should be included in the following claims. Within the scope.
【圖式簡單說明】 本發明可藉由說明書中若干較佳實施例及詳細敛述以 及後附圖式得以瞭解。然而，此領域之技藝者應得以領會 斤有本發明之較佳實施例係用以說明而非用以限制 之申請專利範圍，其中： a 第-圖係本發明之全數位自我校正多相位延遲鎖定迴 路之較佳實施例的示意圖； 第二圖顯示出本發明之快速自我校正演算法之 實施例（Κ=5時）； 第三圖為傳統校正演算法與本發明之快速自我校正演 异法兩者間校正週期—隨機延遲誤差之結果的比較圖、 圖；第四圖係本發明之3位元非平衡式二元搜尋之流程BRIEF DESCRIPTION OF THE DRAWINGS The invention can be understood by the following description of the preferred embodiments and the detailed description and the drawings. However, those skilled in the art should be able to appreciate that the preferred embodiment of the present invention is intended to be illustrative and not to limit the scope of the invention, wherein: a A schematic diagram of a preferred embodiment of the lock loop; the second diagram shows an embodiment of the fast self-correction algorithm of the present invention (Κ=5 o'clock); the third diagram shows the fast correction self-correction of the conventional correction algorithm and the present invention Comparison period between the two methods of the method - comparison graph of the results of the random delay error; the fourth picture is the flow of the 3-bit unbalanced binary search of the present invention
第五圖係本發明之較佳實施例的階段控制器 之示意Figure 5 is a schematic representation of a stage controller of a preferred embodiment of the present invention
第六圖係本發明之較佳實施例的二元控制器之示意 201014187 第七圖係本發明之較佳實施例的校正立. 墙 干凡'^不忍圖； 第八圖係本發明之較佳實施例（當操作頻率為綱腿Z 時）的各個延遲階段之相位誤差的示意圖。 【主要元件符號說明】 100全數位自我校正多相位延遲鎖定迴路 102數位式控制延遲線 104相位偵測器 106鎖定單元 10 8校正單元 500階段控制器 600二元控制器 7 0 0校正單元 702相位偵測器 704數位相對式相位偵測器 706數位相對式相位偵測器 708數位相對式相位偵測器 710數位相對式相位偵測器 712可上下數計時器 714可上下數計時器 716可上下數計時器 718可上下數計時器 720可上下數計時器 15Figure 6 is a schematic representation of a binary controller of a preferred embodiment of the present invention. 201014187. The seventh diagram is a correction of the preferred embodiment of the present invention. The wall is the same as the figure; the eighth figure is the comparison of the present invention. A schematic diagram of the phase error of each delay phase of a preferred embodiment (when the operating frequency is the leg Z). [Main component symbol description] 100 full digit self-correcting multi-phase delay lock loop 102 digital control delay line 104 phase detector 106 locking unit 10 8 correction unit 500 stage controller 600 binary controller 7 0 0 correction unit 702 phase Detector 704 digital relative phase detector 706 digital relative phase detector 708 digital relative phase detector 710 digital relative phase detector 712 can be up and down timer 714 can be up and down timer 716 can be up and down The number timer 718 can count up and down the timer 720 can count up and down the timer 15