TW557518B - Low profile stack semiconductor package - Google Patents

Low profile stack semiconductor package Download PDF

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Publication number
TW557518B
TW557518B TW091108411A TW91108411A TW557518B TW 557518 B TW557518 B TW 557518B TW 091108411 A TW091108411 A TW 091108411A TW 91108411 A TW91108411 A TW 91108411A TW 557518 B TW557518 B TW 557518B
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Taiwan
Prior art keywords
wafer
semiconductor package
substrate
bonding wire
insulating member
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TW091108411A
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Chinese (zh)
Inventor
Chung-Che Tsai
Wei-Heng Shan
Huan-Ping Su
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United Test Ct Inc
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Priority to TW091108411A priority Critical patent/TW557518B/en
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Publication of TW557518B publication Critical patent/TW557518B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899—Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

A low profile stack semiconductor package is proposed, wherein at least two chips having centrally-situated bond pads are stacked on a substrate that is formed with a through opening. A first chip is mounted on the substrate, with bond pads thereof being exposed to the opening. A second chip mounted on the first chip, is formed with a peripherally-situated cushion member, whereby bonding wires are adapted to extend from bond pads of the second chip in a direction parallel to the chip, and reach the cushion member beyond which the bonding wires turn downwardly to be directed toward the substrate, wherein the bonding wires are free of forming wire loops as extending above the second chip. By the above structure, the bonding wires would be firmly held in position to be free of contact or short circuit with the second chip, and overall package profile can be significantly miniaturized.

Description

557518557518

五、發明說明（1) [發明領域] 本發明係有關一種半導體封裝件，尤# _ 疊式半導體封裝件。 "# >晶片堆 [背景技術說明] 堆疊式（Stack)半導體封裝件係一種先進之 術，其特徵在於堆疊多數晶片於單一封裝件結、裳技 倍增半導體封裝件之操作性能及記憶容量。^ ’以瑚 第5 A及5 B圖係顯示習知晶片堆疊結構。如第$ a设 示，二晶片10、η係堆疊於基板12上，並藉銲線圖所 分別電性連接至該基板1 2。此種結構係受限 4而 之尺寸給小於下層晶片1 〇之尺寸，以使晶片1 〇、J丨之 j 結構不會干擾銲線1 3之形成。針對晶片尺寸之限制，如， 5B圖所示，一種解決方法係於該二晶片1 〇、丨丨間敷設一 1 黏劑（A dhe s i v e ) 1 5，該膠黏劑1 5厚度需足以使上層晶片膠 接置至下層晶片1 〇上時，該上層晶片！ ！不會與銲線i 3接11 觸，如此，上層晶片11之尺寸可等於或甚至大於下 1 0之尺寸。 曰曰片 然而’上述晶片堆疊結構中，於模壓（M〇lding)作業 進行時’因用以包覆晶片之封裝膠體（未圖示）之模流衝’擊 ^Impact)，而使銲線13、14極易產生銲線偏位（Sweep)或 你移（Sag)現象。銲線偏位或漂移會導致相鄰銲線或銲線 與晶片間之電性接觸而發生短路，俾使製成品之電性品質 及良率嚴重受損。 再者’由於銲線1 3、1 4係分別水平延展至基板1 2上之V. Description of the invention (1) [Field of the invention] The present invention relates to a semiconductor package, especially a stacked semiconductor package. "# > Wafer Stack [Background Description] Stacked semiconductor packages are an advanced technique, which is characterized by stacking most wafers in a single package junction, and multiplying the operating performance and memory capacity of the semiconductor package. . ^ ‘Figures 5 A and 5 B show the conventional wafer stack structure. As shown in the $ a setting, the two wafers 10 and η are stacked on the substrate 12, and are electrically connected to the substrate 12 by wire bonding diagrams, respectively. This structure is limited in size and the size is smaller than the size of the lower wafer 10, so that the j structure of the wafer 10, J, and J will not interfere with the formation of the bonding wire 13. For the limitation of the size of the wafer, as shown in FIG. 5B, a solution is to lay an adhesive (A dhe sive) 1 5 between the two wafers 10, 丨, and the thickness of the adhesive 15 needs to be sufficient When the upper wafer is glued to the lower wafer 10, the upper wafer! !! It will not be in contact with the bonding wire i 3, so that the size of the upper layer wafer 11 may be equal to or even larger than the size of the lower 10. However, in the above-mentioned wafer stacking structure, when the molding operation is performed, the bonding wire is impacted by the impact of the mold flow of the encapsulation gel (not shown) used to cover the wafer, and the bonding wire is caused. 13, 14 are prone to Sweep or Sag phenomenon. The misalignment or drift of the bonding wire will cause short circuit between the adjacent bonding wire or the electrical contact between the bonding wire and the chip, which will seriously damage the electrical quality and yield of the finished product. Moreover, since the bonding wires 1 3, 1 and 4 are respectively horizontally extended to the substrate 12

16759.ptd16759.ptd

第6頁 557518 五、發明說明（2) s''〜 下層晶片1 0接置處外之不同區域，故基板丨2之使用面積難 以縮減。同時，銲接至上層晶片1 1之銲線1 4，其線狐 、 (Loop)高度需足以使銲線丨4之水平延展距離得遠於銲線 之水平延展距離，而令該銲線1 4之佈設不會干擾銲接至下 層晶片1 0之銲線1 3 ;如此需慮及銲線丨4線弧之高度，則合 使整體結構厚度或高度難以進一步降低。 曰 為解決銲線偏位或漂移問題，已揭露有多種偏移防止 機構，於此參考第6及7圖而說明之。 第6 A及6 B圖顯示銲線先經包覆處理之習知晶片封褒結 構。如第6A圖所示，用以電性連接晶片21至基板22之銲& 2 0，係於形成封裝膠體2 4之前，以樹脂化合物2 3包覆而定 位於原來銲接位置。因此，於用以形成封裝膠體24之模壓 作業進行4，定位於樹脂化合物2 3中之銲線2 〇不會因模流 衝擊而遭受銲線偏位或漂移。或者，如第6β圖所示，樹脂 化合物23係用以部份地包覆銲線2〇，並定位銲線2〇而使其 不會發生銲線偏位或漂移現象，且不會與相鄰銲線或晶片 2 1產生電性接觸、短路。 第7A及7B圖顯示形成有攔壩結構之習知晶片封裝結 構。如第7A圖所示，一攔壩結構3〇係形成於基板“上f以 使用以電性連接晶片33至基板31之銲線32得為該攔壩結構 30支撐而不會與晶片33接觸，因此可有效避免銲線/晶片 間之短路發生。或者，如第圖所示，攔壩結構3〇可形成 於晶片33上，俾得提供相同功效以使銲線32與晶片33間隔 開’以防止銲線3 2與晶片3 3間產生短路現象。Page 6 557518 V. Description of the invention (2) s '' ~ Different areas outside the lower wafer 10 connection area, so the use area of the substrate 2 is difficult to reduce. At the same time, the welding wire 14 of the upper wafer 11 needs to have a wire fox and (Loop) height sufficient to make the horizontal extension distance of the welding wire 丨 4 farther than the horizontal extension distance of the welding wire, so that the welding wire 1 4 The layout will not interfere with the bonding wire 1 3 soldered to the lower wafer 10; so the height of the bonding wire 丨 4 wire arc needs to be taken into account, which makes it difficult to further reduce the overall structure thickness or height. In order to solve the problem of misalignment or drift of the bonding wire, a variety of offset preventing mechanisms have been disclosed, which will be described with reference to FIGS. 6 and 7. Figures 6A and 6B show a conventional wafer encapsulation structure where the bonding wires are first covered. As shown in FIG. 6A, the soldering & 20 for electrically connecting the chip 21 to the substrate 22 is located at the original soldering position before being formed with the encapsulant 2 4 and covered with a resin compound 2 3. Therefore, in the molding operation 4 for forming the encapsulating gel 24, the bonding wire 2 positioned in the resin compound 2 3 will not be subject to offset or drift of the bonding wire due to the impact of the mold flow. Alternatively, as shown in FIG. 6β, the resin compound 23 is used to partially cover the welding wire 20 and position the welding wire 20 so that the welding wire does not deviate or drift, and does not interact with the phase. Adjacent bonding wires or wafer 21 are electrically contacted and short-circuited. Figures 7A and 7B show a conventional chip package structure formed with a dam structure. As shown in FIG. 7A, a dam structure 30 is formed on the substrate "f to use a bonding wire 32 that electrically connects the wafer 33 to the substrate 31 to support the dam structure 30 without contacting the wafer 33. Therefore, a short circuit between the bonding wire / wafer can be effectively avoided. Alternatively, as shown in the figure, the dam structure 30 can be formed on the wafer 33, so that the same effect can be provided to separate the bonding wire 32 from the wafer 33 ' In order to prevent a short circuit between the bonding wire 32 and the wafer 33.

16759.ptd 第7頁 557518 五、發明說明（3) ~ 然而，上述偏移防止機構僅能解決習知晶片堆疊結構 之銲線偏位或短路問題，而無法達到任何結構尺寸縮小之 功效。同時，上述習知晶片堆疊結構係主要用以承載銲塾、 佈設於周圍區域之晶片，而不適用於銲墊佈設於中心區域 之晶片，例如動態隨機存取記憶體（DRAM，Dynamic Random Access Memory) 〇 因此，如何發展出一種半導體封裝件，得適用堆疊具 有佈設於中心區域銲墊之晶片，有效縮小整體結構尺寸， 並得確保其電性品質，實為當務之急。 [發明概述] 本發明之一目的在於提供一種小尺寸堆疊式半導體封 裝件，適用於堆疊於中心區域佈設有銲墊之晶片，如動態 隨機存取記憶體（DRAM，Dynamic Random Access Memory ) ° 本發明之另一目的在於提供一種小尺寸堆疊式半導體 封裝件，得有效減少基板使用面積，並降低整體封裝結構 厚度，有利於半導體封裝件之尺寸縮小。 本發明之再一目的在於提供一種小尺寸堆疊式半導體 封裝件，得有效防止銲線與晶片接觸，以降低短路現象之 產生。 本發明之又一目的在於提供一種小尺寸堆疊式半導體 封裝件，得使銲線穩固定位，而不會產生銲線偏位 (Sweep)或漂移（Sag)現象。 本發明之又一目的在於提供一種小尺寸堆疊式半導體16759.ptd Page 7 557518 V. Description of the Invention (3) ~ However, the above-mentioned offset prevention mechanism can only solve the problem of wire misalignment or short circuit of the conventional chip stacking structure, and cannot achieve any effect of reducing the size of the structure. At the same time, the above-mentioned conventional wafer stacking structure is mainly used to carry the solder pads and the wafers arranged in the surrounding area, and is not suitable for the wafers with the pads arranged in the central area, such as dynamic random access memory (DRAM, Dynamic Random Access Memory). ) 〇 Therefore, how to develop a semiconductor package that is suitable for stacking wafers with pads arranged in the center area, effectively reducing the overall structure size, and ensuring its electrical quality is an urgent task. [Summary of the Invention] An object of the present invention is to provide a small-sized stacked semiconductor package suitable for stacking wafers with pads arranged in a central area, such as Dynamic Random Access Memory (DRAM). Another object of the invention is to provide a small-sized stacked semiconductor package, which can effectively reduce the area of the substrate and reduce the thickness of the overall package structure, which is beneficial to the size reduction of the semiconductor package. Yet another object of the present invention is to provide a small-sized stacked semiconductor package, which can effectively prevent the bonding wires from contacting the wafer, thereby reducing the occurrence of short circuits. Another object of the present invention is to provide a small-sized stacked semiconductor package, which can securely fix the bonding wires without causing the phenomenon of bonding wire offset (Sweep) or drift (Sag). Another object of the present invention is to provide a small-sized stacked semiconductor.

16759.ptd 第8頁 557518 五、發明說明（4) ' "— 封裝件，得有效降低相鄰銲線間之間距（Pitch ^Pacing)，俾使半導體封裝件得適用於需佈設高密度、小 間距（Flne Pitch)電性連接結構之高階產品。 為達成上揭及其他目的，本發明揭露一種小尺寸堆疊 式+導體封裝件，係、包括··_基板，具有—貫穿其中之開 口 ，一第一晶片，具有一作用表面及一相對之非作用表 面，該作用表面之中心區域形成有多數銲墊，其中，該作 用f面係接置至該基板上，以令該銲墊外露於該開口中； 第一晶片，具有一作用表面及一相對之非作用表面，該 非作用表面係接置至該第一晶片之非作用表面上，其中， 該第二晶片之作用表面之中心區域佈設有多數銲墊，而其 周圍區域形成有一絕緣性構件，以令該絕緣性構件向外^ 伸而至少觸及該作用表面之邊緣；多數第一銲線，用以電 性連接該第一晶片之銲塾至該基板；多數第二銲線，用以 電性連接該第二晶片之銲塾至該基板，其中，該第二銲線 係自該第二晶片之銲墊以平行晶片之方向而延伸至該絕緣 性構件，並於越過該絕緣性構件後轉向以朝基板之方向而 繼續延伸至该基板’一封裳膠體，用以包覆該第一與第二 晶片、及該第一與第一銲線；以及多數銲球，植接於該基 板上並外露出該封裝膠體，用以電性連接該第一及第二晶 片至外界裝置。 ％ 上述半導體封裝結構，其特徵在於設置有絕緣性構件 並形成有平行延伸之第一銲線，得提供諸多優點。首先， 平行延伸且不具線弧之第二銲線，助於降低整體封裝結構16759.ptd Page 8 557518 V. Explanation of the invention (4) '" — The package can effectively reduce the pitch between adjacent bonding wires (Pitch ^ Pacing), so that the semiconductor package can be suitable for high-density, High-end products with small pitch (Flne Pitch) electrical connection structure. In order to achieve the above disclosure and other objectives, the present invention discloses a small-sized stacked + conductor package, including a substrate including an opening therethrough, a first chip having an active surface and an opposite non- The active surface has a plurality of solder pads formed in a central region of the active surface, wherein the active f-plane is connected to the substrate so that the solder pad is exposed in the opening; the first wafer has an active surface and a In contrast to the non-active surface, the non-active surface is connected to the non-active surface of the first wafer, wherein a plurality of pads are arranged in the center area of the active surface of the second wafer, and an insulating member is formed in the surrounding area. To make the insulating member extend outwardly and at least touch the edge of the active surface; most of the first bonding wires are used to electrically connect the bonding pads of the first chip to the substrate; most of the second bonding wires are used to The soldering pad of the second wafer is electrically connected to the substrate, wherein the second bonding wire extends from the pad of the second wafer to the insulating member in a direction parallel to the wafer and passes over the insulating member. The insulating member is then turned to extend toward the substrate and continues to the substrate. A piece of colloid is used to cover the first and second wafers and the first and first bonding wires; and most solder balls, plants It is connected to the substrate and the packaging gel is exposed to electrically connect the first and second chips to an external device. The above-mentioned semiconductor package structure is characterized by being provided with an insulating member and forming a first bonding wire extending in parallel, which provides many advantages. First, the second bonding wire that extends in parallel and has no arcs helps reduce the overall packaging structure.

16759.ptd 第9頁 557518 五、發明說明（5) 3度再者’夾置於第二銲線與第：晶片接觸之絕緣性 ^件，係用以防止第二銲線與第二晶片接觸之絕緣性構 ，故得有效避免銲線/晶片間產生短路（Sh〇rt)現象/ 趟二於無銲線/晶片間發生短路之情況下，第二銲線得於 乂絕緣性構件後以較陡（Steep)角度朝下轉向，而 比，伸至基板，俾使基板之使用面積及整體封裝結構尺寸 白传有效降低。 才 此外， 材料製成， 嵌入該絕緣 性構件上， 生銲線偏位 導致短路或 得有效改善 集或緊密地 Spacing)， 密度、小間 性或半固態 之第二銲線 銲線穩固定 距離間隔， ，鲜線偏位 品質，因此 此，第二銲 銲線間之間 件得適用於 結構之高階 之絕緣性 會部分地 位於絕緣 而不會產 或漂移會 ，本發明 線得更密 5E (Pitch 需佈設局 產品。 絕緣性構件係較佳以具彈 故各別與絕緣性構件接觸 性構件中。如此得使第二 並使第二銲線彼此以適當 (Sweep)或漂移（Sag)現象 有損第二銲線之電性連接 製成品之品質及良率。I監 佈設，以進一步縮小相鄰 俾使本發明之半導體封裝 距（F i n e P i t c h )電性連接 於本發明之其他實施例中，設置於第二晶片之作用表 面周圍區域之絕緣性構件，係向外延伸出該作用表面之邊 緣，或更進一步向下延伸至第二晶片之側邊，以包覆住該 作用表面之邊角。如此之結構，使用以電性連接第二晶片 至基板之第二銲線，得更有效地避免與第二晶片接觸，而 防止銲線/晶片間產生短路現象。因此，第二銲線得更陡 峭地於越過絕緣性構件後朝下轉向而延伸至基板，俾使基16759.ptd Page 9 557518 V. Description of the invention (5) 3 degrees and then 'clamped between the second bonding wire and the first: wafer contact insulation, is used to prevent the second bonding wire from contacting the second wafer The insulation structure can effectively avoid the short circuit (Short) phenomenon between the bonding wire / wafer. In the case of no short circuit between the bonding wire / wafer, the second bonding wire must be placed after the insulating member. The steeper angle turns downward, and the ratio extends to the substrate, which effectively reduces the use area of the substrate and the overall package structure size. In addition, the material is embedded in the insulating member, and the welding wire is misaligned, resulting in a short circuit or effective improvement or tight spacing). The density, small space, or semi-solid second welding wire has a fixed distance. The quality of the fresh wire is offset. Therefore, the high-order insulation of the second welding wire between the welding wires can be partially located in the insulation without producing or drifting. The wire of the present invention is denser 5E ( Pitch is required to deploy local products. Insulating members are preferred to be in contact with the insulating members, respectively. In this way, the second and the second bonding wires should be Sweep or Sag to each other. Damage to the quality and yield of the electrical connection finished product of the second bonding wire. I monitor the layout to further reduce the adjacentness so that the semiconductor package pitch (Fine Pitch) of the present invention is electrically connected to other implementations of the present invention In the example, the insulating member provided in the area around the active surface of the second wafer extends outwardly from the edge of the active surface, or further down to the side of the second wafer to cover the The corners of the active surface. With this structure, the second bonding wire electrically connecting the second chip to the substrate is used to more effectively avoid contact with the second chip and prevent the short circuit between the bonding wire and the chip. Therefore, The second bonding wire should be turned steeper after it passes over the insulating member, and then extends to the substrate, causing the base

16759.ptd 第10頁 557518 五、發明說明（6) 板之使用面積大幅降低 效016759.ptd Page 10 557518 V. Description of the invention (6) The area of the board is greatly reduced.

以達縮小整體封裝 件尺寸之功 [發明之詳細說明] 以下即配合所附之第1至4圖詳细雄aH 士々 小尺寸堆疊式半導體封裝件，惟該等各所揭露之 示’僅以示意方式顯示與本發明有關之社構單間化= :二：疋並非以實際數量或尺寸比例繪製，實際之半導體 于裝件之結構佈局應更加複雜。 々如圖所示，本發明之半導體封裝件係包括一基板4 〇 ; 々第一晶片41接置至該基板40上；一第二晶片42接置至該 第一晶片4 1上；多數銲線44、45用以分別電性連接該第 一、第二晶片41、42至該基板40; —封裝膠體46用以包覆 該第一與第二晶片41、42以及該銲線44、45 ;以及多數鋒 球4 7用以電性連接該半導體封裝件至外界裝置。 一基板40具有一上表面400及一相對之下表面401，其 中’該上表面40 0界定有一晶片接置區40 2及一環繞晶片接 置區4 0 2之上銲線區4 0 3。於約該晶片接置區4 0 2之中心位 置處形成有一開口 404，並使該開口 404貫穿基板40之上、 下表面400、401。同時，該基板40之下表面401界定有一 環繞開口 4 0 4之下銲線區4 0 5及一環繞下銲線區4 0 5之植球 區 40 6。 一第一晶片4 1具有一作用表面4 1 0及一相對之非作用 表面412，該作用表面410之中心區域形成有多數銲墊In order to reduce the size of the overall package [detailed description of the invention] The following is a detailed description of the aH Shih small-sized stacked semiconductor packages in conjunction with the attached Figures 1 to 4, but the disclosures of these The schematic representation shows that the social organization related to the present invention is inter-unitized =: 2: 疋 is not drawn based on the actual number or size ratio, and the actual layout of the semiconductor on the package should be more complicated. 々 As shown in the figure, the semiconductor package of the present invention includes a substrate 4; 々 a first wafer 41 is connected to the substrate 40; a second wafer 42 is connected to the first wafer 41; most solder The wires 44 and 45 are used to electrically connect the first and second wafers 41 and 42 to the substrate 40, respectively.-The encapsulant 46 is used to cover the first and second wafers 41 and 42 and the bonding wires 44 and 45. And most of the front balls 47 are used to electrically connect the semiconductor package to an external device. A substrate 40 has an upper surface 400 and a relatively lower surface 401, wherein 'the upper surface 40 0 defines a wafer bonding area 40 2 and a bonding wire area 403 surrounding the wafer bonding area 40 2. An opening 404 is formed at a position about the center of the wafer receiving area 402, and the opening 404 penetrates the upper and lower surfaces 400, 401 of the substrate 40. At the same time, the lower surface 401 of the substrate 40 defines a bonding wire region 405 surrounding the opening 404 and a ball planting region 40 6 surrounding the bonding wire region 405. A first wafer 41 has an active surface 4 1 0 and an opposite non-active surface 412. A plurality of pads are formed in a central area of the active surface 410.

16759.ptd 第11頁 557518 五、發明說明（7) 4 1 1。該第一晶片4 1係接置至該基板4 0之上表面4 0 0上，以 使其作用表面41 0黏接於該上表面40 0之晶片接置區402， 而令其銲塾411外露於該基板40之開口 404中，其中，該開 口 4 0 4之尺寸係足以完全使該第一晶片4 1之銲墊4 11外露於 其中。此種於中心區域佈設有銲墊411之第一晶片41，可 為動態隨機存取記憶體（DRAM，Dynamic Random Access Memory ) 〇 一第二晶片42具有一作用表面420及一相對之非作用 表面422，該作用表面420之中心區域佈設有多數銲塾 4 2 1。該第二晶片4 2係接置至該第一晶片4 1上，以使其非 作用表面422黏接於第一晶片41之非作用表面412。該第二 晶片4 2之作用表面4 2 0之周圍區域形成有一絕緣性構件 4 3，以令該絕緣性構件4 3向外延伸至該作用表面4 2 〇之邊 緣423處。該絕緣性構件43係以絕緣性材料構成，較佳者 為具有彈性如彈性體（E 1 as t ome r )或半固態之絕緣性材 料。 ' 多數第一銲線44，係自第一晶片4丨之銲墊4丨丨上延伸 通過開口 404而至基板40下表面401之下銲線區4〇5，以 第一晶片41藉第一銲線44而電性連接至基板4〇。由於 1°4Λ設Λ，第一鲜線44得經由開口 404以最短線弧（l^p) 長度而使苐一晶片41與基板40電性偶接，俾得有效確 一晶片4 1與基板40間之電性連接品質，此為窗型 ’、 (Window-Type)半導體封裝件之一大優點，而窗型 封裝件之特徵即在於採用具有貫穿式開口之基板。16759.ptd Page 11 557518 V. Description of Invention (7) 4 1 1. The first wafer 41 is connected to the upper surface 400 of the substrate 40 so that the active surface 41 0 of the first wafer 41 is adhered to the wafer receiving area 402 of the upper surface 400 and the solder pad 411 is made. Exposed in the opening 404 of the substrate 40, wherein the size of the opening 4 0 4 is sufficient to completely expose the pad 4 11 of the first wafer 41. Such a first chip 41 provided with a solder pad 411 in the center region may be a Dynamic Random Access Memory (DRAM). A second chip 42 has an active surface 420 and an opposite non-active surface. 422, the center area of the active surface 420 is provided with a plurality of welding pads 4 2 1. The second wafer 42 is connected to the first wafer 41 so that its non-active surface 422 is adhered to the non-active surface 412 of the first wafer 41. An insulating member 43 is formed around the active surface 4 2 0 of the second wafer 4 2 so that the insulating member 4 3 extends outward to the edge 423 of the active surface 4 2 0. The insulating member 43 is made of an insulating material, and is preferably an insulating material having elasticity such as an elastomer (E 1 as t ome r) or a semi-solid state. '' Most of the first bonding wires 44 extend from the bonding pads 4 丨 丨 of the first wafer 4 through the opening 404 to the bonding wire area 405 below the lower surface 401 of the substrate 40, and the first chip 41 borrows the first The bonding wires 44 are electrically connected to the substrate 40. Since 1 ° 4Λ is set to Λ, the first fresh line 44 must be electrically coupled with the first wafer 41 and the substrate 40 by the shortest line arc (l ^ p) length through the opening 404, so that a wafer 41 and the substrate can be effectively identified. The electrical connection quality of 40 rooms is one of the great advantages of window-type semiconductor package, and the characteristic of window-type package is the use of a substrate with a through opening.

16759.ptd 第12頁 557518 五、發明說明（8) 多數第二銲線45用以電性連接第二晶片42至基板40之 上表面40 0。該第二銲線45係自第二晶片42之銲墊421以平 行第二晶片42作用表面420之方向而延伸至位於該作用表 面420周圍區域之絕緣性構件43，以使該第二銲線45於第 二晶片4 2上平行延伸時不會形成有線弧。該第二銲線4 5係 至少接觸於絕緣性構件4 3對應第二晶片4 2之作用表面4 2 0 邊緣423之位置處，以令該絕緣性構件43係夾置於第二銲 線4 5與第二晶片4 2之間，而使第二銲線4 5不會與第二晶片 4 2之銲墊4 2 1以外部位接觸。接著，該第二銲線4 5並於越 過絕緣性構件4 3後轉向以朝基板4 〇之方向繼續延伸，直至 銲接於基板40上表面400之上銲線區403。如此，第二晶片 42得藉第二銲線45而電性連接至該基板4〇上。 一封裝膠體46，係進行一模壓（Molding)作業而以樹 脂化合物如環氧樹脂製成。該封裝膠體4 6用以氣密地包覆 第一與第二晶片41、42以及第一與第二銲線44、45，以使 半導體封裝件之内部元件與外界污染物或衝擊隔絕而 其害。 最後’多數銲球4 7係植接於基板4 〇下表面4 0 1之植球 區406。該銲球47作為半導體封裝件之輸出/輸入端 ^Input/Output Port，I/O port)，用以電性連接第一與 第二晶片41、42至外界裝置如印刷電路板（printed Circuit Board ， PCB) 〇 上述半導體封裝結構得提供諸多優點。平行延伸且16759.ptd Page 12 557518 V. Description of the invention (8) Most of the second bonding wires 45 are used to electrically connect the second chip 42 to the upper surface 40 of the substrate 40. The second bonding wire 45 extends from the pad 421 of the second wafer 42 in a direction parallel to the active surface 420 of the second wafer 42 to the insulating member 43 located in a region around the active surface 420 so that the second bonding wire 45 does not form a wired arc when extending in parallel on the second wafer 42. The second bonding wire 4 5 is at least in contact with the insulating member 4 3 at a position corresponding to the active surface 4 2 0 edge 423 of the second wafer 4 2, so that the insulating member 43 is clamped to the second bonding wire 4. 5 and the second wafer 42, so that the second bonding wire 45 does not contact the parts other than the pads 4 2 1 of the second wafer 42. Then, the second bonding wire 45 passes through the insulating member 43 and turns to extend toward the substrate 40 until it is soldered to the bonding wire region 403 on the upper surface 400 of the substrate 40. In this way, the second chip 42 must be electrically connected to the substrate 40 by the second bonding wire 45. An encapsulant 46 is made of a resin compound such as epoxy resin by a molding operation. The packaging gel 46 is used for hermetically covering the first and second wafers 41 and 42 and the first and second bonding wires 44 and 45 to isolate the internal components of the semiconductor package from external pollutants or impacts. harm. Finally, most of the solder balls 47 are planted in the ball planting area 406 on the bottom surface 401 of the substrate 40. The solder ball 47 serves as an output / input port (input / output port, I / O port) of the semiconductor package, and is used to electrically connect the first and second chips 41 and 42 to an external device such as a printed circuit board. PCB) The above-mentioned semiconductor package structure must provide many advantages. Extends in parallel and

557518 五、發明說明（9) 焊線45之厚度總和相當接近第一與第二晶片41、42之厚度 總和’故有助於降低整體半導體封裝結構之厚度。再者， 用以防止第二銲線4 5與第二晶片4 2接觸之絕緣性構件4 3， 得有效避免第二銲線45與第二晶片42間產生短路（Short) 現象。同時，於無銲線/晶片間發生短路之情況下，第二 銲線45得於越過絕緣性構件43後以較陡（Steep)角度朝下 轉向’而陡靖地延伸至基板4〇之上表面4〇〇，因此，得對 應地減少基板40上表面4〇〇上用以載接第二銲線45之上銲 線區40 3之佈設面積，俾使基板4〇之使用面積及整體封裝 結構尺寸皆得有效降低。 此外’如第2圖所示，由於絕緣性構件43係較佳以且 彈性或，固態之絕緣性材料製成，故各別與絕緣性構件'43 接觸之第二銲線4 5會部分地嵌入該絕緣性構件4 3中。如此 知使第二銲線4 5穩固定位於絕緣性構件4 3上，並使第二銲 線45彼此以適當距離間隔，而不會產生銲線偏位 或漂移（Sag)現象；銲線偏位或漂移會導致短路或有 二銲線45之電性連接品質，因此，本發明得有效改善製成 品之品質及良率。鑑此，第二銲線45得更密集或緊密地佈 設，以進一步縮小相鄰銲線間之間距（pitch ““丨 俾使本發明之半導體封裝件得適用於需佈設高密度、小間 距（Fine Pitch)電性連接結構之高階產品。 第^二實施例 第3圖顯示本發明之半導體封裝件之第二實施例。 二實施例所揭露之封裝結構大致與第一實施例相同，其不557518 V. Description of the invention (9) The sum of the thicknesses of the bonding wires 45 is quite close to the sum of the thicknesses of the first and second wafers 41 and 42, so it helps to reduce the thickness of the overall semiconductor package structure. In addition, the insulating member 43 for preventing the second bonding wire 45 from contacting the second wafer 42 can effectively prevent a short circuit between the second bonding wire 45 and the second wafer 42. At the same time, in the case of a short-circuit between the bonding wire / wafer, the second bonding wire 45 may turn over the insulating member 43 and turn downward at a steep angle, and extend steeply above the substrate 40. The surface 400 is reduced accordingly. The layout area of the upper surface 400 of the substrate 40 for carrying the bonding wire area 40 3 above the second bonding wire 45 must be correspondingly reduced, so that the used area of the substrate 40 and the overall packaging can be reduced. The structure size must be effectively reduced. In addition, as shown in FIG. 2, since the insulating member 43 is preferably made of an elastic or solid solid insulating material, the second bonding wires 45 that are in contact with the insulating member 43 are partially formed. The insulating member 43 is embedded. In this way, it is known that the second bonding wire 45 is fixedly located on the insulating member 43 and the second bonding wires 45 are spaced at an appropriate distance from each other without causing the bonding wire misalignment or drift (Sag) phenomenon; Bits or drifts can cause short-circuits or electrical connection quality with two bonding wires 45. Therefore, the present invention can effectively improve the quality and yield of finished products. In view of this, the second bonding wires 45 should be arranged more densely or densely to further reduce the distance between adjacent bonding wires (pitch "" 丨 俾 makes the semiconductor package of the present invention suitable for high-density, small-pitch ( Fine Pitch) High-order product of electrical connection structure. Second Embodiment FIG. 3 shows a second embodiment of the semiconductor package of the present invention. The package structure disclosed in the second embodiment is substantially the same as the first embodiment, and it is not

557518 五、發明說明（ίο) 同之處在於，設置於第二晶片42之作用表面420周圍區域 之絕緣性構件4 3，係向外延伸出該作用表面4 2 0之邊緣 4 2 3，以使該絕緣性構件4 3之一部份4 3 0突出於自該第二晶 片4 2之侧邊4 2 4。如此，用以電性連接第二晶片4 2至基板 4 0之第二銲線4 5，係自該第二晶片4 2之銲墊4 21延伸，並 至少與該絕緣性構件43之突出部份430接觸，而於越過絕 緣性構件4 3後轉向以朝基板4 0之方向而延伸至該基板4 〇之 上表面4 0 0。該突出部份430之形成得進一步防止第二銲線 4 5與第二晶片4 2接觸，而有效避免銲線/晶片間發生短路 現象。同時，第二銲線4 5得更陡靖地朝下轉向而延伸至基 板40，以有效降低基板40之使用面積及整體封裝件尺寸。 第三實施例 第4圖顯示本發明之半導體封裝件之第三實施例。第 二實施例所揭露之封裝結構大致與第二實施例相同，其不 同之處在於，設置於第二晶片42之作用表面420周圍區域 之絕緣性構件4 3，係向外、向下延伸至第二晶片4 2之側邊 424’以包覆住該第二晶片42作用表面420之邊角425，而 令該絕緣性構件4 3形成有一邊角4 3 1對應地突設於該第二 晶片4 2之邊角4 2 5外。如此，用以電性連接第二晶片4 2至 基板40之第二銲線45，係自該第二晶片42之銲墊421延 伸’並至少與該絕緣性構件4 3之邊角4 3 1接觸，而於越過 絕緣性構件4 3後轉向以朝基板4 0之方向而延伸至該基板4 〇 之上表面400。由於第二晶片42之邊角425與側邊424以絕 緣性構件4 3包覆，故得最佳防止第二銲線4 5與第二晶片4 2557518 V. Description of the invention (ίο) The same point is that the insulating member 4 3 provided in the area around the active surface 420 of the second wafer 42 extends outwardly from the edge 4 2 3 of the active surface 4 2 0 to A part 4 3 0 of the insulating member 4 3 protrudes from a side 4 2 4 of the second wafer 4 2. In this way, the second bonding wire 45 for electrically connecting the second wafer 42 to the substrate 40 extends from the bonding pad 4 21 of the second wafer 42 and at least with the protruding portion of the insulating member 43. Part 430 contacts, and after passing over the insulating member 43, it turns to extend toward the substrate 40 to the upper surface 400 of the substrate 40. The protruding portion 430 is formed to further prevent the second bonding wire 45 from coming into contact with the second wafer 42, and effectively prevent a short circuit between the bonding wire / wafer. At the same time, the second bonding wire 45 has to be turned downwards more steeply and extends to the base plate 40 to effectively reduce the use area of the base plate 40 and the overall package size. Third Embodiment FIG. 4 shows a third embodiment of the semiconductor package of the present invention. The package structure disclosed in the second embodiment is substantially the same as the second embodiment, except that the insulating member 43 arranged in the area around the active surface 420 of the second chip 42 extends outward and downward to The side edge 424 'of the second wafer 42 covers the corner 425 of the active surface 420 of the second wafer 42, so that the insulating member 4 3 is formed with a corner 4 3 1 correspondingly protruding from the second wafer 42. The corners 4 2 5 of the wafer 4 2 are outside. In this way, the second bonding wire 45 for electrically connecting the second wafer 42 to the substrate 40 extends from the bonding pad 421 of the second wafer 42 and at least with the corner 4 3 1 of the insulating member 4 3 Contact, and after passing over the insulating member 43, it turns to extend toward the substrate 40 to the upper surface 400 of the substrate 40. Since the corner 425 and the side 424 of the second wafer 42 are covered with the insulating member 4 3, the second bonding wire 45 and the second wafer 42 can be optimally prevented.

16759.ptd 第15頁 557518 五、發明說明（11) 接觸’並得有效避免第二銲線45 現象。因此，第二銲線45 二晶月42間產生短路 你4Π，抱你其為也朝下轉向而延伸至基 板40 ’俾使基板40之使用面積有效降低，以達縮小整體封 裝件尺寸之功效。 惟以上所述者，僅係用以說明本發明之具體實施例而 已’並非用以限定本發明之可實施範圍，舉凡熟習該項技 藝者在未脫離本發明所指示之精神與原理下所完成之一切 等效改變或修飾，仍應皆由後述之專利範圍所涵蓋。16759.ptd Page 15 557518 V. Description of the invention (11) Contact ′ and effectively avoid the phenomenon of the second bonding wire 45. Therefore, a short circuit occurs between the second bonding wire 45 and the second crystal moon 42, and it will be extended to the substrate 40 so as to turn downward. This effectively reduces the use area of the substrate 40 to reduce the size of the overall package. . However, the above are only used to explain specific embodiments of the present invention, and are not used to limit the implementable scope of the present invention. For those skilled in the art, they can complete it without departing from the spirit and principles indicated by the present invention. All equivalent changes or modifications should still be covered by the scope of patents mentioned later.

16759.ptd16759.ptd

第16頁 557518 圖式簡單說明 [圖式簡單說明] 為讓本發明之上述及其他目的、特徵以及優點能更明 顯易懂，將與較佳實施例，並配合所附圖示，詳細說明本 發明之實施例，所附圖示之内容簡述如下： 第1圖係本發明半導體封裝件之第一實施例之剖視 圖， 第2圖係第1圖之半導體封裝件沿2 - 2線切開之剖視 圖， 第3圖係本發明半導體封裝件之第二實施例之剖視 圖， 第4圖係本發明半導體封裝件之第三實施例之剖視 圖； 第5A及5B圖係習知晶片堆疊結構之剖視圖； 第6A及6B圖係顯示銲線先經包覆處理之習知晶片封裝 結構；以及 第7A及7B圖係顯示形成有攔壩結構之習知晶片封裝結 構。 [元件符號說明] 10 晶片 11 晶片 12 基板 13 焊線 14 銲線 15 膠黏劑 20 鲜線 21 晶片 22 基板 23 樹脂化合物 24 封裝膠體557518 Brief description of the drawings [Simplified description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the present invention will be described in detail with the preferred embodiment and the accompanying drawings. The embodiment of the invention is briefly described as follows: FIG. 1 is a cross-sectional view of the first embodiment of the semiconductor package of the present invention, and FIG. 2 is a cut of the semiconductor package of FIG. 1 along the line 2-2 Sectional view, FIG. 3 is a sectional view of a second embodiment of the semiconductor package of the present invention, and FIG. 4 is a sectional view of a third embodiment of the semiconductor package of the present invention; FIGS. 5A and 5B are sectional views of a conventional wafer stacking structure; Figures 6A and 6B show a conventional chip packaging structure where the bonding wires are first covered; and Figures 7A and 7B show a conventional chip packaging structure with a dam structure formed. [Description of component symbols] 10 wafers 11 wafers 12 substrates 13 bonding wires 14 bonding wires 15 adhesives 20 fresh lines 21 wafers 22 substrates 23 resin compounds 24 encapsulants

16759.ptd 第17頁 55751816759.ptd Page 17 557518

圖式簡單說明 30 搁壤結構 31 基板 32 銲線 33 晶片 40 基板 400 上表面 401 下表面 402 晶片接置區 403 上銲線區 404 開口 405 下銲線區 406 植球區 41 第一晶片 410 作用表面 411 銲墊 412 非作用表面 42 第二晶片 420 作用表面 421 銲墊 422 非作用表面 423 邊緣 424 側邊 425 邊角 43 絕緣性構件 430 部份 431 邊角 44 第一銲線 45 第二銲線 46 封裝膠體 47 鲜球 16759.ptd 第18頁Brief description of the drawing 30 Structure of grounding 31 Substrate 32 Welding wire 33 Wafer 40 Substrate 400 Upper surface 401 Lower surface 402 Wafer receiving area 403 Upper welding line area 404 Opening 405 Lower welding line area 406 Bulb area 41 First wafer 410 Function Surface 411 Solder pad 412 Non-active surface 42 Second wafer 420 Active surface 421 Solder pad 422 Non-active surface 423 Edge 424 Side 425 Corner 43 Insulating member 430 Part 431 Corner 44 First bonding wire 45 Second bonding wire 46 Encapsulated Colloid 47 Fresh Ball 16759.ptd Page 18

Claims (1)

557518 六、申請專利範圍 1. 一種小尺寸堆疊式半導體封裝件，係包括： 一基板，具有一上表面及一相對之下表面，並形 成有一貫穿該上、下表面之開口； 一第一晶片，具有一作用表面及一相對之非作用 表面，該作用表面之中心區域形成有多數銲墊，其中 ，該作用表面係接置至該基板之上表面上，以令該銲 墊外露於該開口中； 、 一第二晶片，具有一作用表面及一相對之非作用 表面，該非作用表面係接置至該第一晶片之非作用表 面上，其中，該第二晶片之作用表面之中心區域佈設 有多數銲墊，而其周圍區域形成有一絕緣性構件，以 * 匕 令該絕緣性構件向外延伸而至少觸及該作用表面之邊 緣； 多數第一銲線，用以電性連接該第一晶片之銲墊 至該基板之下表面； 多數第二銲線，用以電性連接該第二晶片之銲墊 至該基板之上表面，其中，該第二銲線係自該第上晶 片之銲墊延伸，以使該第二銲線至少接觸於該絕緣性 構件對應第二晶片之作用表面邊緣之位置處，並令該 第二銲線於越過該絕緣性構件後轉向以朝基板尤方向 而延伸氧該基板之上表面； , 一封裝膠體，用以包覆該第一與第二晶片、及該 第一與第二銲線；以及 多數銲球，植接於該基板之下滅面上，用以電性557518 6. Scope of patent application 1. A small-sized stacked semiconductor package comprising: a substrate having an upper surface and a relatively lower surface, and forming an opening penetrating the upper and lower surfaces; a first wafer Has an active surface and an opposite non-active surface, and a plurality of solder pads are formed in the center region of the active surface, wherein the active surface is connected to the upper surface of the substrate so that the solder pad is exposed from the opening A second wafer having an active surface and an opposite non-active surface, the non-active surface is connected to the non-active surface of the first wafer, wherein a central area of the active surface of the second wafer is arranged There are a plurality of bonding pads, and an insulating member is formed in the surrounding area, and the insulating member is extended outwardly to touch at least the edge of the active surface; most of the first bonding wires are used to electrically connect the first chip. Solder pads to the lower surface of the substrate; most second bonding wires are used to electrically connect the solder pads of the second chip to the upper surface of the substrate, wherein, the The second bonding wire extends from the bonding pad of the first wafer, so that the second bonding wire contacts at least the position of the insulating member corresponding to the edge of the active surface of the second wafer, and the second bonding wire passes over The insulative member is turned to extend the upper surface of the substrate toward the substrate, and in particular, an encapsulant is used to cover the first and second wafers, and the first and second bonding wires; and most bonding Ball, planted on the underside of the substrate for electrical 16759.ptd 第19頁 557518 六、申請專利範圍 連接該第一及第二晶片至外界裝置。 2. 如申請專利範圍第1項之半導體封裝件，其中，該開口 之尺寸係足以完全使該第一晶片之銲墊外露於其中。 3. 如申請專利範圍第1項之半導體封裝件，其中，該第一 及第二晶片係分別為一動態隨機存取記憶體（DRAM， Dynamic Random Access Memory)0 4. 如申請專利範圍第1項之半導體封裝件，其中，該絕緣 性構件係以一絕緣性材料製成。 5. 如申請專利範圍第4項之半導體封裝件，其中，該絕緣 k材料具有彈性。 6. 如申請專利範圍第5項之半導體封裝件，其中，各該與 絕緣性構件接觸之第二銲線係部分嵌入該絕緣性構件 中 〇 7. 如申請專利範圍第4項之半導體封裝件，其中，該絕緣 性材料係於第二銲線形成時呈半固態狀。 8. 如申請專利範圍第7項之半導體封裝件，其中，各該與 絕緣性構件接觸之第二銲線係部分嵌入該絕緣性構件 中 〇 9. 如申請專利範圍第1項之半導體封裝件，其中，該第二 銲線係自該第二晶片之銲墊以平行晶片之方向而延伸 ，以使該第二銲線於第二晶片上延伸時不會形成有線 弧。 1 0 .·如申請專利範圍第1項之半導體封裝件，其中，該絕緣 性構件係夾置於該第二銲線與該第二晶片之間，以使16759.ptd Page 19 557518 6. Scope of patent application Connect the first and second chips to external devices. 2. For example, the semiconductor package of claim 1, wherein the size of the opening is sufficient to completely expose the pads of the first wafer. 3. For the semiconductor package of the first scope of the patent application, wherein the first and second chips are respectively a dynamic random access memory (DRAM, Dynamic Random Access Memory) 0 4. If the scope of the patent application is first The semiconductor package of claim 1, wherein the insulating member is made of an insulating material. 5. The semiconductor package according to item 4 of the patent application, wherein the insulating k material has elasticity. 6. The semiconductor package as claimed in item 5 of the patent application, wherein each of the second bonding wires in contact with the insulating member is partially embedded in the insulating member. 7. The semiconductor package as described in item 4 of the patent application Wherein, the insulating material is semi-solid when the second bonding wire is formed. 8. The semiconductor package as claimed in item 7 of the patent application, wherein each of the second bonding wires in contact with the insulating member is partially embedded in the insulating member. 9. The semiconductor package as described in item 1 of the patent application Wherein, the second bonding wire extends from the bonding pad of the second wafer in a direction parallel to the wafer, so that a wired arc is not formed when the second bonding wire is extended on the second wafer. 10.. According to the semiconductor package of claim 1, the insulating member is sandwiched between the second bonding wire and the second wafer so that 16759.ptd 第20頁 557518 六、申請專利範圍 該第二銲線不會與第二晶片之銲墊以外部位接觸。 1 1. 一種小尺寸堆疊式半導體封I件，係包括： 一基板，具有一上表面及一相對之下表面’並形 成有一貫穿該上、下表面之開口； 一第一晶片，具有一作用表面及一相對之非作用 表面，該作用表面之中心區域形成有多數銲墊，其中 ，該作用表面係接置至該基板之上表面上，以令該銲 墊外露於該開口中； 一第二晶片，具有一作用表面及一相對之非作用 表面，該非作用表面係接置至該第一晶片之非作用表 面上，其中，該第二晶片之作用表面之中心區域佈設 有多數銲墊，而其周圍區域形成有一絕緣性構件，以 使該絕緣性構件向外延伸出該作用表面之邊緣，而令 該絕緣性構件之一部份突出於該第二晶片之側邊； 多數第一銲線，用以電性連接該第一晶片之銲墊 至該基板之下表面； 多數第二銲線，用以電性連接該第二晶片之銲墊 至該基板之上表面，其中，該第二銲線係自該第二晶 片之銲墊延伸，以使該第二銲線至少與該絕義性構件 之突出部份接觸，並令該第二銲線於越過該絕緣性構 件後轉向以朝基板之方向而延伸至該基板之上表面； 一封裝膠體，用以包覆該第一與第二晶片、及該 第一與第二銲線；以及 多數銲球，植接於該基板之下表面上，用以電性16759.ptd Page 20 557518 6. Scope of patent application The second bonding wire will not be in contact with the parts other than the pads of the second wafer. 1 1. A small-sized stacked semiconductor package I, comprising: a substrate having an upper surface and a relatively lower surface 'and forming an opening penetrating the upper and lower surfaces; a first wafer having a function A surface and an opposite non-acting surface, a plurality of solder pads are formed in the center region of the active surface, wherein the active surface is connected to the upper surface of the substrate so that the solder pad is exposed in the opening; The two wafers have an active surface and an opposite non-active surface. The non-active surface is connected to the non-active surface of the first wafer, and a plurality of pads are arranged in a central area of the active surface of the second wafer. An insulating member is formed in the surrounding area, so that the insulating member extends outward from the edge of the active surface, so that a part of the insulating member protrudes from the side of the second wafer; Wire for electrically connecting the pad of the first chip to the lower surface of the substrate; most of the second wire for electrically connecting the pad of the second chip to the upper surface of the substrate Wherein, the second bonding wire is extended from the bonding pad of the second wafer, so that the second bonding wire is in contact with at least the protruding portion of the insulative member, and the second bonding wire passes over the insulation. The component is turned to extend to the upper surface of the substrate toward the substrate; a packaging gel is used to cover the first and second wafers and the first and second bonding wires; and most solder balls are implanted On the lower surface of the substrate for electrical 16759.ptd 第21頁 557518 六、申請專利範圍 連接該第一及第二晶片至外界裝置。 1 2 .如申請專利範圍第1 1項之半導體封裝件，其中，該開 口之尺寸係足以完全使該第一晶片之銲墊外露於其中 〇 1 3 .如申請專利範圍第1 1項之半導體封裝件，其中，該第 一及第二晶片係分別為一動態隨機存取記憶體。 1 4 .如申請專利範圍第1 1項之半導體封裝件，其中，該絕 緣性構件係以一絕緣性材料製成。 1 5 .如申請專利範圍第1 4項之半導體封裝件，其中，該絕 緣性材料具有彈性。 1 6 .如申請專利範圍第1 5項之半導體封裝件，其中，各該 與絕緣性構件接觸之第二銲線係部分嵌入該絕緣性構 件中。 1 7 .如申請專利範圍第1 4項之半導體封裝件，其中，該絕 緣性材料係於第二銲線形成時呈半固態狀。 1 8 .如申請專利範圍第1 7項之半導體封裝件，其中，各該 與絕緣性構件接觸之第二銲線係部分嵌入該絕緣性構 件中。 1 9 .如申請專利範圍第1 1項之半導體封裝件，其中，該第 二銲線係自該第二晶片之銲墊以平行晶片之方向而延 伸，以使該第二銲線於第二晶片上延伸時不會形成有 線弧。 2 0 .如申請專利範圍第1 1項之半導體封裝件，其中，該絕 緣性構件係夾置於該第二銲線與該第二晶片之間，以16759.ptd Page 21 557518 6. Scope of patent application Connect the first and second chips to external devices. 1 2. If the semiconductor package of item 11 in the scope of patent application, wherein the size of the opening is sufficient to completely expose the pads of the first wafer therein 0 1 3. Such as the semiconductor of package 11 in the scope of patent application The package, wherein the first and second chips are a dynamic random access memory, respectively. 14. The semiconductor package of claim 11 in the scope of patent application, wherein the insulating member is made of an insulating material. 15. The semiconductor package according to item 14 of the patent application scope, wherein the insulating material has elasticity. 16. The semiconductor package according to item 15 of the scope of patent application, wherein each of the second bonding wire systems in contact with the insulating member is partially embedded in the insulating member. 17. The semiconductor package according to item 14 of the scope of patent application, wherein the insulating material is semi-solid when the second bonding wire is formed. 18. The semiconductor package of claim 17 in the scope of patent application, wherein each of the second bonding wire systems in contact with the insulating member is partially embedded in the insulating member. 19. The semiconductor package according to item 11 of the scope of patent application, wherein the second bonding wire extends from the bonding pad of the second wafer in a direction parallel to the wafer, so that the second bonding wire is on the second No wired arc is formed when extending on the wafer. 20. The semiconductor package according to item 11 of the scope of patent application, wherein the insulating member is sandwiched between the second bonding wire and the second wafer to 16759.ptd 第22頁 557518 六、申請專利範圍 使該第二銲線不會與第二晶片之銲墊以外部位接觸。 2 1 . —種小尺寸堆疊式半導體封裝件，係包括： 一基板，具有一上表面及一相對之下表面，並形 成有一貫穿該上、下表面之開口； 一第一晶片，具有一作用表面及一相對之非作用 表面，該作用表面之中心區域形成有多數銲墊，其中 ，該作用表面係接置至該基板之上表面上，以令該銲 墊外露於該開口中； 一第二晶片，具有一作用表面及一相對之非作用 表面，該非作用表面係接置至該第一晶片之非作用表 面上，其中，該第二晶片之作用表面之中心區域佈設 有多數銲墊，而其周圍區域形成有一絕緣性構件，以 令該絕緣性構件向外、向下延伸至該第二晶片之側邊 ，以包覆住該第二晶片作用表面之邊角，而令該絕緣 性構件形成有一邊角對應地突設於該第二晶片之邊角 外； 多數第一銲線，用以電性連接該第一晶片之銲墊 至該基板之下表面； 多數第二銲線，用以電性連接該第二晶片之銲墊 至該基板之上表面，其中，該第二銲線係自該第二晶 片之銲墊延伸，以使該第二銲線至少與該絕緣性構件 之邊角接觸，並令該第二銲線於越過該絕緣性構件後 轉向以朝基板之方向而延伸至該基板之上表面； 一封裝膠體，用以包覆該第一與第二晶片、及該16759.ptd Page 22 557518 6. Scope of patent application The second bonding wire will not be in contact with parts other than the pads of the second wafer. 2 1. A small-sized stacked semiconductor package, comprising: a substrate having an upper surface and a relatively lower surface, and forming an opening penetrating the upper and lower surfaces; a first chip having a function A surface and an opposite non-acting surface, a plurality of solder pads are formed in the center region of the active surface, wherein the active surface is connected to the upper surface of the substrate so that the solder pad is exposed in the opening; The two wafers have an active surface and an opposite non-active surface. The non-active surface is connected to the non-active surface of the first wafer, and a plurality of pads are arranged in a central area of the active surface of the second wafer. An insulating member is formed in the surrounding area, so that the insulating member extends outward and downward to the side of the second wafer, so as to cover the corners of the active surface of the second wafer to make the insulating The component is formed with a corner protruding correspondingly from the corner of the second wafer; most of the first bonding wires are used to electrically connect the pads of the first wafer to the lower surface of the substrate; most A second bonding wire for electrically connecting the bonding pad of the second wafer to the upper surface of the substrate, wherein the second bonding wire extends from the bonding pad of the second wafer so that the second bonding wire is at least It is in contact with the corners of the insulating member, and the second bonding wire is turned after passing the insulating member so as to extend toward the substrate to the upper surface of the substrate; a sealing gel is used to cover the first And the second chip, and the 16759.ptd 第23頁 557518 六、申請專利範圍 第一與第二銲線；以及 多數銲球，植接於該基板之下表面上，用以電性 連接該第一及第二晶片至外界裝置。 2 2 .如申請專利範圍第2 1項之半導體封裝件，其中，該開 口之尺寸係足以完全使該第一晶片之銲墊外露於其中 〇 2 3 .如申請專利範圍第2 1項之半導體封裝件，其中，該第 一及第二晶片係分別為一動態隨機存取記憶體。 2 4 .如申請專利範圍第2 1項之半導體封裝件，其中，該絕 緣性構件係以一絕緣性材料製成。 2 5 .如申請專利範圍第2 4項之半導體封裝件，其中，該絕 緣性材料具有彈性。 2 6 .如申請專利範圍第2 5項之半導體封裝件，其中，各該 與絕緣性構件接觸之第二銲線係部分嵌入該絕緣性構 件中。 2 7.如申請專利範圍第2 4項之半導體封裝件，其中，該絕 緣性材料係於第二銲線形成時呈半固態狀。 2 8 .如申請專利範圍第2 7項之半導體封裝件，其中，各該 與絕緣性構件接觸之第二銲線係部分嵌入該絕緣性構 件中。 2 9 .如申請專利範圍第2 1項之半導體封裝件，其中，該第 二銲線係自該第二晶片之銲墊以平行晶片之方向而延 伸，以使該第二銲線於第二晶片上延伸時不會形成有 線孤。16759.ptd Page 23 557518 6. The first and second bonding wires in the scope of patent application; and most solder balls are planted on the lower surface of the substrate for electrically connecting the first and second chips to external devices. . 2 2. If the semiconductor package of item 21 of the scope of patent application, wherein the size of the opening is sufficient to completely expose the pad of the first wafer therein 0 2 3. The semiconductor of the scope of the scope of patent application 21 The package, wherein the first and second chips are a dynamic random access memory, respectively. 24. The semiconductor package of claim 21, wherein the insulating member is made of an insulating material. 25. The semiconductor package of claim 24, wherein the insulating material has elasticity. 26. The semiconductor package as claimed in claim 25, wherein each of the second bonding wire systems in contact with the insulating member is partially embedded in the insulating member. 2 7. The semiconductor package of claim 24, wherein the insulating material is semi-solid when the second bonding wire is formed. 28. The semiconductor package according to item 27 of the scope of patent application, wherein each of the second bonding wire systems in contact with the insulating member is partially embedded in the insulating member. 2 9. The semiconductor package according to item 21 of the scope of patent application, wherein the second bonding wire extends from the bonding pad of the second wafer in a direction parallel to the wafer, so that the second bonding wire is on the second Wires are not formed when extended on the wafer. 16759.ptd 第24頁 55751816759.ptd Page 24 557518 16759.ptd 第25頁16759.ptd Page 25
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI604593B (en) * 2013-04-01 2017-11-01 矽品精密工業股份有限公司 Semiconductor package and method of manufacture
US11069646B2 (en) 2019-09-26 2021-07-20 Nanya Technology Corporation Printed circuit board structure having pads and conductive wire

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI604593B (en) * 2013-04-01 2017-11-01 矽品精密工業股份有限公司 Semiconductor package and method of manufacture
US11069646B2 (en) 2019-09-26 2021-07-20 Nanya Technology Corporation Printed circuit board structure having pads and conductive wire
TWI749389B (en) * 2019-09-26 2021-12-11 南亞科技股份有限公司 Printed circuit board structure having landing pad
TWI750104B (en) * 2019-09-26 2021-12-11 南亞科技股份有限公司 Printed circuit board structure

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