TWI360088B - Pixel circuit and display device having the pixel - Google Patents
Pixel circuit and display device having the pixel Download PDFInfo
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1360088 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種電路及顯示器，_是指—種有 機電激發光二極體顯示器，及其内部的像素電路。 【先前技術】 參閲圖1 ’習知的有機電激發光二極體顯示器是藉由螢 幕上複數可顯現不同色彩的像素電路來達到顯示影像的功 能。該等像素電路呈陣列排列，每一像素電路可顯現一色 彩，且包括一有機電激發光二極體（〇rganic Light1360088 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit and a display, and _ refers to an electromechanical excitation photodiode display, and a pixel circuit therewith. [Prior Art] Referring to Fig. 1 'the conventional organic electroluminescent diode display is capable of displaying an image by a plurality of pixel circuits of different colors on the screen. The pixel circuits are arranged in an array, each pixel circuit can display a color, and includes an organic electroluminescent diode (〇rganic Light)
Diode’以下簡稱OLED) 71及一驅動草元72。每一 〇led 71可被通電發光而顯現紅、綠、藍三種顏色的其中一種顏 色。 該驅動單元72接收外界的一掃描信號s、一重設信號 RESET及-資料Vdata，並由該資料ν_的值決定輸出至 該0LED 71的電流量’以驅動該〇LED 71發光而在該像素 電路所在的位置顯現一色彩。 該驅動單元72包括一電晶體T1、一具有一電晶體T2 及一電晶體Τ3的開關720、一電晶體τ4及一電容^。該等 電晶體τι〜Τ4為ρ型金屬氧化物半導體（JMype Metal 〇xide Semiconductor ’ 以下簡稱 PM〇s)。 該電晶體τι的汲極與該0LED 71的陽極電連接，且 源極與外界的一定電壓源VDD之高電位端電連接，該電晶 體T2的汲極接收該資料Vdata，且其閘極接收該掃描信號 S。該電晶體T3的源極與該電晶體T2的源極電連接，且其 1360088 閘極與其汲極、該電容C的一端、該電晶體T4的源極及該 電晶體Τ1的閘極電連接。該電容C的另一端與該定電壓源 VDD之高電位端電連接，該電晶體Τ4的閘極與汲極電連接 並接收該重設信號RESET。 當該掃描信號S使該電晶體T2為導通狀態時，該資料 VDATA將透過該電晶體T3被寫入至該電晶體T1之閘極及電 容C，該驅動單元72會根據該資料V DATA 輸出一電流（圖未 示）到該OLED 71，該電流可以如下之方程式表示： I=KP1x[VDD-(VDATA-Vth3)-Vthl]2 式（1) 其中，I是該電流的電流值’ Vth3、V\hi分別是該電晶體T3 及該電晶體 T1 的臨界電壓（threshold voltage)， KP1=(l/2hCox(W/L)，W及L分別為該電晶體T1的通道 (channel)寬度及長度，μ為電洞（hole)遷移速率（drifting velocity)，C〇x為閘極氧化層（gate oxide)的單位電容值 (capacitance per unit area) ° 由於電路佈局（layout)時會使該電晶體T1及該電晶體 Τ3的位置很接近，而使VthlNVth3，因此由式（1)可知該電 流I=Kp1x[VDD-Vdata]2。因此藉由使該等電晶體T3、T1彼 此互相靠近，該電流I即可完全地由該定電壓源VDD及該 資料Vdata的值所決定。 當該掃描信號S使該電晶體T2為不導通狀態時，前述 所寫入資料VDATA將被保持，該驅動單元72持續根據該寫 入資料Vdata的值輸出電流至該〇LED 71。 為了避免當該掃描信號S等於低電位時該電晶體T1的 1360088 閘極電位尚於該資料Vdata的值而使該資料〜以無法傳送 ^該電晶體T1的閘極，在該掃描信號s被設定為低電位之 前的—小段時間，該重設« reset會先被設定為低電位 以透過該電晶n T4清除該電晶體T1問極儲存的電荷以使 該電晶體T1閘極的電位為低電位。 仁疋虽該重設信冑RESET被設為低電位而使該電晶體 的閘極為低電位時，該驅動單元72將輸出電流到該Diode' hereinafter referred to as OLED 71 and a driver unit 72. Each of the 〇led 71 can be energized to emit one of three colors of red, green and blue. The driving unit 72 receives a scan signal s, a reset signal RESET and a data Vdata from the outside, and determines the amount of current outputted to the OLED 71 by the value of the data ν_ to drive the 〇LED 71 to emit light at the pixel. The position where the circuit is located shows a color. The driving unit 72 includes a transistor T1, a switch 720 having a transistor T2 and an transistor Τ3, a transistor τ4, and a capacitor. The transistors τι to Τ4 are p-type metal oxide semiconductors (JMype Metal 〇xide Semiconductor hereinafter referred to as PM 〇s). The drain of the transistor τι is electrically connected to the anode of the OLED 71, and the source is electrically connected to a high potential terminal of a certain voltage source VDD of the outside, the drain of the transistor T2 receives the data Vdata, and the gate thereof receives The scan signal S. The source of the transistor T3 is electrically connected to the source of the transistor T2, and its 1360088 gate is electrically connected to its drain, one end of the capacitor C, the source of the transistor T4, and the gate of the transistor Τ1. . The other end of the capacitor C is electrically connected to the high potential terminal of the constant voltage source VDD, and the gate of the transistor Τ4 is electrically connected to the drain and receives the reset signal RESET. When the scan signal S causes the transistor T2 to be in an on state, the data VDATA is written through the transistor T3 to the gate of the transistor T1 and the capacitor C, and the driving unit 72 outputs according to the data V DATA . A current (not shown) to the OLED 71, the current can be expressed by the following equation: I = KP1x [VDD - (VDATA - Vth3) - Vthl] 2 Equation (1) where I is the current value of the current 'Vth3 V\hi is the threshold voltage of the transistor T3 and the transistor T1, respectively, KP1=(l/2hCox(W/L), and W and L are respectively the channel width of the transistor T1. And length, μ is the hole migration velocity, C〇x is the gate oxide unit capacitance (capacitance per unit area) ° due to the circuit layout (layout) The position of the transistor T1 and the transistor Τ3 is very close, and VthlNVth3 is made, so that the current I=Kp1x[VDD-Vdata]2 can be known from the equation (1). Therefore, the transistors T3 and T1 are brought close to each other. The current I can be completely determined by the constant voltage source VDD and the value of the data Vdata. When the transistor T2 is in a non-conducting state, the written data VDATA will be held, and the driving unit 72 continues to output current to the 〇LED 71 according to the value of the write data Vdata. To avoid the scan signal S being equal to low. At the potential, the 1360088 gate potential of the transistor T1 is still at the value of the data Vdata, so that the data can not be transmitted to the gate of the transistor T1, before the scan signal s is set to a low potential - for a short period of time The reset «set will be set to a low potential first to clear the charge stored in the transistor T1 through the transistor n T4 so that the potential of the gate of the transistor T1 is low. When the signal RESET is set to a low potential and the gate of the transistor is extremely low, the driving unit 72 will output current to the
〇"LED 71 ’導致該電晶體T1還沒接收到該開關720傳來的 資料vDATA前該驅動單元72即輸出電流，如此會縮短該 OLED 71的使用壽命0 〆〇"LED 71' causes the drive unit 72 to output current before the transistor T1 has received the data vDATA from the switch 720, which shortens the service life of the OLED 71.
。而母一列的像素電路是同時接收到該低電位的婦描信 號且該等像素電路是由上至下以列為單位依序接收該掃 描信號S。當第一列的像素電路接收到該低電位的掃描信號 S時’由該列每"像素電路對應所接收到的資料Vdata值來 決定該像素電路之⑽D71是否發光。接著由第二列的像 素電路接㈣該低電位的掃描錢S，並決定該列每—像素 電路之〇咖71是否發光，此時第一列上的像素電路接收 到的掃描錢S是高m由該縣—像素電路的電容C 的決定該像素電路的0led7〗是否發光。依此 電狀螢幕上每—列的像㈣路來決定每—像素 電路之OLED 71是否發光。 因此對任-像素電路而言只有在被掃描科，該朴 :才為低電位，且是由每-像素電路對應的資料VJ 、疋該像素電路之〇LED71發光的情況。其他未被掃猫： 時間I由該像素電路的電容c儲存的電壓值來保持該 像素電路之〇LED 71的發光狀態。 +由於顯㈣畫面每秒才錢⑽次，—像素電路未被掃 /的時間很長大約將近16 6ms’因此該電容。的電壓值必 、維持相田長的時間，才能使該像素電路之發光的 狀態維持穩定。但是該像素電路是製作在低溫多晶石夕（i〇w tempe嶋re p〇ly_silic〇n ’ 簡稱 LTps)或是非晶系 (A崎Ph〇us)上，該電容c常常會因為漏電而造成其儲存的 電荷流失並使其兩端的電壓下降，影響該〇led η的發光 狀態。若是能增加該電容的電容值使其大於一臨界值將可 有效改善漏電問題所造成的電麼下降。 此外，因為-OLED顯示器的像素電路的數目很多， 導致製作出來的電容C大小不容易控制，且往往會因為僅 僅一小部分像素電路的電容而使整個〇咖顯示器的畫面 品質變I，甚i會有亮點或是暗點的出現，因此若是在電 容C製作出來之後，還能調整每一電容c以使每一電容c 的電容值不小於該臨界值，將可以有效降低0LED顯示器 的不良率。但是習知像素電路並無法調整電容C之大小。 【發明内容】 因此，本發明之目的，即在提供—種像素電路，該像 素電路之電容兩端的電壓差可以調整以增加該電容的電容 值。 因此’本發明之另一目的，即在提供-種顯示器，該 該顯示器之每一像素電路的電容值皆可調整。 !360〇88 於是，本發明的像素電路，電連接於外界的一定電壓 源之一高電位端與一低電位端之間並可接收外界輸入的一 調變信號、一掃描信號'一重設信號及一資料，該像素電 路包含一有機電激發光二極體、一第一電晶體、一開關、 一電容及一第四電晶體，。 該有機電激發光二極體之陰極耦合至該定電壓源之低 電位端。 該第一電晶體之第一端與該定電壓源之高電位端電連 接’且其第三端與該有機電激發光二極體的陽極電連接。 該開關與該第一電晶體的第二端電連接並接收該掃描 信號及該資料，且受該掃描信號控制以決定是否將該資料 傳送至該第一電晶體的第二端。 該電容之一端與該第一電晶體的第二端電連接，而其 另一端接收該調變信號，以藉由該調變信號調變其電容值 0 該第四電晶體的第一端及第三端分別電連接該電容的 兩端，而其第二端接收該重設信號以設定該電容兩端的電 壓值。 於是，本發明的顯示器包含複數上述之像素電路，該 等像素電路呈陣列排列，且使位於同一列上的像素電路接 收同-掃描信號但不同的資料，而同—行上的像素電路接 收不同掃W號但同樣的資料且每—列之像素電路接收 的掃描信號是作為相鄰下—列之像素電路的重設信號。 【實施方式】 10 1360088 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之—個較佳實施例的詳細說明中，將可 清楚的呈現。 參閱圖2〜圓4,本發明像素電路的較佳實施例包含一 OLED 11、一電容c、—第一電晶體⑷、一具有一第二電 晶體M2及一第三電晶體M3的開關120、一第四電晶體M4 及-第五電晶^ M5’該像素電路電連接於外界的一定電塵. The pixel circuits of the parent column receive the low-potential signal simultaneously and the pixel circuits sequentially receive the scan signal S in units of columns from top to bottom. When the pixel circuit of the first column receives the low-potential scan signal S, the (10) D71 of the pixel circuit is determined to be illuminated by the data Vdata value corresponding to the received pixel circuit. Then, the pixel circuit of the second column is connected to (4) the low-frequency scanning money S, and determines whether the column 71 of each column of the pixel circuit emits light. At this time, the scanning money S received by the pixel circuit on the first column is high. m is determined by the capacitance of the county-pixel circuit C, whether the 0led7 of the pixel circuit emits light. According to the image (four) of each column on the electric screen, it is determined whether the OLED 71 of each pixel circuit emits light. Therefore, for the any-pixel circuit, only the sector to be scanned is low, and the data VJ corresponding to each pixel circuit and the LED 71 of the pixel circuit emit light. Other unswept cats: Time I is held by the voltage value stored by the capacitance c of the pixel circuit to maintain the illumination state of the LED 71 of the pixel circuit. + Since the display (four) picture is only (10) times per second, the pixel circuit is not swept / the time is very long and is approximately 16 6ms'. The voltage value must be maintained for a long period of time to maintain the state of illumination of the pixel circuit. However, the pixel circuit is fabricated on a low temperature polycrystalline stone (i〇w tempe嶋re p〇ly_silic〇n 'abbreviated as LTps) or an amorphous system (A Sakih Ph〇us), which is often caused by leakage. The stored charge is lost and the voltage across it is lowered, which affects the illuminating state of the 〇led η. If the capacitance value of the capacitor can be increased to be greater than a critical value, the power loss caused by the leakage problem can be effectively improved. In addition, because the number of pixel circuits of the OLED display is large, the size of the fabricated capacitor C is not easy to control, and the picture quality of the entire squirrel display is often changed by the capacitance of only a small portion of the pixel circuit. There will be bright spots or dark spots, so if the capacitance C can be adjusted after the capacitor C is fabricated so that the capacitance value of each capacitor c is not less than the critical value, the defect rate of the OLED display can be effectively reduced. . However, the conventional pixel circuit cannot adjust the size of the capacitor C. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a pixel circuit in which the voltage difference across the capacitance of the pixel circuit can be adjusted to increase the capacitance of the capacitor. Therefore, another object of the present invention is to provide a display in which the capacitance value of each pixel circuit of the display can be adjusted. !360〇88 Thus, the pixel circuit of the present invention is electrically connected between a high potential end and a low potential end of a certain voltage source of the outside world, and can receive a modulated signal input by the outside world, and a scan signal 'a reset signal And a data circuit comprising an organic electroluminescent diode, a first transistor, a switch, a capacitor and a fourth transistor. The cathode of the organic electroluminescent diode is coupled to the low potential end of the constant voltage source. A first end of the first transistor is electrically coupled to a high potential end of the constant voltage source and a third end thereof is electrically coupled to an anode of the organic electroluminescent diode. The switch is electrically coupled to the second end of the first transistor and receives the scan signal and the data, and is controlled by the scan signal to determine whether to transmit the data to the second end of the first transistor. One end of the capacitor is electrically connected to the second end of the first transistor, and the other end receives the modulated signal to modulate the capacitance value of the first transistor by the modulation signal. The third end is electrically connected to both ends of the capacitor, and the second end thereof receives the reset signal to set a voltage value across the capacitor. Thus, the display of the present invention comprises a plurality of pixel circuits as described above, wherein the pixel circuits are arranged in an array, and the pixel circuits on the same column receive the same-scan signal but different data, and the pixel circuits on the same line receive differently. The scan signal received by the W-number but the same data and the pixel circuit of each column is the reset signal of the adjacent lower-column pixel circuit. [Embodiment] 10 1360088 The foregoing and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to FIG. 2 to circle 4, a preferred embodiment of the pixel circuit of the present invention comprises an OLED 11, a capacitor c, a first transistor (4), a switch 120 having a second transistor M2 and a third transistor M3. a fourth transistor M4 and a fifth transistor ^ M5' the pixel circuit is electrically connected to a certain electric dust of the outside
源VDD之-〶電位端與—低電位端之間並接收外界輸入的 一調變信號刪、-掃描信號S' -致能信號EN及一資料A modulation signal between the 〒 potential terminal and the low potential terminal of the source VDD and receiving the external input, the scan signal S' - the enable signal EN and a data
Vdata ° 該OLED 11其陰極耗合至該定電壓源vdd之低電位端 省第電B曰體Ml其第一端與該定電壓源VDD之高電 位端電連接’且其第三端與該第五電晶體M5的第—端電連 接’該第五電晶體M5的第二端接收該致能信號⑽，其第 二端與該OLED 11的陽極電連接。 該電容C之—端與該第一電晶體州的第二端為電連接 其另-端與第四電晶體M4之第三端電連接並接收該調 變信號REG ’以藉由該調變信號REG調變其電容值。 該第二電晶體M2的第一端接收該資料Vdata，且其第 二端接收該掃描信號s，而其第三端與該第三電晶體⑷的 第端電連接，該第三電晶體河3的第二端與第三端及 —電晶體Ml的第-戚雷；鱼妓。 的第一&電連接。該第二電晶體M2受該掃插 。號s㈣以決定式否將該#料v⑽透過該第三電晶體 11 1360088 M3傳送至該第一 電晶體Μ1的第二端。 二端分別電連接該電容 RESET。 該第四電晶體Μ4的第一端與第 的兩端，且其第二端接收該重設信號 ’該等電晶體Ml〜M5是以 體Ml〜M5的第二端是閘極 在本發明之較佳實施例中 PMOS的製程製作，且每一電晶 該電容c是以源極與汲極電連接在一起的製作 ’且以PMOS之汲極與閘極分別為該電容^的兩端。由於 PMOS的基底（substrate)電位與源極電位相同，藉由改變 PMOS電晶體的源極與閘極間的電壓Vsg可以控制其通道空 乏區（depletion region)的載子濃度（carder c〇ncentrati〇n)，進 而改變該電容的電容值。 圖4疋5玄電各c兩端的電壓（等於Vsg)與電容值的關係 圖，彳κ軸疋PM0S電晶體源極與閘極間的電壓且單位 為伏特（voltage)，而縱軸是電容值且單位為法拉（Farad)。若 使該電容C兩端的電壓vSG增大到超過一特定值時，該電 容C的電容值就會不小於該臨界值。因此藉由將每一像素 電路之第四電晶體M4的第三端全部電連接在一起，且將該 調變信號REG增加到適當的值以使該電容c兩端的電壓 VSG恆大於該特定值，即可將每一像素電路的電容c全部增 大，以使每一電容C的電容值皆不會小於該臨界值。 參閱圖3，在第一週期P1時，該重設信號RESET為低 電位（Low)而使該第四電晶體M4導通，因此該電容C的兩 端藉由該第四電晶體M4而短路以使該電容c儲存的電壓值 12 1360088 被清除。而此時該致能信號ΕΝ為高電位（High)而使該第五 電晶體M5不導通’因此該第一電晶體Ml並不會輸出電流 到該OLED 11，進而增加該〇LED 11的使用壽命。 在第一週期P2時，該掃描信號s為低電位，因為該電 容C儲存的電壓值在第一週期P1時已經被清除，因此該資 料vDATA將透過該第二電晶體M2及第三電晶體M3而傳送 至該電容C。而此時該致能信號£]^為低電位，因此該第一 電晶體Ml可以輸出電流到該〇LED n以驅動其發光。 參閱圖5，是本發明顯示器之較佳實施例，該顯示器使 用複數個上面所述的像素電路，且這些像素電路呈陣列排 列。第-列的像素電路接收一第一掃描信號Sl &一第一致 能信號細’而第二列的像素電路接收—第二掃描信號μ 及了第二致能信號EN2，該第一及第二掃描信號si、Μ先 後被設為低電位。對第二列的像素電路而言，因為該列接 收之重4號句頁在該第二掃描信號％之前先被設定為低 電田由於該第一列之像素電路鄰近第二列之像素電路 ’因此為了節省電路佈線的面積且使線路佈線容易，在本 發明之顯示器的較佳實 盔兮筮疋以5亥第一知描信號S1作 為該第一列之像素電路 垔°又彳5號。其他每一列之像素電 路接收的知描信號也是 俨號，作曰尤 乍為相鄰下-列之像素電路的重設 t流但疋不以此為限。 值得注意的H A-Vdata ° The OLED 11 has its cathode depleted to the low potential end of the constant voltage source vdd. The first end of the electric B body M1 is electrically connected to the high potential end of the constant voltage source VDD' and the third end thereof The second end of the fifth transistor M5 receives the enable signal (10), and the second end of the fifth transistor M5 is electrically connected to the anode of the OLED 11. The terminal of the capacitor C is electrically connected to the second end of the first transistor state, and the other end thereof is electrically connected to the third end of the fourth transistor M4 and receives the modulation signal REG′ to be modulated by the modulation. The signal REG modulates its capacitance value. The first end of the second transistor M2 receives the data Vdata, and the second end thereof receives the scan signal s, and the third end thereof is electrically connected to the first end of the third transistor (4), the third transistor river The second end and the third end of 3 and - the first - ray of the transistor Ml; The first & electrical connection. The second transistor M2 is subjected to the sweep. The number s(4) is transmitted to the second end of the first transistor Μ1 through the third transistor 11 1360088 M3 in a decisive manner. The two terminals are electrically connected to the capacitor RESET. The first end and the second end of the fourth transistor 4, and the second end thereof receives the reset signal 'The transistors M1 M M5 are the second ends of the bodies M1 M M5 are gates in the present invention In the preferred embodiment, the PMOS process is fabricated, and each of the capacitors c is electrically connected with the source and the drain. The drain and the gate of the PMOS are respectively the ends of the capacitor. . Since the substrate potential of the PMOS is the same as the source potential, the carrier concentration of the depletion region of the channel can be controlled by changing the voltage Vsg between the source and the gate of the PMOS transistor (carder c〇ncentrati〇) n), in turn changing the capacitance value of the capacitor. Figure 4疋5 shows the relationship between the voltage across the c (equal to Vsg) and the capacitance value, 彳κ axis 疋 PM0S transistor voltage and the voltage between the gate and the unit is volt (voltage), while the vertical axis is the capacitor The value is in Farad. If the voltage vSG across the capacitor C is increased beyond a certain value, the capacitance of the capacitor C is not less than the threshold. Therefore, by electrically connecting the third ends of the fourth transistor M4 of each pixel circuit together, and increasing the modulation signal REG to an appropriate value, the voltage VSG across the capacitor c is always greater than the specific value. The capacitance c of each pixel circuit can be all increased, so that the capacitance value of each capacitor C is not less than the critical value. Referring to FIG. 3, in the first period P1, the reset signal RESET is low (Low) to turn on the fourth transistor M4, so both ends of the capacitor C are short-circuited by the fourth transistor M4. The voltage value 12 1360088 stored by the capacitor c is cleared. At this time, the enable signal ΕΝ is high (High) and the fifth transistor M5 is not turned on. Therefore, the first transistor M1 does not output current to the OLED 11, thereby increasing the use of the 〇LED 11. life. During the first period P2, the scan signal s is low, because the voltage value stored by the capacitor C has been cleared during the first period P1, so the data vDATA will pass through the second transistor M2 and the third transistor. M3 is transferred to the capacitor C. At this time, the enable signal is low, so the first transistor M1 can output a current to the 〇LED n to drive its light. Referring to Figure 5, there is shown a preferred embodiment of the display of the present invention which utilizes a plurality of pixel circuits as described above and which are arranged in an array. The pixel circuit of the first column receives a first scan signal S1 & a first enable signal fine ' and the pixel circuit of the second column receives a second scan signal μ and a second enable signal EN2, the first The second scan signals si, Μ are sequentially set to a low potential. For the pixel circuit of the second column, since the page 4 of the column received by the column is set to the low field before the second scan signal %, the pixel circuit of the first column is adjacent to the pixel circuit of the second column. Therefore, in order to save the area of the circuit wiring and make the line wiring easy, the preferred real helmet of the display of the present invention uses the first visible signal S1 of 5 hai as the pixel circuit of the first column. . The known signal received by the pixel circuits of each of the other columns is also an apostrophe, which is a reset t-stream of the adjacent lower-column pixel circuit, but is not limited thereto. Noteworthy H A-
的疋，每一個電晶體M 麵OS的製程製作，例如 也都了… -電晶體M1〜M5的笛 ㈣8中所不，並且調整每 的第二端所接收之信號的電位以使每-電 13 < S ) 1360088 晶體m〜M5可在導通與不導通之間切換。_ 6巾 體Ml〜M5全部都是以NM〇s的製程製作而在圖7中^ -到第四電晶體M1〜M4是以PM〇s的製裎製作且該第： 晶體M5是以NM0S的製程製作。在圖 四電晶體M1〜M4是以NM〇s的製程製作且^五電= M5是以PMOS的製程製作。此外，該電容c也不限於以 PMOS的製程製作，也可以是以则〇8的製程製作。由於 該等電晶體M1〜M5之型態的置換及每_信號電位的調整為 本發明所屬技術領域中具有通常知識者所熟習，因此在此 不再贅述。 综合上述，相較於習知像素電路之電容c的一端是電 連_位固定的定電壓源VDD之高電位端，無法調整該 電容C的大小，本發明像素電路之電容c的—端是接收電 位值可以調整的調變M REG，且藉由增加該調變㈣ REG到一特定值使全部像素電路的電容c之電容值皆不會 小於該臨界值，降低顯示器的產品不良率，因此確實可以 達到本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1疋一電路圖，說明習知的像素電路； 圖2是本發明之較佳實施例的像素電路的—電路圖，· 14 < S ) 1360088 圖 ^ 是一产0 —^號時序圖，說明該較佳實施例之像素電路 所接收的掃知信號、_資料、一重設信號即及—致能信 號的信號時序； 圖4疋—電容值與電容兩端電壓之關係圖； 圖5疋本發明顯示器之較佳實施例的-電路圖； 疋類似圖2的電路圖，說明本發明像素電路之 較佳實施例中五個分别瓦贫 ZI ^ 刀另J為第一到第五電晶體為NM〇s的態The process of making each of the M-plane OS of the transistor, for example, is also... - The flutes (4) 8 of the transistors M1 to M5 do not, and adjust the potential of the signal received at each second end to make each-electricity 13 < S ) 1360088 Crystals m to M5 can be switched between conduction and non-conduction. _ 6 towel bodies M1 to M5 are all made by the process of NM〇s, and in Fig. 7 - the fourth transistor M1 to M4 are made of PM 〇s and the first: the crystal M5 is NM0S Process production. In the figure, the transistors M1 to M4 are fabricated by the process of NM〇s and the ^5=M5 is fabricated by the PMOS process. Further, the capacitor c is not limited to being fabricated by a PMOS process, and may be fabricated by a process of 〇8. Since the replacement of the types of the transistors M1 to M5 and the adjustment of the signal potential per _ are well known to those skilled in the art, they will not be described again. In summary, the end of the capacitance c of the conventional pixel circuit is the high potential end of the fixed voltage source VDD which is fixed to the bit, and the size of the capacitor C cannot be adjusted. The end of the capacitance c of the pixel circuit of the present invention is Receiving a modulation M REG whose potential value can be adjusted, and by increasing the modulation (4) REG to a specific value, the capacitance value of the capacitance c of all the pixel circuits is not less than the critical value, thereby reducing the product defect rate of the display, It is indeed possible to achieve the object of the present invention. The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a conventional pixel circuit; FIG. 2 is a circuit diagram of a pixel circuit according to a preferred embodiment of the present invention, 14 < S ) 1360088, FIG. The timing diagram of the ^ indicates the signal timing of the sweep signal, the _ data, the reset signal, and the enable signal received by the pixel circuit of the preferred embodiment; FIG. 4 疋—the relationship between the capacitance value and the voltage across the capacitor Figure 5 is a circuit diagram of a preferred embodiment of the display of the present invention; 疋 similar to the circuit diagram of Figure 2, illustrating a preferred embodiment of the pixel circuit of the present invention in which five respectively are poorly ZI^ and the other is first to first Five transistors are in the state of NM〇s
說明本發明像素電路之 PMOS且該第五電晶 圖7疋一類似圖2的電路圖， 較佳實施例中該第一到第四電晶體為 體為NMOS的態樣，·及 圖8疋一類似圖2的電路圖， 較佳营—β _制本發明像素電路之 平乂1主貫施例中該第一到第 體在心 第四電曰曰體為NM〇s且該第五電晶 體為PMOS的態樣。 不电日曰The PMOS of the pixel circuit of the present invention is illustrated, and the fifth transistor is similar to the circuit diagram of FIG. 2. In the preferred embodiment, the first to fourth transistors are in the form of an NMOS, and FIG. Similar to the circuit diagram of FIG. 2, in the embodiment of the pixel circuit of the pixel circuit of the present invention, the first to first body in the fourth electrical body is NM〇s and the fifth transistor is PMOS aspect. No electricity day
15 (S )15 (S )
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| TW96114011A TWI360088B (en) | 2007-04-20 | 2007-04-20 | Pixel circuit and display device having the pixel |
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| TW96114011A TWI360088B (en) | 2007-04-20 | 2007-04-20 | Pixel circuit and display device having the pixel |
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| TWI415076B (en) * | 2010-11-11 | 2013-11-11 | Au Optronics Corp | Pixel driving circuit of an organic light emitting diode |
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