TW200842783A - Pixel circuit and display device having the pixel circuit - Google Patents

Abstract

A pixel circuit is connected electrically between a high voltage terminal and a low voltage terminal of a constant voltage source, and can receive a modulating signal, a scanning signal and data from outside. The pixel circuit includes an OLED whose cathode is connected to the low voltage terminal of the constant voltage source, a first transistor, a switch and a capacitor. A first terminal of the first transistor is connected to the high voltage terminal of the constant voltage source, and a third terminal of the first transistor is connected to an anode of the OLED. The switch is connected electrically to a second terminal of the first transistor, and is controlled by the scanning signal to determine if the data is transmitted to the second terminal of the first transistor. One terminal of the capacitor is connected electrically to the second terminal of the first transistor, and the other terminal receives the modulating signal to adjust its capacitance value.

Description

200842783 _ . . . ： ' 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電蹊糸顧一二& ，兩 人 宅路及顯不态，特別是指一種有 機電激發光二極體顯示哭，^钍 1 免不纩及其内部的像素電路。 【先前技術】 广〗圖1白知的有機電激發光二極體顯示器是藉由營 幕上複數可顯現不同餘 ^ ^ f t ^ ## ^ ^ t ^ τ ^ ^ ^ 形’且包括-有機電激發光二極 _e，以下簡稱咖d) 7 ^ 7[可被通電發光而顯現紅、 色0 綠、藍三種顏色的其中一種顏 該驅動早το 72接收外界的一掃描信號』、一重設信號 RESET ^ ^ # Vdata - Μ ^ m w m Vdata ^ ^ ^ ^ OLED 71 ^ f ^ t , ^ ^ ^ 〇led 7 2 ^ ^ ^ ^ m m ^ 電路所在的位置顯現一色彩 該驅獻單元72包括一電晶體九 及一電晶聲T3的開關72〇、一電晶體T4及一電容c。該等 電晶體T1〜T4為P型金屬氧化物半導體(P‘type Metal 0x此200842783 _ . . . : ' IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electric appliance, a two-person house, and an indication of an organic electric excitation. The light diode shows crying, ^钍1 is free and its internal pixel circuit. [Prior Art] Guangyi Figure 1 Baizhi's organic electro-excitation diode display can be expressed by the complex number on the screen. ^^ ft ^ ## ^ ^ t ^ τ ^ ^ ^ Shape' and includes - organic electricity Excitation light diode _e, hereinafter referred to as coffee d) 7 ^ 7 [can be powered by light and appear red, color 0 green, blue, one of the three colors of the color, the drive το 72 receives a scan signal from the outside world, a reset signal RESET ^ ^ # Vdata - Μ ^ mwm Vdata ^ ^ ^ ^ OLED 71 ^ f ^ t , ^ ^ ^ 〇led 7 2 ^ ^ ^ ^ mm ^ The position where the circuit is present shows a color. The drive unit 72 includes a transistor. Nine and one electro-optical sound T3 switch 72 〇, a transistor T4 and a capacitor c. The transistors T1 to T4 are P-type metal oxide semiconductors (P'type Metal 0x

Semiconductor，以下簡稱 pMOS)。 . .- . - ' . - - . 該電晶體T1的没:裤與談〇LED 7卜的陽極電連接，且 源極與外界的一定電壓源VDD之高電位端電連接，該電晶 體T2的没極接收該資料 S。該電晶體T3的 200842783 -. . . ·. - - . - : ...--- ， - .. -· ； -.. ..- . - . . . . . . .; . - ....... 閘極與其汲極、讓電容c的一端、該電晶體T4的源極及該 電晶體τΓ的閘極電連接。該電容c的另一端與該定電壓源 VDD之高電位端電連接，該電晶體Τ4的閘極與汲極電連接 並接收該重設信號RESET。\ 當該掃描信號S使該電晶體T2為導通狀態時，該資料Semiconductor, hereinafter referred to as pMOS). . . . - ' . - - . The transistor T1 is not electrically connected to the anode of the LED 7b, and the source is electrically connected to the high potential end of a certain voltage source VDD of the outside, the transistor T2 The hobby received the information S. The transistor T3 200842783 -. . . . - - . - : ...---, - .. -· ; -.. ..- . - . . . . . . ..... The gate is electrically connected to its drain, the end of the capacitor c, the source of the transistor T4, and the gate of the transistor τΓ. The other end of the capacitor c is electrically connected to the high potential terminal of the constant voltage source VDD, and the gate of the transistor Τ4 is electrically connected to the drain and receives the reset signal RESET. \ When the scan signal S makes the transistor T2 conductive, the data

VdATA將透過該電晶體T3被寫入至該電晶體T1之閘極及電 容C，談驅動單元72會根據該資料VDATA輸出一電流(爾未 - - - . - · .· - . - ·· ... „ . . • 示)到該OLED 7Γ，該電流可以如下之方程式表示^丨^ Ι=κριχ^ ^(1) . . --- . . - - - -: · 其中，I是該電流的電流值，vth3、vthl分別是該電晶 : .… - .... .... ::— . -. _ . . : 及該電晶體 T1 的臨界電壓（threshold voltage)， ... . . .. : . .. · - - .. . . —. * ,— . -.... KP1=(l/2)pC0X(W/L)，W及L分別為該電晶體T1的通道 (channel)寬度及長度，μ為電洞(hole)遂| velocity)，C〇x為閘極氧化層（gate oxide)的單位電容值 - ；' - . . ' . (capacitance per unit area) ° 由於電路佈局（layout)時會使該電晶體T1及該電晶體 馨 T3的位置很接近，而使Vthl与Vth3，因此由式(1)可 流I=Kp1x[VDD-Vdata]2。因此藉由使該等電晶體T3 ^ ； ； - __ ： - _ : . ； . - - : 、 1. - · ·.. ； 此互相靠近，該電流I即可完全地由該定電壓源VDD及該 v 資料Vdata的值所決定。 〆 ' ：. . . ' ' - :VdATA will be written to the gate of the transistor T1 and the capacitor C through the transistor T3, and the driving unit 72 will output a current according to the data VDATA (Ir - - - - - - . . . - - - - ... „ . . • show) to the OLED 7Γ, the current can be expressed as the following equation ^丨^ Ι=κριχ^ ^(1) . . --- . . - - - -: · where I is the The current value of the current, vth3, vthl are respectively the electric crystal: .... - .... .... ::- . -. _ . . : and the threshold voltage of the transistor T1, .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The width and length of the channel, μ is the hole velocity | velocity), C 〇 x is the unit capacitance value of the gate oxide - ; ' - . . ' . (capacitance per unit area ° Since the position of the transistor T1 and the transistor T3 is very close due to the layout of the circuit, and Vth1 and Vth3 are made, I can flow I=Kp1x[VDD-Vdata]2 from the equation (1). Therefore, by making the transistors T3 ^ ; ; - __ : - _ : . . . - - : , 1. - · · · Recently, the current I can be completely determined by the constant voltage source VDD and the value of the v data Vdata. 〆 ' :. . . ' ' - :

I /' V -:- - - . . ： . ..... : 所寫入資料VDATA將複保持，該驅動專 入貢料Vdata的值輸出電流至該OLED 71。I / ' V -: - - - . . : . . . . : The written data VDATA will be re-held, and the drive exclusively outputs the value of the tributary Vdata to the OLED 71.

為了避免當據掃柢信號S等於條電位時該I 200842783 閘極電位高於該資料 ^該電晶體τι的閘極，在該掃描^信 T4 η ^ t#J^c 該電晶體T1閘極的電位為低電位。 但是當該重設信號 Ti的閘極㈣電位時，^ 71 ’導致該電晶體T1還沒接收到該開關72〇傳來的 貧料vDATA前該驅動單元72即輸出電流，如此會縮短該 OLED 71的使用壽命。 U ^ 二 — ^ ^ ^ -t t ^ ^ ^ ^ ^ ^ ^m^11^ ^^T^ 4^^# V- ·^ VIη ^ Μ ^ # ^ ^ ^ t # VDATA ^ ^In order to avoid the gate potential of the I 200842783 is higher than the gate of the transistor τι when the broom signal S is equal to the strip potential, the gate of the transistor T1 is gated in the scan T4 η ^ t#J^c The potential is low. However, when the gate (four) potential of the reset signal Ti is changed, the transistor T1 causes the drive unit 72 to output current before the transistor T1 has received the poor material vDATA transmitted from the switch 72, thus shortening the OLED. The service life of 71. U ^ 二 — ^ ^ ^ -t t ^ ^ ^ ^ ^ ^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

決疋該像素電路之0LED 71是否發I t ^ # ^ ^ f ^ ^ it E S . ϋ ^ ^ ^ ^ # - ^ ^ 到麟描信號S是高詹It is determined whether the 0LED 71 of the pixel circuit sends I t ^ # ^ ^ f ^ ^ it E S . ϋ ^ ^ ^ ^ # - ^ ^ to the lining signal S is Gao Zhan

# # ^ t M ^ ^ # ^ t^ ^ 〇led 71 . ^ ^ ^ . tF :, 1苗螢幕上每一列神像素電路來決定每、一像辛 電路之〇LED 7r是否發光。 像素 > ^ -I-1 # ^ ^ ^^ t # vdata ： 德像素修:懸 200842783 篇二則是由該像素電路的 像素電路之⑽D71的發態— ρ的士_ v @晝面母秒才更新6g次’-像素電路未被掃 須維持相當長的時間，才驗 狀態維:持穩定。但是該輕 temperature poly-siiicon , ^ # LTPS) ^ ^ ^ (Amorphous 、:’ ·. . .. ... 電壓下降，影響該〇LED 71的發光 狀雖。若是能增加該電容的電容值及^ 有效改善漏電問題所造成的電壓下降。 此外，因為一 0LED顯示器的像素電路# 癸致衣作出來的電容c大小不容易控制，且往往會因為僅 僅^ ’分像素電路的電容而使整個OLED顯示器的晝面 ^口貝變差，甚至會有亮點或是暗點的出覌，因此若是在電 合c衣作出來之後，還能調整每一電容c以使毒一電容c 的電谷值不小於該臨界值，將可以有敢降低〇LED顯示器 的不良率。但是習知像素電路並無法調整電容〇之大犷^ 【發明内容】 ..' , : … . '.;. -.· - .... . ； · · . ·. . , _ . .... .... ; - .... ； ·- 因此’本發明之目的’即在提供一種像素電路，該像 素電路之電容，端的電壓差可以調整以增加該電容的電容 ::俵:。識 ,； . ；: ..... ；. .. .. ... . ·; - -.. 因此’本發明之另一目的，即在提供一種顧示^ . - · .. ... . . . 該顧示器之每一像素電路的電容值皆可調整。 200842783 . . ... ； · . ... . · ' - . . 於是，本發明的像素電路，電達 源之一高電位端輿一低電位端之間並可揍收外界輪入的一 調變信號、一掃描信號、一重設信號及一資料，該像素電 路包含一有機電激發光二極體、一第一電晶體、一開關、 一電容及一第四電晶體， -· · . - . . ...... · 該有翁電激發光二極體之陰極耦合至該定電壓源之低 :·. . ...... 該第一電晶體之第一端與該定電壓源之高電位端電連 齡接，且其第三端與該有機電激發光二極體的陽極電連赛。 ^ ^ ii # I. f - t ^ ^ t ^ ^ ^ m t ^ ^ ^ m # ^ ^ ^ ^ # ^ ^ ^ ^ ^ ^ 傳送至該弟一電晶體的第二端。八^ 該電容之一端與該第一電晶體的第二端電連接，而其 另一端接收該調變信號，以藉由該調變信號調變其電容£ °"苐四電晶體的第—端及第三端分別電連接該電容的 ^ ^ i ^ ^ ^ ^ ^ ^ ^ & ^ ^ ^ -L ^ ^ ^ f ^ ^ 收同—掃描信號但不同的資料，而π 收不同掃，的貝枓而同一# # ^ t M ^ ^ # ^ t^ ^ 〇led 71 . ^ ^ ^ . tF :, 1 Each column of the god pixel circuit on the screen determines whether the LED 7r is illuminated every time after a sim circuit. Pixel > ^ -I-1 # ^ ^ ^^ t # vdata : De pixel repair: hang 200842783 The second is the state of the pixel circuit of the pixel circuit (10) D71 - ρ taxi _ v @昼面母秒Only after updating the 6g sub-pixel circuit is not whisked for a long time, only to check the state dimension: stable. However, the light temperature poly-siiicon, ^ # LTPS) ^ ^ ^ (Amorphous, :' ·. . . . . . voltage drop, affecting the illumination of the LED 71. If it can increase the capacitance of the capacitor and ^ Effectively improve the voltage drop caused by the leakage problem. In addition, because the pixel circuit of a 0 LED display # 癸 作出 作出 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容 电容The surface of the display is poor, and there may even be bright spots or dark spots. Therefore, if the electric c is made, the capacitance c can be adjusted to make the capacitance of the capacitor c. Not less than the critical value, it will be possible to reduce the defect rate of the LED display. However, the conventional pixel circuit cannot adjust the capacitance of the capacitor. [Inventive content] ..' , : ... . '.;. -.· - .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The capacitance, the voltage difference between the terminals can be adjusted to increase the capacitance of the capacitor::俵:.,, . . ;::.. ;. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The capacitance value of the pixel circuit can be adjusted. 200842783 . . . . . . . . . . , the pixel circuit of the present invention, between the high potential end and the low potential end of the power source And receiving a modulation signal, a scan signal, a reset signal and a data, wherein the pixel circuit comprises an organic electroluminescence diode, a first transistor, a switch, a capacitor and a first Four transistors, -·· . . . . . . . The cathode of the electro-optical excitation diode is coupled to the low voltage of the constant voltage source: ·. . . . The first end of the crystal is electrically connected to the high potential end of the constant voltage source, and the third end thereof is electrically connected to the anode of the organic electroluminescent diode. ^ ^ ii # I. f - t ^ ^ t ^ ^ ^ mt ^ ^ ^ m # ^ ^ ^ ^ # ^ ^ ^ ^ ^ ^ is transmitted to the second end of the transistor. Eight ^ one end of the capacitor is electrically connected to the second end of the first transistor And the other end receives the modulation No. modulates the capacitance of the capacitor by the modulation signal. The first end and the third end of the fourth transistor are electrically connected to the ^^ i ^ ^ ^ ^ ^ ^ ^ & ^ ^ ^ ^ -L ^ ^ ^ f ^ ^ Accomplished - scans the signal but different data, while π receives different scans, the same and the same

的掃義響級’且卜 I ：Τ " Τ " " ^ ^ ^ t ^ ^ ί t, ^ . Q 200842783 ... ' ' - :. ..... ...... 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 參閱圖2〜圖4，本發明像素電路的較佳實施例包含一 . . - - . - . . . . OLED 11、一電容C、一第一電晶體Ml、一具^有 晶體M2及一第三電晶體M3的開關120、一第四電晶體1^4 及一第五電晶體M5，談像素電路電連接於外界的一定電壓 ’ 源VDD之一高電位端與一低電位端之間並接收外界輸入的 . ；； - . - . . .... 響一調變信號REG、一掃描信號S、一致能信號ΕΝ及一資料 Vdata ° 該OLED 11其陰極耗合至該定電壓源VDD之低電位端 ....... '. ..... : .. • · · * - , - - - . · _ _ • - - . - - 〇 . . · - ' / .· 該第一電晶體Ml其第一端與該定電壓源VDD之高電 位端電連接，且其第三端與該第五電晶體M5的第一端電連 接，該第五電晶體M5的第二端接收該致能信號EN，其第 ^ . . ... . .. ' - 三端與該OLED 11的陽極電連接。 _ 丨該電容G之一端與讓第一電晶體Ml的第二端為電連接 - .- ' ' . . . - ' . - ，而其另一端與第四電晶體M4之第三端電連接並接收該調 變信號REG，以籍由談調變信號REG調變其電容值。 八 .. .. . ' . ： . ； - .： - - ... - . . . _ , - 二端接收該掃描信號8，而其第三端^ 第一端電連接，該第三電晶體M3的第二端與第三端及該第 : ' . - . ... : - — . ...... 一電晶體ΜΓ的第二端電連接。該第二電晶體M2受該掃描 • . . . ' - - , - ' ； 信號S控制以決定式否將該資料VDATA透過該第三電晶體 200842783 M3傳送至該第一電晶體Ml的第二端。 該第四電晶體M4的第一端與第三端分別電連接該電容 ... ' ·. . - - · - .... .... - ' .-. . - 的雨端，且其第二端接收該重設信號RESET。 在本發明之較佳實施例中，讓等電晶體Ml〜M5是以 PMOS的製程製作，且每一電晶體Ml〜M5的第二端是閘極 〇 . . . : ' . - .. ....... - . - 談電容0是以源極與汲極電連接在一起的PMOS製作 : ，且以PMOS之汲極與閘極分別為該電容C的兩端。由於 _ PMOS的基底（substrate)電位與游極電位相同，藉由改變 PMOS電晶體的源極與閘極間的電壓VSG可以控制其通道空 : :...；.：V.· ' ;：：；；：\； ' ' ；：' ：， ..； ;； ； 乏區（depletion region)的载子滚度（carrier concentration) ’ 進 ...... .. . * ... ......... .. '- ...... ......... 而改變該電容的電容值。 • . _ . . ..‘ - - 圖4是該電容C兩端的電壓（等於VSG)與電容值的關係 圖，横軸是PMOS電晶體源極與閘極間的電壓VSG且單位 ...- ..... . : .. .. 為伏特(voltage)，而縱軸是電容值且單位為法拉(？&以(1)。若 - - . . - . ' . ’ ’ - - - - . 使該電容C雨端的電壓VSG增大到超過一特定值時，該電 —— ..-- . ： .；. ： - ：, ： 電路之第四電晶體M4的第三端全部電連接在一起，且將談 調變信號REG增加到適當的值以使該電容C兩端的電壓 . . - . . .... ... - — . ----- ' - - - : . ·. -次，以使每一電容C的電容值皆不t . - - · · . . . . · 參閱圖3，在第一週期P1時，該重設信號RESET為低 . .. . · .. . . . 、 ； . , ； - 電位(Low)而使該第四電晶體M4導通，因此該電容C的兩 端籍由該第四電晶體M4而短路以使讓電容0儲存的電:壓值 200842783 • .... .. .: . . , . . . . . . · ·... - . .... : ...... ...... j.. ... : . , . . :. - 轉清除。而此時談致能信號EN為高電位(扭gh)而使該第五 電晶體M5不導通，黑此該第一電备 到該OLED U，進而增加該〇LED」!的使用壽命。 在第二週期P2時，該掃描信號8為低電位，因為該電 容C儲存的電壓值在第一週期打時已鏗被清除，因此該資 料VDAta將透過該第二電晶體Μ?及第三電晶體描而傳送 至該電容C。而此時該致能信號迎為低電位，因此該第一 電晶體Ml可以輪出電流到該〇led u以驅動其發光。 參義5 ’是本發明顯示器之敕佳實施例’該顯示器使 用複^個上面所述的像素電路:，且這些像素電路呈陣列排 列。第一列的像素電路接收一第一掃描信號以及一第一致 能信號EN1 ’而第：列— 及^第二故能信號膽2 :，該第一及第二掃描信號s卜幻先 後被設為低電位。對第二列的像素㈣ 收重叹仏破必須在該第二掃權信號以之前先被設定為低 電位，且由於該第-列之像料 口此為了即省電路佈缘的面積且使線路佈線容易，在本 發明之顯示器的較佳實施， 為該第二列之像素電路^^^ 路接收的輪錢也是作魅輸―狀 信號，但是不以此為限。 入， v值得鼻意的是，每—個電晶體:心 NMOS的.藉制从 / 一士日基衣作，例如圖6到圖8中所示，並且諸整每 一電晶體:Ml〜M5的篦-唑齡n 的弟所接收之赁號的電位以使每一電 ' - ....- .，‘·.··-·. · · · · - - *· 13 200842783 ^ n M l ~M5 ^ ^ it ^ f ^ ^ ^ ^ ^ 〇 6 t ^ ^ t ^ 體憶〜M5全部都是以NM0S的氣_ -^ f ^ t ^ ^ M1-M4 ^ ^ PMOS ^ t ^ t ^ i ^ iL t 晶體MS是以NMOS的製程製作。在圖8中，該第一到第 四電晶體M1〜M4是以NM〇s的製程製作且談第五電晶體 M5是以PM0S的製程製作。此^ PMOS的祕製作，也可以纽嶋8的製 該等電晶體福售之型態的置換及每一信號電位的調整為 本發明所屬技術中具有通常知麻 不再贅述。 、 -‘ . ... .' . -. . , ^ ·-' 綜合上述’相較於習知像素電路之電容C的一端是電 ^ # ^ t ^ ® ^^ f VDD ^ ^ ^ ^ , ^ ^ ^ ^ m =的，K ’本發嶋^ 位值可以调整的調—作缺ρ 朴 RFr $丨—姑 ^虎EG ’且错由增加該調變信號 ~ # ^ ^ ^ ^ ^ ^ t f ^ ^ ^ c ^ ^ f ^ ^ ^ ^^ ^ ϋ ^ ^ ^ ^ # 0 Λ ；ε| ^ ^ ^ 達到本發明之目的。 L > 八'員了以 -^ ( € ^ # ^ ^ ^ ^ ^ e , t ^ ‘以此限定本發明奋H : ^ ^ ^ ^ 田个 範圍及發明Μ日/ 範，即大凡依本發明申請專利 屬儀：容所作之簡料 屬本發明專利涵蓋之範圍内。:V V ^仍 【圖式簡單說明】 . . ... '·''； ' ..... 粵:1疋—電路圖’說明習知的像素電路； :圖2是本_ 14 200842783 • : ' ... \ . · ' ' . : . .. ' .-. .. - . . 3是一信號時序圖，說明該較佳實施 .. - 、 · 所接收的一掃描信號、一資料、一重設信號即及一致能信 號的信號時序； .. .. . ... 'Λ...'.. ..: ’V.' 圖4是一電容值與電容兩端電壓之關係圖; 圖5是本發明顯示器之較佳實施例的一電路圖; 圖6是一類似圖2的電路圖，說明本發明像素電路之 較佳實施例中五個分別為第一到第五電晶體為NMOS的態 — . . — .. .... ' 樣； ； · - , _ —. ^ . * . - . ' . ' . - - ' 較佳實施例中該第一到第四電晶體為PMOS且該第五電晶 體為NMOS的態樣；及 圖8是一類似圖2的電路圖，說明本發明像素電路之 較佳實施例中該第一到第四電晶體為NMOS且該第五電晶 體為PMOS的態樣。Sweeping the level of 'I and Τ " Τ "" ^ ^ ^ t ^ ^ ί t, ^ . Q 200842783 ... ' ' - :. ..... ...... The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to FIG. 2 to FIG. 4, a preferred embodiment of the pixel circuit of the present invention comprises a OLED 11 , a capacitor C, a first transistor M1, a transistor M2 and a transistor. The switch 120 of the third transistor M3, a fourth transistor 1^4 and a fifth transistor M5, the pixel circuit is electrically connected to the outside of a certain voltage 'between the high potential end and the low potential end of the source VDD And receiving the external input.;; - . - . . .... ringing a modulation signal REG, a scanning signal S, a uniform energy signal ΕΝ and a data Vdata ° the OLED 11 its cathode is consuming to the constant voltage source The low potential end of VDD....... '. ..... : .. • · · * - , - - - · _ _ • - - . - - 〇. . · - ' / . The first end of the first transistor M1 is electrically connected to the high potential end of the constant voltage source VDD, and the third end thereof is electrically connected to the first end of the fifth transistor M5, and the fifth transistor M5 is The two ends receive the enable signal EN, and the third end is electrically connected to the anode of the OLED 11. _ 之一 one end of the capacitor G is electrically connected to the second end of the first transistor M1 - . - ' ' . . - ' . - and the other end thereof is electrically connected to the third end of the fourth transistor M4 And receiving the modulation signal REG to adjust its capacitance value by talking about the modulation signal REG. VIII.. . . . ' . : . ; - .: - - ... - . . . _ , - The two ends receive the scan signal 8 and the third end ^ is electrically connected to the first end, the third The second end of the crystal M3 is electrically connected to the third end and the second end of the first: ' . - . . : - . . . The second transistor M2 is controlled by the scan . . . ' - - , - ' ; signal S to determine whether the data VDATA is transmitted to the second transistor M1 through the third transistor 200842783 M3. end. The first end and the third end of the fourth transistor M4 are electrically connected to the capacitors respectively... '.. . - - · - .... .... - ' .-. . - the rain end, and The second end thereof receives the reset signal RESET. In the preferred embodiment of the present invention, the isoelectric crystals M1 to M5 are fabricated in a PMOS process, and the second end of each of the transistors M1 to M5 is a gate 〇. . . : ' . - .. ...... - - - Capacitor 0 is made of PMOS whose source and drain are electrically connected: and the drain and gate of PMOS are the two ends of the capacitor C, respectively. Since the substrate potential of the PMOS is the same as the potential of the gate, the channel space can be controlled by changing the voltage VSG between the source and the gate of the PMOS transistor: :...;.:V.· ' ;: :;;:\; ' ' ;:' :, ..; ;; ; carrier concentration of the depletion region 'into... .. . * ... . ........ .. '- .................. And change the capacitance value of this capacitor. • . . . . . . - - Figure 4 is the relationship between the voltage across the capacitor C (equal to VSG) and the capacitance value. The horizontal axis is the voltage VSG between the source and the gate of the PMOS transistor and the unit... - ..... . : .. .. is voltage, and the vertical axis is the capacitance value and the unit is Farad (?& to (1). If - - . . - . ' . ' ' - - - - . When the voltage VSG of the rain terminal of the capacitor C is increased beyond a certain value, the electric - ..-- : : ;; : : :, : The third end of the fourth transistor M4 of the circuit Electrically connected together, and the talkback modulation signal REG is increased to an appropriate value to make the voltage across the capacitor C. . . . . . . . - . . ----- ' - - - : . . . - times, so that the capacitance value of each capacitor C is not t. - - · · . . . . Refer to Figure 3, in the first period P1, the reset signal RESET is low. . . . · . . . . . , . . . , - The potential of the fourth transistor M4 is turned on, so that both ends of the capacitor C are short-circuited by the fourth transistor M4 to allow the capacitor 0 to be stored. Electricity: Pressure 200842783 • .... .. . . . . , . . . . . . . . . . . . . . . . . . . . . . . j.. .. . : . , . . : . - Turn to clear. At this time, the enable signal EN is high (twist gh) and the fifth transistor M5 is not turned on, so the first device is ready to the OLED U. Further increasing the lifetime of the 〇LED"! In the second period P2, the scan signal 8 is low, because the voltage value stored by the capacitor C has been cleared during the first cycle, so the data VDAta will Transmitting to the capacitor C through the second transistor and the third transistor. At this time, the enable signal is ushered to a low potential, so the first transistor M1 can take a current to the 〇led u Driving its illumination. 参义5' is a preferred embodiment of the display of the present invention. The display uses a plurality of pixel circuits as described above: and the pixel circuits are arranged in an array. The pixel circuits of the first column receive a first The scan signal and a first enable signal EN1' and the first: column - and the second second signal (2), the first and second scan signals s are sequentially set to a low potential. Pixel (4) The sigh must be set to a low level before the second sweep signal is Since the image port of the first column is for the purpose of saving the area of the circuit edge and making the line wiring easy, in the preferred implementation of the display of the present invention, the pixel circuit of the second column is received by the circuit. It is also a symbol of charm, but it is not limited to this. Into, v is worthy of the nose, each transistor - heart NMOS. Borrow from / a day of clothing, such as shown in Figure 6 to Figure 8, and each transistor: Ml ~ M5's 篦-azole age n's younger brother receives the potential of the quotation so that each electric '-..-.,'·.··-.. · · · · - - *· 13 200842783 ^ n M l ~M5 ^ ^ it ^ f ^ ^ ^ ^ ^ 〇6 t ^ ^ t ^ Body memory ~ M5 are all gas with NM0S _ -^ f ^ t ^ ^ M1-M4 ^ ^ PMOS ^ t ^ t ^ i ^ iL t Crystal MS is fabricated in an NMOS process. In Fig. 8, the first to fourth transistors M1 to M4 are fabricated in a process of NM 〇s and the fifth transistor M5 is fabricated in a process of PMOS. The secret fabrication of this PMOS can also be made by the fabrication of the 嶋8, and the replacement of each transistor and the adjustment of each signal potential are generally unknown in the art to which the present invention pertains. , -' . . . ' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ^ ^ ^ ^ m =, K '本发嶋 ^ The value of the bit can be adjusted - for the lack of ρ 朴 RFr $丨 - 姑^虎 EG ' and the error is increased by the modulation signal ~ # ^ ^ ^ ^ ^ ^ Tf ^ ^ ^ c ^ ^ f ^ ^ ^ ^^ ^ ϋ ^ ^ ^ ^ # 0 Λ ; ε| ^ ^ ^ achieve the object of the present invention. L > Eight 'members with -^ ( € ^ # ^ ^ ^ ^ ^ e , t ^ ' to limit the invention Fen H : ^ ^ ^ ^ field range and invention day / model, that is, the general The patent application for the invention is within the scope of the patent of the present invention.: VV ^ still [simple description of the drawing] . . . . . . . . . . . . . - Circuit diagram 'Describes a conventional pixel circuit; Figure 2 is this _ 14 200842783 • : ' ... \ . · ' ' . : . . . ' .-. .. - . . 3 is a signal timing diagram, DESCRIPTION OF THE PREFERRED EMBODIMENT: -, · Received a scan signal, a data, a reset signal, and a signal timing of a consistent energy signal; .. .. . . . . . . . . . . . . Figure 4 is a circuit diagram of a capacitor value and a voltage across the capacitor; Figure 5 is a circuit diagram of a preferred embodiment of the display of the present invention; Figure 6 is a circuit diagram similar to Figure 2, illustrating the pixel circuit of the present invention In the preferred embodiment, five states in which the first to fifth transistors are NMOS are respectively - . . . . . . . . . . . . . . . . . . . . . . . - - ' In the preferred embodiment, the first to fourth transistors are PMOS and The fifth transistor is an NMOS state; and FIG. 8 is a circuit diagram similar to FIG. 2, illustrating that the first to fourth transistors are NMOS and the fifth transistor is a PMOS in a preferred embodiment of the pixel circuit of the present invention. The way.

15 200842783 【主要元件符號說明】 Μ1 …·， …第一電晶體 RESET·， •重設信號 M2·* … …第二電晶體 ΕΝ ··.··〜 •致能信號 M3 ·…. •…第三電晶體 ΕΝ1 ··…， .第一致能信號 Μ4 ···*. …·第四電晶體 EN2 ·..·· •第二致能信號 Μ5…· …·第五電晶體 REG” … •調變信號 Ρ1··… •…第一週期 η··"···· «有機電激發光二極 Ρ2·"，· ‘…第二週期 體 S · …·掃描信號 120·“"· •開關丨 S1 ·…， …·第一掃描信號 High · ·" · •高電位 S2 ·‘… •…第二掃描信號 Low ·…· •低電位 Vdata ……資料 VDD.··· -定電壓源15 200842783 [Description of main component symbols] Μ1 ...·, ...first transistor RESET·, • reset signal M2·* ... second transistor ΕΝ ·····~ • enable signal M3 ·.... •... The third transistor ΕΝ1 ··..., the first enable signal Μ4 ···*. ....the fourth transistor EN2 ·..···the second enable signal Μ5...···the fifth transistor REG” ... • Modulation signal Ρ1··... •...first period η··"···· «Organic electroluminescence excitation diode 2·",· '...second period body S · ...·scanning signal 120·" "· • Switch 丨S1 ·..., ...·First scan signal High · ·" · High potential S2 ·'... •...Second scan signal Low ·...· • Low potential Vdata ... Data VDD.·· · - Constant voltage source

Claims (1)

200842783 .... . . :. . ' · .'' ..... ： ； -/ :- · , 十、申請專利範圍r 1 · 一種像素電路，雷遠接於 卜界的-定電壓源之—高電位 位端之間並接收外界輪入的一調變信號、一 知描知號及一資料，該像素電路包含： 之低電位端； ..^ ^ ^ ~ f t ^ ^ > j. % , ^ ^ n ^ m ^ ^ ^ ^ ^ ^ ^ m ^ t _…:.連接..；：. 掃l及該貝料’ i馨掃描信奪控制以決定是否將 該資料傳送至該第一電晶體的第二端；及：〆 一電容，其一端與該第一電晶體的第二端電連接， 而其另一端接收該調變信號，以藉由該調變信號調變其 電容值。 .......... . ....... ... • 2.依據申請專利範圍第丨項所述之像素電路，其中，該調 變k號夠大到使該電容值不小於一臨界值。 3.依據申請專利範圍第2:項所述之象素電路，其中，該電 ^ :)容是以一源極與汲極電連接之金屬氧化物半導禮製作， 、丨且以該金屬氧化物半導體之汲板與閘極分別做為該電:容 ‘ :的兩端。 :. - .... . .. ： ' .·' .. .... .；, …... ".… 夫:依據申清專利範圍第3項所述之像素電路，還色振 電晶體，該第四電晶體的第一端及第三端分別電連接 · · . - ... ' . ' - - · - - ' . .· 該電容的兩端’而其第二端接收外界翁一重設信號队 17 200842783 ： ；,.·ν； . ： --V. ·.；'：' .· ;' .. .. - '...: . :. . ...-： .- · ' ： — ’ . . . . ' · . 定讓電客兩端的電壓。 ... · .--. : ; . —' . ·- ........ 5.依據申讀專科範圍第4項所述之 連接於該第-電晶體和該有料 五電晶體，該第五 電連接V :設信號使該第四電晶體導„ 電晶體不導通… 二極體間的通路 ^ ^ ^ ^ 6 . ^ # t it * ^ II ® ! 5 ^ ^ ^ ^ # ^ 1 ^ ^ ^ 關包括-第二電晶體及一 _^^ 馀一#砬^ 亥弟二電晶體的 :”收該㈣’歸二端接_掃_^ ，端，該第三電晶體的第一㈣ 弟二&、第三端及該第一第晶體的第二端電連接。 7. 依據申請專利範圍第6項所述之像素電路，其中，該等 電晶體是PMOS，且每一電晶體的第:二端是閑極。— 8. 依據申請專利範圍第6項所述之像素電路，立中，該第 一到第四電晶體是PM0S而該第五電晶體是^ 每一電晶體的第二端是間極。 9·依據申請專利範圍第丨項所述之像素電路，還包括一第 四電晶體，铎第四電晶體的第一端及第三端分別電速接 該電容的兩端’而其第二端搔收外界的—重設信號以嚷 疋该電谷兩端的電壓。 10.依據申請專利範圍第9項所述之像素電路v，還包 ' · .· · · · . * ; . · .,’.·. ·‘ ' 18 - . _ . .. .. . : .:. .. -. ......乂 ' ; .，.… ., - .、 ' L 」. .. . . . . .. ..... -， ' / . , ： .^；. - ' ： Λ；；； - ,.. 連接於該弟一電晶體和該有機電激發光二極體之間的第 . … ； ... ' ' - .. ' .. ./ . ' .- 了 _ - _ . : . ' ' - . Γ- - ' - ' ; ；..'' -’.... 五電晶體，該第五電晶體的第一端與該第一電晶f 三端電連接，且第三端與該有機電激發光二極體的陽極 電連接，而其第二端接收外界的一致能信號，且當該重 設信號使該第四電晶體導通時，該致能信號會使該第五 ......； . 電晶體不導通，以中斷該第一電晶體與該有機電激發光 二極體間的通路。 ' 11 · 一種顯示器，包含複數呈陣列排列的^像 0 —定電壓源並產生一調變信號及複數掃描信號且接收複 - -; . . · ; :’： . ~ : _ · . . . 數資料，且使位於同一列上的像素電路接收同一掃描信 ' ' .. ... ，· . _ -. ... ...... - , ; \ ... - - . ’ ％ : . 號但不同的資料，而同一行上的像素電路接收不同掃描 信號但同樣的資料，該定電壓源具有一高電位端與一低 ....... ' .... 電位端，且每一像素電路包括: 一有機電激發光二極體，其陰極麵合至該定電壓源 之低電位端； - ' .' ' · . ' - . : ' ... . - - 一第一電晶體，其第一端與該定電壓源之高電位端 _ 電連揍，且其第三端與談有機電激發光二極體的陽極電 連接；：—V 一開關，與該第一電晶體的第二端電連接並接收該 ‘ 等掃描信號的其中之一及該等資枓的其中之一，且受接 · · : · . · ... : ----- · . - . .. ... .: · . , . - 電晶體的第二端；及 . .. . ;. :.· / —. .· - . 一電容，其一端與读第一電晶體的第二端電連接， 而其另一端接齡該調變信號，以藉由該調變 - ..... , .... ν.：· : -.--.. .. ' : . ·....:. _ . * . :— 電容值。 I 2.依據申W專利乾圍第Η項所述之顯示器，其中，該調變 信號夠大到使每一像素電路之電容值不小於一臨界值。 13•依據申請專利範圍第12項所述之級㈣ ^ μ t ^ ^ ^ ^ 做為該電容的兩端。 .. _ ' - . . - . ' .· 14,依據申請專利範圍第13項所述之顯示器，其中，每一像 Φ t n- m - f ra f ^ ^ , Wa ^ ® f ^ % ^ a =三端分別電連接該像素電路之電容的兩端，而其第二 =接收上一列像素電路之開關所接收的掃描信號以設定 该像素電路之電容兩端的電壓。 15'^^ η^μμμ% u ^ ^ t , . …更產生複數致能信號’且同一列像素電路接收相同的 ^能信號’而同一行的像素電路接收不同的致能信號， _ 卞—像素電路還包括一電連接於該像素電路之第一電晶 举和该像素電路之有機電激發光二極體之間的第五電晶 體》亥第五電晶體的第一端與該像素電路之第一電晶體 • 的第三端電連揍，且第三端與該像素電路之有機電激發 光二極體的陽極電連接，而其第二端接收該致能信號， 且當該第四電晶體被其所接收的掃描信號控制為導道時 :，談致能信號會使該像素電路之第五電晶體不導通 :二斷該像素電路μ 發光二極體間的通路。 20 200842783 I6.依據申請專利:範圍第】5項所述之顯示:幕 素電路之開關包括一第二電晶體及一第v雷皆每'' 像 二電晶體的萆—端接收該資料，且第二㉔二日日體’竣第 的第二端電連接。 Λ Λ ^ ^ ^ 弟日日體 17·依據f請專利範爵第16項所述之顧示器，其中，二 晶體是PM0S，且每一電晶體的心 饥依摔申請專利範圍第16項所述之顯示器，其 ^ f ^ t ^ M ^ PMOS ^ 1¾ ^ ^ 一電晶體的第二端是閘極。 19.依據申請專利範圍第以項所述之顯示器，其中，每一像 ^路還包括一第四電晶體： 第三端分別電連接該像素電路之電容的兩端，而其第二 端接收上一列像素電路之開關所接收的掃描信號以設定 卜該像素電路之電容兩 2〇.依據申請專利範圍第丨9項所述之顯示器，其中，該顯示 ... ... ... \ ..... .'...... ... .. 态更產生複數致能信號，且同—列像素電路接收相同的 - - . - . . - . - - . . V : . 致能信號，而同一行的像素電路接收不同的致能信號， 每一像素電聲還包括一電連接於該像素嗶^ :體和該像素電路之有機電激發光二極體之間的第玉^ ;· …. . . · .- . - 體’該第五電晶體的第一端輿該像素電路之第二 .'' .:..'- . . . ' ' ' . ..... . 的第三秀電連接，且第三端與其像素電路之有機t 光二極體的陽極電連接，而其第丨二端搔故 21 . -:_ - · . - · -… ‘ .:.! . ' ' . : . ，'- . - - . ·... ' ... .. . . .. ： ' - - . - ' ' - . : - . ；' . ' '- . - ' : ' ...... .: ' 且當霉第四電晶體被其所接收的為〆 ，該致能信號會使該像素電 中斷該像素電路之第一蕾 弟五電晶體不導通，以 發光二極體間的通路。 > 像素电路之有機電激 21·—種像素電路，電連接於外界的—〜币 端與—低電位端之門並桩讲疋電壓源之一高電位 . 私4 5虎及一資料，該像素電路包含. i之高·電激發光二極體’其陽極― t ϋ ^ ^ ^ " Μ ^ ^ ^ ^ ^ t Μ ^ t ^ ^ ’且其第三端與該有 .. .. ' ' . '，‘ ' .'' . ' ..... · . . ' . . ‘ .' ‘ . ..... . . . · - ^ } ^ ^ ^-t ^ ^ ^ ^ 知描信號及該資料，且受該播扣 兮〜V 该 4喊控制以決定是否將 邊貝料傳送至該第一電晶體的第二端；及 ？： - * ； . . _ . '. . .... ,... .- · I 一電容，其一端與該第-電晶體的第二端電連接， ’而其另收該調Μ 電容值。 22.依據申請:專利範圍第21項所^ 調變信號典大到使該電容值不小於一乾炎 认依據申請專利範圍第η項所述毛像素電路，其中^該^ 容是以一源極與汲極電連揍之金屬氡化物半導體製^， ^ « ft 4b^ ^ f Μ ^ ^ # Μ ^ 的兩端。 22 200842783 . · - / : ' · .· - - · . · . · . , . . · · 24.㉚據申明專利_ 第二電，體，該第讀 接忒電谷的兩端，而其第二端接收外界的一重詨信號以 設定該電容兩端的電壓。 •依據申^專利範圍第Μ項所述之傢素電路，還包括一電 連^於該第-電晶體和該有機電激發光二極體之間的第 ， ^電『體’该第五電晶體的第一端與讓第一電晶體的第 _ 二端包遑接，且第二端與該有機電激發光二極體的陰極 電越，其勒㈣ ^ ^ ^ ^ ^ ^ ^ f ^ M f it af 5 t ^ ^ f ^ 電晶體不導通，以Φ磨冷兮隹兩从 乂中妨该弟一電晶體與該有機電激發光 —^極體間的通路。 關包括-第二電晶體及一第碰 ! #^ ^ #^^^^^ ^: ^ ^ ^ r 二端與該第三電晶體的端電接兮箆一曰 > 篡一紗镇- > 該弟二電晶體的 一^、弟三蟑及該第一第晶體的第二端電連接。 27. f || ffl f 26^ ^ € , ^ f , ^ 電晶體是觀0S，且每一，^ tm , 一到第四電晶體是NM〇s而該第五電曰_曰七 …弟 母一電晶體的第二端是閘極。 29.依據申請專利範圍第2】年所 23 200842783 .... ... . / .... . . ... ... ： 接該電容的兩端，而其第二端接收外界的一重設信號以 .... . - ; . . ： - · ；. . . ... , ..... 設定該電容兩端的電屋。 3 0.依據申讀專利範圍第29項所述之像素電路，還包括一電 ... - ： , . . ^ · . 連接於談第一電晶體和該有機電激發光二極體之間的第 ..， .. ... . . ' · 五電晶體，該第五電晶體的第一端與該第一電晶體的第 三端電連接，且第三端與該有機電激發光二極體的陰極 電連接，而其第二端接收外界的一致能信號，且當該重 ’ t信號使該第四電晶體導通時，該致能信號會使該第玉 - .... . · . - , . - ；.. - ’ ' • 電晶體不導通，以中斷該第一電晶體與該有機I • - - - .... ·. · ..... 二極體間的通路。 .. ...1 . ... . 31. —種顯示器，包含複數呈陣列排列的像素電路，且具有 一定電壓源並產生一調變信號及複數掃描信號且接收複 數資料，且使位於同一列上的像素電路接收同一掃描信 號但不同的資料，而同一行上的像素電路接收不同掃描 信號但同樣的資料，該定電壓源具有一高電位端與一低 電位端，且每一像素電路包括： .- .. ' . .. _ ' ' .... . . ..,. _ 一有機電激發光二極體，其陽極耦合至該定電壓源 . — :- ' .. .； ： .. V ； 之高電位端; 一第一電晶體，其第一端與該定電壓源之低電位端 :: ; ·: . · . - .. :. : V 電連接，且其第三端與該有機電^ ^ ^開關，與詼第一電晶體的第二端電連接並接收該 . . ' - . . - \ — - . ' ' - - 等掃描信號的其中之一及該等資料的其中之一，且受接 .:..... ..... ' .. ... . 1:、.... ： — .:.1 . 收到的掃描信號控制以決定是否將該資料傳送至該第一 - - - ‘ . - ' - - - ： , ." _ -* - . _ ... . 200842783 電晶體的第二端;及 ^ ^ ^ f _ f 4 it ^ f ^ t ^ # , 而其另-端接收該調變信號，以藉由辑祕 電容值。 . ' 32. 依據申請專利範圍第31項所述^ 信號夠大到使每-像素電路之I· 33. 依據申請專利範圍第3, 素·電路之電容_是'以一源極+ 土上 道舯制从：，、及極電連接之金屬氡化物半 導體製作’且以該金屬氧化物導聽沒朽盥叫* 做為該電容的兩端。及 34. ^^f @ ^ 33 ^ , A t , 素電路還包括-第四電晶體1 h端分別電連接該像素電路之電容的兩^ 4像素電路之電谷兩端的電壓。 35. 依據申請專利範圍第 器更產生複數致能信號，且同—列傻去予中°亥..肩不 紡处产^ ^ ^ ^ ^ 列像素電路接收相同的 ^㈣’㈣-行的錄電够 :[像素電路還包括一電連接於謂 :和!:素電路之有機電激爆 | ^ ^ f ^ ί ^ ^ ^ # . ^ f ^ ^ ^ ^ ^ ^ ^ ㈣弟四"Μ被其㈣ 25 200842783 中斷該像素電路之第_u 發光二極體間的通路。 v ^’、包路之有機電邀 36.^ 素電路之開關包括―第二電晶體及… ^1 ^ M ^ ^ ~ ^ ^ It t # > J. ^ ^ I ^θθ f 1 ^1 號，而其第三端輿該第三電晶體的第山收遠掃推爲 入的弟1峨 m々ω μ ^命異中，氣—认 二電晶體的第二端、裳一山爲斗A ^ : %弟二鈿及该像素電路之第 馨的第二端電連接。 r: 力 37. ^ ^ t II # ^ H S f 36 ^ ^ ^ - ^ ; ^ . 晶體是NMOS，且每一電晶體的第二敎 38. ^€ t ^ ^ a f 36 ^ ^ 到第四電晶體是NMOS而該第五電曰〆e w 〜弟’ ^ ^ ^ ^ ^ ^ ^ 所立电日日體是PMOS，日、 一電晶體的第二端是閘極。 39. 依據申請專利範圍第31項所述之顯示器，其^ 龜素電路還包括一第四電_ m ^ 端接收上一列像素電路之開關所接收的掃描信號以設 該像素電路之電容兩端的電壓。 4〇·依據申請專利範圍第3 9項所述之顯示潟 。更產生複數致能倍號，且同一列像素電路接收相同） 致此V波’而同一行的像素電路接收不同的致能信號 每一參素電路還包括 錢f該像章電路之有機電激發光二極 200842783 體，該第五電晶體的第一端與該像素電路之第一電晶體 的第三端電連接，且第三端與該像素電路之有機電激發 光二極體的陰極電連接，而其第二端接收該致能信號， -- ·. ' - .. - · · · ——·. · - . .. 且當該第四電晶體被其所接收的掃描信號控制為導通時 ’該致能信號會使該像素電路之第五電晶體不導通’以 - ；： .... . '... . - 中斷該像素電路之第一電晶體與該像素電路之有機電激 發光二極體間的通路。 織200842783 .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The source-high potential terminal receives a modulation signal, a known description number and a data, and the pixel circuit comprises: a low potential end; .. ^ ^ ^ ft ^ ^ > j. % , ^ ^ n ^ m ^ ^ ^ ^ ^ ^ ^ m ^ t _...:.Connection..;:. Sweep l and the bedding 'ixin scan control control to determine whether to transmit the data to a second end of the first transistor; and: a capacitor, one end of which is electrically connected to the second end of the first transistor, and the other end of which receives the modulated signal to be modulated by the modulated signal Its capacitance value. ............................ 2. The pixel circuit according to the scope of the patent application, wherein the modulation k is large enough to make the capacitor The value is not less than a critical value. 3. The pixel circuit according to claim 2, wherein the capacitor is made of a metal oxide semi-conductor electrically connected to the source and the drain, and is made of the metal The yoke and the gate of the oxide semiconductor are respectively used as the ends of the electric: capacitance ':. :. - .... . . . : ' .·' .. .... .;, ...... ".... 夫: According to the pixel circuit described in the third paragraph of the patent scope, a vibrating crystal, the first end and the third end of the fourth transistor are electrically connected respectively. · . . . - - . . . - - . Receiving the external Weng Yi reset signal team 17 200842783 : ;,.·ν; . : --V. ·.;':' .· ;' .. .. - '...: . :. . . : .- · ' : — ' . . . . ' . . Let the voltage across the electric passenger. ... · .--. : ; . — — . . . 5. 5. Connected to the first transistor and the five-electrode according to the fourth paragraph of the application scope. The fifth electrical connection V: the signal is such that the fourth transistor leads to the transistor not conducting... the path between the diodes ^ ^ ^ ^ 6 . ^ # t it * ^ II ® ! 5 ^ ^ ^ ^ # ^ 1 ^ ^ ^ Off includes - second transistor and one _^^ 馀一#砬^ haidi two crystals: "receive the (four)'s two ends _sweep_^, the end, the third transistor The first (four) brother two & the third end and the second end of the first crystal are electrically connected. 7. The pixel circuit of claim 6, wherein the transistors are PMOS, and the second end of each transistor is a free pole. 8. The pixel circuit according to claim 6, wherein the first to fourth transistors are PMOS and the fifth transistor is the second terminal of each transistor. The pixel circuit according to the invention of claim 2, further comprising a fourth transistor, wherein the first end and the third end of the fourth transistor are electrically connected to the two ends of the capacitor respectively, and the second The terminal picks up the outside world - resets the signal to illuminate the voltage across the valley. 10. According to the pixel circuit v described in claim 9 of the patent application, the package also includes '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .:. .. -. ......乂' ; .,.... ., - ., ' L ”. . . . . . . . . . . ..,, ' / . , : . ^;. - ' : Λ;;; - ,.. is connected between the transistor and the organic electroluminescent diode. ... . . ' ' - .. ' .. . ' .- _ - _ . : . ' ' - . Γ- - ' - ' ; ;..'' -'.... Five transistors, the first end of the fifth transistor and the first The crystal f is electrically connected at three ends, and the third end is electrically connected to the anode of the organic electroluminescent diode, and the second end thereof receives an external uniform signal, and when the reset signal turns on the fourth transistor The enable signal causes the fifth (...) transistor to be non-conducting to interrupt the path between the first transistor and the organic electroluminescent diode. ' 11 · A display comprising a plurality of arrays of 0-set voltage sources arranged in an array and generating a modulated signal and a plurality of scan signals and receiving complex--; . . ; ; :': . : : _ · . . . Number of data, and the pixel circuits located in the same column receive the same scan letter ' ' . . . , . . . . . . . , , ; \ ... - - . ' % : . but different data, and the pixel circuit on the same line receives different scanning signals but the same data, the constant voltage source has a high potential end and a low .... ... .... potential end And each pixel circuit comprises: an organic electroluminescent diode, the cathode surface of which is coupled to the low potential end of the constant voltage source; - ' . ' ' · . ' - . : ' . . - - one a transistor, the first end of which is electrically connected to the high potential end of the constant voltage source, and the third end of which is electrically connected to the anode of the organic electroluminescent diode;: -V a switch, and the first The second end of the transistor is electrically connected and receives one of the 'scanning signals and one of the assets, and is connected. · · · · · ... : ----- · .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The two ends are electrically connected, and the other end is connected to the modulation signal by the modulation - ....., .... ν.:· : -.--.. .. ' : . ....:. _ . * . : — Capacitance value. 2. The display of claim 1, wherein the modulation signal is sufficiently large that the capacitance of each pixel circuit is not less than a threshold. 13 • According to the level (4) ^ μ t ^ ^ ^ ^ described in item 12 of the patent application scope as the two ends of the capacitor. . . . _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ a = the three terminals are electrically connected to the two ends of the capacitor of the pixel circuit, and the second = the scan signal received by the switch of the previous column of pixel circuits to set the voltage across the capacitor of the pixel circuit. 15'^^ η^μμμ% u ^ ^ t , . . . produces a complex enable signal 'and the same column of pixel circuits receive the same ^ signal" and the same row of pixel circuits receive different enable signals, _ 卞 - The pixel circuit further includes a first transistor electrically connected to the first electro-optic crystal of the pixel circuit and an organic electroluminescent diode of the pixel circuit, and a first end of the fifth transistor and the pixel circuit The third end of the first transistor is electrically connected to the anode, and the third end is electrically connected to the anode of the organic electroluminescent diode of the pixel circuit, and the second end receives the enable signal, and when the fourth When the crystal is controlled by the scanning signal received by the crystal as a channel: the enabling signal causes the fifth transistor of the pixel circuit to be non-conducting: the path between the pixel circuit and the light emitting diode is broken. 20 200842783 I6. According to the patent application: the display of the scope of the fifth item: the switch of the morpheme circuit comprises a second transistor and a first V-ray, each of which receives the data from the 萆-end of the second transistor. And on the second 24th day, the second end of the body of the body is electrically connected. Λ Λ ^ ^ ^ 弟日日体17· According to f, please refer to the patent described in the 16th item of the French Fanjue, in which the two crystals are PM0S, and each transistor's heart hunger falls to apply for the patent scope of the 16th item. In the above display, the second end of the transistor is ^b ^ t ^ M ^ PMOS ^ 13⁄4 ^ ^ . 19. The display of claim 1, wherein each of the pixels further comprises a fourth transistor: the third end is electrically connected to both ends of the capacitor of the pixel circuit, and the second end is received The scan signal received by the switch of the pixel circuit of the previous column is used to set the capacitance of the pixel circuit. The display device according to the ninth aspect of the patent application, wherein the display is ... ..... .............. The state produces a complex enable signal, and the same-column pixel circuit receives the same - - . - . . . The signal is enabled, and the pixel circuits of the same row receive different enable signals, and each pixel of the electrical sound further includes a first jade electrically connected between the pixel and the organic electroluminescent diode of the pixel circuit ^ ;· . . . . . . . . . - The first end of the fifth transistor 第二 the second of the pixel circuit. '' . . .. '- . . . ' ' ' . . . The third show is electrically connected, and the third end is electrically connected to the anode of the organic t-light diode of the pixel circuit thereof, and the second end thereof is 21. -:_ - · · - - -... ' . :.! . ' ' . : . , '- . - - . ·... ' ... .. . . . . : ' - - . - ' ' - . : - . ;' . ' '- . - ' : ' ...... .: ' And when the fourth transistor is received by the mold, the enable signal will cause the pixel to electrically interrupt the first circuit of the pixel circuit. Conducted to the path between the light-emitting diodes. > Organic electro-optical circuit of pixel circuit 21 - a kind of pixel circuit, electrically connected to the outside - the end of the coin and the door of the low potential end and the high voltage of one of the voltage sources. Private 4 5 tiger and a data, The pixel circuit comprises a high-electron excitation photodiode of 'i'-''''''''''''''''''''''''''''''''''''' ' ' . ',' ' .'' . ' ..... · . . ' . . ' .' ' . ..... . . . · - ^ } ^ ^ ^-t ^ ^ ^ ^ Depicting the signal and the data, and being controlled by the broadcast button VVV to determine whether to transmit the side shell material to the second end of the first transistor; and? : - * ; . . _ . '. . .... ,... .- · I A capacitor, one end of which is electrically connected to the second end of the first transistor, 'and the other is the capacitor value. 22. According to the application: the scope of the patent is in the 21st paragraph, the modulation signal is so large that the capacitance value is not less than a dry pixel. According to the patented range, the gross pixel circuit is referred to in item n, wherein the capacitance is a source. The metal telluride semiconductor with the 汲 电 ^ ^ ^ ^ ft 4b ^ ^ f Μ ^ ^ # Μ ^ both ends. 22 200842783 . · - / : ' · . . . . . . . . . . . . . . . . . . . . . . The second end receives a signal from the outside to set the voltage across the capacitor. The home-card circuit according to the scope of the invention, further comprising an electrical connection between the first transistor and the organic electroluminescent diode, the second electrical The first end of the crystal is connected to the second end of the first transistor, and the second end is electrically connected to the cathode of the organic electroluminescent diode, and is (4) ^ ^ ^ ^ ^ ^ ^ ^ ^ M f it af 5 t ^ ^ f ^ The transistor is not conducting, and the channel between the transistor and the organic electroluminescence is obtained by Φ. Off includes - the second transistor and a first touch! #^ ^ #^^^^^ ^: ^ ^ ^ r The two ends are electrically connected to the end of the third transistor > 篡一纱镇- > The second transistor of the second transistor is electrically connected to the second terminal of the first crystal. 27. f || ffl f 26^ ^ € , ^ f , ^ The transistor is the view 0S, and each, ^ tm , the first to fourth transistor is NM〇s and the fifth electrode is _ 曰 seven... The second end of the mother-transistor is a gate. 29. According to the scope of the patent application, the second year of the year 23 200842783 .... ... . / .... . . ... : : The two ends of the capacitor are connected, and the second end receives the outside A reset signal to .... . - ; . . : - · ;. . . ... , ..... Set the electric house at both ends of the capacitor. 3. The pixel circuit according to claim 29, further comprising an electric ... - : , . . . ^ . . connected between the first transistor and the organic electroluminescent diode No.., . . . . . . . . a five-electrode, the first end of the fifth transistor being electrically connected to the third end of the first transistor, and the third end and the organic electroluminescent diode The cathode of the body is electrically connected, and the second end thereof receives an external uniform energy signal, and when the weight signal causes the fourth transistor to be turned on, the enable signal causes the first jade - .... - , . - ;.. - ' ' • The transistor is not conducting to interrupt the path between the first transistor and the organic I • - - - ..... ...... . .. .1 . . . 31. A display comprising a plurality of pixel circuits arranged in an array and having a voltage source and generating a modulated signal and a plurality of scan signals and receiving the plurality of data, and making the same The pixel circuit on the column receives the same scan signal but different data, and the pixel circuit on the same row receives different scan signals but the same data, the constant voltage source has a high potential end and a low potential end, and each pixel circuit Including: .- .. ' . . . _ ' ' .... . . .,. _ An organic electroluminescent diode, the anode of which is coupled to the constant voltage source. — :- ' .. . .. V ; the high potential end; a first transistor, the first end of which is connected to the low potential end of the constant voltage source:: ; . . . . . - .. :. : V electrical connection, and its third And the organic electric ^ ^ ^ switch is electrically connected to the second end of the first transistor and receives one of the scanning signals of the ' ' - . . - \ - - ' ' - - and the like One of the materials, and received.:........ ' .. ... . 1:,.... : — .:.1 . Received scan signal control to determine No to transmit the data to the first - - - ' . - ' - - - : , ." _ -* - . _ ... . 200842783 The second end of the transistor; and ^ ^ ^ f _ f 4 It ^ f ^ t ^ # , and the other end receives the modulation signal to capture the capacitance value. ' 32. According to the scope of the patent application, the signal is large enough to make I-33 per pixel-based circuit. According to the third patent application, the capacitance of the circuit is _ is a source + earth The ballast system is made of:, and a metal-titanium semiconductor electrically connected to the poles, and the metal oxide is used to listen to the squeaking * as the two ends of the capacitor. And 34. ^^f @ ^ 33 ^ , A t , the circuit further includes a voltage across the electric valley of the two-pixel circuit of the second transistor at the 1 h end electrically connecting the capacitance of the pixel circuit. 35. According to the scope of the patent application, the complex enable signal is generated, and the same column is stupid to the middle of the sea. The shoulder is not spinning. ^ ^ ^ ^ ^ The column pixel circuit receives the same ^(four) '(four)-row Recording electricity is enough: [Pixel circuit also includes an electrical connection between the electrical connection of the said: and !: prime circuit | ^ ^ f ^ ί ^ ^ ^ # . ^ f ^ ^ ^ ^ ^ ^ ^ (4) Di Si " ΜThe circuit between the _u illuminating diodes of the pixel circuit is interrupted by its (4) 25 200842783. v ^', the organic circuit of Baolu invites 36. The switch of the circuit includes “second transistor and... ^1 ^ M ^ ^ ~ ^ ^ It t # > J. ^ ^ I ^θθ f 1 ^1 No., and the third end of the third transistor 收 收 收 为 为 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 入 峨 峨 峨 峨 峨 峨 峨 , , , , , , , , Bucket A ^ : % Di 钿 and the second end of the pixel circuit are electrically connected. r: force 37. ^ ^ t II # ^ HS f 36 ^ ^ ^ - ^ ; ^ . The crystal is NMOS, and the second 每一 of each transistor 38. ^€ t ^ ^ af 36 ^ ^ to the fourth The crystal is NMOS and the fifth electric 曰〆 ̄ 〜 ' ' ^ ^ ^ ^ ^ ^ ^ The standing solar day is PMOS, the second end of a transistor is the gate. 39. The display according to claim 31, wherein the cathode circuit further comprises a fourth electrical signal receiving a scan signal received by a switch of the previous column of pixel circuits to set a capacitance across the pixel circuit. Voltage. 4〇· Display diarrhea according to item 39 of the patent application scope. Further generating a complex enable multiple, and the same column of pixel circuits receive the same) to the V wave 'and the same row of pixel circuits receive different enable signals each of the reference circuits also includes money f the chapter circuit of the organic electric excitation light a first end of the fifth transistor is electrically connected to a third end of the first transistor of the pixel circuit, and the third end is electrically connected to a cathode of the organic electroluminescent diode of the pixel circuit, and The second end receives the enable signal, -.. - -.. - - · · · -.. - - . . . and when the fourth transistor is controlled to be turned on by the scan signal it receives The enable signal causes the fifth transistor of the pixel circuit to be non-conducting '--;:..... '. . - interrupting the first transistor of the pixel circuit and the organic electroluminescent light of the pixel circuit The path between the polar bodies. Weaving 2727