TWI358804B - Multichip package structure and the forming method - Google Patents
Multichip package structure and the forming method Download PDFInfo
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- TWI358804B TWI358804B TW096145579A TW96145579A TWI358804B TW I358804 B TWI358804 B TW I358804B TW 096145579 A TW096145579 A TW 096145579A TW 96145579 A TW96145579 A TW 96145579A TW I358804 B TWI358804 B TW I358804B
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- 238000000034 method Methods 0.000 title claims description 63
- 239000002184 metal Substances 0.000 claims description 70
- 229910052751 metal Inorganic materials 0.000 claims description 70
- 239000000758 substrate Substances 0.000 claims description 54
- 239000010410 layer Substances 0.000 claims description 52
- 239000013078 crystal Substances 0.000 claims description 41
- 239000002861 polymer material Substances 0.000 claims description 30
- 238000004806 packaging method and process Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000005538 encapsulation Methods 0.000 claims description 12
- 239000012790 adhesive layer Substances 0.000 claims description 11
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- 238000005520 cutting process Methods 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 239000010931 gold Substances 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 7
- 239000003822 epoxy resin Substances 0.000 claims description 5
- 229920000647 polyepoxide Polymers 0.000 claims description 5
- 238000007789 sealing Methods 0.000 claims description 4
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 claims description 2
- 239000008187 granular material Substances 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- QQVIHTHCMHWDBS-UHFFFAOYSA-N isophthalic acid Chemical compound OC(=O)C1=CC=CC(C(O)=O)=C1 QQVIHTHCMHWDBS-UHFFFAOYSA-N 0.000 claims 2
- 239000004642 Polyimide Substances 0.000 claims 1
- XBDQKXXYIPTUBI-UHFFFAOYSA-M Propionate Chemical compound CCC([O-])=O XBDQKXXYIPTUBI-UHFFFAOYSA-M 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 238000005336 cracking Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 claims 1
- 210000004508 polar body Anatomy 0.000 claims 1
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- 235000012431 wafers Nutrition 0.000 description 34
- 239000004065 semiconductor Substances 0.000 description 9
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- 238000004519 manufacturing process Methods 0.000 description 3
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- 238000012536 packaging technology Methods 0.000 description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 229920000800 acrylic rubber Polymers 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000012792 core layer Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
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- 238000005859 coupling reaction Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
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- 238000005530 etching Methods 0.000 description 1
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- 239000003292 glue Substances 0.000 description 1
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- 239000003550 marker Substances 0.000 description 1
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
1358804 >(ΰ 2〇11年7月躬日修正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體封裝方法，特別是將不同尺寸大小及 ： 功能之晶粒進行重新配置之封裝封方法。 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒 (Dice)必難有錄化的雜的絲，使得半導體晶粒必須要在很小的 區域中配置更多的輸入職墊(!/〇 pads)，因而使得金屬接腳㈣的 _ 密度也快速的提高了。因此，早期的導線架封裝技術已經不適合高密 度之金屬接腳；故發展出-種轉列_丨GridBGA)的封裝技 術’球陣列封裝除了有比導線架封裝更高密度之優點外，其錫球也比 較不容易損害與變形》 隨著3C產品的流行，例如：行動電話（Cdl ph〇ne)、個人數位助 理（PDA)或是iPod等’都必須要將許多複雜的系統晶片放入一個非 常小的空間巾，因此騎決此—問題，_麵為「晶圓級封裝㈣^ level package ’ WLP)」之封裝技術已經發展出來，其可以在切割晶目 φ 成為-顆職晶粒之前’就先對晶圓進行封裝。美國專利公告第 5,323,051號專利即揭露了這種「晶圓級封裝」技術。然而，這種「晶 圓級封裝」技術隨著晶粒主動面上的焊塾_s)數目的增加，使得焊墊 (pads)之間距過小’除了料觀號齡或訊鮮_問耕，也會因 為焊塾間距過小而造成封裝之可靠度降低等問題。因此，當晶粒再更 進-步的料後，使得祕的封裝技_無法滿足。 …為解決此一問題，美國專利公告第7，196,408號已揭露了一種將完 成半導體製程之晶18，經酬試及切贿，制試結果為良好的晶粒 61358804 > (ΰ 7 7 7 修正 修正 修正 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The method of encapsulation and sealing of pellets is reconfigured. [Prior Art] The technology of semiconductors has been developed quite rapidly, so miniaturized semiconductor crystal grains (Dice) must have difficult recording of miscellaneous filaments, so that semiconductor crystal grains must be The smaller input area is equipped with more input pads (!/〇pads), which makes the metal pin (4) _ density also increased rapidly. Therefore, the early lead frame packaging technology is not suitable for high-density metal pins. Therefore, the development of a kind of packaging _ 丨 GridBGA packaging technology 'ball array package in addition to the advantages of higher density than the lead frame package, its solder ball is also less susceptible to damage and deformation" With the popularity of 3C products, For example, mobile phones (Cdl ph〇ne), personal digital assistants (PDAs) or iPods, etc., must put many complex system chips into a very small space towel, so ride this Problems _ face as "wafer level packaging (iv) ^ level package 'WLP)" packaging technologies have been developed, it can be cut crystal mesh φ become - before the post grain pieces' on the first wafer encapsulation. This "wafer level packaging" technique is disclosed in U.S. Patent No. 5,323,051. However, this "wafer-level packaging" technology increases the number of pads between the pads as the number of pads _s increases on the active side of the die. There is also a problem that the reliability of the package is lowered because the pitch of the solder fillet is too small. Therefore, when the grain is further advanced, the secret packaging technique cannot be satisfied. In order to solve this problem, U.S. Patent No. 7,196,408 discloses a crystal 18 which will complete the semiconductor process, and will be tested and cut bribes.
S 2011年7月ί日修正替換頁 (good die)重新放置於另一個基板之上，然後再進行封裝製程如此， 使得這些被重新放置的晶粒間具有較寬關距，故可以紅粒上的焊 墊適當的分配，例如使用向外延伸（fanout)技術，因此可以有效解決 因間距過小，除了會導致訊號耦合或訊號干擾的問題。 然而，為使半導體晶片能夠有較小及較薄的封裝結構，在進行晶 圓切割前，會先對晶圓進行薄化處理，例如以背磨曰)曰 方式將晶®薄化至2〜2Gmn，然後再_成_綱的晶粒。此一經過薄 化處理之晶粒’經過重新配置在另-基板上，再以賴方式將複數個 晶粒形成-封裝體；由於晶粒㈣，使得難體也是非常的薄，故當 封裝體脫離基板讀，雖體本㈣應力會使得縣财缝曲，增 加後續進行切割製程的困難。 曰 另外，在晶圓切割之後，重新配置在另—個基板時，由於新的基 板的尺寸較原來的尺寸為大’因此在後龜球製程巾，會無法對準， 其封裝結構可靠度降低。為此，本發明提供—種在進行晶圓切割之前， 在晶圓背解銳(alig_t. ma峨相有效轉決植球時無 法對準以及封裝體產生翹曲的問題。 此外，在整個封裝的聰中，產生植料，製造設備會對晶 粒產生局部過大的壓力，而可能損傷晶粒的問題；同時，也可^因: 植球口的材料造成與晶粒上的焊賴之雜值變大，而影響晶粒之性能 專問韻。 【發明内容】 β有馨於發明背景巾所述之植球對準以及縣馳_醜，本發 明提供-種糊晶m對準標誌之晶粒重聽置之封裝結構及其方法， 來將複數個晶粒麵進行配置並進行雜之方法。故本發明之主要目 2011年7月25日修正替換頁 的在&供—種在割之前先軸對準麟，鎌藉由對準標諸進 行晶粒重新配置之封裝方法，使得在植球之製程中可以對準之夕^封 裝體本身可以克服應力而會使得封裝體在脫離基板後，保持平整，可 有效提高製造之良率及可靠度。 本發明之另一主要目的在提供一種在晶粒重新配置之封裝方法， 係將不同尺寸大小及魏之晶粒麵配置在-基板上之封裝方法。 此外，本發明還有-主要目的在提供一種晶粒重新配置之封裂方 法’其可以將12时晶圓所切割出來的晶粒重新配置於8(ί寸晶圓之基板 上’如此可以有效運用8心圓之即有之封裝設備，而無需重新設立 12吋晶圓之封裝設備，可以降低12吋晶圓之封裝成本。 本發明之再一主要目的在提供一種晶粒重新配置之封裝方法，使 付進行封裝的晶片都是，，已知是功能正常之晶片，，（Κη_ gQQd㈣， 可以節省封裝材料，故也可以降低製程之成本 本發明之再一主要目的在提供一種晶粒重新配置之封裝方法，使 知進行封裝的晶片都是，，已知是功能正常之晶片，，（Kn〇wn g〇〇d出幻， 可以節省封裝材料，故也可以降低製程之成本。 根據以上所述，本發明提供一種模組化之多晶粒封裝方法，包括: 提供複數個晶粒，每一晶粒具有一主動面且主動面上配置有複數個焊 墊，取放複數個晶粒至一基板上，每一晶粒係以覆晶方式將主動面與 一配置於基板上的黏著層連接；形成一高分子材料層在基板及部份晶 粒之一下表面上；脫離基板’以曝露出每一晶粒之主動面及每一焊墊， 以形成一封裝體；形成複數個圖案化之金屬線段，部份複數個圖案化 之金屬線段之兩端電性連接複數個晶粒之主動面上的複數個焊墊，部 份複數個圖案化之金屬線段之一端電性連接複數個晶粒之主動面上的 複數個焊墊；形成圖案化之保護層以覆蓋複數個圖案化之金屬線段， 1358804 2011年7月25日修正替換頁 並曝露部份複數_案化之金魏段之另1;形成複數個導電元 件，係將複數個導電元件電性連接在已曝露之每一圖案化之金屬線段 之另-端上；及切觸紐’以軸魏個_化之乡晶誠裝結構。 本發明揭露另-種發光二_重新配置之封裝方法，包括:提供複S July 2011 ί correction correction page (good die) is placed on another substrate, and then the packaging process is so that the repositioned grains have a wider separation distance, so it can be red Appropriate distribution of the pads, such as the use of fanout technology, can effectively solve the problem that the spacing is too small, in addition to signal coupling or signal interference. However, in order to enable the semiconductor wafer to have a smaller and thinner package structure, the wafer is thinned before wafer dicing, for example, by thinning the ruthenium to 2~ 2Gmn, then _ into _ class of grains. The thinned film 'is reconfigured on the other substrate, and then the plurality of crystal grains are formed into a package by a lamination method; since the crystal grains (four) make the hard body very thin, the package body Reading out of the substrate, although the body (4) stress will make the county financial rectification, increase the difficulty of subsequent cutting process.曰In addition, after the wafer is diced, when the other substrate is re-arranged, since the size of the new substrate is larger than the original size, the rear turtle ball processing towel will not be aligned, and the reliability of the package structure is lowered. . To this end, the present invention provides a problem in which the back of the wafer is sharpened before the wafer is cut (the alig_t. ma峨 phase is effectively transferred to the ball and the package is warped. In addition, throughout the package) In the Cong Cong, the plant material is produced, and the manufacturing equipment will exert excessive local pressure on the grain, which may damage the grain; at the same time, it may also be caused by: the material of the ball-grating port is caused by the welding on the die. The value of the grain becomes large, and the performance of the grain is affected by the rhyme. [Description of the Invention] The present invention provides a kind of paste crystal m alignment mark. The die-receiving package structure and method thereof are used to configure a plurality of die faces and perform a hybrid method. Therefore, the main purpose of the present invention is to correct the replacement page on July 25, 2011. Before the cutting, the axis is aligned with the lining, and by aligning the encapsulation method for performing grain reconfiguration, the package can be aligned in the process of the ball placement. The package itself can overcome the stress and cause the package to be detached. After the substrate, keep it flat, which can effectively improve the manufacturing Rate and reliability. Another main object of the present invention is to provide a packaging method for reconfiguring a die, which is a packaging method in which different sizes and dimensions of the die are disposed on a substrate. Further, the present invention has - mainly The purpose is to provide a chip reconfiguration sealing method which can reconfigure the die cut from the 12-hour wafer on the substrate of 8 (inch wafer) so that 8 circles can be effectively used. Packaging the device without the need to re-set up the 12-inch wafer packaging device can reduce the packaging cost of the 12-inch wafer. A further main object of the present invention is to provide a die-reconfigurable packaging method for the wafer to be packaged. Yes, it is known to be a functioning chip, (Κη_ gQQd(4), which can save packaging materials, so it can also reduce the cost of the process. Another main object of the present invention is to provide a package method for die reconfiguration, so that the package is known. The wafers are all known to be functional wafers. (Kn〇wn g〇〇d is fantastic, saving packaging materials, so it can also reduce the cost of the process. According to the above, the present invention provides a modular multi-die package method, including: providing a plurality of crystal grains, each die having an active surface and a plurality of pads disposed on the active surface, and taking a plurality of pads The die is connected to a substrate, and each die is connected to an adhesive layer disposed on the substrate in a flip chip manner; a polymer material layer is formed on the lower surface of the substrate and a part of the die; and the substrate is separated from the substrate 'exposing the active surface of each die and each pad to form a package; forming a plurality of patterned metal segments, and electrically connecting the plurality of crystals at a plurality of portions of the plurality of patterned metal segments a plurality of pads on the active surface of the particle, one end of the plurality of patterned metal segments electrically connected to the plurality of pads on the active faces of the plurality of crystal grains; forming a patterned protective layer to cover the plurality of patterns Metallized wire segment, 1358804 Revised replacement page on July 25, 2011 and exposed part of the plural _ case of the Golden Wei section; forming a plurality of conductive elements, electrically connecting a plurality of conductive elements to the exposed Each Another case of metal strip of the - end; and New Osculatory '_ axis of a town Wei Jing Cheng installation structure. The present invention discloses another method for packaging a light-emitting two-reconfiguration, including: providing a complex
數條光二極體，每-發光二極體具有—主動面且主動面上且有一 P 電極及- N電極；取放複數個料二極體至_基板上，每—發光二極 體係以覆晶方式將主動面與-gi置於基板上的黏著層連接；形成一高 分子材料躲基板及部份發光二極體之—下表面上；平坦化高分子材 料層’使高分子材料層充滿於複數個發光二_之間並包覆每一發光 二極體之-下表面；脫離模具裝置，轉露出每—發光二極體之主動 面以及每-電極以形成-封裝體；形成複數個騎化之金屬線段，複 數個圖鎌之金麟段之-齡職性連接每—發光二極體之主動面 上之每- P _及每-N電極，而另__端分別共接於__向外延伸之金 屬線段；形成-圖案化之保護層以覆蓋複數_案化之金屬線段，並 曝露出複數個圖案化之金屬線段之向外延伸之的兩端之部份表面；形 成複數個導電元件，係將複數個導電树電性連接在已曝露之向外延 伸之金屬線段之表面上；及切割封裝體，以形成複數賴組化之之發 光二極體封裝結構。 本發明揭露-辦光二極體重之難結構，包括:複數個發 光二極體’每-發光二極體具有—主動面且主動面上配置有—p電極 及N電極，封裝體，係環覆於每一發光二極體之五個面且曝露出 每-發光二極體之絲面及每—p電極及每—N電極；複數個圖案化 之金屬線段’係其-端分職性連接每—發光二極體之絲面上之每 - P電極及N電極，而另一端則分別共接於一向外延伸之金屬線段； -圖案化之紐層，肋覆蓋複數個@案化之金祕段，轉露出向 外延伸之金屬線段的部份表面；及複數個導電元件，係形成在已曝露 9a plurality of light diodes, each of the light-emitting diodes has an active surface and a P electrode and an -N electrode on the active surface; a plurality of material diodes are placed on the substrate, and each of the light-emitting diodes is covered The crystal method connects the active surface to the adhesive layer on which the -gi is placed on the substrate; forms a polymer material to hide the substrate and the lower surface of the partial light-emitting diode; and planarizes the polymer material layer to fill the polymer material layer Between the plurality of light-emitting diodes _ and covering the lower surface of each of the light-emitting diodes; separating from the mold device, revealing the active surface of each of the light-emitting diodes and each of the electrodes to form a package; forming a plurality of Riding the metal line segment, the multiple figures of the Jinlin section - the age-related connection is connected to each of the active faces of the light-emitting diodes - P _ and each -N electrode, and the other __ terminals are respectively connected to a metal line segment extending outwardly; forming a patterned protective layer to cover the plurality of metal segments and exposing portions of the outwardly extending portions of the plurality of patterned metal segments; forming a plurality of conductive elements electrically connecting a plurality of conductive trees A metal exposed on the surface of the outwardly extending segment of; and cutting the package to form a plurality of groups depends on the material of the light emitting diode package structure. The invention discloses a difficult structure of the light-emitting diode weight, comprising: a plurality of light-emitting diodes each of the light-emitting diodes has an active surface and the active surface is provided with a p-electrode and an N-electrode, and the package is covered with a ring. On each of the five sides of each of the light-emitting diodes and exposing the surface of each of the light-emitting diodes and each of the -p electrodes and each of the -N electrodes; the plurality of patterned metal segments are connected by their ends Each of the P-electrodes and the N-electrodes on the surface of the light-emitting diode, and the other end are respectively connected to an outwardly extending metal line segment; - a patterned layer of gold, the ribs covering a plurality of gold a secret segment that reveals a portion of the surface of the outwardly extending metal segment; and a plurality of conductive elements that are formed in the exposed 9
yC 2011年7月芬曰修正替換頁 之向外延伸之表面上，以形成電性連接。 本發明另揭種模組化之乡晶粒封裝結構，包括··複數個晶粒， 每一晶粒具有一主動面且主動面上配置體複數個焊墊；一封裝體，係 環覆於每一晶粒之五個面且曝露出每一晶粒之主動面及每一焊墊；複 數個圖案化之金屬線段，部份_化之金麟段之兩端f性連接複數 個晶粒之主動面上的複數個焊墊，而部份圖案化之金屬線段之一端電 性連接複數個晶粒之主動面上之複數個焊墊；一圖案化之保護層，係 覆蓋複數個圖案化之金屬線段並曝露部份圖案化之金屬線段之另一 端，形成複數個導電元件，係將複數個導電元件電性連接在已曝露之 每一圖案化之金屬線段之另一端上及一散熱裝置，係形成於封裝體之 一背面上。 有關本發明的特徵與實作，茲配合圖示作最佳實施例詳細說明如 下。（為使對本發明的目的、構造、特徵、及其功能有進一步的瞭解， 茲配合實施例詳細說明如下。） 【實施方式】 本發明在此所探討的方向為一種晶粒重新配置之封裝方法，將複數 個晶粒重新配置於另一基板上，然後進行封裝的方法。為了能徹底地 瞭解本發明，將在下列的描述中提出詳盡的步驟及其組成。顯然地， 本發明的施行並未限定晶片堆疊的方式之技藝者所熟習的特殊細節。 另一方面，眾所周知的晶片形成方式以及晶片薄化等後段製程之詳細 步驟並未描述於細節中，以避免造成本發明不必要之限制。然而，對 於本發明的較佳實施例，則會詳細描述如下，然而除了這些詳細描述 之外，本發明還可以廣泛地施行在其他的實施例中，且本發明的範圍 不受限定，其以之後的專利範圍為準。 在現代的半導體封裝製程中，均是將一個已經完成前段製程（Front 13.58804 2011年7月23·日修正替換頁yC July 2011 Fennish correction replacement page on the outwardly extending surface to form an electrical connection. The invention further discloses a modularized die package structure, comprising: a plurality of crystal grains, each die having an active surface and a plurality of pads on the active surface; a package body covered by a ring Each of the five sides of the die exposes the active face of each die and each pad; a plurality of patterned metal segments, and the ends of the _ _ _ jin lin segment are connected to a plurality of dies a plurality of pads on the active surface, and one of the partially patterned metal segments is electrically connected to a plurality of pads on the active faces of the plurality of crystal grains; and a patterned protective layer covers the plurality of patterns a metal line segment and exposing the other end of the partially patterned metal line segment to form a plurality of conductive elements electrically connecting the plurality of conductive elements to the other end of each of the patterned metal line segments and a heat sink , formed on the back side of one of the packages. The features and implementations of the present invention are described in detail with reference to the preferred embodiments. (In order to further understand the object, structure, features, and functions of the present invention, the following detailed description will be given in conjunction with the embodiments.) [Embodiment] The present invention is directed to a method of encapsulating a die re-arrangement. A method of reconfiguring a plurality of dies on another substrate and then performing a package. In order to thoroughly understand the present invention, detailed steps and compositions thereof will be set forth in the following description. Obviously, the practice of the present invention does not define the specific details familiar to those skilled in the art of wafer stacking. On the other hand, the detailed steps of the well-known wafer formation method and the subsequent process such as wafer thinning are not described in detail to avoid unnecessary limitation of the present invention. However, the preferred embodiments of the present invention will be described in detail below, but the present invention may be widely practiced in other embodiments and the scope of the present invention is not limited by the detailed description. The scope of the patents that follow will prevail. In the modern semiconductor packaging process, one will have completed the front-end process (Front 13.58804 July 23, 2011 revised replacement page
EndPr〇CeSS)之晶圓（wafer)先進行薄化處理（Thinningpr〇cess)，例 如將晶片的厚度研磨至2〜20 mil之間；然後’進行晶圓的切割（讓㈣ process)以形成一顆顆的晶粒110;然後，使用取放裝置（pickandplace) 將一顆顆的晶粒逐一放置於另一個基板100上，如第丨圖所示。很明 顯地，基板100上的晶粒間隔區域比晶粒11〇大，因此，可以使得這些 被重新放置的晶粒110間具有較寬的間距，故可以將晶粒11〇上的焊墊 適當的分配。此外，本實施例所使用的封裝方法，可以將12吋晶圓所 切割出來的晶粒110重新配置於8吋晶圓之基板上，如此可以有效運用 8吋晶圓之即有之封裝設備，而無需重新設立12吋晶圓之封裝設備， 可以降低12吋晶圓之封裝成本。然後要強調的是，本發明之實施例並 未限定使用8吋晶圓大小之基板，其只要能提供承載的功能者，例如： 玻璃、石英、陶瓷、電路板或金屬薄板（metal f〇il)等，均可作為本實 施例之基板100 ’因此基板1〇〇的形狀也未加以限制。 請參考第2圖，係表示一基板其背面具有對準標誌俯視圖。如第2 圖’係表示在晶圓基板的上表面上之背面的X_y方向上，設置有複數個 對準標誌(alignment mark)302。由先前陳述所知，當一晶圓(未在圖中表 示）’例如具有複數個微處理晶粒(microprocessor)之晶圓、具有複數個 δ己憶體晶粒之晶圓或是具有複數個記憶體控制晶粒之晶圓經過切割之 後形成複數個晶粒’再重新將這些晶粒逐一配置在新的基板1〇時，盆 中在新的基板上的晶粒因此’在新的基板上可以是複數個相同功能及 尺寸的晶粒’例如一記憶體模組；或是由不同功能及尺寸之晶粒所構 成之一晶粒模組’例如由微處理晶粒(microprocessor)、記憶體晶粒 (memory)或是記憶體控制晶粒(memory controller)所組成之晶粒模組。 由於新的基板1〇之間的晶粒間隔區域比重新配置的晶粒大，在後續封 裝製程的植球步驟(ball mount)會無法對準，而將導電元件(未在圖中表 示)準確的形成在晶粒的背面上所需的位置，而造成封裝結構的可靠度 11 1358804 2011年7月35日修正替換頁 降低。因此’在本發明的具體實施例中，形成對準標諸3〇2的方式可 以利用絲刻(ph〇to-etching)製程，其係在基板的背面且在方向上 形成複數個對準標諸302，且其形狀為十字之標諸。另外，形成對準標 誌302的方式還包括利用雷射標籤(lasermark)製程，以形成複數個對^ 標誌302在基板的背面上。 接著，第3 ®至第6 ®絲林發明所揭露之晶粒重新配置之實施 例之各步驟示意圖。首先’如第3圖所示，先提供一基板1〇，並在基 板10上配置有-黏著層2〇，此黏著層2〇為一具有彈性之黏著材料， 例如石夕橡膠(silicon rubber)、石夕樹脂(silic〇n概叫、彈性pu、多孔阳、 丙稀酸»(aCrylicrubber)或晶粒切割膠等。料，使用取放裝置(未在 圖中表示)將複數個好的晶粒310逐一放置並貼附至基板1〇上的黏著層 2〇 ’其令晶粒310係以覆晶(flip chip)方式將其主動面上的焊墊犯與 基板10上的黏著層20連接。此外，要強調的是，在此取放過程中， 取放裝置(未在圖中表示)會根據每—顆晶粒31G的背面上的 3〇2以及參考基板1〇上的複數個對準標誌(未在圖中表示)的位置後，準 確地將每-顆晶粒310與基板1()上的黏著層2〇連接。因此，每一顆 晶粒310之主動面上的焊塾312位置均為已知，故可解決後續進行金 屬線連接時的對準問題。 接下來’請繼續參考第3圖，當複數個好的晶粒3⑴已被準確地放 置並貼附至基板1G上_著層2G讀，接著，絲板⑴及部份晶粒 ^ 310上塗佈高分子材料層4〇，其中此高分子材料層4〇可以是石夕膠、 環氧樹脂、丙稀酸（aciylic)、及苯環丁烯（BCB)等材料；然後使 用-模具裝置500將高分子材料層4〇覆平，使得高分子材料層4〇形 成-平坦化的表面’並且使得高分子材料層4〇填滿於晶粒之間並 且每-顆晶粒310的五個面均由高分子材料層4〇所包覆。 然後’可以選擇性地對平坦化的高分子材料層4〇進行一供烤程The wafer of EndPr〇CeSS) is first thinned, for example, the thickness of the wafer is polished to between 2 and 20 mils; then the wafer is cut (to process) to form a wafer. The individual grains 110 are then placed on the other substrate 100 one by one using a pick and place device, as shown in the figure. Obviously, the area of the die on the substrate 100 is larger than that of the die 11 and, therefore, the width of the repositioned die 110 can be made wider, so that the pads on the die 11 can be properly Distribution. In addition, the packaging method used in the embodiment can reconfigure the die 110 cut by the 12-inch wafer on the substrate of the 8-inch wafer, so that the package device of the 8-inch wafer can be effectively used. Without the need to re-set up 12-inch wafer packaging equipment, the packaging cost of 12-inch wafers can be reduced. It is then emphasized that embodiments of the present invention do not limit the use of a substrate having a size of 8 Å, as long as it provides a load bearing function, such as: glass, quartz, ceramic, circuit board or metal sheet (metal f〇il The same can be used as the substrate 100 of the present embodiment. Therefore, the shape of the substrate 1 is not limited. Referring to Fig. 2, there is shown a plan view of an alignment mark on a back surface of a substrate. As shown in Fig. 2, a plurality of alignment marks 302 are provided in the X_y direction of the back surface on the upper surface of the wafer substrate. As known from the previous statements, when a wafer (not shown) is used, for example, a wafer having a plurality of microprocessors, a wafer having a plurality of δ-remembrance grains, or a plurality of The wafers of the memory-controlled dies are diced to form a plurality of dies. When the dies are re-arranged one by one on the new substrate, the grains on the new substrate in the basin are thus 'on a new substrate. It can be a plurality of dies of the same function and size, such as a memory module; or a die module composed of dies of different functions and sizes, for example, by a microprocessor, a memory A die or a memory module composed of a memory controller. Since the die spacing area between the new substrate 1〇 is larger than the reconfigured grain, the ball mount in the subsequent packaging process may not be aligned, and the conductive elements (not shown) are accurate. The formation of the desired position on the back side of the die, resulting in the reliability of the package structure 11 1358804 July 35, 2011 corrected replacement page reduced. Thus, in a particular embodiment of the invention, the manner in which the alignment marks 3〇2 are formed may utilize a ph〇to-etching process that is formed on the back side of the substrate and forms a plurality of alignment marks in the direction. 302, and its shape is the standard of the cross. Additionally, the manner in which the alignment mark 302 is formed further includes utilizing a laser mark process to form a plurality of pairs of marks 302 on the back side of the substrate. Next, a schematic diagram of the steps of the embodiment of the die reconfiguration disclosed in the 3® through 6th Silk inventions. First, as shown in FIG. 3, a substrate 1 is first provided, and an adhesive layer 2 is disposed on the substrate 10. The adhesive layer 2 is an elastic adhesive material, such as silicon rubber. , Shi Xi resin (silic〇n general, elastic pu, porous yang, acrylic acid) (aCrylicrubber) or grain cutting glue, etc., using a pick and place device (not shown in the figure) will be a plurality of good crystal The granules 310 are placed one by one and attached to the adhesive layer 2' on the substrate 1', which causes the die 310 to connect the pads on the active surface to the adhesive layer 20 on the substrate 10 in a flip chip manner. In addition, it should be emphasized that during this pick-and-place process, the pick-and-place device (not shown) will be based on 3〇2 on the back side of each die 31G and a plurality of pairs on the reference substrate 1〇. After the position of the quasi-marker (not shown in the figure), each of the crystal grains 310 is accurately connected to the adhesive layer 2 on the substrate 1 (). Therefore, the solder joint on the active surface of each of the crystal grains 310 The 312 positions are known, so it can solve the alignment problem when the metal wire connection is followed. Next, please continue to refer to Figure 3, when A number of good dies 3(1) have been accurately placed and attached to the substrate 1G, and the layer 2G is read. Then, the core layer (1) and a portion of the dies 310 are coated with a layer of polymer material 4, which is high. The molecular material layer 4〇 may be a material such as Shiqi gum, epoxy resin, aciylic, and benzocyclobutene (BCB); and then the polymer material layer 4 is covered with a mold device 500, so that The polymer material layer 4〇 forms a flattened surface' and causes the polymer material layer 4〇 to fill between the crystal grains and the five faces of each of the crystal grains 310 are covered by the polymer material layer 4〇 Then, 'the selective planarization of the polymer material layer 4 can be selectively performed.
S 12 13.58804 2011年7月4修正替換頁S 12 13.58804 July 4th revised replacement page
序，以使南分子材料層4〇固化。再接著，進行脫模程序，將模具裝置 500與固化後的高分子材料層4〇分離，以裸露出平坦化的高分子材料 層40的表面，如第4圖所示。接著，將高分子材料層40與黏著層20 分離，例如將高分子材料層40與基板1〇 —起放入去離子水的槽中， 使商分子材料層40餘著層20分離，形成一個封裝體；此封裝體包 覆每一顆晶粒310，並且只曝露出每一晶粒31〇之主動面上的焊墊 312。再接著，可以選擇性地使用切割刀（未顯示於圖中）在高分子材 料層40的表面上形成複數條切割道410，如第4圖所示；每-切割道 41〇的深度為0.5]密爾（mil)，而切割道之寬度則為5至25微米。 在-較佳實施财，此_道可以是相互垂直交錯，並且可以作 為實際切割晶粒時的參考線。由於在封裝體之相對於晶粒31〇之主動 面之背面形成魏數條_道，因此當高分子㈣層4()與基板ι〇 剝離後，封裝體上的應力會被這些切割道彻所形成的區域所抵消， 故可有效地解決封裝體翹曲的問題。 丧者’ K第5圖至第6圖’係表示在複數個晶粒3H)上形成複數 ^化之金麟段之俯湖。在本實施财，已先_體製程將Order to solidify the layer of the southern molecular material. Next, a mold release process is performed to separate the mold device 500 from the cured polymer material layer 4 to expose the surface of the planarized polymer material layer 40 as shown in Fig. 4. Next, the polymer material layer 40 is separated from the adhesive layer 20. For example, the polymer material layer 40 and the substrate 1 are placed together in a bath of deionized water, so that the layer of the molecular layer 40 is separated from the layer 20 to form a The package; the package covers each of the die 310 and exposes only the pads 312 on the active side of each die 31〇. Further, a plurality of dicing streets 410 may be selectively formed on the surface of the polymer material layer 40 using a dicing blade (not shown), as shown in FIG. 4; the depth of each scribe line 41 为 is 0.5. Mil, and the width of the scribe line is 5 to 25 microns. In the preferred embodiment, the _ tracks may be vertically interlaced and may serve as reference lines for actually cutting the dies. Since the Wei number strips are formed on the back surface of the package relative to the active surface of the die 31, when the polymer (4) layer 4 () is peeled off from the substrate, the stress on the package is cut by the cut lines. The formed region is offset, so that the problem of warpage of the package can be effectively solved. The mourners 'K 5th to 6th' show the formation of a complex number of Jinlin sections on a plurality of grains 3H). In this implementation, the first _ institutional process will
=裝=的複數個晶粒之主動面上的每一個焊墊M2都曝露出 术接著，即可在晶粒31〇的主動面的提執l 上、+ a 之金屬線段Μ)，每-條金屬線段5G向 麵案化 分別電性連接嫩每-晶粒上聯的方式 之金屬線叙步貌含··仏形^=’=魏侧案化 a- t 鱼屬層5〇A在母一晶粒3〗〇之 絲面之母-谭墊3ί2上，如第5圖所示 術’例如：_、_轉料，先戦-醉化光 =表桃_观之上；然彳_刻方絲雜約 之後，再剝除圓案化之光阻層；因此， 金屬層5〇Α 式來形成抛個職化之金顧段5G 據所$要的電性連接方 又50，而在本實施例t，每-圓案化 13 2011年7月25*曰修正替換頁 之金屬線段50之向外延伸之兩端係電性連接至相鄰之每一晶粒31〇上 之複數個焊㈣2 ’使得；_的每—晶粒31Q彼此細㈣的方式電性 連接；然而，此串聯的電性連接方式僅為本發明之—實施例，其目的 僅在揭路使用圖案化的金屬製程，可以將複數個晶粒依據所要的電性 連接方式完成連接。由上所述，可轉複數個晶粒3iQ以轉或並聯 方式形成-模組(module)，例如：DRAM她，如第6圖所示。此外， 金屬線段5G可以是由銅、金或銅合金等材料所形成，同時，金屬線段 也可以疋由UBM金屬層來形成，此ugM金屬層之材料可以是 Ti/Cu 或是 TiW/Cu。 在此要強調的疋，本發明在將複數個好的晶粒31〇重新配置在另一 基板ίο的過程中’由於每-晶粒⑽的背面上都有對準標誌、3〇2同時 可以進-步參考基板1Gjl的複數個解觀驗置後每—顆晶粒3ι〇 之主動面上的焊塾312位置均為已知，故可賴後續進行金屬線連接 時的對準問題。因此’在㈣高分子材料⑽形成封舰後，由於每一 晶粒3H)的5個面都被高分子材料層4〇所包覆，僅有晶粒31〇之主動 面上的焊墊312曝路出來，而此主動面上的焊塾312位置是可以碟定 的，故可以依據本發明所揭露之方式，將複數個相同或是不相同的好 的晶粒310封裝在-起，然後以半導體製程來形成_化的金屬線5〇 將所要組合成模組（module)的複數個晶粒31〇電性連接在一起。 例如.將4顆256M的DRAM晶粒以串連或並連的方式封裝在一起， 形成個s己憶谷里為ig之記憶模組;或是，將複數個發光二極體(le〇) 串接成-錄狀光源或是並連成—碌光源；或是，將抑功能、不 同大小之晶粒封錢-緣等’都可藉由本實關來達成。以下將會 進一步的說明。 此外，在上述實細t，形成平坦化的高分子材料層4〇的方式可 以選擇使用注模方式（moldingproeess)來形成。此時，將—模具裝置 500覆蓋至基板10上，並且使模具裝置5〇〇與晶粒3i〇間保持一空間， 因此可以將高分子材料層4〇 ’例如環氧樹脂模封材獅卿 Compound ; EMC)，注入模具裝置5〇〇與晶粒3i〇的空間中使得高分 子材料層40形成-平坦化的表面並且使得高分子材料層4〇充滿於晶 粒3K)之間並包覆每-晶粒31〇。由於，使用注模方式來包覆每一晶粒 310之後，其製造過程與前述方式蝴，故不再贊述之。 接著’請參考第7圖’係為上述第6圖之一俯視圖（即第6圖為 第7圖在AA剖面的示意圖）。第7圖係表示每—晶粒训之間係利用 金屬線段50以串聯的方式電性連接以形成—模組，其中可使用四個相 同尺寸大小及功能之晶粒31G (例如：DRAM)形成晶_組或是兩個 的粒形成-¼組。當然，也可以將兩兩並排之晶粒以串聯及並聯之方 式連接成-餘。然而’將複數個晶粒串聯及並聯連接在―起之方式， 即可經由前述第3圖至第6圖的過程中完成。 接著’請參考第8圖，係表示形成一 LED發光模組之示意圖。如 第8圖所示，晶粒320係為發光二極體(LED)，每一發光二極體32〇的 P電極322與相鄰的發光二極體32〇的p電極322電性連接；而發光二 極體320的N電極321係與相鄰的發光二極體32〇的n電極321紐 連接’且每-發光二極|| 320之N電極321及P電極322係藉由金屬 線段50分別與焊墊70電性連接。同樣地，本發明也不限定發光二極 體320之數董或是其電性連接之方式，例如：將複數個發光二極體 (LED) φ接成-個柱狀光源或是並連成—面狀光源；同時，本發明也 不限定發光二極體’之發光顏色，即發光二極體32〇可以是紅光發 光二極體或綠紐光二極體紐紐光二極駐其絲色之發光二極 體（例如：白光）或是前述發光二極體之組合等。另外，如第9圖所 示’係將刊功誠不同大小之晶粒封完成封裝之上視圖。很明顯地， 這些晶粒模組係由複數，晶粒所構成之系統級封裝 2011年7月25曰修正替換頁 (System-In-Package ; SIP)，這些晶粒至少包含微處理裝置 305(micr〇pr〇cessormeans)'記憶體裝置310(mem〇ry咖咖)或是記憶體 控制裝置315(mem〇rycontrollermeans);其中每一晶粒之主動面上具有 複數個焊墊，且在每一晶粒的焊墊上形成複數條金屬線段，以串聯或 是並聯的方式電性連接相鄰之晶粒並與導電元件電性連接。 在刖述將母一顆晶粒完成模組化的封裝及電性連接後，緊接著， 要進行對外連接树的配f如第贏_示，在完成模組化的電性 連接後’隨即在職體之具有金祕段的面上，職—酸化之保護 層60 (例如：_mide)以M複數個圖案化之金屬線段5〇，並在金 屬線段50之向外延伸之兩端之部份表面上形成開口 &，以便曝露出複 數個圖案化之金屬線段50的另一端。此形成圖案化之保護層6〇的步 驟包括观-賴層60在複數_案化之金屬線段5()上；利用半導 體製程’例如顯影，先形成一圖案化之光阻層(未在圖中表示)在保護層 60上，接者，在進仃顯影後，移除相對於複數個圖案化之金屬線段邓 之向外延伸之兩端上之倾層以形綱口 62，即可曝露出位於開口 62 下之複數個瞧化之金屬線段5G之向外延伸之兩端之部份表面。 ,_ ^ 伽圖所示’係在保護層60之複數個開口 62處〕 _元㈣，其_元件7Q可岐_餘_或是 之模组。娜丄 割封裝體，以形成複數個完成封』 此外，如第u圖所示，#顯亍=L圖疋相對第7圖之封裝形式 〇：線段。帛咖㈣社·及第他 在本===系統級封裝一a— 一、藉由薄化製程，使得被封裝體包覆 ^358804 夕曰私+步Λ 3 + , + μ 2011年7月泛日修正替換頁 曰叔“曝路出來後，再於已曝露之晶粒之背面上黏貼一散敎 :12Β圖所不。此外’要強調的是，這種點貼散熱片的實施方 ==在第7圖之實施例中，時，義散熱片的時間，可以選 =拽裝體物_之《是選擇在封裝_行切割之後，都為本發 月之貫知方式，本發明並未加以限制。 雖穌發明赠叙触實施_露如上，财並_以限定本 任何熟習相像技藝者’在不脫離本發明之精神和範圍内，當可= Each of the pads M2 on the active surface of the plurality of dies is exposed, and then on the active surface of the die 31 、, the metal segment of the + a), each - The metal wire segment 5G is surfaced and electrically connected to each other. The metal wire is connected in a manner that is in the form of a wire. The shape of the wire is in the form of a wire. The mother of a grain 3 〇 〇 丝 - - 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 谭 3 After engraving the square wire, the stripped photoresist layer is stripped off; therefore, the metal layer is formed into a 5G, which is based on the electrical connection. In the present embodiment t, each of the two ends of the metal line segment 50 of the correction replacement page of the July 25, 2011, is electrically connected to each adjacent die 31. A plurality of solders (4) 2' enable each of the dies 31Q to be electrically connected to each other in a thin (four) manner; however, the electrical connection of the series is only an embodiment of the present invention, and the purpose is only to use patterning in the road. Metal process, can A plurality of electrical connections in accordance with the desired grain complete the connection. From the above, a plurality of dies 3iQ can be formed to form a module in a rotating or parallel manner, for example, DRAM, as shown in Fig. 6. In addition, the metal line segment 5G may be formed of a material such as copper, gold or a copper alloy, and the metal line segment may also be formed of a UBM metal layer. The material of the ugM metal layer may be Ti/Cu or TiW/Cu. In the process to be emphasized here, the present invention reconfigures a plurality of good dies 31 在 in another substrate ίο's because of the alignment marks on the back side of each dies (10), and 3 〇 2 After the plurality of resolutions of the step-by-step reference substrate 1Gj1, the positions of the pads 312 on the active surface of each of the crystal grains 3 〇 are known, so that the alignment problem in the subsequent connection of the metal wires can be performed. Therefore, after the (four) polymer material (10) is formed into a ship, since the five faces of each of the crystal grains 3H) are covered by the polymer material layer 4, only the pad 312 on the active surface of the die 31 is formed. The exposure is performed, and the position of the pad 312 on the active surface is discizable, so that a plurality of good or different good die 310 can be packaged in the manner disclosed in the present invention, and then The semiconductor wires 5 are formed by a semiconductor process to electrically connect the plurality of crystal grains 31 which are to be combined into a module. For example, four 256M DRAM dies are packaged in series or in parallel to form a memory module that is ig in the memory valley; or, a plurality of light emitting diodes (le〇) It can be achieved by connecting this to a recorded light source or by connecting it into a light source; or by suppressing the function and the size of the grain of the different sizes. The following will be further explained. Further, in the above-described solid t, the formation of the planarized polymer material layer 4〇 can be selectively formed by using molding methods. At this time, the mold device 500 is covered on the substrate 10, and a space is maintained between the mold device 5 and the crystal grains 3i, so that the polymer material layer 4' can be, for example, an epoxy resin molding material. Compound; EMC), injecting into the space of the mold device 5〇〇 and the crystal grains 3i〇, the polymer material layer 40 forms a flattened surface and the polymer material layer 4〇 is filled between the crystal grains 3K) and coated Each crystal grain is 31 〇. Since the molding process is used to coat each of the crystal grains 310, the manufacturing process is the same as that described above, and therefore will not be described. Next, please refer to Fig. 7 for a top view of the above Fig. 6 (i.e., Fig. 6 is a schematic view of Fig. 7 in the AA cross section). Figure 7 shows that each of the die trains is electrically connected in series by a metal segment 50 to form a module in which four crystal grains 31G of the same size and function can be formed (for example, DRAM). The crystal group or the two particles form a group of -1⁄4. Of course, it is also possible to connect two or two side-by-side crystal grains in series and in parallel to form a balance. However, the manner in which a plurality of crystal grains are connected in series and in parallel can be completed through the processes of the aforementioned FIGS. 3 to 6. Next, please refer to Fig. 8, which is a schematic view showing the formation of an LED lighting module. As shown in FIG. 8 , the die 320 is a light emitting diode (LED), and the P electrode 322 of each of the LEDs 32 is electrically connected to the p electrode 322 of the adjacent LED 32 ;; The N electrode 321 of the LED 320 is connected to the n electrode 321 of the adjacent LED 32 ' and the N electrode 321 and the P electrode 322 of each of the LEDs are formed by metal segments. 50 is electrically connected to the bonding pad 70, respectively. Similarly, the present invention does not limit the number of LEDs 320 or the manner in which they are electrically connected. For example, a plurality of LEDs φ are connected to a column light source or connected in parallel. - a planar light source; at the same time, the invention does not limit the luminous color of the light-emitting diode, that is, the light-emitting diode 32 can be a red light-emitting diode or a green light-emitting diode. A light-emitting diode (for example, white light) or a combination of the foregoing light-emitting diodes. In addition, as shown in Fig. 9, the system will complete the package top view with different sizes of die seals. Obviously, these die modules are system-level packages consisting of a plurality of dies, July 25, 2011, System-In-Package (SIP), which include at least a microprocessor 305 ( Mic〇〇pr〇cessormeans) 'memory device 310 (mem〇ry coffee) or memory control device 315 (mem〇rycontrollermeans); each of the die has a plurality of pads on the active surface, and each A plurality of metal line segments are formed on the pads of the die, and the adjacent crystal grains are electrically connected in series or in parallel and electrically connected to the conductive elements. After describing the package and electrical connection of the mother die, the next step is to make the distribution of the external connection tree, such as the first win, after completing the modular electrical connection. On the surface of the body with the gold secret segment, the protective layer 60 of the acid-acidification layer (for example: _mide) is a plurality of patterned metal segments 5 〇, and is at the ends of the metal wire segment 50 extending outward. An opening & is formed on the surface to expose the other end of the plurality of patterned metal segments 50. The step of forming the patterned protective layer 6〇 includes the viewing-and-standing layer 60 on the plurality of metallized segments 5(); using a semiconductor process such as development, first forming a patterned photoresist layer (not shown) In the protective layer 60, the pick-up, after the development of the entrance, removes the inclined layer on the outwardly extending ends of the plurality of patterned metal segments Deng to form the opening 62, which can be exposed A portion of the surface of the outwardly extending ends of the plurality of deuterated metal segments 5G located below the opening 62. , _ ^ gamma is shown in the plurality of openings 62 of the protective layer 60 _ yuan (four), and its _ component 7Q can be _ _ remaining _ or a module. Na丄 cuts the package to form a plurality of completed seals. In addition, as shown in Fig. u, #显亍=L图疋 is compared with the package form of Fig. 7 〇: line segment.帛 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( The pan-day correction replaces the page. "Under the exposure, the paste is attached to the back of the exposed die. The 12-inch image is not. In addition, the emphasis is on the implementation of the heat sink. = In the embodiment of Fig. 7, the time of the heat sink can be selected as follows: "The choice is after the package_row cutting, which is the basic way of the month, the present invention Unrestricted. Although the invention of the invention is a smuggling of the above-mentioned stipulations, the confession of _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
^午之更祕_，耻本發明之專鄉_視本說明 之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖係表示先前技術之示意圖； 在具有對準標誌之基板之背 第2圖係根據本發明所揭露之技術 面之封裝結構之俯視圖；及^The secret of the afternoon _, shame the special home of the invention _ as defined in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a prior art; a back of a substrate having an alignment mark; FIG. 2 is a plan view of a package structure according to the technical surface of the present invention; and
第3圖至^關輯本發衡縣之技術，_晶断準標諸 之晶粒重娜4之職方法職之封躲構之各步驟示意圖； 第7圖係根據本發騎揭露之技術，係絲第6圖之俯視圖； 第8圖係根據本發明所揭露之技術，係表示在複數個發光二極體 上形成電性連接之示意圖； 第9 ®係根據本發騎«之技術，絲錢數個晶粒上形成電 性連接之示意圖； 第ΟΑ圖係根據本發明所揭露之技術，係表示在複數個金屬線段 上形成保護層之示意圖； 17 第⑽圖係根據本發明所揭露之技術，係表月^^替換^ 複數個導電元叙㈣_; ««結構上形成 ^圖係根據本發明所揭露之技術’係表示第8圖沿BB線段之 〇_J式圖及第9圖沿CC線段之剖式圖；及 第12A _根據本發明所揭露之技術，表示具有散熱裝置 結構之示意圖；及 ^ -第12B圖係根據本發日月所揭露之技術，表示經薄化之封裝結構之 示意圖。 【主要元件符號說明】 10基板 20黏著層 100 基板 110 晶粒 302對準標誌 305 微處理裝置 310晶粒/記憶體裝置 312焊墊 315 記憶體控制裝置 320 發光二極體 40高分子材料層 13.58804 2011年7月2T日修正替換頁 410切割道 50金屬線段 60保護層 70導電元件 500模具裝置Figure 3 to ^ Guan Ji This is the technology of the county, _ 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶 晶Figure 8 is a plan view of the wire; Figure 8 is a schematic view showing the formation of electrical connections on a plurality of light-emitting diodes according to the technology disclosed in the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 10 is a schematic view showing the formation of a protective layer on a plurality of metal line segments according to the technology disclosed in the present invention; 17 (10) is a diagram according to the present invention. The technology is a monthly replacement ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ FIG. 12A is a schematic view showing the structure of a heat sink according to the technology disclosed in the present invention; and FIG. 12B is a thinning according to the technique disclosed in the present disclosure. Schematic diagram of the package structure. [Main component symbol description] 10 substrate 20 adhesive layer 100 substrate 110 die 302 alignment mark 305 micro processing device 310 die / memory device 312 pad 315 memory control device 320 light emitting diode 40 polymer material layer 13.58804 July 2, 2011 correction replacement page 410 cutting channel 50 metal wire segment 60 protective layer 70 conductive component 500 mold device
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|---|---|---|---|
| TW096145579A TWI358804B (en) | 2007-11-30 | 2007-11-30 | Multichip package structure and the forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW096145579A TWI358804B (en) | 2007-11-30 | 2007-11-30 | Multichip package structure and the forming method |
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| Publication Number | Publication Date |
|---|---|
| TW200924133A TW200924133A (en) | 2009-06-01 |
| TWI358804B true TWI358804B (en) | 2012-02-21 |
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| Application Number | Title | Priority Date | Filing Date |
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| TW096145579A TWI358804B (en) | 2007-11-30 | 2007-11-30 | Multichip package structure and the forming method |
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| Country | Link |
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| TW (1) | TWI358804B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI695465B (en) * | 2017-11-08 | 2020-06-01 | 南韓商三星電子股份有限公司 | Fan-out semiconductor package |
| TWI706522B (en) * | 2017-12-14 | 2020-10-01 | 南韓商三星電子股份有限公司 | Fan-out semiconductor package |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI456143B (en) * | 2012-04-26 | 2014-10-11 | 新世紀光電股份有限公司 | Light emitting module |
| TWI672832B (en) * | 2018-10-23 | 2019-09-21 | 聯嘉光電股份有限公司 | Wafer level light emitting diode packaging method and structure thereof |
-
2007
- 2007-11-30 TW TW096145579A patent/TWI358804B/en active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI695465B (en) * | 2017-11-08 | 2020-06-01 | 南韓商三星電子股份有限公司 | Fan-out semiconductor package |
| TWI706522B (en) * | 2017-12-14 | 2020-10-01 | 南韓商三星電子股份有限公司 | Fan-out semiconductor package |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200924133A (en) | 2009-06-01 |
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