TWI356588B - Logic circuits using carbon nanotube transistors - Google Patents
Logic circuits using carbon nanotube transistors Download PDFInfo
- Publication number
- TWI356588B TWI356588B TW096140552A TW96140552A TWI356588B TW I356588 B TWI356588 B TW I356588B TW 096140552 A TW096140552 A TW 096140552A TW 96140552 A TW96140552 A TW 96140552A TW I356588 B TWI356588 B TW I356588B
- Authority
- TW
- Taiwan
- Prior art keywords
- cntfet
- cntfets
- reference point
- electrons
- biased
- Prior art date
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims description 9
- 239000002041 carbon nanotube Substances 0.000 title claims description 9
- 229910021393 carbon nanotube Inorganic materials 0.000 title claims description 9
- 239000000463 material Substances 0.000 claims description 8
- 239000002071 nanotube Substances 0.000 claims description 7
- 230000005669 field effect Effects 0.000 claims description 3
- 239000002772 conduction electron Substances 0.000 claims 1
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 230000004888 barrier function Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 230000009191 jumping Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- KZNMRPQBBZBTSW-UHFFFAOYSA-N [Au]=O Chemical compound [Au]=O KZNMRPQBBZBTSW-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000000747 cardiac effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
- H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/464—Lateral top-gate IGFETs comprising only a single gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K85/00—Organic materials used in the body or electrodes of devices covered by this subclass
- H10K85/20—Carbon compounds, e.g. carbon nanotubes or fullerenes
- H10K85/221—Carbon nanotubes
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
- Y10S977/742—Carbon nanotubes, CNTs
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/936—Specified use of nanostructure for electronic or optoelectronic application in a transistor or 3-terminal device
- Y10S977/938—Field effect transistors, FETS, with nanowire- or nanotube-channel region
Description
1356588 第2C圖是一顯示根據某些實施例之一蕭基特屏障 CNTFET的傳導特性之圖形。 第3圖是一顯示根據某些實施例,具有平能帶vgs位移 之一中間間隙蕭基特屏障CNTFET的傳導特性之圖形。
5 第4圖是一使用根據某些實施例之蕭基特屏障CNTFET 的一反相器之示意圖。 第5圖是一使用根據某些實施例之蕭基特屏障CNTFET 的一NAND閘體之示意圖。
第6圖是一使用根據某些實施例之蕭基特屏障CNTFET 1〇 的一 NOR閘體之示意圖。 第7圖是一顯示根據某些實施例,組配來傳導較電子更 強之電洞的一蕭基特屏障CNTFET之傳導特性的圖形。 第8圖是一具有根據某些實施例’有利於電洞傳導之源 極與汲極的一能帶邊緣蕭基特屏障CNTFET之能帶圖。 15 第9圖是一具有一微處理器之一電腦系統之方塊圖,該 微處理器具有使用根據某些實施例之CNTFET設備的一或 更多邏輯電路。 【實施方式】 較佳實施例之詳細說明 20 一 CNTFET(碳奈米管場效電晶體)類似一石夕 MOSFET(金氧半導體場效電晶體)’但CNTFET以一或更多 碳奈米管替代該石夕通道°因為CNT對電洞與電子兩者具有 相當高的傳導移動性,所以除其他電路之外,其適合傳統 使用CMOS電路來實行之互補邏輯電路。 6 1356588 第2C圖顯示具有直徑0.6、1_0、以及1.5 nm之示範奈米 管的ID/VGS曲線。如該等曲線所示’其閘極_源極電壓位於 —”平坦能帶,,準位(此範例中該曲線約VDD/2)時,一通道傳 導最小電流。若VGS超過該準位,則電子傳導,而vGS增加 5時該電子流增加。另一方面,若VGS低於此最小電流準位, 則電洞傳導而非電子,而vGS降低時該電洞流增加。電洞與 電子流彼此互相平衡時,會達成一最小電流點。
如該等曲線所示,通遒電流會受該製造之奈米管的直 挺影響。該直徑增加時,針對一給定的汲極/源極電壓,最 10小與最大通道電流ID間之差異減少。大部分數位應用中, 期望導通與截止電流間之/足夠的差異,所以可尋找一小 的CNT直徑。另一方面,若該直徑太小,則該電晶體之該” 導通”或充電電流降低,這是不希望見到的。例如,可具有 低的”载止”電流以及一良好的導通·截止電流比,但針對所 15 欲之數位應用可不具有一足夠高的,,導通,,電流。因此,可 尋找介於該等競爭因素之一適當的折衷辦法。某些實施例 中’具有一直徑0.5與2.〇 nm間之一CNT適合實行於數位電 路中。下述之一範例中,使用約1 nm之一直徑。 第3圖顯示一針對一雙極性SB CNT之ID/VGS曲線,其平 坦此帶之電壓已位移,造成其ID/VGS曲線沿該VGS軸位移使 知'其最小電流傳導出現在VGS=0。某些實施例中,此可藉由 知用—負偏壓至該CNT電晶體之該低電壓供應側來達成。 由於—平垣能帶VGS為〇,該CNT最好用來作為具有一低輸 入電壓0V以及一高輸入電壓vDD(或約電路操作中之最大電 9 1356588 強超過電子流。
此可以若干方式來達成。如弟8圖所繪示,其可藉由改 變§亥源極/及極材料之s玄工作功能以及之後該蕭基特屏障 來達成。例如,可使用Pd(lG)利於電洞傳導。另一方式是實 5行不同尺寸的電晶體(於每一電晶體之通道中使用不同數 量的碳奈米管)。例如’第4圖之該電路中,cfEti可具有較 CFET2多的奈米管數量而之後較CFET2強。然而,應體認 於一單一通道中封裝多個奈米管時,每單位寬度之奈米管 數量與每個奈米管之電容(與電流)間存有一折衷方案。 第5圖顯示包含根據某些實施例本文討論之cntfET的 一示範NAND閘體。如圖所示,其包含於一高電壓供應參 考點(VDD)與一主動負載電晶體CFET3之間並列輕合一起的 驅動器CNTFET(CNTFET1、CNTFET2),該CFET3搞合至一 低電壓供應參考點Vss。如圖所示,該等驅動電晶體 15 (CNTFET1、CNTFET2)之該等閘極個別提供第一與第二 NAND閘體輸入(Vin A、Vin B),而一閘體輸出設置於CFET3 之該汲極。若每一輸入為低準位(例如,0V),則該輸出為 高準位(接近VDD)。相反地,若兩輸入為高準位(接近VDD), 則該輸出為低準位。 20 第6圖顯示包含根據某些實施例本文討論之CNTFET的 —示範NOR閘體。如圖所示,其包含於一高電壓供應參考 點(Vdd)與一主動負載電晶體CFET3之間串聯耦合一起的驅 動器 CNTFET(CNTFET1、CNTFET2),該CFET3耦合至一低 電壓供應參考點Vss。如圖所示,該等驅動電晶體 11 1356588 (CNTFETl ' CNTFET2)之該等閘極個別提供第一與第二 NOR閘體輸入(Vin a、VinB),而一閘體輸出設置於CFET3 之該汲極。若兩輸入為低準位(例如,0V),則該輸出為高 準位(接近VDD)。相反地,若每一輸入或兩輸入為高準位(接 5 近Vdd),則該輸出為低準位。
諸如閘體、記憶體設備、計時邏輯、等等之其他類型 的數位設備可使用如本文所述之CNTFET來實行。例如,業 界熟於此技者將體認反相器、NOR以及NAND閘體可以是 針對許多更複雜電路之類型的建構方塊。於併合電路之分 10 開電路方塊或組合電路方塊中,沿著該等線段,某些積體 電路可包含MOSFET與CNTFET兩者。例如,目前許多 CMOS應用中,因為P型設備之傳導較其NMOS元件慢(較慢 的移動性),所以其限制電路之效能表現。因此,例如,電 路可使用CNTFET組配來傳導電洞以作為p型設備,而 15 NMOS設備(於矽中或諸如III-V族或II-VI族材料之其他複 合半導體中)可用於N型電晶體》 參照第9圖,其顯示一電腦系統之一範例。該所示系統 一般包含耦合至一電源供應器904、一無線介面9〇6、以及 記憶體908之一處理器902。其耦合至該電源供應器9〇4以便 20 操作時從其接收電源。該無線介面906耦合至一天線91〇而 以通訊方式將該處理器經過該無線介面晶片9〇6鏈接至一 無線網路(未顯示)。微處理器902包含使用如本文揭示之 CNTFET反相器的一或更多邏輯電路903。 應注意該繪示系統可以不同形式來加以實行。亦即, 12 1356588 其可於-單一晶片模組、一電路板或具有多個電路板之 -底盤中實行。同樣地,其可組成_或更多完整的電腦, 或者,其可組成於一計算系統中有用的一構件。 本發明並不侷限於所示之該等實施例中,但於該等後 5附申凊專利範圍之精神與範嘴令進行修改與變動時亦可加 以實作。例#,應體認纟發明可應用於所有類型之半導體 積體電路(“IC”)晶片中。該等1C晶片之範例包括但不偏限於 處理器、控制器、晶片組構件、可程式化邏輯陣列(PLA)、 記憶體晶片、網路晶片、等等。 10 再者’應體認雖然已給定示範的尺寸/模型/數值/範 圍’但本發明並不侷限於該等相同的條件。當製造技術⑼ 如,光刻術)已成熟-段時間後,可期待製造較小尺寸之設 備。此外,為了簡化舉例圖式與說明,連接至心曰曰片與其 他構件之著名電源/接地可顯示或可不顯示於圖形中,以避 】5免混淆本發明。再者,電路安排可以方塊圖形式來顯示以 避免混淆本發明,並且有鑑於關於該類方塊圖安排之實施 態樣的特性會高度根據本發明欲實行中之平台的事實,亦 即,該類特性應於業界之熟於此技者所知的範圍中。其中 本文提出特定細節(例如,電路)來說明本發明之示範實施 20例,很明顯地對業界之熟於此技者而言,在不具有、或具 有該等特定細節的情況下本發明可加以實作。因此,該說 明視為舉例解說而扑限制。 【闽式簡單説明3 第1圖是一顯示根據某些實施例之一CNTFET的橫截面 13
Claims (1)
- 第96140552號申請案申請專莉—— 十、申請專利範圍: 1· 一種積體電路,其包含: 串聯耦合於高與低準位供應器參考點間之第一及 第一$厌奈米管場效電晶體(CNTFET),該第—CNTFET 具有一閘極來提供用以接收高與低邏輯值之一邏輯輸 入’該第二CNTFET具有耗合至一偏壓供應器之一閘 極’使得該第二CNTFET為該第一CNTFET提供一主動 負載以提供適當的邏輯高與低輸出準位。 2. 如申請專利範圍第1項之積體電路,其中該低準位供應 器參考點之準位低於一邏輯低準位。 3. 如申請專利範圍第2項之積體電路,其中該等第一與第 二CNTFET組成一反相器閘體。 4. 如申請專利範圍第3項之積體電路,其中該等第一與第 二CNTFET傳導電洞之能力較電子強。 5·如申請專利範圍第4項之積體電路,其中該第一CNTFET 受偏壓來傳導電洞,而該第二CNTFET受偏壓來傳導電 子,其中該第一 CNTFET於傳導電洞方面較該第二 CNTFET於傳導電子方面為強。 6. 如申請專利範圍第5項之積體電路,其中該等第一與第 二CNTFET包含汲極與源極,此等電極以具有接近一價 能帶的程度比接近一傳導能帶的程度更高之一費米能 量準位的一材料來形成。 7. 如申請專利範圍第5項之積體電路,其中該等第一與 第一 CNTFET具有包含一或更多碳奈米管之通道,該 "申請案下^鼻利範gfgy- Too; 03.14. 第一 CNTFET通道具有較該第二CNTFET通道多之碳 奈米管,使得該第一CNTFET之傳導較該第二CNTFET 強。 8. 如申請專利範圍第1項之積體電路,其中該等第一與第 二CNTFET具有以本質碳奈米管形成之通道。 9. 一種反相器電路,其包含: 一耦合於一第一供應器參考點與該反相器電路之 一輸出節點間的第一 CNTFET ;以及 一耦合於該輸出節點與一第二供應器參考點間的 第二CNTFET,該第一CNTFET用於為該反相器電路提 供一輸入端,該第二CNTFET受偏壓來為該第一 CNTFET提供一主動負載。 10. 如申請專利範圍第9項之反相器電路,其中在電壓值方 面該第一供應器參考點大於該第二供應器參考點。 11·如申請專利範圍第10項之反相器電路,其中該等第—與 第二CNTFET傳導電洞之能力較電子強。 12. 如申請專利範圍第丨丨項之反相器電路,其中該第— CNTFET受偏壓來傳導電洞,而該第二CNTFET受偏 壓來傳導電子,其中該第一 CNTFET於傳導電洞方面 較該第二CNTFET於傳導電子方面為強。 13. 如申請專利範圍第12項之反相器電路,其中該等第—與 第二CNTFET包含汲極與源極,此等電極以具有接近— 價能帶的程度比接近一傳導能帶的程度更高之一費米 能量準位的一材料來形成。 17 1356588 第96140552號申請案申請專利嚴CTggT"仂〇7的了14. 14.如申請專利範圍第13項之反相器電路,其中該等第一與 第二CNTFET具有包含一或更多碳奈米管之通道,該第 一 CNTFET通道具有較該第二CNTFET通道多之碳奈米 管,使得該第一CNTFET之傳導較該第二CNTFET強。 5 15.如申請專利範圍第9項之反相器電路,其中該等第一與 第二CNTFET具有以本質碳奈米管形成之通道。 16. —種電腦系統,其包含: a) —具有一或更多反相器電路之處理器,該等反相 ί 器包含.一搞合於一第一供應器參考點與該反相器電路 10 之一輸出節點間的第一CNTFET、以及一耦合於該輸出 節點與一第二供應器參考點間的第二CNTFET,該第一 CNTFET用於為該反相器電路提供—輸入端,該第二 CNTFET受偏壓來為該第一 CNTFET提供一主動負載; b) —記憶體晶片,其耦合至該處理器以提供其額外 15 的隨機存取記憶體;以及 c) 一天線,其耦合至該處理器而以通訊方式將其與 B —無線網路鏈接。 17. 如申請專利範圍第μ項之電腦系統,其中在電壓值方面 該第一供應器參考點大於該第二供應器參考點。 20 I8·如申請專利範圍第Π項之電腦系統,其中該等第一與第 二CNTFET傳導電洞之能力較電子強。 19.如申請專利範圍第18項之電腦系統,其中該第一 CNTFET觉偏壓來傳導電洞,而該第二cntfet受偏壓 來傳導電子,其巾該第-CNTFET於料電洞方面較該 18 1356588 第96140552號申請案申請專利範圍替換頁 100. 03.14. 第二CNTFET於傳導電子方面為強。 20.如申請專利範圍第19項之電腦系統,其中該等第一與第 二CNTFET包含汲極與源極,此等電極以具有接近一價 能帶的程度比接近一傳導能帶的程度更高之一費米能 5 量準位的一材料來形成。19
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/613,134 US8004043B2 (en) | 2006-12-19 | 2006-12-19 | Logic circuits using carbon nanotube transistors |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200832912A TW200832912A (en) | 2008-08-01 |
TWI356588B true TWI356588B (en) | 2012-01-11 |
Family
ID=39526377
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096140552A TWI356588B (en) | 2006-12-19 | 2007-10-29 | Logic circuits using carbon nanotube transistors |
Country Status (6)
Country | Link |
---|---|
US (2) | US8004043B2 (zh) |
JP (1) | JP5373624B2 (zh) |
KR (1) | KR20090091777A (zh) |
DE (1) | DE112007003087T5 (zh) |
TW (1) | TWI356588B (zh) |
WO (1) | WO2008076529A1 (zh) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8004043B2 (en) | 2006-12-19 | 2011-08-23 | Intel Corporation | Logic circuits using carbon nanotube transistors |
US7858918B2 (en) * | 2007-02-05 | 2010-12-28 | Ludwig Lester F | Molecular transistor circuits compatible with carbon nanotube sensors and transducers |
KR101432037B1 (ko) * | 2008-04-25 | 2014-08-20 | 삼성전자주식회사 | 앰비폴라 특성을 가진 탄소나노튜브 트랜지스터를 구비한전환가능한 논리회로 |
KR20100094192A (ko) * | 2009-02-18 | 2010-08-26 | 삼성전자주식회사 | 탄소나노튜브 박막을 이용한 에스램 |
KR102084288B1 (ko) | 2012-11-05 | 2020-03-03 | 유니버시티 오브 플로리다 리서치 파운데이션, 아이엔씨. | 디스플레이의 휘도 보상 |
US9601707B2 (en) | 2012-11-30 | 2017-03-21 | University Of Florida Research Foundation, Inc. | Ambipolar vertical field effect transistor |
CN104103696B (zh) * | 2013-04-15 | 2018-02-27 | 清华大学 | 双极性薄膜晶体管 |
JP2015213994A (ja) * | 2014-05-12 | 2015-12-03 | 国立大学法人東北大学 | ナノメカニカル・スイッチを利用したデジタル回路 |
US11782057B2 (en) | 2014-12-18 | 2023-10-10 | Cardea Bio, Inc. | Ic with graphene fet sensor array patterned in layers above circuitry formed in a silicon based cmos wafer |
US11921112B2 (en) | 2014-12-18 | 2024-03-05 | Paragraf Usa Inc. | Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same |
US10006910B2 (en) | 2014-12-18 | 2018-06-26 | Agilome, Inc. | Chemically-sensitive field effect transistors, systems, and methods for manufacturing and using the same |
US9618474B2 (en) | 2014-12-18 | 2017-04-11 | Edico Genome, Inc. | Graphene FET devices, systems, and methods of using the same for sequencing nucleic acids |
US10594319B2 (en) * | 2016-06-03 | 2020-03-17 | Northwestern University | System and method for complimentary VT-drop ambipolar carbon nanotube logic |
US10665799B2 (en) | 2016-07-14 | 2020-05-26 | International Business Machines Corporation | N-type end-bonded metal contacts for carbon nanotube transistors |
US10665798B2 (en) * | 2016-07-14 | 2020-05-26 | International Business Machines Corporation | Carbon nanotube transistor and logic with end-bonded metal contacts |
US10170702B2 (en) | 2017-01-12 | 2019-01-01 | International Business Machines Corporation | Intermetallic contact for carbon nanotube FETs |
US11309846B2 (en) | 2017-08-25 | 2022-04-19 | University Of South Florida | Cascode common source transimpedance amplifiers for analyte monitoring systems |
KR102124110B1 (ko) * | 2019-10-08 | 2020-06-17 | 서경대학교 산학협력단 | 탄소나노튜브 트랜지스터로 구성된 버퍼를 갖는 제어구동장치 및 이를 이용하는 디스플레이 장치 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5308782A (en) * | 1992-03-02 | 1994-05-03 | Motorola | Semiconductor memory device and method of formation |
US5286674A (en) | 1992-03-02 | 1994-02-15 | Motorola, Inc. | Method for forming a via structure and semiconductor device having the same |
JPH08148537A (ja) | 1994-11-18 | 1996-06-07 | Toshiba Corp | 半導体集積回路 |
JPH0982978A (ja) * | 1995-09-20 | 1997-03-28 | Hitachi Ltd | 半導体装置及びこれを用いた液晶表示装置 |
TWI277290B (en) * | 2002-01-17 | 2007-03-21 | Semiconductor Energy Lab | Electric circuit |
US7358121B2 (en) | 2002-08-23 | 2008-04-15 | Intel Corporation | Tri-gate devices and methods of fabrication |
JP4774665B2 (ja) * | 2003-02-05 | 2011-09-14 | ソニー株式会社 | 半導体装置の製造方法 |
WO2005001899A2 (en) | 2003-06-09 | 2005-01-06 | Nantero, Inc. | Non-volatile electromechanical field effect devices and circuits using same and methods of forming same |
US7130234B2 (en) | 2003-12-12 | 2006-10-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
EP1544842B1 (en) * | 2003-12-18 | 2018-08-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
US7345296B2 (en) * | 2004-09-16 | 2008-03-18 | Atomate Corporation | Nanotube transistor and rectifying devices |
US8362525B2 (en) * | 2005-01-14 | 2013-01-29 | Nantero Inc. | Field effect device having a channel of nanofabric and methods of making same |
WO2006098501A1 (ja) * | 2005-03-17 | 2006-09-21 | The University Of Tokushima | 半導体装置及び電子装置 |
US7492015B2 (en) * | 2005-11-10 | 2009-02-17 | International Business Machines Corporation | Complementary carbon nanotube triple gate technology |
US8004043B2 (en) | 2006-12-19 | 2011-08-23 | Intel Corporation | Logic circuits using carbon nanotube transistors |
-
2006
- 2006-12-19 US US11/613,134 patent/US8004043B2/en not_active Expired - Fee Related
-
2007
- 2007-10-29 TW TW096140552A patent/TWI356588B/zh not_active IP Right Cessation
- 2007-10-30 WO PCT/US2007/082965 patent/WO2008076529A1/en active Application Filing
- 2007-10-30 KR KR1020097012726A patent/KR20090091777A/ko active Search and Examination
- 2007-10-30 JP JP2009542989A patent/JP5373624B2/ja not_active Expired - Fee Related
- 2007-10-30 DE DE112007003087T patent/DE112007003087T5/de not_active Ceased
-
2011
- 2011-08-23 US US13/216,120 patent/US8513741B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
KR20090091777A (ko) | 2009-08-28 |
JP2010514219A (ja) | 2010-04-30 |
JP5373624B2 (ja) | 2013-12-18 |
US20080143389A1 (en) | 2008-06-19 |
US20120049890A1 (en) | 2012-03-01 |
DE112007003087T5 (de) | 2009-10-15 |
US8513741B2 (en) | 2013-08-20 |
US8004043B2 (en) | 2011-08-23 |
WO2008076529A1 (en) | 2008-06-26 |
TW200832912A (en) | 2008-08-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI356588B (en) | Logic circuits using carbon nanotube transistors | |
Trommer et al. | Elementary aspects for circuit implementation of reconfigurable nanowire transistors | |
JP5767323B2 (ja) | 高電圧端子のための伝送ゲート回路およびその作動方法 | |
TWI493659B (zh) | 匹配裝置中之奈米線電路 | |
CN104134978B (zh) | 具有高的有效维持电压的静电放电(esd)钳位电路 | |
US9184586B2 (en) | SiGe based gate driven PMOS trigger circuit | |
US20180287600A1 (en) | Output circuit | |
JP5699666B2 (ja) | 半導体装置 | |
Narendar et al. | Design of high-performance digital logic circuits based on FinFET technology | |
Buddharaju et al. | Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach | |
US20140080255A1 (en) | Ultra-low power swnt interconnects for sub-threshold circuits | |
US8729883B2 (en) | Current source with low power consumption and reduced on-chip area occupancy | |
US9181089B2 (en) | Carbon nanotube crossbar based nano-architecture | |
JP5299752B2 (ja) | 半導体装置 | |
US8638122B2 (en) | Apparatus for metastability-hardened storage circuits and associated methods | |
Moon et al. | Silicon nanowire CMOS NOR logic gates featuring one-volt operation on bendable substrates | |
US20170133923A1 (en) | Reducing thermal runaway in inverter devices | |
JP2007048788A (ja) | 半導体装置 | |
Magraiya et al. | Design of CNTFET based domino wide OR gates using dual chirality for reducing subthreshold leakage current | |
Kim et al. | Flexible silicon nanowire low-power ring oscillator featuring one-volt operation | |
Imran et al. | Optimized design of hybrid CMOS and CNFET 32 nm dual-X current conveyor | |
Fujita et al. | Novel architecture based on floating gate CNT-NEMS switches and its application to 3D on-chip bus beyond CMOS architecture | |
Srikanth et al. | Design of Logic Gates Using CNTFETs | |
Prabhu et al. | Hspice implementation of CNTFET digital gates | |
CN100533733C (zh) | 具有稳定导通电流的布局电路以及具有该电路的ic芯片 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |