1356305 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種通用串列匯流排（Universal Serial ' Bus，USB)主機控制器，特別是一種符合USB2.0規範的 USB主機控制器及其控制方法，其能夠支援USB主機控制 器與通用串列匯流排設備之間的週期傳輸（Periodic Transfer)與非同步傳輸（Asynchronous Transfer)。 •[先前技術】 USB是一種由Intel和Microsoft開發的外設匯流排的 資料通信標準。最大的特點是支援熱插拔（Hot plug)和即 插即用（Plug&Play)的功能。當設備***時，主機牧舉 (enumerate)此設備並載入所需的驅動程式，因此使用遠 比PCI和ISA匯流排方便。通用串列匯流排可以連接的外 部設備有滑鼠、鍵盤、gamepad、搖桿、掃描器、數位相機、 • 印表機、硬碟和網路元件等，其應用非常廣泛。 USB目前常見的有兩個規範，即USB 1.1和USB 2.0。 USB1.1規範’其高速方式的傳輸速率為12百萬位元元/秒 (Mbps)，低速方式的傳輸速率為l_5Mbps。USB2.0規範 是由USB 1.1規範演變而來的，傳輸速率可達到480Mbps， 即60MB/S ’足以滿足大多數外部設備的速率要求。USB 2.0 中的“增強主機控制器介面” （Enhanced Host Controller Interface，EHCI)定義了一個與USB 1.1相相容的架構，可 以用USB 2.0的驅動程式驅動USB 1.1設備。也就是說， VIC08-0009-TW/ 0608-A41727-TW/Final 5 1356305 • 所有支援USB 1.1的設備都可以直接在USB 2 〇的介面上 使用，而不必擔心相容性問題，而且像USB線、插頭等 等附件也都可以直接使用。 USB系統的設計為非對稱式的，它由一個USb主機 (host)控制器和若干透過集線器（Hub)設備以樹形連接 USB設備所組成。USB主機控制器負責實現主機與usb 設備之間的物理資料傳輸，是構成USB主機不可或缺的核 心元件。USB主機控制器與USB設備之間傳輸資料的管道 鲁 （Pipe)可分為四種類型：控制傳輸（Control Transfer)， 等時傳輸（Isochronous Transfer)，中斷傳輸（Interrupt Transfer)和批量傳輸（Buik Transfer)。其中，控制傳輸 一般用於短的、簡單的對設備的命令和狀態回饋，例如用 於匯流排控制的0號管道，〇號管道是USB設備必備的管 道，用於控制匯流排上的設備，其編號為〇 ;等時傳輸是 按照保障連續的速度（可能但不必然是較快地）傳輸，可 能有資料丟失的問題，例如即時的音頻、視頻；中斷傳輸 ^ 用於必須保證儘快反應的設備（僅容許有限延遲），例如 滑鼠、鍵盤；而批量傳輸是使用餘下的帶寬大量地（但是 沒有對於延遲、連續性、帶寬和速度的保證）傳輸資料， 例如普通的檔傳輸。根據這四種傳輸類型的特點，一般將 等時傳輸與中斷傳輸統稱為週期傳輸（Periodic Transfer )，將控制傳輸與批量傳輸統稱為非同步傳輸 (Asynchronous Transfer) 0 USB主機控制器作為USB主機的核心元件，其下最多 VIC08-0009-TW/ 0608-A41727-TW/Final 6 1356305 v . 可以有5級Hub，包括各級的Hub在内，最多可以連接127 個USB設備，而一 USB主機可以同時有多個USB主機控 制器。由於現今USB的應用日益廣泛，如何設計低成本， 小面積，高效能的USB主機控制器晶片，已成為USB系 ' 統設計中的一大焦點。 【發明内容】 本發明提供一種USB主機控制器，包括一第一控制 φ 器，用來控制一主機與一通用串列匯流排設備間的第一傳 輸；一第二控制器，用來控制該主機與該通用串列匯流排 設備間的第二傳輸；以及一第一記憶體，分別耦接於該第 一控制器與該第二控制器，用來緩存該主機控制器與該通 用串列匯流排設備間傳輸的資料；其中，於該第一傳輸階 段，該第一控制器存取該第一記憶體，於該第二傳輸階段， 該第二控制器存取該第一記憶體。 本發明另提供一種應用於USB主機控制器的控制方 • 法，包括步騾：於一第一傳輸階段，透過一第一控制器存 取一第一記憶體以執行該主機控制器與一通用串列匯流排 設備間的第一傳輸；於一第二傳輸階段，透過一第二控制 器存取該第一記憶體以執行該主機控制器與該通用串列匯 流排設備間的第二傳輸；其中，該第一控制器與該第二控 制器都是透過一第一直接記憶體存取引擎存取該第一記憶 體。 該第一傳輸為週期傳輸（Periodic transfer)，該第一 控制器為一週期控制器；該第二傳輸為非同步傳輸 VIC08-0009-TW/ 0608-A41727-TW/Final 7 1356305 • ( Asynchronous transfer)，該第二控制器為一非同步控制 器。 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 第1圖是根據本發明的一個實施例應用於一主機的 • USB主機控制器的示意圖，如圖所示，USB主機控制器14 位於一主機10内，與一記憶體16相連接，一 USB設備 12透過匯流排的集線器（Hub )(圖中未示出）連接到USB 主機控制器Η。通常，當USB設備12連接到USB主機控 制器14時，USB主機控制器14會分配一個特定的7位 元位址給USB設備12 ’用以標識USB設備12。並且，USB 主機控制器14透過投票分配流量’例如透過輪詢模式分配 流量，因此，在沒有明確向USB主機控制器14提出請求 籲 之前，USB設備12不能傳輸資料。需要注意的是，本發 明所指的傳輸是指雙向的傳輸，即資料從USB設備12傳 輸到USB主機控制器14’或是從USB主機控制器14傳輸 到USB設備12。一旦建立起傳輸資料的管道，USB主機 控制器14就可以控制各種類型的資料從USB設備12傳輸 到USB主機控制器14,或是從USB主機控制器14傳輸到 USB設備12。 根據前述兩種不同的資料傳輸類型（週期傳輸和非同 步傳輸），USB主機控制器14内設有對應的一個或多個週 VIC08-0009-TW/ 0608-A41727-TW/Final 8 1356305 期控制器和非同步控制器，在本發明的一個實施射，脳 主機控制器14内设有-個週期控制器窗，和兩個非同步 控制器102 ’ 103 ’以分別控制執行USB設備12與USB主 機控制器14之間的週期傳輸和非同步傳輸，如第丨圖所 不。與此對應的，USB主機控制器14内設有三個記憶體， 即第一記憶體107,第二記憶體1〇8和第三記憶體1〇9,用 來暫存USB設備12與USB主機控制器14之間傳輸的資 料。其中，當USB主機控制器14執行週期傳輸時，週期 控制器101透過第一直接記憶體存取（DMA)引擎1〇4存 取第一記憶體107 ;而USB主機控制器14執行非同步傳 輸時，非同步控制器102和1〇3分別透過第二DMA引擎 105和第三DMA引擎106存取第二記憶體108和第三記憶 體 109。 在記憶體的實現上，第一記憶體1〇7，第二記憶體108 和第三記憶體109均可為靜態隨機存取記憶體（static Random Access Memory ’ SRAM )，或者其他類型的記憶體 裝置。另外’由於目前USB設備的傳輸速率大大提高（高 速USB設備的傳輸速率已達到了 480Mbps)，記憶體的容 量設計若不恰當，過大會造成資源浪費，過小則極易在暫 存傳輸的資料時’因記憶體超載（Overrun )或欠載 (Underrun)而導致資料出錯。因此，在本實施例中，記 憶體的容量設計乃是以所傳輸資料包的最大容量為准，即 第一記憶體107的容量為週期傳輸的最大資料包的容量 256x32位元元（1024位元組）’第二記憶體1〇8和第三記 VIC08-0009-TW/ 0608-A41727-TW/Final 9 1356305 . 憶體109的容量均為非同步傳輸的最大資料包的容量128x 32位元元（512位元組）。如此，以避免出現記憶體的超載 或欠載。 上述的USB主機控制器14能較好地支援高速USB設 備與主機控制器之間各種類型的資料傳輸，且能避免主機 控制器内記憶體的超載或欠載。 請參考第2圖，第2圖是根據本發明的另一個實施例 應用於一主機的USB主機控制器的示意圖。同樣，USB主 ® 機控制器24位於一主機20内，與一記憶體26相連接，一 USB設備22透過匯流排的集線器（Hub)(圖中未示出） 連接到USB主機控制器24。USB主機控制器24内設有一 個週期控制器201，和兩個非同步控制器202，203，以分 別控制執行USB設備22與USB主機控制器24之間的週 期傳輸和非同步傳輸。本發明實施例的USB主機控制器内 雖然共設置了三個控制器，但是並不限定於此，本發明也 適用於在内部設置其他數量或類型控制器的USB主機控 *制器。 與第1圖中的USB主機控制器14不同的是，本實施 例的USB主機控制器24内僅設置了兩個記憶體：第一記 憶體207和第二記憶體208，及對應的第一 DMA引擎204 和第二DMA引擎205。由於USB設備22與USB主機控 制器24之間通常以微幀（Microframe )的形式傳輸資料， 每一微幀以125毫秒為單位，且在同一微幀的傳輸週期 中，週期傳輸的優先順序要高於非同步傳輸，因此，本實 VIC08-0009-TW/ 0608-A41727-TW/Final 1356305 雜兩個階段：週期傳輪階段和非同步 段’USB主機控制器24僅執 f傳輸；於非同步傳輪階段，僅執行非同步傳輸。1356305 IX. Description of the Invention: [Technical Field] The present invention relates to a universal serial bus (USB) host controller, in particular to a USB host controller conforming to the USB 2.0 specification and The control method thereof is capable of supporting periodic transfer and asynchronous transfer between the USB host controller and the universal serial bus device. • [Prior Art] USB is a data communication standard for peripheral busses developed by Intel and Microsoft. The biggest feature is the ability to support hot plugs and Plug & Play (Plug & Play). When the device is plugged in, the host enumerates the device and loads the required drivers, so it is much easier to use than the PCI and ISA bus. The external devices that the universal serial bus can connect to include mouse, keyboard, gamepad, joystick, scanner, digital camera, • printer, hard disk and network components, etc., which are widely used. USB currently has two specifications, USB 1.1 and USB 2.0. The USB 1.1 specification 'has a high-speed mode with a transmission rate of 12 megabits per second (Mbps) and a low-speed mode with a transmission rate of l_5 Mbps. The USB 2.0 specification evolved from the USB 1.1 specification with a transfer rate of 480 Mbps, or 60 MB/s, which is sufficient for the speed requirements of most external devices. The Enhanced Host Controller Interface (EHCI) in USB 2.0 defines a USB 1.1-compatible architecture that can drive USB 1.1 devices with a USB 2.0 driver. In other words, VIC08-0009-TW/ 0608-A41727-TW/Final 5 1356305 • All devices that support USB 1.1 can be used directly on the USB 2 interface without worrying about compatibility issues, and like USB cable Accessories such as plugs and the like can also be used directly. The USB system is designed to be asymmetric, consisting of a USb host controller and a number of USB devices connected in a tree via a hub device. The USB host controller is responsible for realizing the physical data transfer between the host and the usb device, and is an indispensable core component of the USB host. Pipes for transferring data between USB host controllers and USB devices can be divided into four types: Control Transfer, Isochronous Transfer, Interrupt Transfer, and Buik (Buik). Transfer). Among them, the control transmission is generally used for short and simple command and status feedback to the device, such as the No. 0 pipe for the bus bar control, and the nickname pipe is a necessary pipe for the USB device to control the devices on the bus bar. The number is 〇; isochronous transmission is transmitted according to the guaranteed continuous speed (possibly but not necessarily faster), and there may be problems of data loss, such as instant audio and video; interrupt transmission ^ used to ensure that the response is as soon as possible Devices (only limited delays are allowed), such as mice, keyboards; and bulk transfers use a large amount of bandwidth (but no guarantees for delay, continuity, bandwidth, and speed) to transfer data, such as normal file transfers. According to the characteristics of these four types of transmission, isochronous transmission and interrupt transmission are generally referred to as periodic transmission (Periodic Transfer), and control transmission and bulk transmission are collectively referred to as asynchronous transmission (Asynchronous Transfer). 0 USB host controller as USB host Core components, up to VIC08-0009-TW/ 0608-A41727-TW/Final 6 1356305 v . There can be 5 levels of Hub, including all levels of Hub, up to 127 USB devices can be connected, and a USB host can There are also multiple USB host controllers at the same time. Due to the increasing use of USB today, how to design a low-cost, small-area, high-performance USB host controller chip has become a major focus in the USB system design. SUMMARY OF THE INVENTION The present invention provides a USB host controller including a first control φ device for controlling a first transmission between a host and a universal serial busbar device; and a second controller for controlling the a second transmission between the host and the universal serial bus device; and a first memory coupled to the first controller and the second controller, respectively, for caching the host controller and the universal serial The data transmitted between the bus devices; wherein, in the first transmission phase, the first controller accesses the first memory, and in the second transmission phase, the second controller accesses the first memory. The present invention further provides a control method for a USB host controller, including the steps of: accessing a first memory through a first controller to perform the host controller and a general a first transmission between the serial bus devices; accessing the first memory through a second controller to perform a second transmission between the host controller and the universal serial bus device in a second transmission phase The first controller and the second controller both access the first memory through a first direct memory access engine. The first transmission is a periodic transfer, the first controller is a periodic controller; the second transmission is an asynchronous transmission VIC08-0009-TW/ 0608-A41727-TW/Final 7 1356305 • (Asynchronous transfer The second controller is a non-synchronous controller. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the appended claims appended claims One embodiment of the present invention is applied to a USB host controller of a host. As shown, the USB host controller 14 is located in a host 10, connected to a memory 16, and a USB device 12 is connected through a bus. A hub (not shown) is connected to the USB host controller. Typically, when USB device 12 is connected to USB host controller 14, USB host controller 14 assigns a particular 7-bit address to USB device 12' for identifying USB device 12. Also, the USB host controller 14 distributes traffic by polling, e.g., by polling mode, so that the USB device 12 cannot transmit data until a request is made to the USB host controller 14 explicitly. It should be noted that the transmission referred to in the present invention refers to bidirectional transmission, i.e., data is transferred from the USB device 12 to the USB host controller 14' or from the USB host controller 14 to the USB device 12. Once the pipeline for transferring data is established, the USB host controller 14 can control the transfer of various types of data from the USB device 12 to the USB host controller 14, or from the USB host controller 14 to the USB device 12. According to the foregoing two different data transmission types (periodic transmission and non-synchronous transmission), the USB host controller 14 is provided with one or more corresponding VIC08-0009-TW/ 0608-A41727-TW/Final 8 1356305 period control. And a non-synchronous controller, in one implementation of the present invention, the host controller 14 is provided with a cycle controller window, and two asynchronous controllers 102' 103' to control the execution of the USB device 12 and the USB, respectively. Periodic transmission and non-synchronous transmission between the host controller 14, as shown in the figure below. Correspondingly, the USB host controller 14 is provided with three memories, namely, a first memory 107, a second memory 1〇8 and a third memory 1〇9 for temporarily storing the USB device 12 and the USB host. Information transmitted between controllers 14. Wherein, when the USB host controller 14 performs periodic transmission, the cycle controller 101 accesses the first memory 107 through the first direct memory access (DMA) engine 1〇4; and the USB host controller 14 performs asynchronous transmission. The non-synchronous controllers 102 and 101 access the second memory 108 and the third memory 109 through the second DMA engine 105 and the third DMA engine 106, respectively. In the implementation of the memory, the first memory 1〇7, the second memory 108 and the third memory 109 may each be a static random access memory (SRAM), or other types of memory. Device. In addition, because the transmission rate of USB devices is greatly improved (the transmission rate of high-speed USB devices has reached 480Mbps), if the capacity design of the memory is not appropriate, the resources will be wasted due to the excessive use, and when it is too small, it is easy to temporarily store the data. 'Data error due to memory overload (Overrun) or underrun (Underrun). Therefore, in this embodiment, the capacity design of the memory is based on the maximum capacity of the transmitted data packet, that is, the capacity of the first memory 107 is the maximum data packet size of 256×32 bits (1024 bits). Tuple) 'Second memory 1〇8 and third record VIC08-0009-TW/ 0608-A41727-TW/Final 9 1356305. The capacity of the memory 109 is the maximum data packet size of 128x 32 bits for asynchronous transmission. Yuan (512 bytes). This is to avoid overloading or underloading of the memory. The USB host controller 14 described above can better support various types of data transmission between the high-speed USB device and the host controller, and can avoid overloading or underloading of the memory in the host controller. Please refer to FIG. 2, which is a schematic diagram of a USB host controller applied to a host in accordance with another embodiment of the present invention. Similarly, the USB host controller 24 is located in a host 20, connected to a memory 26, and a USB device 22 is connected to the USB host controller 24 via a bus hub (not shown). The USB host controller 24 is provided with a cycle controller 201 and two asynchronous controllers 202, 203 for separately controlling the execution of the periodic transmission and the asynchronous transmission between the USB device 22 and the USB host controller 24. Although three controllers are provided in the USB host controller of the embodiment of the present invention, the present invention is not limited thereto, and the present invention is also applicable to a USB host controller in which other numbers or types of controllers are internally provided. Different from the USB host controller 14 in FIG. 1 , only two memories are provided in the USB host controller 24 of the present embodiment: the first memory 207 and the second memory 208, and the corresponding first DMA engine 204 and second DMA engine 205. Since the USB device 22 and the USB host controller 24 usually transmit data in the form of a microframe, each microframe is in units of 125 milliseconds, and in the transmission period of the same microframe, the priority order of the periodic transmission is Higher than asynchronous transmission, therefore, this real VIC08-0009-TW/ 0608-A41727-TW/Final 1356305 mixed two phases: cycle transmission phase and non-synchronization segment 'USB host controller 24 only f transmission; Yu Fei In the synchronous pass phase, only asynchronous transfers are performed.
主機參考第3圖’第3圖繪示本發明-實施例的USB 如第二&備22之間傳輸資料的微鳩格式。 回所不’每微φ貞時長為125毫秒以一開始標識 拙二束標識為界。在傳輸資料時，先執行週期傳輸，再The host refers to FIG. 3'. FIG. 3 illustrates a micro-format of the data transmitted between the USB, such as the second & Go back to no more than 125 milliseconds per micro φ 以 to mark the beginning of the second beam identification. When transmitting data, first perform periodic transmission, and then
執仃非同步傳輸。本實施例中的微巾貞時長也可為其他值， 並不限定於125毫秒。 本發明一實施例的具體操作如下，於一微幅的週期傳 輸階段’USB主機控制器24内的週期控制器2()1透過第 一 DMA引擎2〇4存取第一記憶體2〇7與第二記憶體2〇8， 且嬴週期控制器201存取第一記憶體207達一預定數量的 資料，例如存滿或取空第一記憶體2〇7時，週期控制器2〇1 控制其内部的一位址指標指向第二記憶體2〇8，以透過第 一 DMA引擎204接續存取第二記憶體208。如此，對於週 期控制器201而言，其對應可存取的記憶體容量相當於是 第一記憶體207與第二記憶體208的容量之和。而後，於 同一微幀的非同步傳輸階段，USB主機控制器24内的非 同步控制器202透過第一 DMA引擎204存取第一記憶體 207，非同步控制器203透過第二DMA引擎205存取第二 記憶體208。因此，對於非同步控制器202，其對應可存取 的記憶體容量為第一記憶體207的容量；而對於非同步控 制器203，其對應可存取的記憶體容量為第二記憶體208 VIC08-0009-TW/ 0608-A41727-TW/Final 1356305 . 的容量。 需要注意的是，同一微幀執行完週期傳輸後，在非同 步傳輸階段每次傳輸一個非同步傳輸的資料包之前，USB 主機控制器24會透過其内部的一計數器206計算微幀的剩 餘時間，以判定剩餘時間是否足以傳輸一整個非同步傳輸 的資料包。若USB主機控制器24判定得出微幀的剩餘時 間足夠傳輸一整個非同步傳輸的資料包，則非同步控制器 202或203控制傳輸一個非同步傳輸的資料包；當判定得 • 出微幀的剩餘時間不足以傳輸一整個非同步傳輸的資料包 時，則非同步控制器202與203停止執行非同步傳輸。 在記憶體的實現上，第一記憶體207和第二記憶體208 同樣均可為靜態隨機存取記憶體，且為避免出現記憶體的 超載或欠載，記憶體的容量設計仍以所傳輸資料包的最大 容量為准。根據本發明的一個實施例，第一記憶體207與 第二記憶體208的容量之和應等於或大於週期傳輸的最大 資料包的容量，且第一記憶體207與第二記憶體208的容 ^ 量均應等於或大於非同步傳輸的最大資料包的容量。若週 期傳輸的最大資料包的容量為1024位元元組，非同步傳輸 的最大資料包的容量為512位元元組，則第一記憶體207 與第二記憶體208的容量均可設定為128x32位元，這樣， 二者之和為1024位元組，就能滿足週期傳輸和非同步傳輸 的需求。在不脫離本發明的精神的情況下，本發明的其他 實施例也可使用其他的記憶體組合，例如設定第一記憶體 207和第二記憶體208的容量都等於或大於週期傳輸的最 VIC08-0009-TW/ 0608-A41727-TW/Final 12 1356305 大資料包的容量，而第三記憶體的容量等於或大於非同步 傳輸的最大資料包的容量。 本發明實施例中的記憶體雖然使用的是SRAM,但是並 不僅限於此，其他可讀寫的記憶體例如快閃（Flash)記憶 體等，都可用來作為本發明USB主機控制器内的記憶體， 且記憶體可以整合在同一晶片或是分開在兩個晶片上，也 可以有不同的配置，例如一個記憶體分成兩部分，分別支 援兩種傳輸等。 由此可見，第2圖的USB主機控制器24要比第1圖 的USB主機控制器14至少減少了三分之一的記憶體面積 和一個DMA引擎。因此，透過分階段執行週期傳輸和非 同步傳輸，共用DMA引擎和記憶體，就能在保證記憶體 不出現超載或欠載的基礎上，減少記憶體的容量和DMA 引擎的個數，從而精簡了整個USB主機控制器的電路面 積。 為了進一步提高運作效能，本發明的USB主機控制器 24可以於週期傳輸階段結束時執行一預取功能，具體操作 如下：在週期傳輸階段，當週期控制器201控制傳輸最後 一個週期傳輸的資料包期間，USB主機控制器24會檢測 第一記憶體207與第二記憶體208的儲存狀態，若第一記 憶體207與第二記憶體208之一被取空或者剩下小於一預 定數量的資料，則USB主機控制器24執行一預取動作， 即預先從記憶體26取出一個或多個非同步傳輸的資料包 存入到被取空或剩餘資料不足預定數量的記憶體中。這 VIC08-0009-TW/ 0608-A41727-TW/Final 13 1356305 樣，在接下去的非同步傳輸階段，若執行的是從usb主機 控制器24至，J USB設備22的非同步傳輸，則開始發送的第 一個非同步傳輸的資料包或者之後的資料包就不需要再從 記憶體26中取出，而是直接將記憶體中暫存的賴步傳輸 的資料包發送給USB設備22，從而提高了工作效^。Perform asynchronous transmission. The duration of the micro-masks in this embodiment may also be other values, and is not limited to 125 milliseconds. The specific operation of an embodiment of the present invention is as follows: in a micro-period transmission phase, the periodic controller 2()1 in the USB host controller 24 accesses the first memory 2〇7 through the first DMA engine 2〇4. And the second memory 2〇8, and the cycle controller 201 accesses the first memory 207 for a predetermined amount of data, for example, when the first memory 2〇7 is full or empty, the cycle controller 2〇1 The address pointer of the internal control is directed to the second memory 2〇8 to access the second memory 208 through the first DMA engine 204. Thus, for the cycle controller 201, the corresponding accessible memory capacity is equivalent to the sum of the capacities of the first memory 207 and the second memory 208. Then, in the asynchronous transmission phase of the same micro frame, the asynchronous controller 202 in the USB host controller 24 accesses the first memory 207 through the first DMA engine 204, and the asynchronous controller 203 stores the second DMA engine 205 through the second DMA engine 205. The second memory 208 is taken. Therefore, for the asynchronous controller 202, the corresponding accessible memory capacity is the capacity of the first memory 207; and for the asynchronous controller 203, the corresponding accessible memory capacity is the second memory 208. VIC08-0009-TW/ 0608-A41727-TW/Final 1356305 . Capacity. It should be noted that after the periodic transmission of the same micro-frame is completed, the USB host controller 24 calculates the remaining time of the micro-frame through a counter 206 internally therein before each asynchronous transmission of the data packet is transmitted in the asynchronous transmission phase. To determine if the remaining time is sufficient to transmit an entire asynchronously transmitted packet. If the USB host controller 24 determines that the remaining time of the microframe is sufficient to transmit an entire asynchronously transmitted data packet, the asynchronous controller 202 or 203 controls to transmit an asynchronously transmitted data packet; when determining the microframe When the remaining time is insufficient to transmit an entire asynchronously transmitted packet, the non-synchronous controllers 202 and 203 stop performing the asynchronous transmission. In the implementation of the memory, the first memory 207 and the second memory 208 can also be static random access memory, and in order to avoid overload or underload of the memory, the capacity design of the memory is still transmitted. The maximum capacity of the data package is subject to change. According to an embodiment of the present invention, the sum of the capacities of the first memory 207 and the second memory 208 should be equal to or greater than the capacity of the largest data packet periodically transmitted, and the capacity of the first memory 207 and the second memory 208. ^ The quantity should be equal to or greater than the maximum packet size of the asynchronous transmission. If the capacity of the largest data packet transmitted periodically is 1024 bytes, and the capacity of the largest data packet for asynchronous transmission is 512 bytes, the capacity of the first memory 207 and the second memory 208 can be set to 128x32 bits, so that the sum of the two is 1024 bytes, which can meet the needs of periodic transmission and asynchronous transmission. Other embodiments of the present invention may use other memory combinations without departing from the spirit of the present invention, for example, setting the capacity of the first memory 207 and the second memory 208 to be equal to or greater than the most VIC08 of the periodic transmission. -0009-TW/ 0608-A41727-TW/Final 12 1356305 The capacity of a large packet, and the capacity of the third memory is equal to or greater than the capacity of the largest packet of asynchronous transmission. Although the memory in the embodiment of the present invention uses SRAM, it is not limited thereto, and other readable and writable memory such as flash memory can be used as the memory in the USB host controller of the present invention. The body, and the memory can be integrated on the same wafer or separated on two wafers, or can have different configurations, for example, one memory is divided into two parts, respectively supporting two kinds of transmissions and the like. Thus, the USB host controller 24 of Fig. 2 is at least one-third smaller than the USB host controller 14 of Fig. 1 and a DMA engine. Therefore, by performing periodic transmission and asynchronous transmission in stages, sharing the DMA engine and memory, the memory capacity and the number of DMA engines can be reduced, so as to reduce the memory without overload or underload. The circuit area of the entire USB host controller. In order to further improve the operational efficiency, the USB host controller 24 of the present invention may perform a prefetch function at the end of the periodic transmission phase, as follows: In the periodic transmission phase, the periodic controller 201 controls the transmission of the data packet transmitted in the last cycle. During the period, the USB host controller 24 detects the storage state of the first memory 207 and the second memory 208, if one of the first memory 207 and the second memory 208 is emptied or less than a predetermined amount of data remains. Then, the USB host controller 24 performs a prefetching operation, that is, the one or more asynchronously transferred data packets are taken out from the memory 26 in advance and stored in a predetermined amount of memory which is emptied or the remaining data is insufficient. This VIC08-0009-TW/ 0608-A41727-TW/Final 13 1356305, in the next asynchronous transmission phase, if the asynchronous transfer from the usb host controller 24 to the J USB device 22 is performed, then The first asynchronously transmitted data packet or the subsequent data packet does not need to be taken out from the memory 26, but the data packet transmitted in the memory is directly sent to the USB device 22, thereby Improve the work efficiency ^.
為了更清楚地說明本發明的USB主機控制^^作過 程，請參考第4圖，第4圖示出了應用於第2圖的usb主 機控制器24的控制方法流程圖。首先，在步驟s4i，usb 主機控制器24開始控制傳輸一微巾貞；在此微巾貞的傳輸週期 中，USB主機控制器24首先會透過週期控制器2〇ι執行 一第一傳輸，例如透過存取第一記憶體2〇7或第二記憶體 208執行週期傳輸，如步驟S42。在步驟S43，如上文所述 在週期傳輸的最後一個資料包時，USB主機控制器24~會 檢測第一記憶體207與第二記憶體208的儲存狀態，判斷 是否有足夠的儲存空間，例如剩餘可用空間大於一預定數 量，或是其中一個記憶體被取空。若上述條件成立，例如 第一 δ己憶體207與第一 §己憶體208之一空出預定數量的空 間，則進入步驟S44，USB主機控制器24執行一預取動作^ 將從記憶體中預取的一或多個第二傳輸（例如非同步傳輸） 的資料包存入空出足夠空間的記憶體，例如存入到空出預 定數量空間的記憶體；反之，則返回步驟S42，繼續執行 週期傳輸。而後，進入第二傳輸階段，例如對第二記憶體 208進行存取的非同步傳輸階段。在步驟S45，USB主機 控制器24透過其内部的一計數器206計算微悄的剩餘時 VIC08-0009-TW/ 0608-A41727-TW/Final !3563〇5 間；並判斷剩餘時間是否足以傳輸一個— 的資料包，如步驟S46。若剩餘時間足：：的非同步傳輪 非同步傳輸的資料包，則非同步控制$ ，個凡整的 ，一個非同步傳輸的資料包，如步驟_ ;若剩餘時間不 2傳輸-個完整的非同步傳輸的#料包時，則非同步控 I态202與203停止執行非同步傳輪，即結束。因此， =同步傳㈣段’每讀輸-個非㈣傳輸的轉 =:Γ主機控制器24都會計算㈣的剩餘時間， ^有^餘時間充足才會執行非同步傳輪動作，如此循環往 貞的剩餘時間不再Μ傳輪—整 的-貪料包，便就此結束。 得輸 需要說明的是，本發明所述的主機可為_ 其他可搞式設備等；而本發明的Us 2 ^疋 增強主機控觀介面（EHCI)規_±^=可為符合 雖然本發明的USB主機控制器是 工°此外， 與兩個非同步控制器為例，但其迷不：二：週期控制器 器或非同步控制器的數目，對於包、^ ^的週期控制 同步控制器的USB主機控制器，仍可二丄：控制态或非 思’並同樣能達到精簡電路面積的功二。"明的發明構 另外，除上述實施例外，本發 傳輸裝置，而不僅限於USB主機控制器^匕、他類型的 一雖然本發明已以較佳實施例揭露二，然 P艮疋本發明，任何所屬技術領域中 、、、卜用以 脫離本發明之精神和範圍内，當可;!:者，在不 1 乍些淬之更動與潤飾， VIC08-0009-TW/0608-A41727 xW/f. 1356305 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 第1圖是根據本發明的一個實施例應用於一主機的 USB主機控制器的示意圖； 第2圖是根據本發明的另一個實施例應用於一主機的 USB主機控制器的示意圖； 第3圖是第2圖中的USB主機控制器與USB設備之 間傳輸資料的微幀（Microframe)格式示意圖；以及 第4圖是根據本發明的一個實施例應用於第2圖的 USB主機控制器的控制方法的流程圖。 【主要元件符號說明】 10、20 :主機； 12、22 : USB 設備； 14、24 : USB主機控制器； 16、26 :記憶體； 101、 201 :周期控制器； 102、 103、202、203 :非同步控制器； 104、 204 :第一 DMA 引擎； 105、 205 :第二 DMA 引擎； 106 :第三DMA引擎； 107、 207 :第一記憶體； 108、 ：第二記憶體； VIC08-0009-TW/ 0608-A41727-TW/Final 16 1356305 109 :第三記憶體； 206 :計數器； S41〜S47 :步驟° VIC08-0009-TW/ 0608-A41727-TW/FinalIn order to more clearly explain the USB host control process of the present invention, please refer to Fig. 4, which shows a flow chart of the control method applied to the usb host controller 24 of Fig. 2. First, in step s4i, the usb host controller 24 starts to control the transmission of a micro-film; during the transmission cycle of the micro-frame, the USB host controller 24 first performs a first transmission through the cycle controller 2〇, for example The periodic transmission is performed by accessing the first memory 2〇7 or the second memory 208, as by step S42. In step S43, when the last packet is periodically transmitted as described above, the USB host controller 24~ detects the storage state of the first memory 207 and the second memory 208 to determine whether there is sufficient storage space, for example. The remaining free space is greater than a predetermined amount, or one of the memories is emptied. If the above condition is met, for example, one of the first δ hexamed body 207 and the first § mnemonic 208 vacates a predetermined amount of space, proceeding to step S44, the USB host controller 24 performs a prefetching action ^ from the memory The pre-fetched one or more second transmission (for example, asynchronous transmission) data packets are stored in a memory that vacates a sufficient space, for example, stored in a memory that is vacated by a predetermined amount of space; otherwise, the process returns to step S42 to continue. Perform periodic transmission. Then, the second transfer phase is entered, such as the asynchronous transfer phase of accessing the second memory 208. In step S45, the USB host controller 24 calculates the remaining time VIC08-0009-TW/0608-A41727-TW/Final!3563〇5 through a counter 206 of its internal; and determines whether the remaining time is sufficient to transmit one- The package is as in step S46. If the remaining time is sufficient:: the non-synchronous transmission non-synchronous transmission of the data packet, the non-synchronous control $, a whole, an asynchronous transmission of the data packet, such as step _; if the remaining time is not 2 transmission - complete When the #material packet is asynchronously transmitted, the asynchronous control I state 202 and 203 stop performing the asynchronous transfer, that is, the end. Therefore, = synchronous transmission (four) segment 'per read-to-non-four (four) transmission rotation =: Γ host controller 24 will calculate the remaining time of (four), ^ have more than enough time to perform non-synchronous transfer action, so cycle to The rest of the time is no longer a rumor--the whole-gracious package, and it ends. It should be noted that the host device of the present invention may be other compliant devices, etc.; and the Us 2 疋 enhanced host control interface (EHCI) specification of the present invention may be in accordance with the present invention. The USB host controller is working. In addition, with two non-synchronous controllers as an example, but its fans are not: two: the number of periodic controllers or non-synchronous controllers, for the package, ^ ^ cycle control synchronous controller The USB host controller can still be used to control the state of the circuit or the same. In addition to the above-described embodiments, the present invention is not limited to a USB host controller, but a type of the present invention has been disclosed in the preferred embodiment. , in any of the technical fields, and in the spirit and scope of the present invention, when it can be used, it is not necessary to change and refine, VIC08-0009-TW/0608-A41727 xW/ f. 1356305 The scope of the invention is therefore defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a USB host controller applied to a host according to an embodiment of the present invention; FIG. 2 is a USB host controller applied to a host according to another embodiment of the present invention. 3 is a schematic diagram of a microframe format for transferring data between a USB host controller and a USB device in FIG. 2; and FIG. 4 is a diagram applied to FIG. 2 according to an embodiment of the present invention. Flowchart of the control method of the USB host controller. [Main component symbol description] 10, 20: host; 12, 22: USB device; 14, 24: USB host controller; 16, 26: memory; 101, 201: cycle controller; 102, 103, 202, 203 : non-synchronous controller; 104, 204: first DMA engine; 105, 205: second DMA engine; 106: third DMA engine; 107, 207: first memory; 108, second memory; VIC08- 0009-TW/ 0608-A41727-TW/Final 16 1356305 109: third memory; 206: counter; S41~S47: step ° VIC08-0009-TW/ 0608-A41727-TW/Final