200842601 九、發明說明： 【發明所屬之技術領域】 本申請㈣關於通料列匯流排（USB)f料傳送架構及 方法。更具體言之，本申請案係關於用於增加腦周邊設 備中之資料輸送量的USB資料傳送架構及方法。 【先前技術】 諸如含有非揮發性記憶體之資料儲存設備的usb周邊設 備通常在家庭及商務計算環境中被用於緊密及攜帶型封裝 2的可靠資料儲存。此類型之USB周邊設備可包括利用協 定處理常式與USB實體層（PHY)設備建立介面之卿控制 器及與快閃記憶體通信之後端電路。當經由usb設備之 USB連接ϋ連接之主機希望向該USB設備寫人或自其讀取 資料時，藉由適當USB協定且以根據一約定標準之適當袼 式來呈現命令及資料。該等USB標準以理論上最大資料傳 运速率而設計。雖然USB標準理論上將支援此等最大資料 速率，但歸因於儲存媒體及相關聯電路的限制，usb資料 儲存設備之效能實際上可能不能達成最大資料速率。、 USB資料儲存設備中之USB控制器管理資料傳送至及傳 送自欠該USB資料儲存設備。通常，以已知長度之批量來傳 送資料並在主機與USB設備之間交換交握訊息以管理資料 傳达期間的時序及錯誤檢查。一處理USB周邊設備中之資 料交換的方法為USB控制器回應於隨著每一批量之資料^ 動至或移動自緩衝器所產生之處理器中斷而執行一内部微 處理上的多個韌體指令。然而，涉及韌體可顯著影響資 127934.doc 200842601 料傳送效能。每一中斷腺 斷將^遲内部微處理器可能參與之其 他動作，或將微處理器自任何臨時睡眠或閒置模式喚醒， =可能需要時間來識別、解譯及作用於關於該中斷之勃 " 目此，usb控制器中之微處理器動作可減慢可達 成之資料傳送速率且增加USB設備中的功率消耗。 【發明内容】 十為解決對經改良之USB控制器架構及傳送資料之方法的 ;要，提出可在某些資料傳送功能期間減少或避免使用勃 體及微處理器額外耗用的具有完全傳送自動化之謂控制 器。 根據一第一態樣’揭示一種在一通用串列匯流排卿) 控制器中實祐&入屑、、， 了一 傳达自動化之方法。該方法包括在該 二制裔處自-主機接收_刪大量資料傳送起始訊息 —在-咖大量資料傳送操作期間傳送資料封包。在該大 ^料傳送操作之一資料傳送階段期間，在該USB控制器 2主機介面模組與一後端模組之間交換關於該刪控制 為内^ -身料傳送狀態的硬體產生邏輯信號。在一實施 中乂換硬體產生邏輯信號可包括在該usb大量資料傳送 操作期間在該USB控制器之—後端模組中產生指示一緩衝 5己憶體準備就緒將資料傳送入或傳送出大量儲存媒體之至 少一後端硬體邏輯信號。另外’交換硬體產生邏輯信號可 。括在„亥USB控制器之一主機介面模組中產生至少一主機 ^面模組硬體邏輯信號，使得在一刪大量資料傳送讀取 〆寫入插作期間，該後端模組及主機介面模組可經組態以 127934.doc 200842601 彼此進行關於該USB抻击丨哭& ^ 控制裔内之資料傳送狀態的通信。 在另一態樣中，一種在一 丄& 牡通用串列匯流排（USB)控制器 中實施完全傳送自動化之太 法包括在該USB控制器處接收 USB大里傳送寫入操作一曰 ^ USB大罝資料傳送起始訊息， 及在该USB控制器内初始 办 、， ttct^㈢+ σ化凡全傳达自動化模式。在該 USB大s傳送寫入择作 ^ 輞作期間，於該USB控制器處，自主機 接收貧料封包，並在技必200842601 IX. Description of the invention: [Technical field to which the invention pertains] This application (4) relates to a structure and method for transferring a bus (USB) material. More specifically, the present application relates to a USB data transfer architecture and method for increasing the amount of data transfer in a brain peripheral device. [Prior Art] USB peripheral devices such as data storage devices containing non-volatile memory are commonly used for reliable data storage in compact and portable packages 2 in home and business computing environments. This type of USB peripheral device may include a clear controller that establishes an interface with a USB physical layer (PHY) device using a protocol processing routine and a back end circuit that communicates with the flash memory. When a host connected via a USB port of a USB device wishes to write to or read data from the USB device, the command and data are presented by an appropriate USB protocol and in accordance with an agreed standard. These USB standards are designed with a theoretical maximum data transfer rate. Although the USB standard will theoretically support these maximum data rates, the performance of the usb data storage device may not actually achieve the maximum data rate due to limitations of the storage media and associated circuitry. The USB controller management data in the USB data storage device is transferred to and from the USB data storage device. Typically, data is transmitted in batches of known length and handshake messages are exchanged between the host and the USB device to manage timing and error checking during data transmission. A method of processing data exchange in a USB peripheral device is to execute a plurality of firmware on an internal microprocessor in response to a processor interrupt generated by moving or moving the buffer from each batch of data. instruction. However, the firmware involved can significantly affect the throughput of the 127934.doc 200842601. Each interrupt gland will delay other actions that the internal microprocessor may be involved in, or wake up the microprocessor from any temporary sleep or idle mode. = It may take time to identify, interpret, and act on the interrupt. For this reason, the microprocessor action in the usb controller can slow down the achievable data transfer rate and increase the power consumption in the USB device. SUMMARY OF THE INVENTION To solve the problem of the improved USB controller architecture and the method of transmitting data, it is proposed to reduce or avoid the use of Bosch and the microprocessor for additional consumption during certain data transfer functions. Automation is called a controller. According to a first aspect, a method for revealing a kind of communication is disclosed in a general-purpose serial bus controller. The method includes receiving, at the second-generation, a self-host receiving _ deleting a large amount of data transmission start message - transmitting a data packet during a large data transfer operation. During the data transfer phase of the bulk transfer operation, hardware generation logic for exchanging the control state into the internal transfer state is exchanged between the USB controller 2 host interface module and a backend module. signal. In an implementation, the hardware generation logic signal may include generating an indication in the USB-back-end module during the mass transfer operation of the USB device. The buffer is ready to transfer data into or out of the memory. At least one back-end hardware logic signal of the mass storage medium. In addition, the exchange hardware generates a logic signal. The at least one host module module hardware logic signal is generated in one of the host controller modules of the USB controller, so that the back end module and the host are deleted during a large amount of data transfer read/write write The interface module can be configured to communicate with each other about the USB sniper crying & ^ control data transfer status within the 127934.doc 200842601. In another aspect, a 丄 & The method of implementing full transfer automation in the bus (USB) controller includes receiving a USB transfer operation at the USB controller, a USB data transfer start message, and initializing in the USB controller. Talk, ttct^(3)+ σ化凡全的自动模式。 During the USB s transfer write selection ^ 辋, at the USB controller, the poor material packet is received from the host, and
在接收該專資料封包的同時，於該USB 控制裔之一主機介面握知命 , 。 與—後端模組之間，交換關於該 USB控制器内之一資料禮、主此At 貝钭傳运狀恶的硬體產生邏輯信號。 在又一替代實施中，娓-体^ 揭不一種在一通用串列匯流排 (USB)控制器中實絲*入 w 凡王傳迗自動化之方法，其中 USB控制器處，自一 /、r任口褒 機接收一 USB大量傳送讀取操作之 =大置-貝料傳送起始訊息，且該刪控制器在該⑽控 制裔内起始一完令禮< 、自動化模式。在該大量傳送讀取操 作』間，该元全傳送自動化模式可包括自該 該該主機傳輪資粗封七 別裔向 打貝枓封包，及在傳輸該等資料封包的同時， ;只USBUJ益之一主機介面模組與一後端模組之間，、六 :關於該⑽控制器内之資料傳送狀態的硬體產生邏輯^ 根據另一態樣’揭示-種用於-刪周邊設備中之 串列匯流排击丨一 用 )拴制态。該USB控制器可包括_且右 衝記憶體之後端模組，該緩衝記憶體經組態以將資料傳； 一或傳达出諸如非揮發性記憶體之大量儲存媒體。另外， 主機介面模組與該後端模組通信，且經組態以與—主機 127934.doc 200842601 通信。後端模組及主應人二》 機）丨面杈組亦經組態以在一 USB大量 資料傳送讀取或寫入摔作 饰作期間’經由硬體邏輯信號而彼此 進行關於該USB控制涔向— 一， & 制益内之一資料傳送狀態的通信。 在另〜樣巾’描述—種通用串列匯流排（USB)周邊設 備。該刪周邊設備可包括諸如非揮發性記憶體之大量儲 存媒體’ $大量儲存媒體經調適用於自-主機及-USB控 制斋接收貝料或向该主機及該USB控制器提供資料。該 USB控制器可包括一具有緩衝記憶體之後端模組，該緩衝While receiving the special data packet, the host device of the USB control family grasps the life. And the back-end module exchanges a logic signal about the hardware of the USB controller and the hardware of the At-Beat. In still another alternative implementation, the 娓-body does not expose a method in a universal serial bus (USB) controller, where the USB controller is operated by a USB controller. The port machine receives a USB mass transfer read operation = a large-to-bee feed start message, and the delete controller initiates a command in the (10) control family, automatic mode. Between the mass transfer read operation, the meta-transfer automation mode may include, from the host transfer, the seven-member squad to the beibei packet, and at the same time as transmitting the data packet; only the USBUJ Between one of the host interface module and a back-end module, six: hardware generation logic about the data transfer state in the (10) controller ^ according to another aspect 'disclosed--used--deleting peripheral devices In the series of busbars, the busbars are used for killing. The USB controller can include a _ and a right-back memory back-end module configured to transfer data; or to convey a large amount of storage media such as non-volatile memory. In addition, the host interface module communicates with the backend module and is configured to communicate with the host 127934.doc 200842601. The back-end module and the main 二 》 》 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦 亦涔——, a communication of data transmission status within &. In the other ~ sample towel described - a universal serial bus (USB) peripheral device. The deleted peripheral device may include a large amount of storage medium such as non-volatile memory. A large amount of storage medium is adapted to receive data from the host-and-USB control or to provide data to the host and the USB controller. The USB controller can include a buffer memory back end module, the buffer
記憶體經組態以將資料傳送人或傳送出該大量射媒體。 另外，該控制器可包括—與該後端模組通信且經組態以與 口亥主機通^之主機介面模組，其中在_ usb大量資料傳送 賣取或寫人操作期間’後端模組及主機介面模組經組態以 、、二由硬體邏輯化號而彼此進行關於該USB控制器内之一資 料傳送狀態的通信。 在審閱以下圖式、實施方式及申請專利範圍後，本發明 之其他特徵及優點即變得顯而易見。 【實施方式】 圖1说明經由USB通信線14與主機12連接之通用串列匯 流排（USB)周邊設備1〇的方塊圖。主機12可為個人電腦之 USB埠或例如MP3播放器、行動電話等具有USB能力之任 何電子組件。USB通信線14可為USB周邊設備10經由一標 準USB連接器至主機12的直接USB連接，或可包括諸如集 線器之介入USB功能。如圖1中所示，USB周邊設備10可為 經組態用於大量資料儲存之快閃記憶體拇指驅動器（thumb 127934.doc 200842601 dnve)。USB周邊設備包括由主機介面模組（Him) i8、緩 衝器官理單元（BMU) 20、快閃記憶體介面模組（FIM)以及 中央處理單元（CPU) 24組成之USB控制器16。USB控制器 16與USB周邊設備10外部的USB通信線14通信且亦與含於 USB周邊設備丨〇内之快閃記憶體26通信。雖然υ§Β控制器 16之一或多個組件可被組態為分立組件，但在一實施例 中，HIM 18、BMU 20、FIM 22ACPU 24全部被形成於單 一特殊用途積體電路（ASIC)上。又，雖然說明了快閃記憶 體，但涵蓋其他非揮發性記憶體或大量儲存媒體。 現參看圖2，更詳細地展示HIM 1 8。HIM 1 8包括實體層 介面28，諸如用於在一側與USB串列匯流排資料線接合且 在另一側與一UTMI介面接合的USB 2.0實體介面。實體層 介面28自串列流提取時脈資訊及資料、檢查所接收資料中 之錯誤、執行NRZI解碼、位元抽取、串列至並列轉換， 且接著將此資料發送至USB設備核心30。實體層介面28亦 執行相反功能，進而將以UTMI並列資料格式自USB設備 核心30接收之資料轉譯成USB串列資料格式。在一實施 中，UTMI傳輸可為並列30 MHz 16位元匯流排。在其他實 施中，可以用於USB應用之多個數位介面標準中之任一者 來替代UTMI，諸如UTMI+或ULPI。可以多個USB 2.0 PHY IP核心配置中的任一者來實施實體層介面28，諸如彼 等可購得於葡萄牙里斯本（Lisbon)之Chipidea Microelectr0nica S.A·的配置。又，實體層介面28可支援符 合USB 2.0規格之高速（480 Mbps)、全速（12 Mbps)及低速 127934.doc •10· 200842601 (1.5 Mbps)資料傳送速率。 USB設備核心30包括媒體存取控制（MAC)控制器32及直 接記憶體存取（DMA)區塊36。每一者經由微處理器介面40 而與CPU 24通信以允許CPU 24讀取及寫入至USB設備核心 30暫存器、以設置並觸發USB異動且回應USB設備核心30 所報告之異動事件及狀態改變。MAC控制器32經由UTMI 資料路徑而與實體層介面2 8通信、解析自主機接收之所有 USB符記並產生回應封包。另外，MAC控制器32亦負責所 有錯誤檢查、檢查填充產生、USB交握格式、ping命令及 資料回應封包，及必須基於USB時序要求而產生之任何信 號。 DMA區塊36與MAC控制器32通信，且負責在USB設備核 心與BMU 20中之緩衝RAM (BRAM)之間移動所有待傳送 至或傳送自USB周邊設備10中之快閃記憶體26的資料。在 一實施中，當管理諸如USB大量資料輸入或輸出傳送（亦分 別稱為大量資料讀取或寫入傳送）之資料傳送時，DMA區 G 塊36經由USB完全傳送自動化（FTA)介面與USB周邊設備 10中之BMU 20通信，以交換硬體邏輯產生交握信號。諸 .如BVCI介面之資料匯流排連接將DMA區塊36與CPU 24連 接。另外，DMA區塊36維持内容資訊，並在MAC控制器 32與DMA區塊36之間建置可組態FIFO緩衝器42、44。此 等FIFO解耦來自USB協定本身所要求之緊密時序的系統處 理器記憶體匯流排請求，並衡消影響DMA區塊36與MAC 控制器32之間之資料傳送之時序之内部時脈頻率的差異。 127934.doc -11 - 200842601 可為系統中之活動端點之每一者維持多個FIF〇通道。基於 所支援之設備端點之數目，及獲取匯流排並擷取一資料區 塊的最壞情況潛時，確定TX及RX FIFO緩衝器之大小。 在一實施中，USB核心30可為來自PortUgaliLisb〇n之 Chipidea Microelectronica S.A·的 IP核心。亦可使用來自其 他USB IP核心提供者之多個其他Ip核心中的任一者。The memory is configured to transfer the data to or from the mass media. In addition, the controller can include a host interface module that communicates with the backend module and is configured to communicate with the host computer, wherein the backend mode is during the _usb bulk data transfer or write operation The group and host interface modules are configured to communicate with each other about a data transfer state in the USB controller by a hardware logic number. Other features and advantages of the present invention will become apparent upon review of the appended claims. [Embodiment] FIG. 1 is a block diagram showing a general-purpose serial bus (USB) peripheral device 1A connected to a host 12 via a USB communication line 14. The host computer 12 can be a USB port of a personal computer or any electronic component having USB capabilities such as an MP3 player, a mobile phone, or the like. The USB communication line 14 can be a direct USB connection of the USB peripheral device 10 to the host 12 via a standard USB connector, or can include an intervening USB function such as a hub. As shown in Figure 1, USB peripheral device 10 can be a flash memory thumb drive configured for mass data storage (thumb 127934.doc 200842601 dnve). The USB peripheral device includes a USB controller 16 composed of a host interface module (Him) i8, a buffer organ unit (BMU) 20, a flash memory interface module (FIM), and a central processing unit (CPU) 24. The USB controller 16 communicates with the USB communication line 14 external to the USB peripheral device 10 and also with the flash memory 26 included in the USB peripheral device. Although one or more components of the controller 16 can be configured as discrete components, in one embodiment, the HIM 18, BMU 20, FIM 22ACPU 24 are all formed in a single special purpose integrated circuit (ASIC). on. Also, although flash memory is described, other non-volatile memories or mass storage media are contemplated. Referring now to Figure 2, HIM 18 is shown in more detail. The HIM 18 includes a physical layer interface 28, such as a USB 2.0 physical interface for bonding with a USB serial bus data line on one side and a UTMI interface on the other side. The physical layer interface 28 extracts clock information and data from the serial stream, checks for errors in the received data, performs NRZI decoding, bit extraction, serial to parallel conversion, and then sends this data to the USB device core 30. The physical layer interface 28 also performs the inverse function to translate the data received from the USB device core 30 in the UTMI parallel data format into a USB serial data format. In one implementation, the UTMI transmission can be a side-by-side 30 MHz 16-bit bus. In other implementations, UTMI, such as UTMI+ or ULPI, can be used in any of a number of digital interface standards for USB applications. The physical layer interface 28 can be implemented in any of a number of USB 2.0 PHY IP core configurations, such as those available from Chipidea Microelectr 0nica S.A. of Lisbon, Portugal. In addition, the physical layer interface 28 supports high speed (480 Mbps), full speed (12 Mbps) and low speed 127934.doc •10·200842601 (1.5 Mbps) data transfer rates in accordance with USB 2.0 specifications. USB device core 30 includes a media access control (MAC) controller 32 and a direct memory access (DMA) block 36. Each communicates with the CPU 24 via the microprocessor interface 40 to allow the CPU 24 to read and write to the USB device core 30 register to set and trigger USB transactions and to respond to the transaction events reported by the USB device core 30 and The status changes. The MAC controller 32 communicates with the physical layer interface 28 via the UTMI data path, parses all USB tokens received from the host, and generates response packets. In addition, the MAC controller 32 is responsible for all error checking, checking pad generation, USB handshake format, ping commands, and data response packets, as well as any signals that must be generated based on USB timing requirements. The DMA block 36 is in communication with the MAC controller 32 and is responsible for moving all of the data to be transferred to or from the flash memory 26 in the USB peripheral device 10 between the USB device core and the buffer RAM (BRAM) in the BMU 20. . In one implementation, when managing data transfers such as USB mass data input or output transfer (also referred to as mass data read or write transfer, respectively), DMA area G block 36 via USB full transfer automation (FTA) interface and USB The BMU 20 in the peripheral device 10 communicates to exchange the hardware logic to generate a handshake signal. The data bus connection, such as the BVCI interface, connects the DMA block 36 to the CPU 24. In addition, DMA block 36 maintains the content information and builds configurable FIFO buffers 42, 44 between MAC controller 32 and DMA block 36. These FIFOs decouple the system processor memory bus request from the tight timing required by the USB protocol itself and offset the internal clock frequency that affects the timing of data transfer between the DMA block 36 and the MAC controller 32. difference. 127934.doc -11 - 200842601 Multiple FIF〇 channels can be maintained for each of the active endpoints in the system. The size of the TX and RX FIFO buffers is determined based on the number of supported device endpoints, and the worst case latency for obtaining the bus and extracting a data block. In one implementation, the USB core 30 can be an IP core from Chipidea Microelectronica S.A. of PortUgali Lisb〇n. Any of a number of other Ip cores from other USB IP core providers may also be used.
18亦包括FTA暫存器46及FTA邏輯模組48。FTA暫存器46 經組態以接收用於啟用完全傳送自動化模式之設立資訊， 其中如下文更详細描述，USB控制器16可利用硬體產生邏 輯信號而非經由中斷之C P U動作及韌體指令來管理資料區 塊移動至及移動自BRAM。隨著硬體產生邏輯信號遞增一 預期之大量資料傳送中已完成之資料區塊傳送的數目， FTA暫存器亦維持諸如#前傳送狀態之資訊。模組 含有刪控制器16在打八模式中操作時用於產生内部交握 信號之硬體邏輯。辅助介面5〇可含有具有供處理器以處理 諸如CPU睡眠或喚醒常式之各種任務之_的輔助暫存 器。 圖兒月USB控制益16之其餘部分，並展示周邊設備 之决閃。己隐體26(本文中將其組合稱為咖周邊設備⑺之 後端叫。缓衝器管理單元（BMU) 2Q可包括與bram %通 信之自動緩衝管理器(細"4。可以多種方式來分割 56’（例如）以提供用於傳輸或接收待寫人或讀取自 記憶體26之大量資料傳送之資料封包(諸如USB高速應 用中之川位元區塊）的第—緩衝器58及第二缓衝器6〇。 127934.doc -12- 200842601 U 20與在BMU 2〇與快閃記憶體26之間協調的快閃介面 模組（FIM) 22通信。 為在USB周邊設備1G巾實施完全傳送自動化，並相應地 輔助增加資料速度及降低功率消耗，刪周邊設㈣包括 對標準USB控制器架構的若干修改，以使用硬體邏輯在 USB控制器16中提供額外内部交握。可在該控制器之硬體 邏輯中實施用於在HIM 18與後端52之間通信之此等額外内 部交握訊息，以消除某些傳統韌體實施步驟要求涉及 24的需求。 USB標準支援四種傳送/端點類型：控制傳送、中斷傳 迗、等時傳送及大量傳送。如下文指出，大量傳送涉及以 固定長度區塊處理之大資料叢發，且可最大受益於本文中 描述之完全傳送自動化。在一實施中，USB控制器16僅在 大I>料傳送任務期間調用本文描述之完全傳送自動化， 且將多個標準中之任一者或已知的基於CPU之傳送機制用 於專時端點、控制端點或中斷端點。 關於USB標準下之大量資料傳送，提供如圖4中所說明 的三個階段。在第一階段，主機^向!^^周邊設備1〇發送 一 CBW(命令區塊包）訊息，且該訊息被置入緩衝器管理單 元20之BRAM 46中（步驟62處）。CBW訊息為31個位元組且 包括關於USB周邊設備1〇將執行之傳送之類型的資訊。在 接收該CBW訊息後，USB周邊設備中之韌體（例如，在cpu 24之主RAM (MRAM)中）讀取此訊息並將資料寫入HIM 18 中的完全傳送自動化（FTA)暫存器46。下文更詳細地論 127934.doc -13- 200842601 述，FTA暫存器46包括諸如BRAM 56中之起始位址、緩衝 器大小及傳送方向之資訊。在該CBW階段之後，大量資料 傳送之資料階段發生且主機12視CBW訊息中所指示之傳送 方向而將資料封包發送至（大量輸出傳送或寫入操作）USB 周邊设備1 〇或自其接收資料封包（大量輸入傳送或讀取操 作）（步驟64、66處）。USB大量資料傳送之最後階段為結束 主機12與USB周邊設備1〇之間的交換之csw(命令狀態包） 訊息（步驟6 8處）。 參看圖5，在於第一階段中自主機12接收到CBW訊息 後，CPU執行韌體以向FTA暫存器46寫入實施FTA程序所 必需之資料。圖5中之暫存器表76包括表示循環緩衝器 (BRAM)之記憶體單元的記憶體單元位址78、循環緩衝器 基位址80、結束位址82且含有該等BRAM基位址及結束位 址之字位址。當前位址84在FTA傳送進行時由硬體更新， 以指向傳送中當前涉及之記憶體位置。fta暫存器表76亦 包括傳送大小86(依據預期之區塊（資料封包）的總數）。當 前傳送大小88為在正進行之FTA傳送期間由硬體更新的攔 位，其追蹤資料封包已被傳送之數目。傳送描述符鏈接清 單基位址90含有資料傳送描述符（dTD)鏈接清單之字基位 址，傳輸（Tx) 92及接收（RX) 94自動化之傳送自動化控制 含有基於端點控制傳送自動化特徵的資訊，且端點傳送完 成暫存器96指示大量輸出傳送（資料自主機輸出）或大量資 料輸入傳送（資料輸入主機）在已傳送所有資料封包後之结 束狀恶。端點MISC控制98包括用於迫使USB設備核心30在 127934.doc -14- 200842601 自主機之輸出傳送期間以確認（ACK)符記進行回應的指 令。停止傳送控制1〇〇暫存器包括一控制位元以停止完全 傳送自動化過程，且傳送自動化狀態1〇2含有隨著每一資 料傳送描述符及資料查詢標頭設立完成之硬體更新的狀 態。Tx FIFO低標組態暫存器ι〇4界定用於為讀取（IN)傳送 起始對TX FIFO暫存器之預擷取的臨限值。18 also includes an FTA register 46 and an FTA logic module 48. The FTA register 46 is configured to receive setup information for enabling the full transfer automation mode, wherein as described in more detail below, the USB controller 16 can utilize hardware to generate logic signals rather than interrupted CPU actions and firmware. Instructions to manage the movement of data blocks to and from BRAM. The FTA register also maintains information such as the status of the pre-transmission status as the hardware generated logic signal is incremented by the expected number of data block transfers in the bulk data transfer. The module contains hardware logic for generating an internal handshake signal when the controller 16 is operating in the eight mode. The auxiliary interface 5A may contain an auxiliary register having a processor for processing various tasks such as CPU sleep or wake-up routines. The monthly USB control benefits the rest of the 16 and shows the flash of peripheral devices. The hidden body 26 (herein referred to as the coffee peripheral device (7) later called. Buffer Management Unit (BMU) 2Q may include an automatic buffer manager that communicates with the bram % (thin "4. There are many ways to Segmentation 56', for example, to provide a first buffer 58 for transmitting or receiving a data packet to be written to or read from a large amount of data transferred from the memory 26 (such as a channel block in a USB high speed application) and The second buffer 6〇. 127934.doc -12- 200842601 U 20 communicates with the flash interface module (FIM) 22 coordinated between the BMU 2〇 and the flash memory 26. For the USB peripheral device 1G towel Implementing full transfer automation and correspondingly increasing data speed and power consumption, the peripherals (4) include several modifications to the standard USB controller architecture to provide additional internal handshake in the USB controller 16 using hardware logic. These additional internal handshake messages for communication between the HIM 18 and the back end 52 are implemented in the hardware logic of the controller to eliminate the need for some conventional firmware implementation steps to address 24. USB Standard Support Four Transfer/endpoint type : Control Transfer, Interrupt Transfer, Isochronous Transfer, and Mass Transfer. As noted below, mass transfer involves large bursts of data processed in fixed length blocks and can benefit most from the full transfer automation described herein. The USB controller 16 invokes the full transfer automation described herein only during the large I> material transfer task, and uses any of a number of standards or known CPU-based transfer mechanisms for the time-of-day endpoint, control Endpoint or Interrupt Endpoints For the bulk data transfer under the USB standard, three phases are provided as illustrated in Figure 4. In the first phase, the host sends a CBW (command block) to the peripheral device 1〇 The packet is messageed and placed in the BRAM 46 of the buffer management unit 20 (at step 62). The CBW message is 31 bytes and includes information about the type of transmission that the USB peripheral device 1 will perform. After receiving the CBW message, the firmware in the USB peripheral device (for example, in the main RAM (MRAM) of the CPU 24) reads the message and writes the data to the Full Transfer Automation (FTA) register in the HIM 18. 46. More detailed below In detail, the FTA register 46 includes information such as the start address, buffer size, and transfer direction in the BRAM 56. After the CBW phase, a large data transfer data phase occurs. And the host 12 sends the data packet to (a large number of output transfer or write operations) the USB peripheral device 1 or receives the data packet (a large number of input transfer or read operations) according to the transfer direction indicated in the CBW message (step 64, 66) The final stage of USB mass data transfer is to csw (command status packet) message between the host 12 and the USB peripheral device 1 (step 6 8). Referring to Figure 5, after receiving the CBW message from the host 12 in the first phase, the CPU executes the firmware to write to the FTA register 46 the information necessary to implement the FTA program. The register table 76 in FIG. 5 includes a memory unit address 78 representing a memory unit of a circular buffer (BRAM), a circular buffer base address 80, an end address 82, and includes the BRAM base addresses and The address of the end address. The current address 84 is updated by the hardware as the FTA transfer proceeds to point to the memory location currently involved in the transfer. The fta register table 76 also includes the transfer size 86 (based on the total number of blocks (data packets) expected). The current transfer size 88 is the block that was updated by the hardware during the ongoing FTA transfer, which tracks the number of data packets that have been transmitted. The transfer descriptor link list base address 90 contains the base address of the data transfer descriptor (dTD) link list, and the transport (Tx) 92 and receive (RX) 94 automated transport automation controls contain automation features based on endpoint control transfer Information, and the endpoint transfer completion register 96 indicates that a large number of output transfers (data from the host output) or a large number of data input transfers (data entry hosts) have ended after all data packets have been transmitted. The endpoint MISC control 98 includes instructions for forcing the USB device core 30 to respond with an acknowledgement (ACK) token during the output of the 127934.doc - 14 - 200842601 from the host. Stop Transfer Control 1 The scratchpad includes a control bit to stop the full transfer automation process, and the transfer automation state 1〇2 contains the status of the hardware update as each data transfer descriptor and data query header is set up. . The Tx FIFO Low-Scale Configuration Register ι〇4 defines the threshold for pre-fetching of the TX FIFO register for the read (IN) transfer.
L 當啟用USB控制器16之FTA模式並以圖5之資料表76中所 不的資料裝填FTA暫存器46時，USB控制器16亦準備端點 貝料傳达描述符（dTD)及端點資料佇列頭（dQH)資料結構。 在初始資料結構設立中，如圖6中所示，USB控制器16亦 產生FTA啟用資料，該FTA啟用資料包括：一啟用位元 70，其作為將為特定資料傳送資料交換啟用完全傳送自動 化之USB設備核心30的旗標；以及xfer 一方向位元72，其指 示傳送之方向。異動之封包長度1〇6及總預期位元組ι〇8亦 可連同指向每-預期資料封包所需之BRAM緩衝器位址的 DMA指標1〇9-起被記錄於該資料結構中。此等資料結構 可由HIM 18之FTA模組48中之硬體邏輯來產生，或以㈣ 24所執行之韌體來實施。視預期之資料量而定，可能需要 產生-個以上資料結構，以識別處理大量f料傳送中:所 有組成t #區塊所需要之位址集纟中的每一者之指栌 1〇9。彻及_資料結構資訊被寫人至以適當偏移設^ 適應dTD及dQH之大小的心暫存器之傳送指示符鍵接清 单基位址9G所指向的位置。dTD及_資料結構向HIM 18 甲之腿區塊36通知總傳送大小、DMA來源/目的位址及 127934.doc 200842601 其他傳送資訊。 旦CBW訊息已被處理，其中已設立dTD及dQH資料並 產生FTA暫存器中之初始資訊，USB控制器16便準備處理 F T A模式下之資料傳送並消除或減少大量資料傳送中之韌 體以及如圖7中所示，說明利用USB控制器16之FTA模式 的可犯同速设備大罝輸出異動。此實例說明以bram中 存在兩個緩衝器可用於支援資料傳送開始之情況。當主機 12傳輸後面緊跟一資料區塊（亦稱為資料封包）之資料傳送 112之輸出符記110時，大量輸出資料傳送階段開始。假定 刪周邊設備10操作於高速模式下，資料封包大小可為 =2個位元組。USB周邊設備1G在刪_接收資訊並將 資料傳遞至BMU 2G以供儲存於組態於BRAM 56中之緩衝 :58 60中的一者中。BMU 2〇中之abm 54提供指示該等 緩衝时已準備好接收貧訊的硬體邏輯產生信號㈣一吻工 114及buf—rdy2 116。對於大量輸出資料傳送，abm 54基 於冲數BRAM中之空閒緩衝器之數目的緩衝器計數器來產 生^一^及^一吻以^^可使用多個類型之數位計數 器電路中之任一者來形成產生buf—rdyl及buf rdy2之數位 邏輯信號的緩衝器計數器。buf—rdyl信號指示抓趟中至 少一緩衝器之可用十生，且buf—rdy2指示狀趟中兩個或兩 個以上緩衝器之可用性。在此實施例中，術語“緩衝器” 才曰代BRAM中鄰接5 12位元組位置。 在第一資料封包至緩衝器之傳送完成後，由於buf rdy2 及在該傳送開始時皆為M"(高），目此mM _ 127934.doc -16 - 200842601 觸發MAC控制器32以向主機12發送一確認（ACK)l 16訊 息。同時，HIM 18中之FTA模組48經由硬體產生一 ”早期 釋放”信號脈衝，該信號脈衝被傳達回至BMU 20以向BMU 2 0通知該資料封包之傳送已完成。回應於此釋放信號， BMU 20確定buf一rdy2為兩個或兩個以上緩衝器不可用之事 實的較低表示。又，BMU可接著指導FIM 22開始將此資料 寫入快閃記憶體26。 在USB周邊設備10處接收來自主機之下一輸出符記，且 伴隨之負料封包傳送將貧料置於BRAM 56中兩個專用緩衝 器中的第二緩衝器中。HIM 1 8於該傳送開始時解譯其狀態 表中的buf一rdyl與buf一rdy2之組合，並向主機12發送出 NYET 父握訊* 息 120 (buf—rdy2 = 0，buf—rdyl = l)。同時， HIM 18向後端中之BMU 20發送另一早期釋放信號122(或 等同的最終釋放信號），以使得BMU 20知道該傳送已完 成。在通知此釋放後，後端52經由BMU 20除了發送已為 低之buf一 rdy2信號外，還發送一 buf—rdyl低信號來向HIM 18指示目前無緩衝器58、60可用。NYET訊息120向主機12 傳達前一資料傳送被接收，但主機12在未首先檢查狀態的 情況下可能不發送更多資訊。在圖7之情形中，主機丨2向 USB周邊設備1〇發送PING符記124。注意，buf—rdy2及 buf一 rdyl #號皆處於邏輯低，表示當前無緩衝器可用， HIM 1 8以NAK回應126進行回應。當該等緩衝器中之一者 k得可用時（由ABM 54硬體邏輯所產生之buf_r(iyi之邏輯 向没定來表示），USB周邊設備自主機接收後續PINg，且 127934.doc -17- 200842601 HIM以ACK回應128進行回應，藉以通知主機準備就緒接 收後續資料。 在圖7之實例中，對於大量輸出資料傳送，緩衝器準備 就緒信號（buf—rdy2及buf—rdyl)為BMU 20中之自動緩衝管 理器44所產生之硬體信號。硬體實施信號可基於回應於佔 用第一緩衝器48及第二緩衝器50之資料的基本數位邏輯， 其中buf—rdy2可係自BMU 20中維持存在於BRAM 56中之有 效緩衝器之計數的計數器得出。若來自該計數器之計數值 超過一臨限值，則ABM將確定_buf—rdy2高信號。該臨限 值為可組態的且可藉由韌體來設定。在USB資料傳送中， 臨限值被設定為2。當BMU中之計數器之計數值大於或等 於1時，ABM 54中之額外硬體實施邏輯產生一匕乙以^高 信號。因此，當兩個緩衝器皆準備就緒時，ABM所產生並 發达至HIM的buf—rdyl及buf—rdy2交握信號皆為高，當兩 個緩衝器皆未準備就緒時，兩個交握信號皆為低，且當僅 一個緩衝器可用時，buf-rdyl為高且buf—rdy2為低。在一 實施中，使用計數器產生buf—rdy i及buf—rdy2信號以識別 BRAM 56中空閒緩衝器之數目。 HIM 18利用buf—rdyl及buf—rdy2之緩衝器可用性信號來 產生對自主機12接收之OUT及PING符記的回應。圖8中展 不USB控制器16回應於buf—rdyl及buf—rdy2信號的三個有 效組合而為0UTR記及為PING符記所產生之USB交握封包 的狀悲表130。當兩個緩衝器皆準備好（兩個可用性信號皆 處於邏輯而或丨）時，HIM 18答覆OUT或PING符記而產生一 127934.doc -18- 200842601 ACK回應封包。當兩個緩衝器皆不可用（兩個可用性信號 皆處於邏輯低或0)時，HIM 18答覆OUT或pING符記而產生 一NAK回應封包。當僅1個緩衝器準備好時，所產生之回 應封包對於OUT符記及PING符記係不同的··為piNG產生 ACK且為OUT產生NYET。 在相反方向上，亦產生自HIM 18至後端52中之BMU 2〇 的交握信號，早期釋放信號及最終釋放信號為可實施為 HIM 18之FTA模組38中之數位邏輯的硬體產生邏輯信號。 ( 視USB控制器16正在處理大量輸出資料傳送（圖7中所見之 傳送的實例）還是大量輸入資料傳送（圖9中所示之傳送的實 例）而定，FTA模組38使早期釋放交握訊息及最終釋放交握 訊息基於不同輸入資訊。對於大量輸出資料傳送，早期釋 放仏號與最終釋放信號等同。在大量輸出資料傳送之情況 下，FTA模組48自USB核心30之MAC控制器32所產生之成 f資料封包傳送信號導出早期釋放信號。對於高速刪大 S輸出傳送，-旦接收到—5 12位元組封包便觸發成功資 I ㈣包傳送信號。在資料封包大小可為64個位元組的全速 或低速USB大量輸出傳送之情況下，在觸發早期釋放/最終 . 釋放信號之前，使用MAC控制器資訊來計數8個成功資料 封包傳送。 參看圖9，使用上文論述之緩衝器可用性及 及緩衝器釋放（㈣釋放及最終釋放）硬體產生交 握訊息來說明大量輸入傳送情形。在大量輸入傳送中，將 資料自USB周邊設備中之快閃記憶體傳送至主機。類似於 127934.doc •19- 200842601 大量輸出傳送，CBW訊息被HIM 18接收，該HIM 18將 CBW訊息置於BMU 20之BRAM 56中。HIM 18接著通知 CPU 24 CBW訊息已被接收，且CPU 24接著自BRAM 56讀 取該訊息並初始化HIM中之FTA暫存器48。CBW訊息中所 指示之資料量所必需之資料傳送指示符及資料佇列頭被產 生，且FIM 22開始自快閃記憶體26將資料封包讀取至 BRAM56之緩衝器中。再次假定BRAM46中有兩個緩衝器 組態，一旦來自第一緩衝器之資料自BMU傳輸至HIM， HIM 18便向BMU 20發送一早期釋放邏輯脈衝。 早期釋放硬體信號係由FTA模組48產生。在此例項中， 早期釋放硬體信號及最終釋放硬體信號由於FTA模組48分 別導出早期釋放信號及最終釋放信號而不同。BMU 20使 用早期釋放信號為預填充傳輸（讀取）資料至TX FIF〇 44檢 查緩衝器可用性。若當BRAM中之緩衝器未準備好時BMU 接收一早期釋放信號，則BMU否定buf 一 rdyl信號（亦即，該 信號變低）’以防止HIM 18自該緩衝β預擷取資料。在大 量輸入資料傳送中，當ΗΙΜ 18起始自TX FIF0 44向主機12 發送讀取資料時，FTA模組48基於產生於MAC控制器32中 之邏輯信號來產生一早期釋放。最終釋放信號證實早期釋 放，並向BMU發信：既然已自主機接收到ACK回應，則可 最終釋放封包。FTA模組48基於產生於MAC控制器32中的 指示自主機接收到ACK之邏輯信號而產生最終釋放信號。 由於來自MAC控制器32之此等信號係在不同於FTA模組48 所使用之時脈頻域中產生’因此該FTA模組亦包括將mac 127934.doc •20- 200842601 控制器32信號自MAC控制器之USB PHY時脈域轉換成FTA 模組藉以操作之系統時脈域的電路。 圖9之大量輸入傳送情形中的第一早期釋放信號132向 ΒΜϋ 20指示：若第二BRAM緩衝器50可用，則現在適合將 輸入讀取資料填充於該緩衝器之緩衝器空間中。歸因於快 閃記憶體26與BRAM緩衝器58、60之間的通常比自BRAM 緩衝器58、60經由HIM 18至主機12更慢的資料傳送速率，When the FTA mode of the USB controller 16 is enabled and the FTA register 46 is loaded with the data not shown in the data table 76 of FIG. 5, the USB controller 16 also prepares the endpoint feed descriptor (dTD) and the end. Point data column header (dQH) data structure. In the initial data structure setup, as shown in FIG. 6, the USB controller 16 also generates FTA enablement material, the FTA enablement material including: an enable bit 70 that will enable full transfer automation for specific data transfer data exchanges. The flag of the USB device core 30; and the xfer one direction bit 72, which indicates the direction of the transfer. The packet length 1〇6 and the total expected byte ι8 can also be recorded in the data structure along with the DMA indicator 1〇9 pointing to the BRAM buffer address required for each-expected data packet. Such data structures may be generated by hardware logic in the FMA module 48 of the HIM 18, or implemented in (4) 24 firmware. Depending on the amount of data expected, it may be necessary to generate more than one data structure to identify the processing of a large number of f-material transfers: all indicators of each of the address sets required to form the t# block 1栌9 . The data structure information is written to the location pointed to by the single base address 9G by the transfer indicator of the heart register which is adapted to the size of dTD and dQH. The dTD and _ data structures inform the HIM 18 leg leg block 36 of the total transfer size, DMA source/destination address, and other transmission information for 127934.doc 200842601. Once the CBW message has been processed, where the dTD and dQH data have been created and the initial information in the FTA register is generated, the USB controller 16 is ready to handle the data transfer in the FTA mode and eliminate or reduce the firmware in the bulk data transfer and As shown in FIG. 7, it is explained that the FTA mode of the USB controller 16 can be used to make a large-scale output transaction. This example shows that there are two buffers in the bram that can be used to support the start of data transfer. When the host 12 transmits an output token 110 followed by a data transfer 112 of a data block (also referred to as a data packet), a large number of output data transfer phases begin. Assuming that the peripheral device 10 is operating in the high speed mode, the data packet size can be = 2 bytes. The USB peripheral device 1G deletes the received information and passes the data to the BMU 2G for storage in one of the buffers: 58 60 configured in the BRAM 56. The abm 54 in the BMU 2 provides a hardware logic generating signal (4) a kisser 114 and a buf-rdy2 116 indicating that the buffer is ready to receive the poor. For a large amount of output data transfer, abm 54 generates a ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ A buffer counter that generates digital logic signals for buf-rdyl and buf rdy2 is formed. The buf-rdyl signal indicates that at least one of the buffers is available, and buf-rdy2 indicates the availability of two or more buffers in the buffer. In this embodiment, the term "buffer" replaces the 5 12-bit position in the BRAM. After the transfer of the first data packet to the buffer is completed, since buf rdy2 and M" (high) at the beginning of the transfer, the MM_127934.doc -16 - 200842601 triggers the MAC controller 32 to the host 12 Send an acknowledgment (ACK) 16 message. At the same time, the FTA module 48 in the HIM 18 generates an "early release" signal pulse via the hardware that is communicated back to the BMU 20 to inform the BMU 20 that the transfer of the data packet has been completed. In response to this release signal, BMU 20 determines that buf-rdy2 is a lower representation of the fact that two or more buffers are unavailable. Again, the BMU can then instruct the FIM 22 to begin writing this data to the flash memory 26. An output token from the host is received at the USB peripheral 10, and the accompanying negative packet transfer places the poor material in a second buffer in the two dedicated buffers in the BRAM 56. HIM 18 interprets the combination of buf-rdyl and buf-rdy2 in its state table at the beginning of the transfer, and sends a NYET parent handshake* to host 12 (buf_rdy2 = 0, buf_rdyl = l ). At the same time, the HIM 18 sends another early release signal 122 (or equivalent final release signal) to the BMU 20 in the back end to cause the BMU 20 to know that the transfer has been completed. After notifying this release, the back end 52 sends a buf_rdyl low signal via the BMU 20 in addition to the already low buf-rdy2 signal to indicate to the HIM 18 that no buffers 58, 60 are currently available. The NYET message 120 conveys to the host 12 that the previous data transfer was received, but the host 12 may not send more information without first checking the status. In the case of Fig. 7, the host port 2 transmits a PING tag 124 to the USB peripheral device 1A. Note that both buf_rdy2 and buf-rdyl# are both logic low, indicating that no buffer is currently available, and HIM 18 responds with a NAK response 126. When one of the buffers is available (buf_r generated by the ABM 54 hardware logic), the USB peripheral receives the subsequent PINg from the host, and 127934.doc -17 - 200842601 The HIM responds with an ACK response 128 to inform the host that it is ready to receive subsequent data. In the example of Figure 7, for a large number of output data transfers, the buffer ready signals (buf-rdy2 and buf-rdyl) are in the BMU 20 The hardware signal generated by the automatic buffer manager 44. The hardware implementation signal may be based on basic digital logic responsive to the data occupying the first buffer 48 and the second buffer 50, where buf-rdy2 may be from the BMU 20. A counter that maintains the count of valid buffers present in BRAM 56 is derived. If the count from the counter exceeds a threshold, ABM will determine the _buf-rdy2 high signal. The threshold is configurable. It can be set by firmware. In the USB data transmission, the threshold is set to 2. When the counter value of the counter in the BMU is greater than or equal to 1, the additional hardware implementation logic in the ABM 54 generates a ^高信Therefore, when both buffers are ready, the buf-rdyl and buf-rdy2 handshake signals generated by ABM and developed to HIM are high. When both buffers are not ready, the two handshakes are The signals are all low, and buf-rdyl is high and buf-rdy2 is low when only one buffer is available. In one implementation, the counter is used to generate the buf-rdy i and buf-rdy2 signals to identify the free buffer in BRAM 56. The number of devices. The HIM 18 utilizes the buffer availability signals of buf-rdyl and buf-rdy2 to generate responses to the OUT and PING tokens received from the host 12. In Figure 8, the USB controller 16 responds to buf-rdyl and The three valid combinations of the buf-rdy2 signal are 0UTRs recorded as the sorrow table 130 of the USB handshake packet generated by the PING token. When both buffers are ready (both usability signals are in logic or 丨When the HIM 18 answers the OUT or PING token to generate a 127934.doc -18- 200842601 ACK response packet. When both buffers are unavailable (both availability signals are at logic low or 0), the HIM 18 reply OUT or pING token to generate a NAK response packet. When only one buffer is ready, the resulting response packet is different for the OUT token and the PING token. · Generates an ACK for piNG and NYET for OUT. In the opposite direction, it also generates from HIM 18 to the back end. The BMU 2〇 handshake signal, the early release signal and the final release signal in 52 are hardware-generated logic signals that can be implemented as digital logic in the FMA module 38 of the HIM 18. (Depending on whether the USB controller 16 is processing a large amount of output data transfer (an example of the transfer seen in Figure 7) or a large amount of input data transfer (an example of the transfer shown in Figure 9), the FTA module 38 enables early release of the handshake. The message and the final release handshake message are based on different input information. For a large amount of output data transmission, the early release nickname is equivalent to the final release signal. In the case of a large amount of output data transmission, the FTA module 48 is from the USB core 30 of the MAC controller 32. The generated data packet transmission signal derives the early release signal. For the high-speed large S output transmission, the -5 12-bit packet is received to trigger the successful I (four) packet transmission signal. The data packet size can be 64. In the case of a full-speed or low-speed USB mass output transmission of a single byte, the MAC controller information is used to count 8 successful data packet transmissions before triggering the early release/final. release signal. Referring to Figure 9, using the above discussion Buffer availability and buffer release ((4) release and final release) hardware generates a handshake message to illustrate a large number of input transfer scenarios. In the transfer, the data is transferred from the flash memory in the USB peripheral device to the host. Similar to 127934.doc •19- 200842601 A large number of output transmissions, the CBW message is received by the HIM 18, and the HIM 18 places the CBW message on the BMU 20 The BRAM 56. The HIM 18 then notifies the CPU 24 that the CBW message has been received, and the CPU 24 then reads the message from the BRAM 56 and initializes the FTA register 48 in the HIM. The amount of data indicated in the CBW message is required. The data transfer indicator and data header are generated, and the FIM 22 begins reading the data packet from the flash memory 26 into the buffer of the BRAM 56. Again assume that there are two buffer configurations in the BRAM 46, once from the first The buffer data is transmitted from the BMU to the HIM, and the HIM 18 sends an early release logic pulse to the BMU 20. The early release hardware signal is generated by the FTA module 48. In this example, the early release of the hardware signal and the final release The hardware signal differs because the FTA module 48 derives the early release signal and the final release signal, respectively. The BMU 20 uses the early release signal to pre-fill the transmitted (read) data to the TX FIF 〇 44 to check the buffer availability. If the BMU receives an early release signal when the buffer in the BRAM is not ready, the BMU negates the buf-rdyl signal (ie, the signal goes low) to prevent the HIM 18 from prefetching data from the buffer β. In a large amount of input data transfer, when ΗΙΜ 18 starts to send read data from TX FIF0 44 to host 12, FTA module 48 generates an early release based on the logic signal generated in MAC controller 32. The final release signal confirms early Release and send a message to the BMU: Since an ACK response has been received from the host, the packet can eventually be released. The FTA module 48 generates a final release signal based on a logic signal generated in the MAC controller 32 indicating that an ACK was received from the host. Since the signals from the MAC controller 32 are generated in a different frequency domain than the one used by the FTA module 48, the FTA module also includes the mac 127934.doc • 20- 200842601 controller 32 signal from the MAC. The controller's USB PHY clock domain is converted to the circuitry of the system clock domain through which the FTA module operates. The first early release signal 132 in the bulk input transfer scenario of Figure 9 indicates to ΒΜϋ 20 that if the second BRAM buffer 50 is available, it is now appropriate to fill the input read data into the buffer space of the buffer. Due to the slower data transfer rate between flash memory 26 and BRAM buffers 58, 60 than from BRAM buffers 58, 60 via HIM 18 to host 12,
HIM 18將自BRAM向TX FIFO暫存器44預擷取資料，並同 時將資料自TX FIFO 44暫存器發送至主機12。僅在自主機 接收到指示先前資料封包成功接收之ACK訊息136後，自 HIM 18向BMU 20發送最終釋放硬體信號134。圖7中說明 第二IN符記138及第三IN符記140以及資料傳送封包142、 144。在第二傳送與第三傳送之間，存在由於USB周邊設 備10未自主機接收到ACK訊息而產生於該USB周邊設備内 的匯流排逾時146。由於未自主機接收到確認，因此him 未產生最終釋放信號且未見到下一傳送之早期釋放信號。 此係由於在不存在首次嘗試被正確接收之確認的情況下必 須再次發送來自第二傳送之相同資料。以上實例假定 b*dyl信號始終為高，指示快閃記憶體26已完成一讀取 細作且BRAM緩衝ϋ中之有效資料可用。若謂㈣定該緩 衝器由於某原因而未準備妊，目丨k 个干W奸，則buf—rdy 1信號可保持為低 且HIM 18可基於此buf rdvWK e~ - yl低#號而向主機傳輸一NAK交 握封包。 ，FTA引擎48在 在USB大量資料輸人或輸出傳送結束時 127934.doc -21 - 200842601 達到傳送大小86時自動僖+俏、、， 目勖知止傳迗。亦在一大量傳送結束 時’自主機接收到對咖訊息之請求。作為回應，動體準 備CSW且亦在大量傳送結束時將其發送回至主機。作為回 體準備CSW且將其發送回至主機。在心啟用之大 T資料傳送進行的同0主 j 返仃的冋時，此實施不阻礙至其他端點之 送。 在大置輸出傳送情形及大量輸人傳送情形巾皆說明了產 生於HIM 18及BMU 2G中的提供硬體交握以增加刪周邊 設備讀取及寫人資料之能力的硬體信號之使用。每一資料 叢發未使用或需要要求CPU干預之勃體中斷。在不需要參 與及中斷的情況下將資料傳送入或傳送出快閃記憶體(及 大體而言USB周邊設備）避免觸發、由cpu讀取，且作用於 中斷所必而的時間。邏輯上結果是’在此資料傳送階段期 間將不需要CPU活動，且因此可節省USB周邊設備之總功 率使用。 使用硬體交握在後端與η〗M之間進行關於緩衝器空間可 用性通信的另一優點在於，可將緩衝器中之記憶體大小維 持於較低位準，從而釋放為其他使用而另外規劃之緩衝記 憶體。另外，在不需要中斷及CPUt預的情況下，cpu額 外耗用被降低且與需要韌體追蹤資料傳送及管理緩衝器空 間的實施相比可降低CPU時脈速度。基於較低Cpu額外耗 用之較低時脈速度實施亦可有助於額外功率節省。 雖然已提供USB控制器16中之後端52之實例（其中已分 配兩個緩衝器用於實施大量資料傳送操作之FTA模式），但 127934.doc -22- 200842601 在其他實施中，可僅使用單一緩衝器。該緩衝器可具有單 一資料傳送區塊（封包）之大小。或者’上文描述之USB控 制器及方法同樣可經調適成使用BRAM中之兩個以上緩衝 器，其中該等緩衝器中之每一者可與資料封包具有相同大 小。在其他實施中，例如當以全速模式或低速模式（分別 為12百萬位元每秒或1 · 5百萬位元每秒’而非南速模式之 480百萬位元每秒）執行USB周邊設備時’ FTA操作模式可 經調整而適應全速模式或低速模式中支援之64位元組資料 封包大小。在其他實施中’ USB周邊設備10可經組態成相 當於一主機並如所描述將相同FTA模式用於大ϊ傳送操 作。又，雖然論述了特定資料封包大小’例如對於高速為 5 12個位元組且對於全速及低速為64個位元組’但可根據 選擇用於USB周邊設備之後端中的快閃記憶體類型而將後 端所處理之此資料大小設定為其他長度。 以下同時申請（2006年12月31曰）、共同擁有之美國專利 申請案（藉由美國專利申請案序號’’USSN’’引用）之整體以引 用的方式併入本文中："Selectively Powering Data Interfaces，，（具有 USSN 1 1/649,325 及代理人參考號SDA-1076x) ; “ Selectively Powered Data Interfaces，，（具有 USSN ll/649,326 及代理人參考號 SDA-1076y); "Internally Protecting Lines at Power Island Boundaries”（具有 USSN 1 1/618,874 及代理人參考號 SDA_1090x) ; "Integrated Circuit with Protected Internal Isolation” （具有 USSN 1 1/618,875及代理人參考號SDA-1090y) ; ’’Updating Delay 127934.doc -23- 200842601The HIM 18 will prefetch data from the BRAM to the TX FIFO register 44 and simultaneously send the data from the TX FIFO 44 register to the host 12. The final released hardware signal 134 is sent from the HIM 18 to the BMU 20 only after receiving an ACK message 136 from the host indicating that the previous data packet was successfully received. The second IN symbol 138 and the third IN symbol 140 and the data transfer packets 142, 144 are illustrated in FIG. Between the second transmission and the third transmission, there is a bus timeout 146 generated in the USB peripheral device due to the USB peripheral device 10 not receiving the ACK message from the host. Since no acknowledgment is received from the host, he does not produce a final release signal and does not see an early release signal for the next transmission. This is because the same data from the second transmission must be resent in the absence of an acknowledgment that the first attempt was received correctly. The above example assumes that the b*dyl signal is always high, indicating that the flash memory 26 has completed a read and that the valid data in the BRAM buffer is available. If (4) the buffer is not prepared for some reason, and the target is k, the buf-rdy 1 signal can be kept low and the HIM 18 can be based on the buf rdvWK e~ - yl low ## The host transmits a NAK handshake packet. The FTA engine 48 is automatically 僖 俏 俏 、 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , A request for a coffee message is also received from the host at the end of a large number of transfers. In response, the mobile prepares the CSW and also sends it back to the host at the end of the bulk transfer. Prepare the CSW as a backhaul and send it back to the host. This implementation does not hinder the delivery to other endpoints when the heart is enabled for the T-data transfer. The use of hardware signals generated in HIM 18 and BMU 2G to provide hardware handshake to increase the ability of peripheral devices to read and write data is described in both the large output transmission situation and the large number of input transmission scenarios. Each piece of information is not used or requires a disruption of the body that requires CPU intervention. Transferring data into or out of flash memory (and, in general, USB peripherals) without the need for participation and interruption. Avoid triggering, reading by cpu, and the time necessary for interrupts. The logical result is that 'CPU activity will not be required during this data transfer phase, and thus the total power usage of USB peripherals can be saved. Another advantage of using hard-handed grips for buffer space availability communication between the back end and η M is that the memory size in the buffer can be maintained at a lower level, thereby releasing for other uses. Planning buffer memory. In addition, without the need for interrupts and CPUt pre-emption, the extra CPU consumption is reduced and the CPU clock speed can be reduced compared to the implementation that requires firmware trace data transfer and management buffer space. Lower clock speed implementations based on additional CPU overhead can also contribute to additional power savings. Although an example of the rear end 52 in the USB controller 16 has been provided (in which FBA mode has been allocated for implementing a large number of data transfer operations), 127934.doc -22- 200842601 In other implementations, only a single buffer may be used. Device. The buffer can have the size of a single data transfer block (packet). Alternatively, the USB controller and method described above can be adapted to use more than two buffers in the BRAM, wherein each of the buffers can be the same size as the data packet. In other implementations, such as when performing USB in full speed mode or low speed mode (12 megabits per second or 1.25 megabits per second instead of 480 megabits per second in south speed mode) Peripheral device's FTA mode of operation can be adjusted to accommodate 64-bit data packet sizes supported in full-speed mode or low-speed mode. In other implementations, the USB peripheral device 10 can be configured to operate as a host and use the same FTA mode for the large transfer operation as described. Also, although the specific data packet size is discussed, 'for example, 5 12 bytes for high speed and 64 bytes for full speed and low speed', but can be selected for the type of flash memory in the rear end of the USB peripheral device. The size of this data processed by the backend is set to other lengths. The following simultaneous application (December 31, 2006), co-owned US patent application (referenced by US Patent Application Serial No. 'USSN'') is incorporated herein by reference: "Selectively Powering Data Interfaces,, (with USSN 1 1/649, 325 and agent reference number SDA-1076x); "Selectively Powered Data Interfaces,, (with USSN ll/649, 326 and agent reference number SDA-1076y); "Internally Protecting Lines at Power Island Boundaries" (with USSN 1 1/618, 874 and agent reference number SDA_1090x); "Integrated Circuit with Protected Internal Isolation" (with USSN 1 1/618, 875 and agent reference number SDA-1090y); ''Updating Delay 127934. Doc -23- 200842601
Trim Values，’（具有USSN 1 1/618,897及代理人參考號80八-1091x) ； "Module with Delay Trim Value Updates on Power-Up，，（具有USSN 1 1/618,898及代理人參考號80八-1091y) ; ’’Limiting Power Island Inrush Current”（具有 USSN 1 1/618,855 及代理人參考號 SDA-1092x); "Systems and Integrated Circuits with Inrush-Limited Power Islands” (具有USSN 1 1/618,854及代理人參考號SDA-1092y); "Method for Performing Full Transfer Automation in a USB Controller，，（具有USSN 1 1/618,865及代理人參考號80八-1094x(10519/201)) ； "USB Controller with Full Transfer Automation”（具有USSN 1 1/61 8,867及代理人參考號80八-1094y (10519/202) ； "Method for Configuring a USB PHY to Loopback Mode·’（具有 USSN 1 1/618,849及代理人參考號 SDA-1095x (10519/203));及"Apparatus for Configuring a USB PHY to Loopback Mode”（具有 USSN 1 1/618,852 及代 理人參考號 SDA-1095y (10519/204))。 根據前述内容，已描述用於在USB控制器中實施完全傳 送自動化之方法及裝置。已在USB周邊設備中之USB控制 器内部提供了四個新的硬體產生邏輯信號以用於主機介面 模組與後端模組之間的交握。經由硬體邏輯而非經由使用 韌體及微處理器時間所產生之内部交握信號可改良資料傳 送速度並降低USB控制器之功率消耗。 因此，意欲將前述實施方式視作說明性的而非限制性 的，且應瞭解，以下申請專利範圍（包括所有等效物）意欲 127934.doc -24- 200842601 界定本發明之精神及範疇。 【圖式簡單說明】 圖1為與一主機連接之USB周邊設備的方塊圖。 圖2為圖iiUSB周邊設備中之主機介面模組的方塊圖。 圖3為適合用於圖iiUSB周邊設備中的USB控制器之後 端的方塊圖。 圖4為一USB大量傳送操作之流程圖。 圖5為促進圖i至圖3之USB周邊設備中之完全傳送自動Trim Values, '(with USSN 1 1/618, 897 and agent reference number 80 8-1091x); "Module with Delay Trim Value Updates on Power-Up,, (with USSN 1 1/618, 898 and agent reference number 80 -1091y) ; ''Limiting Power Island Inrush Current' (with USSN 1 1/618,855 and agent reference number SDA-1092x); "Systems and Integrated Circuits with Inrush-Limited Power Islands" (with USSN 1 1/618,854 and Agent reference number SDA-1092y); "Method for Performing Full Transfer Automation in a USB Controller,, (with USSN 1 1/618, 865 and agent reference number 80 eight-1094x (10519/201)); "USB Controller With Full Transfer Automation" (with USSN 1 1/61 8,867 and agent reference number 80 eight-1094y (10519/202); "Method for Configuring a USB PHY to Loopback Mode·' (with USSN 1 1/618,849 and agent Person reference number SDA-1095x (10519/203)); and "Apparatus for Configuring a USB PHY to Loopback Mode" (with USSN 1 1/618,852 and agent reference number SDA-1095y (10519/204)). Contents, methods and apparatus for implementing full transfer automation in a USB controller have been described. Four new hardware generated logic signals have been provided within the USB controller in the USB peripheral for host interface modules and The handshake between the back-end modules. The data transfer speed is reduced and the power consumption of the USB controller is reduced via hardware logic rather than via the internal handshake signals generated by the firmware and microprocessor time. The foregoing embodiments are to be considered as illustrative and not restrictive, and the scope of the claims BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a USB peripheral device connected to a host. 2 is a block diagram of a host interface module in the USB peripheral device of FIG. Figure 3 is a block diagram of the rear end of a USB controller suitable for use in the USB peripheral device of Figure ii. Figure 4 is a flow chart of a USB mass transfer operation. Figure 5 is a diagram showing the automatic transfer of the USB peripheral devices of Figures i to 3
化而準備之資料的暫存器表。 圖6為用於圖iiUSB周邊設備中之大量資料傳送的資料 結構。 、 圖7為利用KrUSB周邊設備的咖高速大量輸出異動 之一實例。 圖:為說明用於回應於大量資料傳送符記之接收而產生 USB交握封包之邏輯的狀態表。 圖9為利用^之腦周邊設備之刪高速大量輸入異動 【主要元件符號說明】 10 USB 12 主機 14 USB 16 USB 18 主機 20 緩衝 127934.doc 周邊設備 通信線 控制器 介面模組（HIM) 器管理單元（BMU) • 25 - 200842601 22 24 26 28 30 32 36 38 40 42 44 46 48 50 52 54 56 58 60 70 72 76 127934.doc 快閃記憶體介面模組（FIM) 中央處理單元（CPU) 快閃記憶體 實體層介面 USB設備核心 媒體存取控制（MAC)控制器 直接記憶體存取（DMA)區塊 完全傳送自動化（FTA)模組 微處理器介面 可組態FIFO緩衝器 可組態FIFO緩衝器/自動緩衝管理器/TX FIFO/TX FIFO 暫存器 完全傳送自動化（FTA)暫存器 完全傳送自動化（FTA)邏輯模組/第一緩衝器/ FTA引擎 輔助介面/第二緩衝器/第二BRAM緩衝器 後端 自動緩衝管理器（ABM)A register table of information prepared. Figure 6 is a data structure for a large amount of data transfer in the USB peripheral device of Figure ii. Figure 7 is an example of a high-speed output error transaction using a KrUSB peripheral device. Figure: A state diagram for illustrating the logic for generating a USB handshake packet in response to receipt of a large number of data transfer tokens. Figure 9 shows the use of the brain peripheral device to delete a large number of input variables [main component symbol description] 10 USB 12 host 14 USB 16 USB 18 host 20 buffer 127934.doc peripheral device communication line controller interface module (HIM) management Unit (BMU) • 25 - 200842601 22 24 26 28 30 32 36 38 40 42 44 46 48 50 52 54 56 58 60 70 72 76 127934.doc Flash Memory Interface Module (FIM) Central Processing Unit (CPU) Fast Flash Memory Physical Layer Interface USB Device Core Media Access Control (MAC) Controller Direct Memory Access (DMA) Block Full Transfer Automation (FTA) Module Microprocessor Interface Configurable FIFO Buffer Configurable FIFO Buffer/Automatic Buffer Manager/TX FIFO/TX FIFO Scratchpad Full Transfer Automation (FTA) Scratchpad Full Transfer Automation (FTA) Logic Module / First Buffer / FTA Engine Auxiliary Interface / Second Buffer / Second BRAM Buffer Backend Auto Buffer Manager (ABM)
BRAM 第一緩衝器/BRAM緩衝器 第二緩衝器/BRAM缓衝器 行3_啟用位元 xfer_*向位元 暫存器表/ FTA暫存器表/資料表 -26- 200842601 78 記憶體單元位址 80 循環緩衝器基位址 82 循環缓衝器結束位址 84 循環缓衝器當前位址 86 傳送大小 88 當前傳送大小 90 傳送描述符鏈接清單基位址 92 傳輸（Tx)傳送自動化控制 94 接收（Rx)傳送自動化控制 96 端點傳送完成暫存器 98 端點MISC控制 100 停止傳送控制 102 傳送自動化狀態 104 Tx FIFO低標組態暫存器 106 封包長度 108 總位元組 109 DMA指標 110 輸出符記 112 資料傳送 114 硬體邏輯產生信號buf_rdy 1 116 硬體邏輯產生信號bixf_rdy2信號/確認（ACK) 120 NYET交握訊息 122 另一早期釋放信號 124 PING符記 127934.doc •27- 200842601 126 ΝΑΚ回應 128 ACK回應 130 狀態表 132 第一早期釋放信號 134 最終釋放硬體信號 136 ACK訊息 138 第二IN符記 140 第三IN符記 142 資料傳送封包 144 資料傳送封包 146 匯流排逾時 ί 127934.doc -28-BRAM First Buffer/BRAM Buffer Second Buffer/BRAM Buffer Line 3_Enable Bits xfer_* to Bit Unit Register Table / FTA Register Table / Data Sheet -26- 200842601 78 Memory Unit Address 80 Circular Buffer Base Address 82 Circular Buffer End Address 84 Circular Buffer Current Address 86 Transfer Size 88 Current Transfer Size 90 Transfer Descriptor Link List Base Address 92 Transfer (Tx) Transfer Automation Control 94 Receive (Rx) Transfer Automation Control 96 Endpoint Transfer Complete Register 98 Endpoint MISC Control 100 Stop Transfer Control 102 Transfer Automation Status 104 Tx FIFO Low Label Configuration Register 106 Packet Length 108 Total Bytes 109 DMA Indicator 110 Output Symbol 112 Data Transfer 114 Hardware Logic Generate Signal buf_rdy 1 116 Hardware Logic Generate Signal bixf_rdy2 Signal/Acknowledge (ACK) 120 NYET Rush Message 122 Another Early Release Signal 124 PING Symbol 127934.doc •27- 200842601 126 ΝΑΚRespond 128 ACK Response 130 Status Table 132 First Early Release Signal 134 Final Release Hardware Signal 136 ACK Message 138 Second IN Symbol 140 Ί 127934.doc -28- IN token packet 144 when transmitting data bus 146 transmits the packet data over 142