TWI355591B

TWI355591B - Usb apparatus and usb system

Info

Publication number: TWI355591B
Application number: TW94138770A
Authority: TW
Inventors: Chun Ting Liao; An Ming Lee; Jun-Jie Xie; Ying-Hui Zhu
Original assignee: Realtek Semiconductor Corp
Priority date: 2005-11-04
Filing date: 2005-11-04
Publication date: 2012-01-01
Also published as: TW200719154A

Description

1355591 ^ ： k〆 < V'· X. •-夕 > / . 九、發明說明：【發明所屬之技術領域】本發明提供-種通用串列區流排(USB)裝置以及通用串列匯机排系統’尤指-種不需要精確解元件的通用㈣匯流排⑽ 裝置以及通用串列匯流排系統。【先前技術】 • 通用串列匯流排(USB)是目前電腦系統上常見的-種串列傳輸"面由於其連接方式非常方便，且傳輸速度很高（usb2〇可達480Mbps)，因此逐漸成為標準的傳輸介面，幾乎各種外接式的1355591 ^ : k〆< V'· X. • 夕> / . IX. Description of the Invention: [Technical Field of the Invention] The present invention provides a universal serial area stream (USB) device and a universal serial A platoon system is a generic (four) bus (10) device and a universal serial bus system that do not require precise solution of components. [Prior Art] • Universal Serial Bus (USB) is a common type of serial transmission on computer systems. Because of its convenient connection method and high transmission speed (usb2〇 up to 480Mbps), it gradually Become a standard transmission interface, almost all kinds of external

裝置’都開始採用聰作為與電腦系統(如第i圖之USB主機D S要連接方式，例如：隨身朗卡機、隨身式儲存裝置、掃描器等(如第1圖之USB裝置2)。 •股而言職_介面對於傳輸頻率的準確度要求很高，在低速或是全速α_模式下，頻率誤差必須在仏2瑪师在高速（HS)模式下，更要求頻率誤差必須在+/_ 啊二為了相上述__差的要求，通常在咖晶片的外部電路中，都要使用能夠產生精確頻率#^ 信號源3)，如:石英件，1=件(如第1圖之精確頻率央辰盈7G仵如第1圖所示；或精確頻率赵電路，以提做__精確度。、、對於某些低成上述的精麵率產生元件或電_成本很高， 5 1355591The device 'has started to use Cong as a way to connect with the computer system (such as USB host DS in Figure i), such as: portable card machine, portable storage device, scanner, etc. (such as USB device 2 in Figure 1). The _ interface has high requirements for the accuracy of the transmission frequency. In the low-speed or full-speed α_ mode, the frequency error must be in the high-speed (HS) mode, and the frequency error must be +/ _ ah 2 In order to meet the above requirements, usually in the external circuit of the chip, it is necessary to use the accurate frequency #^ signal source 3), such as: quartz, 1 = (as shown in Figure 1) The frequency of the central phase is 7G, as shown in Figure 1; or the precise frequency Zhao circuit, to improve the accuracy of __, for some low-level yield elements or electricity _ high cost, 5 1355591

10%以上，因此開方案是十分重要本的應用場合’甚至可能高達整體祕成本的發不需要使用上述外部精確頻率訊號源的解決【發明内容】因此本發明之目的之-在於提供—種不需要使用上述的外部精確頻率訊號源的USB電路設計方法與架構，可以在不影響產品性能的前提下，有效的降低系統的製造成本。曰根據本發明之申請專利範圍，係揭露一種通用串列匯流排卿)裝置，其包含健侧單元，时伽自—㈣匯流排主機(USB Ηο_傳送之—封包信號，並根__結果產生一通知信號卜誤差_單元，祕至該訊號侧單元，用來根據該通知信號以產生-控齡號；以及—解產生單元，輪至該誤差偵測單元，用來根據該控制信號以產生一輸出時脈信號〇 “ 根據本發明之申請專利範圍，另揭露一種通用串列匯流排 (USB)系統’其包含有一通用串列匯流排裝置，用來接收自一串列匯_主機(USB Host)所傳送之一封包信號並產生一控制信號；以及-頻率產生單元，雛至該通财舰流排裝置，用來根據該控制信號以產生-輸㈣脈健，其中該醉產生單元包含有一Λ 參考時脈產生單元，用來產生一第一時脈信號。 3 6 135559110% or more, so the solution is a very important application. It may even be as high as the overall cost of the solution. It is not necessary to use the above external precise frequency signal source. [Inventive content] Therefore, the object of the present invention is to provide The USB circuit design method and architecture that require the use of the external precision frequency signal source described above can effectively reduce the manufacturing cost of the system without affecting the performance of the product. According to the scope of the patent application of the present invention, a universal serial busbar device is disclosed, which comprises a healthy side unit, a gamma self-(four) busbar host (USB Ηο_transmitted-packet signal, and root__ result Generating a notification signal, the error_unit, to the signal side unit, for generating a control age number according to the notification signal; and a solution generation unit, in turn, the error detection unit for using the control signal according to the control signal Generating an output clock signal 〇 "In accordance with the scope of the present invention, a universal serial bus (USB) system is disclosed which includes a universal serial bus arrangement for receiving from a serial a packet signal transmitted by the USB Host and generating a control signal; and a frequency generating unit that is configured to generate a transfusion (four) pulse according to the control signal, wherein the drunk generating unit A reference clock generation unit is included to generate a first clock signal. 3 6 1355591

【實施方式】請參閱第2圖’第2圖為依據本發明之USB系統架構圖。如第2圖所示，USB主機(USB Host)10，例如一個人電腦，透過傳輸纜線或是PCB導線，傳送信號給相同連線上的通用串列匯流排裝置(USB裝置)100’該通用串列匯流排裴置丨〇〇耦接一頻率信號源20,而根據USB操作模式的不同，信號的傳送週期也會隨之不同0[Embodiment] Please refer to FIG. 2'. FIG. 2 is a diagram showing the architecture of a USB system according to the present invention. As shown in Fig. 2, a USB host 10, such as a personal computer, transmits signals to a universal serial bus device (USB device) 100' on the same connection line through a transmission cable or a PCB wire. The serial bus bar is coupled to a frequency signal source 20, and depending on the USB operating mode, the signal transmission period will also be different.

凊參閱第3圖’第3圖為依據本發明一實施例之通用串列匯流排裝置100之功能方塊圖。如第3圖所示，通用串列匯流排裝置100包含有一 SOF (Start of Frame)封包信號偵測電路(s〇FReferring to Figure 3, FIG. 3 is a functional block diagram of a universal serial bus device 100 in accordance with an embodiment of the present invention. As shown in FIG. 3, the universal serial busbar device 100 includes an SOF (Start of Frame) packet signal detecting circuit (s〇F).

Detect〇r)lH); —頻率誤差偵測電路12〇，耦接於該s〇F封包信號偵測電路110 ;以及一頻率產生器13〇，耦接於該頻率誤差偵測電路120。關於本發明之通用串列匯流排裝置1〇〇中各個元件的功能與操作，將於以下的揭露中詳細敘述。 SOF (Start of Frame)信號是USB協定所特有的一種週期性封包信號，USB主機(USB Host)每隔-段固定的時間，就會透過傳輸纜線或是PCB導線，傳送SOF封包信號給相同連線上的USB 裝置(USB Device)，而根據USB操作模式的不同，的傳送週期也會隨之不同。在低速或是全速（LS/FS)模式下，此週期為 +/-2500PPm ;而在高速（HS)模式下，此週細，丨縮短為i25us+/· 500PPm。由上述說明可知，S0F封包信號可以被用來作為系統上 1355591 的一個標準時脈信號，如模式下的SOF封包信號，操作頻率的校正。修正遇充如果USB裝置朗正確的彳貞測到各種操作 t ’就可以彻其錢的週雜來進行内部在偵測動作巾，雜紐献全速（LS/PS)赋以及高速 (HS)模式採用的方法並不相同，其說明如下： =)低速或是全速（LS/FS)模式之s〇F封包信號侦測方式：口月參閱第4圖。第4圖為依據本發明一實施例之fs/ls模式下的SOF封包信號偵測電路n〇。s〇F封包信號偵測電路ιι〇包含有一時脈與資料回復電路112以及一狀態機114。由於LS模式的傳輸速率只有每秒丨5百萬位元(1 5Μ_㈣，而FS模式的傳輸速率也只有每秒12百萬位元(12_价吻，因此可以採用過取樣(Over-sampling)的方式，即使在晶片内部頻率不是很準確的情況下，也可以偵測到S〇f封包信號。如第4圖所示’在USB傳輸纜線或是PCB導線上所接收到的信號’經過以96MHz為取樣頻率的時脈與資料回復電路112後，即可得到相對應的回復所得時脈與回復所得資料。再將上述的時脈與資料交給下一級的狀態機114進行分析，就可以確認目前所接收到的信號是否就是SOF封包信號，如果是的話就發出一通知信號給下一級的電路使用。至於在狀態機114的操作上，於系統 1355591 補充重置後，狀態機H4會進入一閒置狀態402，此時，若是偵測到任何一個K-state訊息’則狀態機114進入步驟404以檢測SYNC(同步）資料；之後，若是偵測到連續兩個K-state訊息，則狀態機114 進入步驟 406 以檢測 PID (physical identification data)資料，若是檢測結果為確定是S0F封包，則進入步驟408並判斷目前所接收到的信號就是S0F封包信號’並發出一通知訊號之後回到步驟術的閒置狀態，反之，若是檢測結果為確定不是s〇F封包，則回到 • 步驟402的閒置狀態。此外，第4圖中的K-State、SE0-state均為 USB標準所定義的狀態，應為熟悉此項技藝者可了解其涵義故不再贅述。 (2)尚速（HS )模式之S0F封包信號偵測方式凊參閱第5圖。第5圖為依據本發明一實施例之Hs模式下的狀態機114之示意圖。在HS模式下的傳輸速率為每秒48〇百萬位元(48〇Mbit/Sec) ’因此不適合再採用過取樣的方式來偵測s〇f封包信號，但由於在每-個HS模式下的s〇F封包信號中都會存在一段長達40個位元的連續的，，〇”或是連續的”】，，的信號，稱之為 E0P(EndGfPaeket)，而在正常的㈣封包信射，由於資料編石馬的關係’至多只會有連續7個位元的連續的，，〇，，或是連續的”ι，，發生’絕對不會出現上述的EQP信號，因此可以藉由侧此一獨特且低頻的E0P信號來確$ s〇F封包信號的存在與否。如第5圖所示，如果將接收到的資料藉由狀態機ιΐ4來進行 9 1355591The frequency error detecting circuit 12 is coupled to the s〇F packet signal detecting circuit 110; and a frequency generator 13 is coupled to the frequency error detecting circuit 120. The function and operation of each element in the universal serial busbar device 1 of the present invention will be described in detail in the following disclosure. The SOF (Start of Frame) signal is a periodic packet signal unique to the USB protocol. When the USB host (USB Host) is fixed every other time, the SOF packet signal is transmitted to the same through the transmission cable or PCB wire. The USB device is connected to the USB device, and the transfer cycle varies depending on the USB operating mode. In low-speed or full-speed (LS/FS) mode, this period is +/-2500PPm; in high-speed (HS) mode, this week is reduced to i25us+/·500PPm. As can be seen from the above description, the SOF packet signal can be used as a standard clock signal of the 1355591 on the system, such as the SOF packet signal in the mode, and the correction of the operating frequency. Correction If the USB device is correct, the various operations t' can be used to carry out the internal detection action towel, the full-speed full-speed (LS/PS) assignment and the high-speed (HS) mode. The method used is not the same, the description is as follows: =) Low-speed or full-speed (LS/FS) mode s〇F packet signal detection mode: See Figure 4 for the month. Figure 4 is a diagram showing the SOF packet signal detecting circuit n in the fs/ls mode according to an embodiment of the present invention. The s〇F packet signal detecting circuit ιι〇 packet includes a clock and data recovery circuit 112 and a state machine 114. Since the transmission rate of LS mode is only 丨5 million bits per second (1 5Μ_(4), and the transmission rate of FS mode is only 12 million bits per second (12_price kiss), over-sampling can be used. The way, even if the internal frequency of the chip is not very accurate, the S〇f packet signal can be detected. As shown in Figure 4, the signal received on the USB transmission cable or PCB wire passes. After 96MHz is used as the sampling frequency clock and data recovery circuit 112, the corresponding recovered clock and the recovered data can be obtained. Then the above clock and data are transferred to the state machine 114 of the next stage for analysis. It can be confirmed whether the currently received signal is the SOF packet signal, and if so, a notification signal is sent to the next stage of the circuit. As for the operation of the state machine 114, after the system 1355591 is reset, the state machine H4 will Entering an idle state 402, at this time, if any K-state message is detected, the state machine 114 proceeds to step 404 to detect SYNC data; after that, if two consecutive K-states are detected The state machine 114 proceeds to step 406 to detect PID (physical identification data) data. If the detection result is determined to be a S0F packet, the process proceeds to step 408 and determines that the currently received signal is the S0F packet signal 'and sends a notification signal. Then, it returns to the idle state of the step operation. Otherwise, if the detection result is determined not to be the s〇F packet, the process returns to the idle state of step 402. In addition, the K-State and SE0-state in FIG. 4 are all USB standards. The defined state should be understood by those skilled in the art and will not be described again. (2) The S0F packet signal detection mode of the HS (HS) mode is referred to Figure 5. Figure 5 is a diagram of the present invention. Schematic diagram of state machine 114 in Hs mode of an embodiment. The transmission rate in HS mode is 48 megabits per second (48 〇 Mbit/Sec) 'so it is not suitable for oversampling to detect s 〇f packet signal, but because there is a continuous, 40-bit continuous signal in the s〇F packet signal in each HS mode, the signal is called For E0P (EndGfPaeket) In the normal (four) packet letter, because of the relationship between the data and the stone horse, at most there will be only 7 consecutive contiguous, 〇, or continuous "ι,, occurrences" will never appear above. The EQP signal, so the presence or absence of the packet signal can be confirmed by the unique and low frequency E0P signal. As shown in Fig. 5, if the received data is performed by the state machine ιΐ4 9 1355591

卜部财I 分析，我們也可以確認目前所接收到的信號是否就是s〇F封g信號，如果是的話，就對下一級電路發出一通知信號。凊參閱第6圖。第6圖為依據本發明一實施例之頻率誤差偵測電路120演算法之示意圖。如前所述，s〇F封包信號偵測電路 110可以得到-個週期性的SOF#包通知信號，因此如果可以利用-個可控綱解信龍來航SQF封包通知錢的週期進行計數的話，就可以依據計㈣結果來調整·率信號源的輸出頻率，進而朗鮮校正的目^透過此演算法，我們可以得到一組控制信齡雕上述的鮮信麟的輸㈣率。此外，由於低速或是全速（LS/FS)模式以及高速（HS)模式的_封包信號的週期並不-樣，因此其鮮校正的方式也有些不同。 ⑴低速或是全速（LS/FS)模式之頻率校正方式 ⑻LS/FS的SOF封包信號產生週期為lms+/_25〇〇ppm^ (b)假設时計數的時脈錢之頻率為6_^ ⑹則在每隔1ms時_，頻率信號源將會發出_ * 60MHz個週期的計數用時脈信號 ⑹因此每個·断數料脈信號可以表示為 1/60000 二 16.7ppm的頻率誤差 (2)高速（HS)模式之頻率校正方式 ⑻HS的S0F封包信號產生週期為次 ⑼假設用來計數的時脈信號之頻率為_Hz (C)則在每隔125US時間内’頻率信號源將會發出 125us* 1355591 1355591Bu Bucai I analysis, we can also confirm whether the currently received signal is the s〇F seal g signal, and if so, send a notification signal to the next level circuit.凊 See Figure 6. Figure 6 is a diagram showing the algorithm of the frequency error detecting circuit 120 in accordance with an embodiment of the present invention. As described above, the s〇F packet signal detecting circuit 110 can obtain a periodic SOF# packet notification signal, so if it is possible to count the period of the money by using the controllable solution, the SQF packet is notified. According to the result of the calculation (4), the output frequency of the rate signal source can be adjusted, and then the target of the correction is obtained. Through this algorithm, we can obtain a set of control (S) rate of the above-mentioned fresh letter. In addition, since the period of the low-speed or full-speed (LS/FS) mode and the high-speed (HS) mode _ packet signal is not the same, the way of fresh correction is somewhat different. (1) Frequency correction mode for low-speed or full-speed (LS/FS) mode (8) The SOF packet signal generation period of LS/FS is lms+/_25〇〇ppm^ (b) The frequency of the clock when counting is assumed to be 6_^ (6) Every 1ms _, the frequency signal source will emit _ * 60MHz cycle count clock signal (6), therefore each break number pulse signal can be expressed as 1/60000 two 16.7ppm frequency error (2) high speed ( HS) mode frequency correction mode (8) HS's S0F packet signal generation period is second (9) Assuming that the frequency of the clock signal used for counting is _Hz (C), the frequency signal source will emit 125us* 1355591 every 125US time. 1355591

480MHz = 60000個週期的時脈信號 (d)因此每個週期的計數用時脈信號可以表示為1/6〇〇〇〇 = 16.7ppm的頻率誤差如前所述，在相鄰兩個S〇F封包信號的發生時段内，如果頻率信號源所產生的時脈錢數目小於預先蚊的目標值的話則產生的控制信號將會指示該鮮健職幅提高輸出時脈的頻率’反之’如果鮮錢源所產生的時脈信號數目大於預先設定的目心值的4 ’職生的控制信號將會指示該鮮信號源微幅降低輸出時脈的解。這樣_饋機制，將相使得該頻率信號源的輸出報_轉確度特接近於產生sot封包信號的頻率準確度。 -旦計數的結果與我們所預先設定的目標值—致時，即代表此時的輸出辭，或稱之為校正後時脈信號_率已經與產生 SOF封包信編神同步，如此—來，射爾於得到了一個準 USB主機的頻物步的喊信號並且可以個來作為後續的資料處理之用。已足以作為此^，果要縮短辭校正所需㈣間，我們可以設定一個所絲圍’只要在相鄰兩個卿封包錢的發生時段内， =付_日輪數目與__標值㈣小於此誤差範就可視為兩者的解誤差值已經非常接近， 1355591 弇卻气名：|480MHz = 60000 cycles of the clock signal (d) Therefore, the count clock signal for each cycle can be expressed as 1/6 〇〇〇〇 = 16.7ppm frequency error as described above, in the adjacent two S〇 During the occurrence period of the F packet signal, if the number of clock money generated by the frequency signal source is less than the target value of the pre-mosquito, the control signal generated will indicate that the fresh job increases the frequency of the output clock 'inverse' if fresh The 4' vocational control signal generated by the source of the clock signal greater than the preset centroid value will indicate that the fresh signal source slightly reduces the output clock solution. In this way, the feedback mechanism will make the output signal of the frequency signal source very close to the frequency accuracy of the sot packet signal. If the result of the counting is the same as the target value we set in advance, it means that the output word at this time, or the corrected clock signal _ rate has been synchronized with the generation of the SOF packet, so - She is able to get a shout signal from the quasi-USB host's frequency step and can be used as a follow-up data processing. It is enough for this ^, if you want to shorten the correction required (4), we can set a line around 'as long as the time between the two adjacent seals, the number of payday_days and the __value (four) is less than This error vane can be regarded as the solution error value of the two is very close, 1355591 弇 but gas name: |

後續的資料處理之用，因此可以停止上述“^作。.I 月參閱第7圖。第7圖為依據本發明一實施例之高輸出頻率解析度的頻率產生器130之架構圖。頻率產生器的主要功用就在於實現上述的可控織率錢源，此外，由於此頻率產生器 130的輸_率之頻率解析度與後續的料校正的料度直接相關’因此’如果要提高校正後時脈信號的頻率準確度的話，頻率產生器130的輸出頻率解析度就必須越高越好。頻率產生器U0包括-個參考時脈產生電路(Refe_eC⑹kFor subsequent data processing, it is possible to stop the above-mentioned operation. See Figure 7 for the month of Figure I. Figure 7 is a block diagram of the frequency generator 130 with high output frequency resolution according to an embodiment of the present invention. The main function of the device is to realize the above-mentioned controllable weaving rate source. In addition, since the frequency resolution of the frequency_rate of the frequency generator 130 is directly related to the material of the subsequent material correction, "if the correction is to be improved" For the frequency accuracy of the clock signal, the output frequency resolution of the frequency generator 130 must be as high as possible. The frequency generator U0 includes a reference clock generation circuit (Refe_eC(6)k

Generator)132 * H(Fractional-N FrequencyGenerator)132 * H(Fractional-N Frequency

Synthesizer)l34 ’以及-個傳統的頻率合成器(Frequency Synthesizer)136。其功用分別說明如下： ⑴參考時脈產生電路(Reference cl〇ck Generator)132 - 參考時脈產生電路I32的主要功能是產生一個時脈錢源，以作為後續的非整數型型頻率合成器134的參考時脈信馨號(ReferenceClock)之用。一般而言，利用電阻，電容〇或是電感(L)等元件’搭配轩電路元件，即可完成—個時脈產生電路，且其輸出頻率則與上述的電阻值，電容值以及電感值相關。如果上述的R/L/c元件都是採用晶片外部元件力話，則根據元㈣造麟的生紐術，系統顧可以很容易找到電阻值，電容值或是電感值的誤差在+/_ 1〇%，甚至是+人 5%以下的產品，進而得到較佳的輸出頻率準確度。但是如果 12 補充1 將上述的電阻，電容或是電感元件製作於晶片内部，則由於製程的不準確性’所製作出來的電阻值，電容值或是電感值通吊都可能會有+/- 20%的誤差’以至於參考時脈產生電路i32 所輸出之時脈信號頻率可能會有+/_3〇%的誤差。此外’也可以採用鏈狀反向器(Ring 〇sciUat〇r)的方式來設計時脈產生電路，以這種方式所產生的時脈信號源，其輸出的時脈信號頻率會與反向器的輸出延遲(Pr〇pagati〇n她力直接相關，因此如果該反向器是料在晶片内部的話，則輪出的時脈信號頻率將會與製作時的製程條件有很大的關係，也就是說，製程敏感度會比較高。請參閲第8圖。第8圖為一個參考頻率產生電路132的示意圖。此參考頻率產生電路132同時採用了電容以及鏈狀反向器的結構，藉由電流對於電容的充放電關係來產生週期性震盈的效果，並由此產生—個參考頻率，不過由於結構的關係’此參考頻率將會與電容，充放電電流，以及製程有很大的關聯。 (2)#(Fractional-NFrequency Synthesizer) 134 4參閱第9 ffil。第9 gj辅整數型鮮合絲以的示意圖°與傳統的整數型頻率合成器相比，非整數型頻率合成器134的最大特點是可以在輸入參考時脈信號的頻率不^變 1355591 的情況下，將輸出時脈信號的頻率做小幅度的: 輸入參考軸f號的鮮為12MHZ，但是輸㈣脈信號的頻率可以由驗彻至微難z较魏树接近的頻率。換句話說，如果搭配前述的參脈產生電路132 一起使用的話’就可以完成-個輸出解崎度很高的頻率信號源。 (3)頻率合成器(Frequency Synthesizei^36 由上述的非整數型頻率合成器134所產生的調整後時脈錢雖財以達麻高的頻率解析度，但是卻也料產生較而的時脈抖動(Clock㈣，對於报多通訊領域的應用上這會是-個很大_題。因此，在某些同時需要高頻率解析度〇低時脈抖動的應用領域，通常會再加上—個傳統的頻率人 =36 ’將前述的調整後時脈信號進行爐波的動作，以確保 /產生的輸出時脈信號的時脈抖動量可以符合規格的要 =;如果原先由非整數型頻率合成器134所產 =叙已經符合規格的話，則·傳統的 136就可以節省下來了。乂盗Synthesizer) l34' and a conventional Frequency Synthesizer 136. The functions are respectively described as follows: (1) Reference cl〇ck Generator 132 - The main function of the reference clock generation circuit I32 is to generate a clock source as a subsequent non-integer type frequency synthesizer 134 The reference clock is used for ReferenceClock. In general, the use of resistors, capacitors or inductors (L) and other components 'matching the circuit components, you can complete a clock generation circuit, and its output frequency is related to the above resistance value, capacitance value and inductance value. . If the above R/L/c components are all based on the external components of the wafer, then according to the (4) arboring technique, the system can easily find the resistance value, and the error of the capacitance value or the inductance value is +/_. 1〇%, even +5% of the product, to get better output frequency accuracy. However, if 12 is added 1 to make the above-mentioned resistor, capacitor or inductor component inside the wafer, the resistance value, capacitance value or inductance value produced by the process inaccuracy may have +/- The error of 20% is such that the frequency of the clock signal output by the reference clock generation circuit i32 may have an error of +/_3〇%. In addition, the clock generator can also be designed by means of a chain inverter (Ring 〇sciUat〇r). In this way, the clock source generated by the clock signal source and the output of the clock signal frequency and the inverter The output delay (Pr〇pagati〇n her force is directly related, so if the inverter is inside the wafer, the frequency of the clock signal that is rotated will have a great relationship with the manufacturing process conditions. That is to say, the process sensitivity is relatively high. Please refer to Fig. 8. Fig. 8 is a schematic diagram of a reference frequency generating circuit 132. This reference frequency generating circuit 132 employs both a capacitor and a chain reverser structure. The effect of periodic shock is generated by the charge-discharge relationship of the current to the capacitor, and a reference frequency is generated therefrom, but due to the structural relationship, the reference frequency will have a large capacitance, charge and discharge current, and process. (2)#(Fractional-NFrequency Synthesizer) 134 4 See the 9th ffil. Schematic diagram of the 9th gj auxiliary integer type of fresh wire. Compared with the traditional integer frequency synthesizer, the non-integer frequency combination The biggest characteristic of the device 134 is that the frequency of the output clock signal can be made small when the frequency of the input reference clock signal is not changed to 1355591: the input reference axis f is rarely 12 MHz, but the input (four) pulse signal The frequency can be verified to a frequency that is slightly more difficult than the Wei tree. In other words, if used together with the aforementioned pulse generating circuit 132, it can be completed - a frequency source with a high output resolution. (3) Frequency Synthesizer (Frequency Synthesizei^36) The adjusted clock generated by the above-described non-integer type frequency synthesizer 134 has a high frequency resolution, but it is expected to generate a relatively good clock. Jitter (Clock (4), this will be a big problem for the application of multi-communication field. Therefore, in some applications that require high frequency resolution and low clock jitter, usually a traditional one is added. Frequency person = 36 'The above-mentioned adjusted clock signal is subjected to the action of the furnace wave to ensure that the amount of clock jitter of the output clock signal can be met according to the specification =; if originally synthesized by a non-integer type frequency 134 = Syria has produced meet the specifications, then-traditional 136 can save down. Qe Pirates

以在in頻率產生方式可以有很多種變化，舉例而言，可以在參考時脈的_不㈣情況下 J 合成器…的除數Z率如果只更動參考時脈的頻率，卜，㈣丨而不改變非整數型頻率合成器 f的除法11，也仰改變輸出改變來考時脈的頻率與非整數型頻率合成器m的除法器甚至傳 =的頻率合成器！36的除法器的話，也可以改變輸出時脈信號的頻率。由上述的說明可知，如果將此頻率產生器m搭配上述的頻率誤差偵測電路120 一起使用，就可利用上述的s〇F封包信號的週期性來校正此頻率產生器的輸出頻率誤差，並將此誤差值控制在USB協定所規定的範圍内，以確保系統仍然可以正㊉操作。其中用來連接頻率誤差摘測電路12〇的所謂校正後時脈信號，可以是由上述的非整數型頻率合成器⑼ 所輸出的調整後時脈信號來產生，也可以是由上述的傳統頻率合成器136所輸出的時脈信號來產生。由上述揭露可崎知，藉纟本發撕提㈣方法與架構，可以將原先所採用的精確頻率信號源，^石英震盛树等，換成 ”利用電阻(R)，電容(Q,或者電感(L)所組合而成的頻率信號源，此頻率信號源成本較低，但精準度較差；另外，亦可由鍵狀反向雖ing Oscillator)來組成頻率信號源，且不影響***的正常功能。上述的電阻’電容，電感，或是反向H等it件可以外接於晶片之外’但並不以此為限’亦可製作於晶片内，以進—步地節省成本。以上所賴為本發明之較佳實細，驗本發”請專利範 15 比 5591There are many variations in the way in which the frequency is generated. For example, in the case of _ not (four) of the reference clock, the divisor Z rate of the J synthesizer can only change the frequency of the reference clock, and (4) Without changing the division 11 of the non-integer type frequency synthesizer f, it also changes the output change to the frequency of the clock and the divider of the non-integer type frequency synthesizer m or even the frequency synthesizer of the =. The 36 divider can also change the frequency of the output clock signal. It can be seen from the above description that if the frequency generator m is used together with the frequency error detecting circuit 120 described above, the periodicity of the frequency signal of the s〇F packet can be used to correct the output frequency error of the frequency generator, and This error value is controlled within the range specified by the USB protocol to ensure that the system can still operate in ten. The so-called corrected clock signal for connecting the frequency error extracting circuit 12〇 may be generated by the adjusted clock signal output by the non-integer frequency synthesizer (9), or may be the conventional frequency described above. The clock signal output from the synthesizer 136 is generated. According to the above disclosure, it can be known that the method and architecture of the tearing method can replace the original precise frequency signal source, quartz shock tree, etc. with "resistance (R), capacitance (Q, or The frequency signal source combined by the inductor (L), the frequency signal source has lower cost, but the accuracy is poor; in addition, the key signal source can be formed by the key reverse ing Oscillator, and does not affect the normality of the system. Function: The above-mentioned resistor 'capacitance, inductance, or reverse H and other components can be externally connected to the wafer 'but not limited to this' can also be fabricated in the wafer to further save costs. Lai is the best detail of the invention, the test of the hair" please patent van 15 than 5591

圍所做之够變化與修飾皆應屬本發明之涵蓋範圍。【圖式簡單說明】第1圖為習知USB系統應用的方塊圖。第2圖為依據本發明之USB系統應用的方塊圖。置100之功能第3圖為依據本發明一實施例之通用串列匯流排裝方塊圖。第4圖為依據本發明一實施例之FS/LS模式下的s〇f封包信號偵測電路及狀態機之示意圖。 D…、第5圖為依據本發明一實施例之HS模式下的狀態機之示意圖。第6圖為依據本發明一實施例之頻率誤差偵測電路12〇演算法之示意圖。第7圖為依據本發明-實施例之頻率產生器⑽之架構圖。第8圖為依據本發明-實施例之參考頻率產生電路i32#示意圖。第9圖為依據本發曰月-實施例之非替數型頻率合成器134的示意【主要元件符號說明】 1 USB主機 2 USB裝置 3 精確頻率信號源 10 USB主機 20 頻率信號源 1355591 100 通用串列匯流排裝置 110 SOF封包信號偵測電路 120 頻率誤差偵測電路 130 頻率產生器 112 時脈與資料回復電路 114 狀態機 132 參考時脈產生電路 134 非整數型頻率合成器 136 頻率合成器修正補良1All changes and modifications made by the invention are intended to be within the scope of the present invention. [Simple Description of the Drawing] Figure 1 is a block diagram of a conventional USB system application. Figure 2 is a block diagram of a USB system application in accordance with the present invention. Function of Setting 100 FIG. 3 is a block diagram of a universal serial bus bar according to an embodiment of the present invention. 4 is a schematic diagram of a s〇f packet signal detecting circuit and a state machine in the FS/LS mode according to an embodiment of the invention. D..., Fig. 5 is a schematic diagram of a state machine in HS mode according to an embodiment of the present invention. Figure 6 is a diagram showing the algorithm of the frequency error detecting circuit 12 according to an embodiment of the present invention. Figure 7 is a block diagram of a frequency generator (10) in accordance with an embodiment of the present invention. Figure 8 is a schematic diagram of a reference frequency generating circuit i32# in accordance with the present invention. Figure 9 is a schematic diagram of the non-replacement type frequency synthesizer 134 according to the present invention. [Main component symbol description] 1 USB host 2 USB device 3 Precision frequency signal source 10 USB host 20 Frequency signal source 1355591 100 General Serial bus arrangement 110 SOF packet signal detection circuit 120 frequency error detection circuit 130 frequency generator 112 clock and data recovery circuit 114 state machine 132 reference clock generation circuit 134 non-integer frequency synthesizer 136 frequency synthesizer correction Buliang 1

1717

Claims

十 '申請專利範圍： t------------ h 一種通用串列匯流排(USB)裝置，其包含有：一信號偵測電路，用來偵測自一串列匯流排主機(USB Host)所傳送之一封包信號，並根據該偵測結果產生一通知信號；一誤差偵測電路，耦接至該訊號偵測電路，用來根據該通知信號以產生一控制信號；以及一頻率產生器’耦接至該誤差偵測電路，用來根據該控制信號以產生一輸出時脈信號。 2. 如申請專利範圍第1項所述之通用串列匯流排裝置，其中該信 "5虎偵刮電路包含有：一回復電路，用來根據該封包信號以產生至少一回復信號；以及一狀態機’耦接於該回復電路，以根據該回復信號來產生該通知信號。 3. 如申請專利範圍第2項所述之通用串列匯流排裝置，其中該狀態機根據該回復信號來判斷該封包信號是否為—S〇f (Start of Frame)信號。 4.如申請專利範圍第1項所述之通用串列匯流排裝置，其中該信號偵測電路包含有一狀態機，用來判斷該封包信號是否為一 SOF (Start of Frame)信號。 1355591Ten 'application patent scope: t------------ h A universal serial bus (USB) device, comprising: a signal detection circuit for detecting a series of confluences a packet signal transmitted by the host (USB Host), and generating a notification signal according to the detection result; an error detection circuit coupled to the signal detection circuit for generating a control signal according to the notification signal And a frequency generator 'coupled to the error detection circuit for generating an output clock signal according to the control signal. 2. The universal serial bus arrangement device of claim 1, wherein the letter "5 tiger detection circuit comprises: a reply circuit for generating at least one reply signal according to the packet signal; A state machine 'couples to the reply circuit to generate the notification signal according to the reply signal. 3. The universal serial busbar device of claim 2, wherein the state machine determines whether the packet signal is a -S〇f (Start of Frame) signal based on the reply signal. 4. The universal serial bus arrangement of claim 1, wherein the signal detection circuit includes a state machine for determining whether the packet signal is an SOF (Start of Frame) signal. 1355591

補充 5. 如申請專利範圍第〗項所述之通用㈣匯流排裝置，其中該輸出時脈信號個⑽數該通知錢，且該誤差_單元根據該計數之結果以產生該控制信號。 6.如申請專利範圍第i項所述之通用串列匯流排裝置，其中該頻率產生器包含有： • 參考時脈產生電路，时產生—參考時脈信號； =非整數型頻率合成ϋ，用來根據該參考時脈信號以及該控制k號以產生一調整時脈信號；以及一頻率合成H，絲根職調整時脈信奴及雛制信號以產生該輸出時脈信號。 7·如申請專利範圍第！項所述之通用串列匯流排裝置’其中該頻率產生器包含有：藝:參考時脈產生電路，用來產生—參考時脈信號；以及非數型頻率合成$ ’用來根據該參考時脈減以及該控制信號以產生該輸出時脈信號。 8.一種通用串列匯流排(USB)系統，其包含有：一串列匯流排主機(USB Host) ’用來傳送一封包訊號； ^串舰w排裝置’㈣一傳輸線輕接於該串舰流排主機用來接收自料寵祕主機賴送找封包信號並產生一控制佗號，其中該通用串列匯流排裝置包含有： —------ 一信號_電路’用來勤丨自一串舰流排主機所傳送之一封包信號，並根據該偵測結果產生一通知信號；以及誤差偵測電路，耦接至該訊號偵測電路，用來根據該通知信號以產生一控制信號；以及頻率產生器，耦接至該通用串列匯流排裝置，用來根據該控制信號以產生一輸出時脈信號，其中該頻率產生器包含有一參考時脈產生電路，用來產生一第一時脈信號。 9.如申請專利範圍第8項所述之通用串列匯流排系統，其中該信 5虎4貞測電路包含有：一回復電路，用來根據該封包信號以產生至少一回復信號；以及一狀態機，耦接於該回復電路，以根據該回復信號來產生該通知信號。 10_如申請專利範圍第g項所述之通用串列匯流排系統，其中該頻率產生器另包含有一非整數型頻率合成器，用來根據該第一時脈信號以及該控制信號以產生一第二時脈信號。十一、圓式：Supplement 5. The general (four) busbar device as described in claim </ RTI> wherein the output clock signal (10) counts the money, and the error_unit generates the control signal based on the result of the counting. 6. The universal serial bus arrangement of claim i, wherein the frequency generator comprises: • a reference clock generation circuit, generating a time reference signal; = a non-integer frequency synthesis, And according to the reference clock signal and the control k number to generate an adjusted clock signal; and a frequency synthesis H, the root line adjusts the clock and the signal to generate the output clock signal. 7. If you apply for a patent scope! The universal serial bus arrangement device of the item wherein the frequency generator comprises: an art: reference clock generation circuit for generating a reference clock signal; and a non-digital frequency synthesis $' for use according to the reference The pulse is subtracted and the control signal is generated to generate the output clock signal. 8. A universal serial bus (USB) system, comprising: a serial bus host (USB Host) 'used to transmit a packet signal; ^string ship w row device' (four) a transmission line lightly connected to the string The shipboard host is configured to receive the self-fed host to send a packet signal and generate a control nickname, wherein the universal serial bus device includes: —------ a signal_circuit’ is used to a packet signal transmitted from a host of the shipboard and generating a notification signal according to the detection result; and an error detection circuit coupled to the signal detection circuit for generating a signal according to the notification signal a control signal; and a frequency generator coupled to the universal serial bus device for generating an output clock signal according to the control signal, wherein the frequency generator includes a reference clock generation circuit for generating a The first clock signal. 9. The universal serial bus system of claim 8, wherein the signal comprises: a reply circuit for generating at least one reply signal according to the packet signal; The state machine is coupled to the recovery circuit to generate the notification signal according to the reply signal. 10) The universal serial bus system of claim g, wherein the frequency generator further comprises a non-integer frequency synthesizer for generating a signal according to the first clock signal and the control signal Second clock signal. Eleven, round: