1354291 九、發明說明： 本申請案主張2006年9月29日申請之韓國專利申請 案第2006-96007號與2007年6月27日申請之韓國專利申 請案第2007-63576號，在此將其全文倂入供參考。 【發明所屬之技術領域】 本發明係關於一種快閃記億體裝置與其編程方法，且 更特別地，係關於一種快閃記億體裝置與可增加編程速度 之編程方法。 【先前技術】 —般而言，快閃記憶體裝置包含絕緣層、浮動閘、電 介質層及控制閘，其係層積於半導體基板上。該浮動閘係 用作電荷儲存層且將說明其詳細內容。 當編程電壓透過選擇字元線而施加至控制閘時，於半 導體基板與浮動閘之間產生福勒一諾德漢（Fowler-No rdheim， F-N) 穿 隧現象 ，並因 此電子從半導 體基板 流入該 浮動閘中以執行編程操作。 儲存電子之浮動閘成爲電壓高於抹除之臨界電壓的編 程胞元，並因此藉由讀取此臨界電壓的分佈差異可區別該 編程胞元與抹除胞元。 快閃記憶裝置具有二個狀態，例如，抹除狀態或編程 狀態，且該記憶體裝置於一個抹除狀態中被驅動及一個編 程狀態稱爲單階晶片（SLC)。另一方面，已發展多階中的每 一個記憶胞元儲存大於單階晶片SLC之資料的編程方法， 其稱爲多階晶片（MLC)。該多階晶片MLC係以界定每一個 1354291 資料狀態的方式下操作，其中該資料狀態在各 之分佈間隔中是互相不同的。將說明其更詳細 例如，當資料儲存於該多階晶片MLC中時 胞元可能具有之狀態可被分成抹除狀態、PV1 狀態與PV 3狀態。在此，假設該PV1狀態爲具 電壓間隔中最低間隔之編程狀態時，該PV2的 高於該PV1狀態，且該PV3狀態係高於PV2狀 相對於各個臨界電壓間隔，可依序定義多位元 11’ 01，00與01)。在下述中，其說明將參照j 第1A到ID圖顯示傳統快閃記憶體裝置之 —個記憶胞元可能具有之各個臨界電壓間隔， 狀態、PV1狀態、PV2狀態與PV3狀態，且於 義2位元（多個位元）的資料値。2位元之資料値 稱爲低頁面，且較高位元稱爲高頁面》該低頁 作稱爲低頁面編程”LSB編程”，且該高頁面之 爲高頁面編程’’MSB編程”。 多階晶片MLC之編程順序將說明如下。 首先，在由一單元區塊所構成之記憶胞元 除所有選擇區塊之記憶胞元（第1A圖）。接著， 編程LSB操作。 在低頁面編程LSB操作中，於抹除狀態 中，施加接地電壓至選擇記憶胞元之位元線， 電壓至沒有選擇的記憶胞元之位元線。該低頁 操作以下述方式執行：施加編程電壓至選擇字 個臨界電壓 的內容。 :，一個記憶 狀態、PV2 有編程臨界 臨界分佈係 態。像這樣， 資料（亦即， 赛1圖。 編程方法。 被分成抹除 每個狀態定 的較低位元 面之編程操 編程操作稱 陣列中，抹 執行低頁面 之記憶胞元 並施加電源 面編程LSB 元線與並施 1354291 此，透 選擇記 程MSB 編程爲 以LSB 態，並 PV2狀 編程爲 係以下 電壓至 該選擇 除狀態 態），故 的多階 至位元 編程操 加通過電壓（pass voltage)至沒有選擇的字元線。因 過這些低頁面編程LSB操作的程序’該抹除狀態之 憶胞元變成PV1狀態（第1B圖）。 該高頁面編程MSB操作可被分成第一高頁面編 與第二高頁面編程MSB。 該第一高頁頁編程MSB操作係將選擇記憶胞元 PV2狀態之操作。爲編程抹除記憶胞元爲PV2狀態， 編程來將選擇的記憶胞元從抹除狀態編程至PV1狀 接著執行第一MSB編程，使該選擇的記憶胞元處於 態中（第1C圖）。 該第二高頁面編程MSB操作係將選擇記憶胞元 PV3狀態之操作（第1D圖）。該第二高頁面編程MSB 述方式執行：於抹除狀態之記憶胞元中，施加接地 選擇記憶胞元之位元線，且施加編程電壓至連接至 記憶胞元之字元線。 由於必須執行每一編程操作，藉以將胞元從抹 編程至各個編程狀態（PV1狀態、PV2狀態或PV3狀 多階晶片MLC之編程操作速度會被降低。 【發明內容】 依照本發明，於具有各種編程臨界電壓之間隔 晶片之編程操作中，施加臨界電壓間之不同的電壓 線，並因此可同時執行具有不同臨界電壓間隔之 作》因此，編程的操作頻率可被減少以降低編程操作時間。 依照本發明之一個實施例之快閃記憶體裝置之編程方 1354291 法，包含：執行第一編程’以編程胞元至第一狀態與高於 該第一狀態之第二狀態；及同時與該第一編程一起執行第 二編程，以編程胞元至第二狀態與高於該第二狀態之第三 狀態。 執行該第一編程，用以使抹除狀態之胞元中所選擇的 胞元成爲第一狀態。 該選擇的胞元爲欲編程至第一狀態與第二狀態之胞 元，且當執行該第一編程時’將被編程至第二狀態之胞元 係與欲編程至第一狀態之胞元一起同時被編程爲第一狀 態。 執行該第二操作，用以抹除狀態之胞元中所選擇的胞 元編程爲第三狀態，並同時將第一編程胞元中欲編程至第 二狀態的胞元，編程至第二狀態。 當執行該第二編程時，施加正電壓至與欲編程至第二 狀態之胞元連接的位元線。 施加第二狀態之臨界電壓與第三狀態之臨界電壓之間 的正電壓差。 依照本發明之另一個實施例，一種編程具有抹除狀 態、第一狀態、第二狀態與第三狀態之快閃記憶體裝置之 方法，該方法包含：執行第一編程，使得抹除狀態之某些 第一記億胞元變成第一狀態之第二記憶胞元；及以下列方 式執行第二編程：施加接地電壓至與包含該第一記憶胞元 之串連接的第一位元線，施加正電壓至與包含該第二記憶 胞元之串連接的第二位元線，使得該第一記憶胞元變成第 1354291 二狀態之第三記憶胞元及該第二記億胞元變成第三狀態之 第四記憶胞元。 在第二狀態中，臨界電壓藉由該第二編程操作而變得 高於第一狀態之臨界電壓，且在該第三狀態中，臨界電壓 藉由該第二編程操作而變得高於第二狀態之臨界電壓。 該正電壓爲高於接地電壓之電壓，且低於施加至選擇 的位元線與包含於該串中之汲極選擇電晶體之編程電壓間 的臨界電壓差。 依照本發明之另一實施例之編程快閃記億體裝置之方 法，包含：執行第一編程，以編程某些抹除胞元至第一狀 態與高於該第一狀態之第二狀態；及以下列方式執行第二 編程：施加接地電壓至連接於包含選擇的記憶胞元之串的 第一位元線，以編程某些抹除的胞元至高於該第二狀態之 第三狀態，及同時施加正電壓至連接於記憶胞元之第二位 元線，以將被第一編程之胞元編程至第二狀態。 施加該第二狀態與第三狀態之臨界電壓間的正電壓 差。 ‘ 依照本發明之快閃記憶體裝置，包含：記億胞元陣列’ 其中儲存資料；及頁面緩衝器，其透過位元線連接至記憶 胞元，並在執行編程時，施加第一電壓、第二電壓或該第 一與第二電壓之間的第三電壓中其中一電壓至各個位元 線。 該第一電壓爲電源電壓，且該第二電壓爲接地電壓及 該第三電壓爲正電壓。 1354291 施加該第二狀態與第三狀態之臨界電壓間的正電壓 差。 該正電壓係以下列方式傳送：從頁面緩衝器傳送電壓 到位元線之元#的接通電壓並非^全接通而是輕微地接 通》 本發明之實施例將參照附隨圖式解釋。然而，本發明 並不侷限於所揭示的實施例。本發明附加的優點、目的與 特徵將於下列提出，且使所屬技術領域中具有通常知識者 於隨後審查將變得明確。 【實施方式】 第2圖爲依照本發明顯示快閃記憶體裝置之編程方法 之電路圖。 參照第2圖，其顯示構成記憶胞元陣列及與其連接的 頁面緩衝器之一個胞元區塊100。該胞元區塊100包含複數 串（strings)S。到Sk。汲極選擇電晶體DST、記憶胞元F。到 F。及源極選擇電晶體SST係以串聯連接的方式來構成每一 個串。每一汲極選擇電晶體DST係連接至每一位元線BL。 到BLk，以傳送頁面緩衝器PB之電壓至該等串S。到Su或 從該等串S。到31；接收頁面緩衝器PB之電壓。該各個源極 選擇電晶體SST係連接至共源極線CSL。複數記憶胞元F。 到Fn係串聯配置於該汲極選擇電晶體DST與該源極選擇電 晶體SST之間。 汲極選擇電晶體DST之閘極係共用汲極選擇線DSL。 該源極選擇電晶體SST之每一閘極係共用源極選擇線ssl -10- 1354291 並與其連接。 當編程與抹除時，該頁面緩衝器PB將編程與抹除操作 所對應之電壓傳送至位元線BL。到BLk，並當讀取時，接收 由該位元線BL。到BLt施加的電壓。 在本發明中，除了於典型編程操作中產生的第一電壓 (亦即，0V)與第二電壓（亦即，Vcc)以外，更在該第一電壓 與該第二電壓之間產生第三電壓Vd。該第三電壓Vd爲第 一電壓與第二電壓之間的正電壓，且其將參照第3圖說明 如下。 第3圖爲顯示第2圖之頁面緩衝器之電路圖。 參照第3圖，即使使用於本發明之頁面緩衝器PB爲進 —步產生如上述之第三電壓的頁面緩衝器，其結構係類似 於傳統頁面緩衝器PB之結構。然而，藉由調整構成該頁面 緩衝器PB之元件中的某些元件的接通（turn on)電壓，可從 該頁面緩衝器PB將該第一到第三電壓之一選擇性地傳送 至位元線BL。爲便於了解，該頁面緩衝器PB將參照第3 圖簡短說明。 該頁面緩衝器PB包含用以選擇複數位元線之選擇電 路32，並以雙閂鎖設計構成。 在更詳細之說明中，預充電元件P1藉由響應預充電信 號PRECHb而操作之PMOS電晶體來實施，並連接於電源 電壓Vcc與感測節點SO之間。編程元件P2係響應編程信 號PGM而進行操作’並連接於該感測節點SO與第一節點 E1之間。第一控制元件P3與第二控制元件P4係串聯連接 -11- 1354291 於第二節點E2與接地Vss之間，且該第一控制元件p3係 響應該感測節點SO之電壓而進行操作，及該第二控制元件 P4係響應第一閂鎖信號LAT1而進行操作。重置元件p5係 響應第一重置信號RST1而進行操作，並連接於第一節點 E1與接地Vss之間。第一閂鎖33係連接於第一節點e i與 第二節點E2之間，並包含二個反相器13、14。傳送元件 P6係響應傳送信號PDUMP而進行操作，並連接於感測節 點S0與第三節點E3之間。第三控制元件P7與第四控制元 件P8係串聯連接於第三節點E3與接地Vss之間，且第rr 控制兀件P 7係響應施加至感測節點S 0之電壓而進行操 作’及第四控制元件P8係響應第二閂鎖信號LAT2而進行 操作。第二重置元件P9係操作響應第二重置元件rST2並 連接於第四節點E4與接地Vss之間。第二閂鎖34係連接 於第三節點E3與第四節點E4，其包含二個反相器15、16。 依照第一輸入元件P10與第二輸入元件PH之操作來儲存 輸入至該第二問鎖34之資料。該第一輸入元件ριο係響應 第一輸入信號DI而進行操作，並連接於第四節點E4與第 五節點E 5之間。該第二輸入元件p丨丨係響應第二輸入信號 nDI而進行操作，並連接於第三節點E3與第五節點E5之 間》輸入與輸出元件P12係響應輸入與輸出信號PBD〇而 進行操作，並連接於第一節點E1與第五節點E5之間，且 該第五節點E5係連接至輸入與輸出線DI0。 該選擇電路32包含偶數充電元件p丨3、奇數充電元件 P14、偶數選擇元件P15與奇數選擇元件P16，用以連接位 -12- 1354291 元線BLe、BLo到該頁面緩衝器pb。該偶數充電元件P13 與奇數充電元件P14係透過第六節點E6串聯連接於位元線 BLe、BLo之間。該偶數充電元件p13係響應偶數充電信號 DISCHe而進行操作’並連接於偶數位元線BLe與第六節點 E6之間’該奇數充電元件P14係響應奇數充電信號DISCHo 而進行操作，並連接於奇數位元線BLo與第六節點E6之 間。施加充電電壓VIRPWR至該第六節點E6。該偶數選擇 元件P15係響應偶數選擇信號BSLe而進行操作，並連接於 該感測節點SO與偶數位元線BLe之間。該奇數選擇元件 P16係響應奇數選擇信號BSLo而進行操作，並連接於該感 測節點SO與奇數位元線BLo之間。 當操作編程時，若活化（activate)編程信號PGM，則接 通編程元件P2並因而傳送第一閂鎖33之電壓至該感測節 點SO。傳送至該感測節點SO之電壓係透過選擇電路32之 偶數選擇元件P15或奇數選擇元件P16，傳送至偶數位元 線BLe或奇數位元線BLo。 另一方面，當傳送第三電壓至該偶數或奇數位元線 BLe或BLo時，若編程元件P2沒有完全接通而是輕微接通 且活化選擇BSLe或BSLo之選擇信號時，則第三電壓可被 輸出至位元線，其中該第三電壓於第一電壓與第二電壓之 間爲正電壓》此外，若活化編程信號PGM並輕微接通選擇 BSLe或BSLo之選擇信號，則該第三電壓可被輸出至位元 線。此時，較佳地，於位元線BLe或BLo爲0V電壓的狀 態下執行編程操作。 -13- 1354291 接下來，依照本發明之編程方法將參照第2圖之一個 頁面110而詳細說明。 第4圖爲顯示第2圖之部分電路圖，以說明依照本發 明之快閃記憶體裝置之編程方法。依照本發明的一個觀 點，在選擇頁面之記億胞元0F。到kF〇之中，編程使得第〇 個記憶胞元0F。爲抹除狀態、第一胞元1 F。爲PV 1狀態、第 二胞元2F。爲PV2狀態、第三胞元3F。爲PV3狀態及第k 胞元kF。爲PV3狀態。此時，該抹除狀態、pv 1狀態、PV2 狀態及PV3狀態分別稱爲11、10、00及01。然而，此可 依其定義而改變，且在本發明中，取決於增加的臨界電壓 之等級，編程狀態係定義爲抹除狀態、PV1狀態、PV2狀 態及PV3狀態。其範例將參照第5A到5F圖說明。 第5A到5F圖顯示依序依照本發明之快閃記億體裝置 之編程方法。 參照第5A圖，在執行編程操作前，藉由單元胞元區塊 執行抹除操作，使得記憶胞元（包含記憶胞元0F。到kF。之 胞元區塊的所有記憶胞元）成爲抹除狀態之第一記憶胞 元。執行該抹除操作使得第一電壓（亦即，0V)施加至選擇 字元線WLO，且第二電壓（亦即，Vcc)係連接至所有位元線 BLo到BLk。依照該抹除操作，臨界電壓分佈變爲抹除狀 態（第5B圖）。 參照第5C圖，執行作爲低頁面編程LSB操作之第一 編程操作，以編程第—胞元（1F。）爲PV1狀態之第二記憶胞 元。此時，同時對第二胞元2F。與欲被編程爲PV2狀態的 -14- 1354291 第K胞元KF。執行該低頁面編程LSB操作，藉以成爲PVl 狀態。 詳而言之’當進行低頁面編程LSB時，施加編程電壓 至選擇字元線WLO，且施加第一電壓（亦即，〇v)至選擇位 元線BL1 ' BL2與BLk並施加第二電壓（亦即，vcc)至沒有 被選擇的位元線BLO與BL3。因此，第〇胞元（〇F。）保持抹 除狀態’且第一胞元（1FO、第二胞元（2F。）及第K胞元（kF。) 變成PV1狀態（第5D圖）。 參照第5E圖，執行作爲高頁面編程MSB操作之第二 編程操作，以編程第三胞元（3 F。）變成PV3狀態。同時，編 程第二胞元2F。與第K胞元KF。成爲PV2狀態。其更詳細 的說明/如下所述。 施加編程電壓至選擇的字元線WLO且施加第一電壓 (亦即，0V)至連接至第三胞元3F〇之位元線BL3，以編程第 三胞元3F〇’以便成爲PV3狀態。同時，施加第三電壓Vd 至連接至第二胞元2F〇之位元線BL2,以編程第二胞元爲具 有高於PV1狀態且低於PV3狀態之PV2狀態（第5F圖）》 同時，若PV1狀態之確認電壓係參照Va，PV2狀態之 確認電壓係參照Vb且PV3狀態之確認電壓係參照Vc，則 較佳地是，施加與Vc與Vb之電壓差同等的第三電壓Vd， 因PV2狀態之臨界電壓將被分佈於PV1狀態與PV3狀態之 臨界電壓之間。 然而，可有各種因素決定該臨界電壓分佈，其主要取 決於儲存在浮動閘中的電子數量。該儲存在浮動閘中的電 -15- 1354291 子數量可藉由字元線與半導體基板之間的電壓差而決定。 若施加編程電壓至字元線且經由位元線施加接地電壓 至半導體基板之通道時，控制閘與浮動閘之間的耦合現象 因編程電壓而產生。此耦合現象透過電子從半導體基板流 至該浮動閘而感應穿隧現象，且已編程胞元之臨界電壓可 取決於穿隧的電子數量而改變。因此，決定編程胞元之臨 界電壓的一個重要因素，爲施加至字元線的編程電壓與施 加至位元線的電壓間的電壓差。關於此，將參照如下給定 之曲線圖詳細說明》 第6圖爲比較本發明與習知技術之快閃記憶體裝置之 編程頻率曲線圖。 參照第6圖’X軸表示編程頻率，且y軸表示臨界電壓。 在習知技術中，爲了編程至PV3狀態，首先執行編程操作 (a)以達到PV2狀態，並接著必須執行編程操作（b)以更提升 臨界電壓至PV3狀態。 然而，在本發明中，與PV2狀態與PV3狀態之臨界電 壓差相同的Vd電壓，係同時施加至連接至欲編程成爲PV2 狀態之胞元的位元線，並因而僅透過一個編程操作（A)，就 可執行PV2狀態與PV3狀態之編程，以縮短編程操作時間。 對於那些所屬技術領域中具有通常知識者將顯而易見 的是，在本發明中可作成各種修改與改變。因此，其意指 本發明涵蓋於附隨之申請專利範圍與其等效物之範圍內所 提供本發明之修改與改變。 在本發明中，當執行具有複數臨界電壓間隔之多階晶 -16- 1354291 片的編程操作時，不同的電壓與施加至位元線之臨界電壓 間的差異相同’並因此具有不同的臨界電壓間隔之胞元之 編程操作可同時被執行。因此，可降低複數編程操作的頻 率，以減少編程操作時間。 【圖式簡單說明】 第1 A到1 D圖係分別說明傳統編程快閃記憶體之方 法。 第2圖爲依照本發明顯示快閃記憶體裝置之編程方法 ^ 之電路圖。 第3圖爲顯示第2圖之頁面緩衝器之電路圖》 第4圖爲說明依照本發明之快閃記憶體裝置之編程方 法顯示第2圖之部分電路圖。 第5 A到5 F圖顯示依序依照本發明之快閃記憶體裝置 之編程方法。 第6圖爲比較本發明與習知技術之快閃記憶體裝置之 編程頻率曲線圖。 -17- 1354291 【主要元件符號說明】1354291 IX. INSTRUCTIONS: This application claims Korean Patent Application No. 2006-96007, filed on Sep. 29, 2006, and Korean Patent Application No. 2007-63576, filed on Jun. 27, 2007. The full text is for reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a programming method thereof, and more particularly to a flash memory device and a programming method capable of increasing programming speed. [Prior Art] In general, a flash memory device includes an insulating layer, a floating gate, a dielectric layer, and a control gate which are laminated on a semiconductor substrate. This floating gate is used as a charge storage layer and its details will be explained. When a programming voltage is applied to the control gate through the selected word line, a Fowler-Nordheim (FN) tunneling phenomenon is generated between the semiconductor substrate and the floating gate, and thus electrons flow from the semiconductor substrate. The floating gate is used to perform programming operations. The floating gate storing the electrons becomes a programming cell having a voltage higher than the threshold voltage of the erase, and thus the programming cell and the erasing cell can be distinguished by reading the difference in the distribution of the threshold voltage. The flash memory device has two states, e.g., an erase state or a program state, and the memory device is driven in an erase state and a programmed state is referred to as a single-stage wafer (SLC). On the other hand, a programming method in which each of the memory cells in the multi-stage has been developed to store data larger than the single-order wafer SLC is called a multi-order wafer (MLC). The multi-level wafer MLC operates in a manner that defines the state of each of the 1354291 data, wherein the data states are different from one another in each of the distribution intervals. More details will be explained. For example, when data is stored in the multi-stage wafer MLC, the state that the cell may have can be divided into an erase state, a PV1 state, and a PV 3 state. Here, assuming that the PV1 state is a programming state with the lowest interval among the voltage intervals, the PV2 is higher than the PV1 state, and the PV3 state is higher than the PV2 shape with respect to each threshold voltage interval, and multiple bits may be sequentially defined. Yuan 11' 01, 00 and 01). In the following description, the description will refer to j 1A to ID diagram showing the threshold voltage interval, state, PV1 state, PV2 state and PV3 state of a memory cell of a conventional flash memory device, and The data of the bit (multiple bits). The 2-bit data is called the low page, and the higher bit is called the high page. The low page is called the low page programming "LSB programming", and the high page is the high page programming ''MSB programming'." The programming sequence of the order chip MLC will be explained as follows. First, the memory cells of all the selected blocks are divided by the memory cells composed of one unit block (Fig. 1A). Next, the LSB operation is programmed. The LSB is programmed at a low page. In operation, in the erase state, a ground voltage is applied to the bit line of the selected memory cell, and the voltage is to the bit line of the unselected memory cell. The low page operation is performed in the following manner: applying the programming voltage to the selected word The content of a threshold voltage: :, a memory state, PV2 has a programmed critical critical distribution system. Like this, the data (that is, the game 1 map. The programming method is divided into the lower bit surface of each state. The programming operation is called the array, and the memory cell of the low page is executed and the power plane is programmed to apply the LSB element line and the 1354291 is used. The selection path MSB is programmed to be in the LSB state and PV2 The process is the following voltage to the selection state except the state), so the multi-level to bit programming operates the pass voltage to the unselected word line. Because of these low-page programming LSB operations, the program In addition to the state, the cell becomes a PV1 state (Fig. 1B). The high page programming MSB operation can be divided into a first high page programming and a second high page programming MSB. The first high page programming MSB operating system will select the memory. The operation of the cell PV2 state. To erase the memory cell for the PV2 state, programming to program the selected memory cell from the erase state to the PV1 state and then perform the first MSB programming, so that the selected memory cell is in the state Medium (Fig. 1C). The second high page programming MSB operation will select the operation of the memory cell PV3 state (Fig. 1D). The second high page programming MSB mode performs: memory cells in the erased state Applying a bit line of the ground selection memory cell and applying a programming voltage to the word line connected to the memory cell. Since each programming operation must be performed, the cell is programmed from the stencil to each programming state (P The programming operation speed of the V1 state, the PV2 state, or the PV3 multi-level wafer MLC may be lowered. [Invention] According to the present invention, different voltages between threshold voltages are applied in a programming operation of a wafer having various programming threshold voltages. The lines, and thus the different threshold voltage intervals, can be performed simultaneously. Thus, the programmed operating frequency can be reduced to reduce the programming operation time. The programming method 1354291 method of the flash memory device in accordance with one embodiment of the present invention includes Performing a first programming 'to program a cell to a first state and a second state higher than the first state; and simultaneously performing a second programming with the first programming to program the cell to a second state and above The third state of the second state. The first programming is performed to cause the selected cell in the cell of the erased state to be in the first state. The selected cell is a cell to be programmed to the first state and the second state, and when the first programming is performed, 'the cell to be programmed to the second state and the cell to be programmed to the first state Together they are programmed to the first state. Performing the second operation, the selected cell in the cell for erasing the state is programmed to the third state, and simultaneously programming the cell to be programmed to the second state in the first programming cell to the second state . When the second programming is performed, a positive voltage is applied to the bit line connected to the cell to be programmed to the second state. A positive voltage difference between the threshold voltage of the second state and the threshold voltage of the third state is applied. In accordance with another embodiment of the present invention, a method of programming a flash memory device having an erased state, a first state, a second state, and a third state, the method comprising: performing a first programming such that the erased state is Some first cells are converted into a second memory cell of the first state; and the second programming is performed in the following manner: applying a ground voltage to the first bit line connected to the string including the first memory cell, Applying a positive voltage to the second bit line connected to the string including the second memory cell, such that the first memory cell becomes the third memory cell of the 1354291 state and the second cell becomes the first The fourth memory cell of the three states. In the second state, the threshold voltage becomes higher than the threshold voltage of the first state by the second programming operation, and in the third state, the threshold voltage becomes higher than the first by the second programming operation The threshold voltage of the two states. The positive voltage is a voltage above the ground voltage and is below a threshold voltage difference applied between the selected bit line and the programming voltage of the drain select transistor included in the string. A method of programming a flash device according to another embodiment of the present invention includes: performing a first programming to program a certain erase cell to a first state and a second state higher than the first state; Performing a second programming in the following manner: applying a ground voltage to a first bit line connected to a string comprising selected memory cells to program certain erased cells to a third state above the second state, and A positive voltage is applied simultaneously to a second bit line connected to the memory cell to program the first programmed cell to the second state. A positive voltage difference between the threshold voltages of the second state and the third state is applied. A flash memory device according to the present invention, comprising: a memory cell array in which data is stored; and a page buffer connected to the memory cell through a bit line, and applying a first voltage when performing programming, One of the second voltage or the third voltage between the first and second voltages is applied to each of the bit lines. The first voltage is a power supply voltage, and the second voltage is a ground voltage and the third voltage is a positive voltage. 1354291 A positive voltage difference between the threshold voltages of the second state and the third state is applied. The positive voltage is transmitted in such a manner that the turn-on voltage of the element #1 from the page buffer to the bit line is not fully turned on but slightly turned on. Embodiments of the present invention will be explained with reference to the accompanying drawings. However, the invention is not limited to the disclosed embodiments. Additional advantages, objects, and features of the invention will be set forth in the <RTIgt; [Embodiment] Fig. 2 is a circuit diagram showing a programming method of a flash memory device in accordance with the present invention. Referring to Fig. 2, a cell block 100 constituting a memory cell array and a page buffer connected thereto is shown. The cell block 100 contains a plurality of strings S. To Sk. The bungee selects the transistor DST and the memory cell F. To F. And the source selective transistor SST is constructed in series to form each string. Each drain select transistor DST is connected to each bit line BL. Go to BLk to transfer the voltage of page buffer PB to the strings S. Go to Su or from these strings S. Up to 31; receiving the voltage of the page buffer PB. The respective source selection transistors SST are connected to the common source line CSL. Complex memory cell F. The Fn series is arranged in series between the drain selective transistor DST and the source selective transistor SST. The drain selects the gate of the transistor DST to share the drain select line DSL. Each of the gate selection transistors SST shares a source selection line ssl -10- 1354291 and is connected thereto. When programming and erasing, the page buffer PB transfers the voltage corresponding to the program and erase operation to the bit line BL. To BLk, and when read, is received by the bit line BL. The voltage applied to BLt. In the present invention, in addition to the first voltage (ie, 0V) generated in a typical programming operation and the second voltage (ie, Vcc), a third is generated between the first voltage and the second voltage. Voltage Vd. The third voltage Vd is a positive voltage between the first voltage and the second voltage, and will be described below with reference to Fig. 3. Figure 3 is a circuit diagram showing the page buffer of Figure 2. Referring to Fig. 3, even if the page buffer PB used in the present invention is a page buffer which further generates the third voltage as described above, the structure is similar to that of the conventional page buffer PB. However, one of the first to third voltages can be selectively transferred from the page buffer PB to the bit by adjusting the turn-on voltage of some of the elements constituting the page buffer PB. Yuan line BL. For ease of understanding, the page buffer PB will be briefly described with reference to FIG. The page buffer PB includes a selection circuit 32 for selecting a plurality of bit lines and is constructed in a double latch design. In a more detailed description, precharge element P1 is implemented by a PMOS transistor that operates in response to precharge signal PRECHb and is coupled between supply voltage Vcc and sense node SO. The programming element P2 is operative in response to the programming signal PGM and is coupled between the sensing node SO and the first node E1. The first control element P3 and the second control element P4 are connected in series between 111-1354291 between the second node E2 and the ground Vss, and the first control element p3 is operated in response to the voltage of the sensing node SO, and The second control element P4 operates in response to the first latch signal LAT1. The reset element p5 operates in response to the first reset signal RST1 and is connected between the first node E1 and the ground Vss. The first latch 33 is connected between the first node e i and the second node E2 and includes two inverters 13, 14. The transmitting element P6 operates in response to the transmission signal PDUMP and is connected between the sensing node S0 and the third node E3. The third control element P7 and the fourth control element P8 are connected in series between the third node E3 and the ground Vss, and the rr control element P7 is operated in response to the voltage applied to the sensing node S0. The four control elements P8 operate in response to the second latch signal LAT2. The second reset element P9 is operative in response to the second reset element rST2 and is coupled between the fourth node E4 and the ground Vss. The second latch 34 is coupled to the third node E3 and the fourth node E4 and includes two inverters 15, 16. The data input to the second challenge lock 34 is stored in accordance with the operation of the first input element P10 and the second input element PH. The first input element ριο operates in response to the first input signal DI and is coupled between the fourth node E4 and the fifth node E 5 . The second input element p is operated in response to the second input signal nDI and is connected between the third node E3 and the fifth node E5. The input and output elements P12 are operated in response to the input and output signals PBD. And connected between the first node E1 and the fifth node E5, and the fifth node E5 is connected to the input and output line DI0. The selection circuit 32 includes an even charging element p丨3, an odd charging element P14, an even number selecting element P15 and an odd number selecting element P16 for connecting the bit -12- 1354291 element lines BLe, BLo to the page buffer pb. The even charging element P13 and the odd charging element P14 are connected in series between the bit lines BLe, BLo through the sixth node E6. The even charging element p13 operates in response to the even charging signal DISCHe and is connected between the even bit line BLe and the sixth node E6. The odd charging element P14 operates in response to the odd charging signal DISCHo and is connected to the odd Between the bit line BLo and the sixth node E6. A charging voltage VIRPWR is applied to the sixth node E6. The even selection element P15 operates in response to the even selection signal BSLe and is coupled between the sense node SO and the even bit line BLe. The odd selection element P16 operates in response to the odd selection signal BSLo and is connected between the sensing node SO and the odd bit line BLo. When the programming is performed, if the programming signal PGM is activated, the programming element P2 is turned on and thus the voltage of the first latch 33 is transferred to the sensing node SO. The voltage transmitted to the sense node SO is transmitted to the even bit line BLe or the odd bit line BLo through the even selection element P15 or the odd selection element P16 of the selection circuit 32. On the other hand, when the third voltage is transmitted to the even or odd bit line BLe or BLo, if the programming element P2 is not fully turned on but is slightly turned on and the selection signal of the selection BSLe or BSLo is activated, then the third voltage Can be output to the bit line, wherein the third voltage is a positive voltage between the first voltage and the second voltage. Further, if the programming signal PGM is activated and the selection signal of the BSLe or BSLo is selected to be slightly turned on, the third The voltage can be output to the bit line. At this time, preferably, the program operation is performed in a state where the bit line BLe or BLo is a voltage of 0V. -13- 1354291 Next, the programming method according to the present invention will be described in detail with reference to a page 110 of Fig. 2. Fig. 4 is a partial circuit diagram showing Fig. 2 for explaining a method of programming a flash memory device in accordance with the present invention. According to one aspect of the present invention, the cell of the selected cell is 0F. To kF, programming causes the third memory cell to be 0F. To erase the state, the first cell 1 F. It is the PV 1 state and the second cell 2F. It is the PV2 state, the third cell 3F. It is the PV3 state and the kth cell kF. For the PV3 state. At this time, the erase state, the pv 1 state, the PV2 state, and the PV3 state are referred to as 11, 10, 00, and 01, respectively. However, this may vary depending on its definition, and in the present invention, the programming state is defined as the erase state, the PV1 state, the PV2 state, and the PV3 state depending on the level of the increased threshold voltage. An example of this will be explained with reference to Figures 5A through 5F. Figures 5A through 5F show the programming method of the Flash Flash device in accordance with the present invention. Referring to FIG. 5A, the erase operation is performed by the cell cell block before the program operation is performed, so that the memory cell (including all the memory cells of the memory cell 0F. to the kF cell block) becomes a wiper. The first memory cell except the state. Executing the erase operation causes a first voltage (i.e., 0 V) to be applied to the select word line WLO, and a second voltage (i.e., Vcc) is connected to all of the bit lines BLo to BLk. According to this erase operation, the threshold voltage distribution becomes the erased state (Fig. 5B). Referring to Figure 5C, a first programming operation as a low page programming LSB operation is performed to program the first cell (1F.) as the second memory cell of the PV1 state. At this time, the second cell 2F is simultaneously applied. The K-cell KF of -14-1354291 to be programmed to the PV2 state. The low page programming LSB operation is performed to become the PVl state. In detail, when the low page programming LSB is performed, the programming voltage is applied to the selected word line WLO, and the first voltage (ie, 〇v) is applied to the selected bit line BL1 'BL2 and BLk and the second voltage is applied. (ie, vcc) to the bit lines BLO and BL3 that are not selected. Therefore, the second cell (〇F.) maintains the erased state' and the first cell (1FO, the second cell (2F.), and the Kth cell (kF.) become the PV1 state (Fig. 5D). Referring to FIG. 5E, a second programming operation as a high page programming MSB operation is performed to program the third cell (3F.) to become a PV3 state. At the same time, the second cell 2F is programmed with the Kth cell KF. PV2 state. Its more detailed description / as follows: Apply a programming voltage to the selected word line WL0 and apply a first voltage (ie, 0V) to the bit line BL3 connected to the third cell 3F , to The third cell 3F〇 is programmed to become the PV3 state. Meanwhile, the third voltage Vd is applied to the bit line BL2 connected to the second cell 2F〇 to program the second cell to have a state higher than the PV1 state and lower than PV2 state of PV3 state (Fig. 5F). When the voltage of the PV1 state is referred to Va, the voltage of the PV2 state is referred to Vb, and the voltage of the PV3 state is referred to Vc. Preferably, Vc is applied. The third voltage Vd equal to the voltage difference of Vb, the threshold voltage of the PV2 state will be distributed in the PV1 state and PV Between the threshold voltages of the three states. However, there may be various factors that determine the threshold voltage distribution, which depends mainly on the amount of electrons stored in the floating gate. The number of electricity -15 - 1354291 stored in the floating gate can be The voltage difference between the word line and the semiconductor substrate is determined. If a programming voltage is applied to the word line and a ground voltage is applied to the channel of the semiconductor substrate via the bit line, the coupling phenomenon between the control gate and the floating gate is due to the programming voltage. The coupling phenomenon is induced by electrons flowing from the semiconductor substrate to the floating gate, and the threshold voltage of the programmed cell may vary depending on the number of electrons tunneled. Therefore, the threshold voltage of the programming cell is determined. An important factor is the voltage difference between the programming voltage applied to the word line and the voltage applied to the bit line. In this regard, a detailed description will be made with reference to the following given graph. FIG. 6 is a comparison of the present invention and the conventional The programming frequency curve of the flash memory device of the technology. Referring to Fig. 6, the 'X axis represents the programming frequency, and the y axis represents the threshold voltage. In order to program to the PV3 state, the programming operation (a) is first performed to reach the PV2 state, and then the programming operation (b) must be performed to further increase the threshold voltage to the PV3 state. However, in the present invention, the PV2 state and the PV3 state The Vd voltages of the same threshold voltage difference are simultaneously applied to the bit lines connected to the cells to be programmed into the PV2 state, and thus the PV2 state and the PV3 state can be programmed through only one programming operation (A). In order to shorten the programming operation time, it will be apparent to those skilled in the art that various modifications and changes can be made in the present invention. Therefore, it is intended that the present invention encompasses the scope of the accompanying claims and the like. Modifications and variations of the invention are provided within the scope of the invention. In the present invention, when a programming operation of a multi-order crystal-16-1354291 piece having a complex threshold voltage interval is performed, the difference between the different voltages and the threshold voltage applied to the bit line is the same 'and thus has a different threshold voltage The programming operations of the spaced cells can be performed simultaneously. Therefore, the frequency of the complex programming operation can be reduced to reduce the programming operation time. [Simple diagram of the diagram] The 1A to 1D diagrams respectively illustrate the traditional method of programming flash memory. Figure 2 is a circuit diagram showing a programming method of a flash memory device in accordance with the present invention. Fig. 3 is a circuit diagram showing the page buffer of Fig. 2. Fig. 4 is a partial circuit diagram showing the second diagram of the method of programming the flash memory device in accordance with the present invention. Figures 5A through 5F show a programming method for a flash memory device in accordance with the present invention. Fig. 6 is a graph showing the programming frequency of the flash memory device of the present invention and the prior art. -17- 1354291 [Description of main component symbols]
32 選 擇 電 路 33、34 閂 Λ4> 鎖 100 記 憶 胞 元 丨品- 塊 110 頁 面 DSL 汲 極 選 擇 線 WL0 〜WLn 字 元 線 SSL 源 極 選 擇 線 CSL 共 源 極 線 DST 汲 極 選 擇 電 晶 F0 ~ Fn 記 憶 胞 元 SST 源 極 選 擇 電 晶 SO〜Sk 串 BLO〜BLk 位 元 線 PB 頁 面 緩 衝 器 BLe 偶 數 位 元 線 BLo 奇 數 位 元 線 PI~P16 元 件 LAT1-LAT2 閂 鎖 信 m PRECHb 預 充 電 信 號 VIRPWR 充 電 電 壓 DISCHe 偶 數 充 電 信 號 DISCHo 奇 數 充 電 信 Wl BSLe 偶 數 選 擇 信 號 -18- 1354291 BSLo 奇 數 選 擇 信 號 PGM 編 程 信 號 PDUMP 傳 送 信 號 13-16 反 相 器 El ~E3 節 點 PBDO 輸 入 與 輸 出 信號 DI 、 nDI 輸 入 信 號 DIO 輸 入 與 輸 出 線32 selection circuit 33, 34 latch 4> lock 100 memory cell product - block 110 page DSL drain select line WL0 ~ WLn word line SSL source select line CSL common source line DST drain select transistor F0 ~ Fn Memory cell SST Source select transistor SO~Sk String BLO~BLk Bit line PB Page buffer BLe Even bit line BLo Odd bit line PI~P16 Component LAT1-LAT2 Latch letter m PRECHb Precharge signal VIRPWR Charging Voltage DISCHe Even Charge Signal DISCHo Odd Charge Signal Wl BSLe Even Select Signal -18- 1354291 BSLo Odd Select Signal PGM Program Signal PDUMP Transmit Signal 13-16 Inverter El ~E3 Node PBDO Input and Output Signal DI, nDI Input Signal DIO Input With output line
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