CN101202112B - Flash memory device and program method thereof - Google Patents
Flash memory device and program method thereof Download PDFInfo
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- CN101202112B CN101202112B CN2007103068631A CN200710306863A CN101202112B CN 101202112 B CN101202112 B CN 101202112B CN 2007103068631 A CN2007103068631 A CN 2007103068631A CN 200710306863 A CN200710306863 A CN 200710306863A CN 101202112 B CN101202112 B CN 101202112B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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Abstract
The present invention comprises a method of programming a flash memory device comprising performing a first program for programming cells to a first state and a second state higher than the first state, and performing a second program simultaneously together with the first program, for programming cells to the second state and a third state higher than the second state.
Description
Technical field
The present invention relates to a kind of flash memory device and programmed method thereof, relate in particular to a kind of flash memory device and programmed method that can improve program speed.
Background technology
Usually, flash memory device comprises insulation course, floating grid, dielectric layer and the control grid that is stacked on the Semiconductor substrate.Floating grid will be described its details below as charge storage layer.
When applying program voltage, producing F-N (Fowler-Nordheim) tunnelling phenomenon to the control grid by selected word line between Semiconductor substrate and floating grid, thereby electronics flows into floating grid to carry out programming operation from Semiconductor substrate.
The floating grid of store electrons becomes the programming unit with voltage higher than erase threshold voltage, and therefore can distinguish programming unit and this erase unit by this difference in distribution of read threshold voltages.
Flash memory device for example has two states, erase status or programming state, and will be called single-stage chip (" SLC ") with the memory device of an erase status and a programming state driving.On the other hand, developed the programmed method that is used for storing than each multistage storage unit of single-stage chip SLC more data, it is known as multistage chip (" MLC ").Operate this multistage chip MLC by the mode that in each distributed area of threshold voltage, defines each data mode that differs from one another.Below its more details will be described.
For example, when data are stored on the multistage chip MLC, the state that a storage unit may have can be divided into erase status, PV1 state, PV2 state and PV3 state.Here, suppose that the PV1 state is the programming state that has in the programmed threshold voltage interval between lowest region, the PV2 state is higher than the PV1 state in threshold distribution, and the PV3 state is higher than the PV2 state.So, for each threshold voltage interval, can define long numeric data (promptly 11,10,00 and 01) successively.Below, be described with reference to figure 1.
Figure 1A to Fig. 1 D illustrates traditional programmed method of flash memory device.Each threshold voltage interval that storage unit may be had is divided into erase status, PV1 state, PV2 state and PV3 state, and to 2 (multidigit) data values of each state definition.The low level of this 2 bit data value is called low page or leaf (lowpage), and a high position is called high page or leaf (high page).The programming operation of low page or leaf is called low page or leaf programming " LSB programming ", and the programming operation of high page or leaf is called high page or leaf programming " MSB programming ".
The programmed sequence of multistage chip MLC will be described below.
At first, in the memory cell array that with the piece is the unit configuration, all storage unit (Figure 1A) of wiping selected block.Subsequently, carry out low page or leaf programming LSB operation.
In low page or leaf programming LSB operation, be among the storage unit of erase status, ground voltage is applied to the bit line of selected storage unit, and supply voltage is applied to the bit line that does not select storage unit.Program voltage be applied to selected word line and will be applied to the mode of unselected word line, carry out low page or leaf programming LSB operation by voltage (pass voltage).So by these processes of low page or leaf programming LSB operation, the selected storage unit of erase status becomes PV1 state (Figure 1B).
High page or leaf programming MSB operation can be divided into the first high page or leaf programming MSB and the second high page or leaf programming MSB.
The first high page or leaf programming MSB operation is the operation that is used for selected storage unit is programmed for the PV2 state.For the storage unit of will wipe is programmed for the PV2 state, selected storage unit is programmed into the PV1 state from erase status by LSB, and afterwards it is carried out MSB programming so that selected storage unit becomes PV2 state (Fig. 1 C).
The second high page or leaf programming MSB operation is the operation (Fig. 1 D) that is used for selected storage unit is programmed for the PV3 state.Carry out the second high page or leaf programming MSB in the following manner, promptly in the storage unit of erase status, ground voltage is applied on the bit line of selected storage unit and and is applied on the word line that links to each other with selected storage unit program voltage.
Execution is programmed into each programming operation of each programming state (PV1 state, PV2 state or PV3 state) with the unit from erase status owing to have to, so may reduce the programming operation speed of multistage chip MLC.
Summary of the invention
According to the present invention, in the programming operation of multistage chip, the different voltages between the threshold voltage can be applied to bit line, and therefore can carry out programming operation simultaneously with different threshold voltages interval with different programmed threshold voltage interval.Therefore, can reduce the operating frequency of programming to reduce the programming operation time.
A kind of method that flash memory device is programmed according to an embodiment of the invention comprises: carry out first programming, the unit is programmed to first state and second state that is higher than this first state; And carry out second simultaneously with described first programming and programme, the unit is programmed to described second state and the third state that is higher than this second state.
This first programming is carried out in selected unit among the unit that is in erase status, make it to become this first state.
Selected unit is to be programmed to the unit of first state and second state, and when carrying out this first programming, with the unit that will be programmed to first state, the unit that will be programmed to second state is programmed to first state simultaneously.
Carry out this second programming, be programmed to the third state with the selected unit among the unit that will be in erase status, and the unit that will will be programmed to second state simultaneously among described first programmed cells is programmed to this second state.
When carrying out this second programming, positive voltage is put on the bit line that is connected to the unit that will be programmed to second state.
This positive voltage that is applied is poor between the threshold voltage of the threshold voltage of described second state and the described third state.
According to another embodiment of the present invention, a kind of method that flash memory device with erase status, first state, second state and third state is programmed, this method comprises: carry out first programming, so that some that are in first storage unit of erase status become second storage unit of first state that is in; And carry out second in the following manner and programme, being about to ground voltage puts on first bit line that is connected to the string (string) that comprises first storage unit, positive voltage is put on second bit line that is connected to the string that comprises second storage unit, so that described first storage unit becomes the 3rd storage unit of second state that is in, and described second storage unit becomes the 4th storage unit that is in the third state.
In described second state, by this second programming operation, threshold voltage becomes and is higher than the threshold voltage of first state; And in the third state, by this second programming operation, threshold voltage becomes and is higher than the threshold voltage of this second state.
Described positive voltage is a voltage and be lower than and be applied to selected bit line and be included in the voltage that the difference of the threshold voltage between the transistorized program voltage is selected in drain electrode in the described string above Ground.
According to another embodiment of the present invention, a kind of method that flash memory device is programmed comprises: carry out first programming, with some second states that are programmed to first state and are higher than first state in will the unit through wiping; And carry out second in the following manner and programme, being about to ground voltage puts on first bit line that is connected to the string that comprises selected storage unit and is programmed to the third state that is higher than second state with in will the unit through wiping some, and simultaneously, positive voltage is put on be connected to storage unit second bit line being programmed to second state through first programmed cells.
The positive voltage that is applied is poor between the threshold voltage of second state and the third state.
A kind of flash memory device according to the present invention comprises: memory cell array, storage data on it; And page buffer, it is connected to described storage unit by bit line, and when carrying out programming, and it applies in the tertiary voltage between first voltage, second voltage or this first and second voltage one to each bit line.
Described first voltage is supply voltage, and described second voltage is ground voltage, and tertiary voltage is a positive voltage.
The positive voltage that is applied is poor between the threshold voltage of second state and the third state.
Transmit described positive voltage in the following manner: (slightly) conducting rather than complete conducting transmit the forward voltage of the element of voltage to bit line from page buffer promptly slightly.
Embodiments of the invention are described with reference to the accompanying drawings.Yet the present invention is not limited to the disclosed embodiments.To describe other advantage of the present invention, purpose and feature in the following description, and to those skilled in the art, by research hereinafter, it is conspicuous.
Description of drawings
Figure 1A to Fig. 1 D shows the classic method that flash memory is programmed respectively.
Fig. 2 is the circuit diagram that shows according to the programmed method of flash memory device of the present invention.
Fig. 3 is the circuit diagram that shows the page buffer of Fig. 2.
Fig. 4 shows the part of Fig. 2 to explain the circuit diagram according to the programmed method of flash memory device of the present invention.
Fig. 5 A to Fig. 5 F shows the programmed method according to flash memory of the present invention successively.
Fig. 6 is the chart of the programming frequency of the flash memory device between relatively the present invention and the prior art.
Embodiment
Fig. 2 is the circuit diagram that illustrates according to the programmed method of flash memory device of the present invention.
With reference to figure 2, show the cell block 100 and the connected page buffer that comprise memory cell array.Cell block 100 comprises a plurality of strings (string) S
0To S
kDispose each string in the following manner: transistor DST, storage unit F are selected in drain electrode
0To F
n, and drain selection transistor SST be connected in series.Each drain electrode selects transistor DST to be connected to bit line BL
0To BL
kIn each, with to the string S
0To S
kTransmit the voltage of page buffer PB or from string S
0To S
kReceive the voltage of page buffer PB.Each drain selection transistor SST is connected to common source polar curve CSL.Select a plurality of storage unit F of arranged in series between transistor DST and the drain selection transistor SST in drain electrode
0To F
n
Drain electrode selects the gate electrode of transistor DST to share drain electrode selection wire DSL.Each gate electrode of drain selection transistor SST is shared drain selection line SSL and is connected thereto.
When programming and wiping, page buffer PB is to bit line BL
0To BL
kTransmit and the corresponding voltage of operation of programming and wiping, and when reading, receive from bit line BL
0To BL
kThe voltage that applies.
In the present invention, (be V except first voltage (being 0V) and second voltage that in the typical programmed operation, produces
Cc) outside, also produce the tertiary voltage V between first voltage and second voltage
dTertiary voltage V
dBe the positive voltage between first voltage and second voltage, will be described with reference to figure 3.
Fig. 3 is the circuit diagram of operation that the page buffer of Fig. 2 is shown.
With reference to figure 3, although employed page buffer PB is the page buffer that further produces tertiary voltage as previously mentioned among the present invention, its configuration is similar to traditional page impact damper PB.Yet,, can optionally transmit first to the tertiary voltage one to bit line BL from page buffer PB by the connection voltage of some element among the element that adjust to constitute page buffer PB.For the ease of understanding, will page buffer PB be described briefly with reference to figure 3.
Page buffer PB comprises the selection circuit 32 that is used to select multiple bit lines, and is configured to twin-lock and deposits design (dual latch design).
More specifically explanation, precharge element P1 is implemented as the PMOS transistor, and it is worked in response to precharging signal PRECHb, and is connected supply voltage V
CcAnd read between the node S0.Programmed element P2 works in response to programming signal PGM, and is connected and reads between node S0 and the first node E1.The first control element P3 and the second control element P4 are connected in series in Section Point E2 and ground V
SsBetween, and the described first control element P3 works in response to the voltage of reading node S0, and the described second control element P4 works in response to the first latch signal LAT1.Reposition element P5 works in response to the first reset signal RST1, and is connected described first node E1 and ground V
SsBetween.First latch 33 is connected between described first node E1 and the Section Point E2, and comprises two phase inverter I3, I4.Conveying element P6 response transmits signal PDUMP and works, and is connected described reading between node S0 and the 3rd node E3.The 3rd control element P7 and the 4th control element P8 are connected in series in described the 3rd node E3 and ground V
SsBetween, and described the 3rd control element P7 works in response to being applied to the voltage of reading node S0, and the 4th control element P8 works in response to the second latch signal LAT2.The second reposition element P9 works in response to the second reset signal RST2, and is connected the 4th node E4 and ground V
SsBetween.Second latch 34 is connected between described the 3rd node E3 and the 4th node E4, comprises two phase inverter I5, I6.According to the operation of the first input element P10 and the second input element P11, the data that are input to second latch 34 are stored thereon.The first input element P10 works in response to the first input signal DI, and is connected between the 4th node E4 and the 5th node E5.The second input element P11 works in response to the second input signal nDI, and is connected between described the 3rd node E3 and the 5th node E5.Input and output element P12 works in response to input and output signal PBDO, and is connected between described first node E1 and the 5th node E5, and described the 5th node E5 is connected to input and output line DI0.
Select circuit 32 to comprise and be used for bit line BLe, BLo are connected to the even charge member P13 of page buffer PB, strange charge member P14, idol selection element P15 and very select element P16.Idol charge member P13 and strange charge member P14 are connected in series between bit line BLe, the BLo by the 6th node E6.Idol charge member P13 works in response to even charging signals DISCHe, and is connected between even bit line BLe and the 6th node E6, and strange charge member P14 works in response to strange charging signals DISCHo, and is connected between strange bit line BLo and the 6th node E6.Charging voltage VIRPWR is applied to the 6th node E6.Idol is selected element P15 to select signal BSLe in response to idol and is worked, and is connected described reading between node S0 and the even bit line BLe.The strange element P16 that selects works in response to the strange signal BSLo of selection, and is connected described reading between node S0 and the strange bit line BLo.
When programming operation, if programming signal PGM is activated, then programmed element P2 is switched on, and the voltage of first latch 33 is sent to reads node S0 thus.Being sent to the voltage of reading node S0 selects element P15 by the idol of selecting circuit 32 or very selects element P16 to be sent to even bit line BLe or strange bit line BLo.
On the other hand, when tertiary voltage is sent to occasionally strange bit line BLe or BLo, if programmed element P2 is not complete conducting but omits lightly conducting, and select signal BSLe or BSLo to activate, then can export tertiary voltage to bit line, this tertiary voltage is the positive voltage between first voltage and second voltage.In addition, if programming signal PGM be activate and slightly lightly conducting select signal BSLe or BSLo, then can export tertiary voltage to bit line.At this moment, preferably, be that the state of 0V is carried out programming operation with the voltage of bit line BLe or BLo.
Next, will describe in detail according to programmed method of the present invention with reference to one page 110 of figure 2.
Fig. 4 illustrates the part of Fig. 2 to explain the circuit diagram according to the programmed method of flash memory device of the present invention.According to an aspect of the present invention, the storage unit 0F in the selected page
0To kF
0Among, programming is so that the 0th unit 0F
0Be erase status, first module 1F
0Be the PV1 state, the second unit 2F
0Be the PV2 state, the 3rd unit 3F
0Be PV3 state and k unit kF
0Be the PV2 state.At this moment, erase status, PV1 state, PV2 state and PV3 state are called 11,10,00 and 01.Yet this can define according to it and change, and in the present invention, the order according to threshold voltage increases is defined as erase status, PV1 state, PV2 state and PV3 state with programming state.With reference to figure 5A to Fig. 5 F embodiment is described.
Fig. 5 A to Fig. 5 F shows the programmed method according to flash memory of the present invention successively.
With reference to figure 5A, before carrying out programming operation, be that unit carries out erase operation with the cell block, so that storage unit (comprises storage unit 0F
0To kF
0Whole storage unit of cell block) become first storage unit that is in erase status.Carry out erase operation, thereby first voltage (being 0V) put on selected word line WLO and (be V second voltage
Cc) be connected to all bit line BLo to BLk.According to erase operation, threshold voltage distribution becomes erase status (Fig. 5 B).
With reference to figure 5C, carry out first programming operation, with first module (1F as low page or leaf programming LSB operation
0) be programmed to second storage unit that is in the PV1 state.At this moment, simultaneously to being programmed to second and K unit 2F of PV2 state
0And KF
0Carry out low page or leaf programming LSB operation, make it to become the PV1 state.
More detailed, when low page or leaf is programmed LSB, program voltage is applied to selected word line WLO, and first voltage (that is, 0V) is applied to selected bit line BL1, BL2 and BLk, and second voltage (being Vcc) is applied to not bit selecting line BL0 and BL3.As a result, the 0th unit (0F
0) keep erase status, and first module (1F
0), the second unit (2F
0) and k unit (kF
0) become PV1 state (Fig. 5 D).
With reference to figure 5E, carry out second programming operation, with the 3rd unit (3F as high page or leaf programming MSB operation
0) be programmed to and become the PV3 state.Simultaneously, with the second unit 2F
0With K unit KF
0Be programmed to the PV2 state.To be described in more detail it subsequently.
Program voltage is put on selected word line WLO, and first voltage (being 0V) put on be connected to the 3rd unit 3F
0Bit line BL3, with the 3rd unit 3F
0Be programmed to the PV3 state.Simultaneously, tertiary voltage Vd is put on be connected to the second unit 2F
0Bit line BL2, Unit second is programmed to PV2 state (Fig. 5 F) with threshold voltage distribution high and lower than the threshold voltage distribution of PV3 state than the threshold voltage distribution of PV1 state.
Simultaneously, if the calibration voltage of PV1 state is called the calibration voltage that the calibration voltage of Va, PV2 state is called Vb and PV3 state and is called Vc, then because the threshold voltage of PV2 state must be distributed between the threshold voltage of PV1 state and PV3 state, therefore the tertiary voltage Vd that is preferably applied equals the voltage difference of Vc and Vb.
The various factors that may exist decision threshold voltage to distribute, however it depends primarily on the amount that is stored in the electronics on the floating grid.Can determine to be stored in the amount of the electronics on the floating grid by the voltage difference between word line and the Semiconductor substrate.
If program voltage is applied to word line and by bit line ground voltage is applied to the raceway groove of Semiconductor substrate, then produce the control grid that causes by program voltage and the coupling phenomenon between the floating grid.This coupling phenomenon causes the tunnelling phenomenon, and by this tunnelling phenomenon, electronics flows to floating grid from Semiconductor substrate, and the threshold voltage of unit by programming may change with the amount of tunnelling electronics.Therefore, determine that the key factor of the threshold voltage of unit by programming is to be applied to the program voltage of word line and to be applied to voltage difference between the voltage of bit line.About this point, reference chart is described in detail subsequently.
Fig. 6 is the chart of the programming frequency of the flash memory device between relatively the present invention and the prior art.
With reference to figure 6, the x axle is represented the frequency of programming.And the y axle is represented threshold voltage.In the prior art,, at first carry out programming operation a to reach the PV2 state in order to be programmed to the PV3 state, must carry out then programming operation b with further raising threshold voltage to the PV3 state.
Yet, in the present invention, simultaneously apply voltage Vd to being connected to the bit line that to be programmed to the unit that becomes the PV2 state, this voltage Vd equals threshold voltage poor of PV2 state and PV3 state, thereby only promptly can carry out the programming of PV2 state and PV3 state, therefore reduce the programming operation time by the one-time programming operation A.
It will be apparent to those skilled in the art that and to make various modifications and distortion to the present invention.Therefore, this invention is intended to cover interior modification of the present invention and the distortion of scope that falls into appended claims and equivalent thereof.
In the present invention, when execution has the programming operation of multistage chip in a plurality of threshold voltages interval, apply the different voltage of the difference that equals threshold voltage to bit line, thereby can carry out programming operation to unit simultaneously with different threshold voltages interval.Therefore, can reduce the frequency of a plurality of programming operations to reduce the programming operation time.
Cross reference to related application
The application requires the korean patent application 2006-96007 that submits on September 29th, 2006 and the right of priority of the korean patent application 2007-63576 that submits on June 27th, 2007, and its full content is by with reference to being incorporated in this.
Claims (10)
1. method that flash memory device is programmed, described equipment comprises page buffer, this page buffer comprises that described method comprises via being used to select the selection circuit of bit line to be couple to reading node, be connected first latch and read the programmed element between the node of bit line and to be connected the precharge element of reading between node and the supply voltage node:
By ground voltage being applied to second bit line that couples with second programming unit among first bit line that couples with first programming unit among the bit line and the bit line, carry out first programming, so that first programming unit and second programming unit are programmed to first state; And
Carry out second programming in the following manner, second programming unit is programmed to second state that is higher than this first state by second bit line that positive voltage is applied among the bit line, and the 3rd programming unit is programmed to the third state that is higher than this second state by ground voltage being applied to the 3rd bit line that couples with the 3rd programming unit
Wherein said positive voltage is applied to second bit line by omiting the lightly conducting programmed element.
2. method according to claim 1 wherein, is carried out this first programming to the selected unit among the unit that is in erase status, makes it to become this first state.
3. method according to claim 1 wherein, when execution described first is programmed, with first programming unit, is programmed to this first state with second programming unit simultaneously.
4. method according to claim 1, wherein, carry out this second programming, be programmed to the described third state with described the 3rd programming unit among the unit that will be in erase status, and the unit that will will be programmed to described second state simultaneously among described first programmed cells is programmed to this second state.
5. method according to claim 1, wherein, when programming signal was activated, programmed element was switched on.
6. method according to claim 1, wherein, this positive voltage is poor between the threshold voltage of the threshold voltage of described second state and the described third state.
7. method that the flash memory device with one of erase status, first state, second state and third state is programmed, and described equipment comprises page buffer, this page buffer comprises that this method comprises via being used to select the selection circuit of bit line to be couple to reading node, be connected first latch and read the programmed element between the node of bit line and to be connected the precharge element of reading between node and the supply voltage node:
Carry out first programming, so that some that are in first storage unit of erase status become second storage unit of first state that is in; And
Carry out second programming in the following manner, being about to ground voltage puts on first bit line that is connected to the string that comprises first storage unit among the bit line, positive voltage is put on second bit line that is connected to the string that comprises second storage unit among the bit line, so that described first storage unit becomes the 4th storage unit that is in the third state, and described second storage unit becomes the 3rd storage unit of second state that is in
Wherein this positive voltage is applied to second bit line by omiting the lightly conducting programmed element.
8. according to the method described in the claim 7, wherein, in described second state, by described second programming, its threshold voltage becomes and is higher than the threshold voltage of first state; And in the described third state, by this second programming, its threshold voltage becomes and is higher than the threshold voltage of described second state.
9. flash memory device with page buffer, described page buffer comprises
Be couple to the node of reading of bit line via the selection circuit that is used to select bit line;
First latch and second latch;
The precharge element is connected and reads between node and the supply voltage node; And
Programmed element transmits supply voltage, ground voltage or positive voltage,
Described flash memory device is carried out first programming and second programming, wherein
By ground voltage being applied to second bit line that couples with second programming unit among first bit line that couples with first programming unit among the bit line and the bit line, carry out first programming, so that first programming unit and second programming unit are programmed to first state; And
Carry out second programming in the following manner, second programming unit is programmed to second state that is higher than this first state by second bit line that positive voltage is applied among the bit line, and the 3rd programming unit is programmed to the third state that is higher than this second state by ground voltage being applied to the 3rd bit line that couples with the 3rd programming unit
Wherein said positive voltage is sent to the described node of reading by omiting the lightly conducting programmed element.
10. according to the flash memory device described in the claim 9, wherein, described programmed element is connected reads between the node and first latch.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR96007/06 | 2006-09-29 | ||
| KR20060096007 | 2006-09-29 | ||
| KR1020070063576A KR100898684B1 (en) | 2006-09-29 | 2007-06-27 | Flash memory device and program method thereof |
| KR63576/07 | 2007-06-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101202112A CN101202112A (en) | 2008-06-18 |
| CN101202112B true CN101202112B (en) | 2011-11-23 |
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| CN2007103068631A Expired - Fee Related CN101202112B (en) | 2006-09-29 | 2007-09-29 | Flash memory device and program method thereof |
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|---|---|
| KR (1) | KR100898684B1 (en) |
| CN (1) | CN101202112B (en) |
| TW (1) | TWI354291B (en) |
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| US8031517B2 (en) | 2008-07-30 | 2011-10-04 | Samsung Electronics Co., Ltd. | Memory device, memory system having the same, and programming method of a memory cell |
| US7800949B2 (en) * | 2008-09-25 | 2010-09-21 | Macronix International Co., Ltd | Memory and method for programming the same |
| KR101044540B1 (en) | 2009-06-30 | 2011-06-27 | 주식회사 하이닉스반도체 | Semiconductor memory device and programming method thereof |
| KR20140028582A (en) | 2012-08-29 | 2014-03-10 | 에스케이하이닉스 주식회사 | Semiconductor memory device and operating method thereof |
| CN106856102B (en) * | 2015-12-08 | 2020-11-03 | 西安格易安创集成电路有限公司 | Programming method for Nand Flash |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288935B1 (en) * | 1999-09-20 | 2001-09-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device for storing multivalued data |
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|---|---|---|---|---|
| KR100432889B1 (en) * | 2002-04-12 | 2004-05-22 | 삼성전자주식회사 | 2 bit programable non-valotile memory device and method of operating and fabricating the same |
| KR100512181B1 (en) * | 2003-07-11 | 2005-09-05 | 삼성전자주식회사 | Flash memory device having multi-level cell and method for its reading operation and program operation |
-
2007
- 2007-06-27 KR KR1020070063576A patent/KR100898684B1/en not_active IP Right Cessation
- 2007-09-27 TW TW096135847A patent/TWI354291B/en active
- 2007-09-29 CN CN2007103068631A patent/CN101202112B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6288935B1 (en) * | 1999-09-20 | 2001-09-11 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device for storing multivalued data |
| US6496412B1 (en) * | 1999-09-20 | 2002-12-17 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device for storing multivalued data |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101202112A (en) | 2008-06-18 |
| KR100898684B1 (en) | 2009-05-22 |
| TW200816204A (en) | 2008-04-01 |
| TWI354291B (en) | 2011-12-11 |
| KR20080029758A (en) | 2008-04-03 |
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