TWI351740B - Electronic part - Google Patents
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- TWI351740B TWI351740B TW096105253A TW96105253A TWI351740B TW I351740 B TWI351740 B TW I351740B TW 096105253 A TW096105253 A TW 096105253A TW 96105253 A TW96105253 A TW 96105253A TW I351740 B TWI351740 B TW I351740B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Description
1351740· 九、發明說明： 【發明所屬之技術領域】 本發明係關於電子元件，牿β 框、右媸甘』 疋關於稱呼為由引括 有機基板、陶究基板等所構成之封裝的電子元件引線 【先前技術】 近年來，搭載有半導體等晶片的電子 知且稱呼為所謂之IC 糸為種種已 I其叔物。°例如是由引線框、有檣 基板、陶兗基板等所構成之封震。 有機 子凡件因高密度實裝的要求，的電 认电 旳百日益朝小型化、多銷化 改良，然此要求有越來越嚴格的傾向。 、有~述ic封裝基本上係由包括具連接端子的晶片 以及具經由連接端子而搭載前述晶片之晶片搭載部及用以 實裝於基板上之實裝端子的基體所構成的電子元件。還 有，在前述結構之電子元件中，習知對使用焊料或結合導 線作為接合材料储確立為冑le封裝實裝於㈣線路板 等基板時不可欠缺的接合技術。 關於此電子元件實裝技術而言，已知者例如是在引線 框之情形下’為了提高在導線接合及焊料接合端子方面的 接合特性，係有於構成端子的銅表面上依序形成鎳電鍍披 覆膜、鈀電鍍披覆膜、金電鍍披覆膜的結構（參照專利文獻 1) 〇 其甲使用把電鑛披覆膜是因為不僅要防止基礎銅的擴 散’而且還要確實地進行利用焊料或導線結合等的結合。 2169-8661-PF；Ahddub 1.351.740 然而’近年來因為電子元件或半導體元件的小型化、高密 度化所致之貫裝技術進展結果，前述接合特性要求係趨於 更加嚴格。 為此，一種在此鈀電鍍披覆膜中添加錄或銻等元素’ 以形成引線框外引線接合部的技術被提出（參照專利文獻 2)。然此種鈀電鍵披覆膜僅可在承受一定程度之熱經歷 下，實現良好的接合特性。 [專利文獻1]日本專利特開平9 — 8438號公報 [專利文獻2]曰本專利特開平6-23231 1號公報 【發明内容】 [發明所欲解決的課題] 然而，隨著封裝的小型化或高密度化，在進行接合部 分本身薄膜化或小面積化的現實狀況下，接合技術係被要 求在接合部分受到高溫熱經歷的情形下以實現良好接合狀 態1別是在焊料的接合中，從提高製造效率的觀點看， 現實狀況疋為了在承受高溫熱經歷情形下獲得良好接合， 而強烈要求電子元件包括有具較佳耐熱性之接合部分； 本發明係在以上述事情為背景之情形下，於由包括且 =端子的晶片以及具經由連接端子而搭載前述晶片之晶 =載部及用以實裝於基板上之實裝端子的基體所構成的 π件令’提供一種禪料等接合特性進一步提升的電子 兀件。特別是在焊料的接合中 之4供一種具較佳耐熱性 2169-866l-pF;Ahddub 7 [用以解決課題的手段] 為了解決上述問題，太欢。口 I 谁〜發月者等重覆對鈀電鍍披覆膜 進仃深入研究的結果，發 赞現藉由把電鍍披覆膜中添加鍺而 传之披覆膜，可以大幅提異蛩工_丄 、 钕升電子π件中因焊料或導線接合 形成連接端子或實裝端子的妨L人4士 千的接合特性，而致完成本發明。1351740. IX. Description of the Invention: [Technical Field] The present invention relates to an electronic component, an 牿β frame, and a right 媸 』 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋 疋Leads [Prior Art] In recent years, an electronic device in which a semiconductor such as a semiconductor is mounted is known as a so-called IC. ° is, for example, a shock shield composed of a lead frame, a ruthenium substrate, a ceramic substrate, or the like. Due to the high-density mounting requirements of the organic parts, the number of electronic products is becoming more and more miniaturized and multi-marketing. However, there is an increasing demand for stricter requirements. The ic package is basically an electronic component including a wafer having a connection terminal and a substrate having a wafer mounting portion on which the wafer is mounted via a connection terminal and a mounting terminal mounted on the substrate. Further, in the electronic component of the above-described structure, it is conventionally known that the use of solder or a bonding wire as a bonding material is established as a bonding technique which is indispensable when it is mounted on a substrate such as a (4) wiring board. With regard to this electronic component mounting technology, for example, in the case of a lead frame, in order to improve bonding characteristics in wire bonding and solder bonding terminals, nickel plating is sequentially formed on the copper surface constituting the terminal. The structure of the coating film, the palladium-plated coating film, and the gold-plated coating film (see Patent Document 1). The use of the electric ore coating film is because it is not only necessary to prevent the diffusion of the base copper, but also to be used reliably. A combination of solder or wire bonding, etc. 2169-8661-PF; Ahddub 1.351.740 However, in recent years, as a result of the advancement of the packaging technology due to miniaturization and high density of electronic components or semiconductor components, the aforementioned bonding characteristics have become more stringent. For this reason, a technique of adding an element such as a recording or ruthenium to the palladium-plated coating film to form a lead frame outer wire bonding portion has been proposed (see Patent Document 2). However, such a palladium bond coating film can achieve good bonding characteristics only under a certain degree of thermal experience. [Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 9-8438 (Patent Document 2) Japanese Patent Application Laid-Open No. Hei 6-23231 No. Or high density, in the actual situation where the bonding portion itself is thinned or small-area, the bonding technique is required to achieve a good bonding state in the case where the bonding portion is subjected to high-temperature heat history 1 in the bonding of the solder. From the viewpoint of improving manufacturing efficiency, the reality is that in order to obtain good bonding under the experience of withstanding high-temperature heat, it is strongly required that the electronic component includes a joint portion having better heat resistance; the present invention is based on the above matters. In the case of the π-piece of the wafer including the = terminal and the substrate having the crystal-mounted portion of the wafer and the mounting terminal mounted on the substrate via the connection terminal, a zen is provided An electronic component whose bonding characteristics are further improved. In particular, in the bonding of solder 4, a kind of heat resistance 2169-866l-pF is preferred; Ahddub 7 [means for solving the problem] is too happy to solve the above problems. The result of in-depth study of the palladium-plated drape film by the mouth I, the moon, etc., and the praise can be greatly improved by adding the enamel to the plating film. In the π and 钕 电子 电子 π 因 因 焊料 焊料 焊料 焊料 焊料 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。
發月在由包括具連接端子的晶片以及具經由連接端 子而搭載前述晶片之晶片搭載部及用以實裝於基板上之實 裝端：的基體所構成的電子元件中，前述晶片的連接端 子、前述基體的晶片搭載部、實裝端子中至少任—個係形 成有含錯之鈀電鍍披覆膜。依據本發明，可以實現因焊料 或導線結合等接合中耐熱性非常高的電子元件。In the electronic component including the wafer including the connection terminal and the substrate mounting portion on which the wafer is mounted via the connection terminal, and the substrate to be mounted on the substrate, the connection terminal of the wafer At least one of the wafer mounting portion and the mounting terminal of the base body is formed with a palladium-plated plating film having an error. According to the present invention, it is possible to realize an electronic component having very high heat resistance in bonding due to solder or wire bonding.
本發明電子元件較佳是形成錄電鑛披覆膜作為飽電鍍 披覆膜之基礎電鍍披覆膜。雖然銅等導電部分上也可以直 接形成趣電鑛披覆膜，然在形成有鎖電鍵披覆膜作為基礎 電鑛披覆膜的導電部分上’形成含錯之把電鑛披覆膜時， 則可以更確實實現可於晶片連接端子、基體之晶片搭載部 或貫裝端子形成時具較佳对熱性的電子元件。 此把電鍍披覆膜厚度較佳是〇· 001微米至5微米，把 電鍍披覆膜中鍺含量較佳是PiOOOOppm。披覆膜厚度不足 0. 001微米時，會減少鈀電鍍彼覆膜的阻擋效果，而難以 實現較佳耐熱性；而披覆膜厚度超過5微米時，則因鈀量 過多導致成本增加而為不實用。還有，鈀電鍍披覆膜中錯 含量未滿1 ppm時，會減少鈀電鍍披覆膜的阻擋效果，而難 以實現較佳耐熱性；而鈀電鍍披覆臈中鍺含量超過 2169-8661-PF;Ahddub 8 1351740 1 000Oppm 時， 則會有影響導線結合特性 或焊料接合特性的 還有’係非常適用於有引線框、有 中任-種所構成之封裝的電子元# +板陶光基板 線框型式的1C封裝時，钟θ *如ώ 件為引 裝時就疋在内引線或外引線上形成含錯 鈀電鍍披覆膜。還有，本發 3鍺 电于兀件為由有機基板或陶 瓷基板所構成之1C封穿砗，钱β *從 4陶 L对裒時，就疋在稱呼為銲墊、銷、合Preferably, the electronic component of the present invention forms a recording electroplating film as a base plating film for a saturating plating film. Although the conductive portion of copper or the like may directly form the coating of the electric ore, when the electroless ore coating film is formed on the conductive portion of the base electric ore coating film formed by the lock electric button coating film, Further, it is possible to more reliably realize an electronic component which is preferably heat-sensitive at the time of forming the wafer connection terminal, the wafer mounting portion of the substrate, or the via terminal. The thickness of the plating film is preferably from 001 μm to 5 μm, and the content of bismuth in the plating film is preferably PiOOOOppm. When the thickness of the coating film is less than 0.001 μm, the barrier effect of the palladium plating film is reduced, and it is difficult to achieve better heat resistance. When the thickness of the coating film exceeds 5 μm, the cost is increased due to the excessive amount of palladium. Not practical. In addition, when the content of the palladium plating coating is less than 1 ppm, the barrier effect of the palladium-plated coating film is reduced, and it is difficult to achieve better heat resistance; and the content of yttrium in the palladium plating coating exceeds 2169-8661- PF; Ahddub 8 1351740 1 000Oppm, there will be some influence on the wire bonding characteristics or solder bonding characteristics, and the system is very suitable for the package with the lead frame, the middle of the package of the electronic element # + plate ceramic substrate In the wire-frame type 1C package, the clock θ * is formed on the inner lead or the outer lead when the ferrule is used as a lead. In addition, the present invention is a 1C seal that consists of an organic substrate or a ceramic substrate. When the money β* is from 4 ceramics, it is called a pad, pin, and joint.
面之部分上形成含鍺鈀電鍍披覆膜。亦即形成電子：件 之際，晶片搭載或連接於基體之情形，或者將電子元件實 裝於基板等之情形下，係於進行依據焊料或導線結合的接 合時，於前述的接合部合μ # 士、人& Λ 』丧口。丨刀上形成合鍺鈀電鍍披覆膜，即可 得到耐熱性提高的電子元件。還有，電子元件被實裝於基 板侧的連接部分上，形成含錢電鑛披覆膜也是有效的。 形成本發明電子元件時，較佳是在含可溶性鈀鹽與電 傳導鹽㈣電㈣中，使用含錯的㈣鑛液。更具體而言， 以紐金屬換算量來看，也可以使用前述可溶性㈣量為〇1 克/升至50克/升、前述電傳導鹽為1〇克/升至4〇〇克/升、 前述鍺為0.1毫克/升至1 000毫克/升等的鈀電鍍液。 此鈀電鍍液之前述可溶性鈀鹽較佳是包含氨基系鈀錯 合物或氨系鈀錯合物的物質，更具體的是使用由二氣乙烯 一胺把（II)、氯化把、二氣二氨合鈀（II)、二硝基二氨合 鈀（11)、四氨合鈀（11)硝酸鹽、四氨合鈀（〗丨）硫酸鹽、草 酸根二氨合鈀（II)、四氨合鈀草酸鹽、四氨合鈀（11) 氣化物中至少一種。還有也可以組合使用前述2種以上。 2169-8661-PF;Ahddub 9 1351740 硫酸銨等。 還有，電傳導鹽可乂 J从使用亂化録、確酸錢 [發明效果] 發明’可以實現由引線框、有機基板、陶瓷基 任-種所構成之封裝中，於因焊料或導線結合等接合中 具有高耐熱性、接合特性佳的電子元件。 【實施方式】 φ 以下，基於本發明較佳實施例進行詳細說明。在本實 施例中，本發明電子元件一例係採用引線框型式IC封裝， 進行使用含鍺鈀電鍍披覆膜時的焊料潤濕性評估，並對關 於ic封裝耐熱性調查而得之結果進行說明。 焊料潤濕性評估係使用鋼合金引線框，並以前述引線 框表面上形成有被鎳電鍍披覆膜、鈀電鍍披覆膜、金電鍍 披覆膜依序電鍍處理的接合部的結構作為評估樣品。以 下’係對形成此接合部時各電鍍處理條件進行說明。 鲁鎳電鍍處理（目標膜厚為〇· 7微米）A palladium-containing electroplated coating film is formed on the surface portion. In the case where an electronic component is formed, when the wafer is mounted or connected to the substrate, or when the electronic component is mounted on the substrate or the like, the bonding is performed at the bonding portion when bonding by solder or wire bonding is performed. #士,人& Λ 』 An electronic component with improved heat resistance can be obtained by forming a palladium-plated plating film on the file. Further, it is also effective that the electronic component is mounted on the connection portion on the substrate side to form a money-containing electric ore coating film. In forming the electronic component of the present invention, it is preferred to use a miscible (iv) ore solution in the soluble palladium salt and the electrically conductive salt (iv) electricity (d). More specifically, in terms of the amount of the neodymium metal, it is also possible to use the aforementioned soluble (four) amount of 〇1 g / liter to 50 g / liter, and the aforementioned electrically conductive salt of 1 gram / liter to 4 gram / liter, The foregoing crucible is a palladium plating solution of 0.1 mg/liter to 1 000 mg/liter. The aforementioned soluble palladium salt of the palladium plating solution is preferably a substance containing an amino-based palladium complex or an ammonia-based palladium complex, and more specifically, (II), chlorinated, and Gas diamine palladium (II), dinitrodiammine palladium (11), tetraammine palladium (11) nitrate, tetraammine palladium (〗 〖) sulfate, oxalate diammine palladium (II) At least one of tetraammine palladium oxalate and tetraammine palladium (11) vapor. Further, two or more of the above may be used in combination. 2169-8661-PF; Ahddub 9 1351740 Ammonium sulfate, etc. In addition, the electrically conductive salt can be used in a package composed of a lead frame, an organic substrate, or a ceramic substrate, from the use of a chaotic recording, and an acid source [invention effect]. An electronic component having high heat resistance and good bonding characteristics during bonding. [Embodiment] φ or less will be described in detail based on a preferred embodiment of the present invention. In the present embodiment, an example of the electronic component of the present invention is a lead frame type IC package, and the solder wettability evaluation using the palladium-containing palladium plating film is performed, and the results of the ic package heat resistance investigation are explained. . The solder wettability evaluation uses a steel alloy lead frame and evaluates the structure of the joint portion on which the nickel plating film, the palladium plating film, and the gold plating film are sequentially plated on the surface of the lead frame. sample. Hereinafter, each plating treatment condition when forming the joint portion will be described. Lu Nickel plating treatment (target film thickness is 〇·7 μm)
Sulfurous Mex 100(ELECTROPLATING ENGINEERS OF JAPAN 股份有限公司製，液體組成：含氨基磺酸的電錢液） 液溫 攝氏5 0度 電流密度 3安培/平方公尺 鈀電鍍處理（目標膜厚為0· 03微米） 二氯二氨合鈀（以鈀金屬換算）4克/升 氨水 20毫升/升 氣化銨 100克/升 2169-8661-PF;Ahddub 10 1-351740 液溫 電流密度 金電鍍處理（目標膜厚為〇.〇〇7微米） 氧化鍺（以鍺金屬換算） 酸驗值（pH) 10、100、500 毫克/升 8. 5 攝氏55度 0. 75安培/平方公尺Sulfurous Mex 100 (ELECTROPLATING ENGINEERS OF JAPAN Co., Ltd., liquid composition: sulfamic acid-containing liquid money solution) Liquid temperature Celsius 50 degrees Current density 3 amps / square meter palladium plating treatment (target film thickness is 0 · 03 Micron) Dichlorodiammine palladium (calculated as palladium metal) 4 g / liter ammonia water 20 ml / liter of ammonium sulphate 100 g / liter 2169-8661-PF; Ahddub 10 1-351740 liquid temperature current density gold plating treatment (target The film thickness is 〇.〇〇7 μm) yttrium oxide (calculated as ruthenium metal) acid value (pH) 10, 100, 500 mg / liter 8. 5 ° C 55 ° 0. 75 amp / m ^ 2
Post Flash 100(ELECTROPLATING ENGINEERS OF JAPAN 股 份有限公司製’含氰化金鉀的電鍍液） 液溫Post Flash 100 (Electroplating solution containing potassium cyanide) manufactured by ELECTROPLATING ENGINEERS OF JAPAN Co., Ltd.
攝氏50度 電流密度 0· 05安培/平方公尺 將上述各電鍍處理依據第1圖所示之流程，於引線框 表面上依序進行處理，以製作焊料潤濕性評估用的評估樣50 degrees Celsius Current density 0·05 amps/m2 The above plating treatments are sequentially processed on the surface of the lead frame in accordance with the flow shown in Fig. 1 to prepare an evaluation sample for solder wettability evaluation.
於此第1圖中，最初的電解脫脂處理（E_Trex 12 : ELECTROPLATING ENGINEERS OF JAPAN 股份有限公司製， 液溫為攝氏60度，施加電壓為6伏特，浸潰時間為3〇秒） _係為用以去除引線框表面污染物或氧化物等的前處理。 作成的評估樣品，係為使電鍍液中鍺添加量分別為 10、100、500毫克/升而形成鈀電鍍披覆膜，而製作得到， 合計有3種（表1所示之實施例1至實施例3) 表1 錄添加量 實施例1 10毫克/升 實施例2 100毫克/升 實施例3 500毫克/升 還有，使用習知鈀電鍍液作成評估樣品（習知例）。此 2169-8661-PF;Ahddub 11 1351740 %知例除改進仃以下所示之把電鐘處理外，其餘鎳電錄處 理、金電鐘處理條件及流程全部與上述實施例之評估樣品 習知例之鈀電鍍處理（目標膜厚為〇〇3微米） 氣二氨合鈀（以鈀金屬換算）ίο克/升In the first figure, the first electrolytic degreasing treatment (E_Trex 12: ELECTROPLATING ENGINEERS OF JAPAN Co., Ltd., liquid temperature is 60 degrees Celsius, applied voltage is 6 volts, and the immersion time is 3 sec.) To remove pre-treatment of contaminants or oxides on the surface of the lead frame. The prepared evaluation sample was prepared by forming a palladium plating coating film by adding lanthanum in an amount of 10, 100, and 500 mg/liter in the plating solution, respectively. There are three kinds in total (Example 1 shown in Table 1). Example 3) Table 1 Addition amount Example 1 10 mg/liter Example 2 100 mg/liter Example 3 500 mg/liter Further, an evaluation sample (conventional example) was prepared using a conventional palladium plating solution. This 2169-8661-PF; Ahddub 11 1351740 % know that except for the improvement of the electric clock processing shown below, the remaining nickel electro-recording processing, gold electric clock processing conditions and procedures are all the same as the evaluation examples of the above examples. Palladium plating treatment (target film thickness is 〇〇3 μm) gas diammine palladium (calculated as palladium metal) ίο克/liter
氨水 氣化録 酸鹼值（pH) 液溫 電流密度 20毫升/升 100克/升 8. 5 攝氏55度 0.75安培/平方公尺 甚使用含鎊（Te)之鈀電鍍液作成評估樣品（比較例） 以進行比較。此比較例除改進行以下所示之纪電鑛處理 外，其餘錄電鑛處理、金電鑛處理條件及流程全部與上述 實施例之評姑樣品相同。還有，在此比較例把電鐘披覆膜 中，披覆膜中錡共析量為29ppm。Ammonia gasification recording pH value Liquid temperature Current density 20 ml / liter 100 g / liter 8. 5 ° C 55 ° 0.75 amp / m ^ 2 even using Pp (Te) palladium plating solution for evaluation samples (comparison Example) for comparison. This comparative example is the same as the jujube sample of the above-mentioned embodiment except that the following electric power treatment is performed. Further, in the comparative example, in the electric bell coating film, the amount of ruthenium co-deposition in the coating film was 29 ppm.
比較例=飽電鍍處理（目標膜厚為0.03微米 二氣二氨合鈀（以鈀金屬換算）4克〆升 氨水 氣化铵 鎊 酸鹼值（pH) 20毫升/升 100克/升 5〇毫克/升 8. 5 液溫 電流密度 以上述各評估樣品 攝氏55度 0.75安培/平方公尺 進订焊料潤濕性評估測試。此焊料 2169-8661-PF;Ahddub 满濕性評估測試係 ^ ^ 自坪估樣品浸潰於焊料$ # 知枓冷之承受力為0( 卄冷起，至該 稱之為對焊料潤濕性 此、，·=果時間 ’’’、f ”子估的測試（所謂之盞 測試）。具體條件如下所示。 …、a時間（ZCT) 焊料潤濕性評估測試條件 .助熔劑：松脂助熔劑 .焊料浴：百分之63的錫—百分之 氏230度±攝氏5度 液皿為攝 .樣品的浸潰速度：2毫米/秒 •樣品的浸潰深度：2毫米 •樣品的浸潰個數：1個 接著，在上述焊料潤濕性評估十，各評估樣品係分別 於加熱溫度為攝氏380度±攝氏5度中保持1分鐘、加熱溫 度為攝氏400度土攝氏5度中保持3〇㈣情形下進行測 試。還有，各評估樣品係於同一條件下進行3次測量，結 果如表2(加熱溫度為攝氏38〇度±攝氏5度之情形）及表 3(加熱溫度為攝氏400度土攝氏5度之情形）所示。 表2 無交錯時間（秒） 最小值 最大值 平均值 實施例1 0.46 0.53 0. 49 實施例2 0.49 0.54 0.50 實施例3 0.41 0.51 0.46 習知例 2.09 4. 03 3.06 比較例 1.43 1.46 1.44 (加熱條件為攝氏380度±攝氏5度中保持1分鐘) 表3 2169-8661-PF;Ahddub 13 1351740 無交錯時間（秒） __ 最小值 最大值 平均值 實施例1 0.31 0.40 實施例2 0.45 0.47 0.16~ 實施例3 0.35 Γ 0.46 '0.38 習知例 3.72 5. 00 4. 36 比較例 1.41 1.54 1.47 於表2及表3中’係分別表示各評估樣品於3次測量 結果中之最大時間、最小時間及平均時間。依據表2及表 籲3進行判斷’實施例！η各評估樣品不論加熱溫度為攝 氏380度還是攝氏400度，無交錯時間都很短，且每次测 量變動較少，而可判定為穩定焊料潤濕性。亦即，即使施 加高溫度熱經歷，焊料的潤濕性可以判定為極良好。另一 方面，於習知例中，不僅無交錯時間長，且每次測量變動 較大。更甚之，於比較例中’亦認定施加高溫熱經歷後， 有無交錯時間變長的傾向。 接著，於上述焊料潤濕性評估測試中，進行更高溫的 攝氏430度±攝氏5度中保持30秒的加熱處理，再對評估 樣品進行調查之結果進行說明。在此所使用之評估樣品係 使用實施你"、習知例、比較例等3個。除加熱條件外， 皆與上述各條件相同。結果如表4所示。 表4 無交錯時間（秒） 最小值 最大值 平均值 0.63 5.00 實施例2 0.62 0.67 習知例 5.00 5.00 比較例 5.00 5. 00 5.00 (加熱條件為攝氏430度±攝氏5度中保持30秒) 2169-8661-PF; Ahddub 14 1351740 如表4所示，習知例、比 全部在5秒以上，而得焊料m 樣口口之無父錯時間 侍綷科潤濕性非常差的结 面，實施例2之無交錯時間則平均為〇㈦ 另一方 斷出即使在攝氏430度的加執處/以明顯判 料潤濕性。由上述表2至表4之姓果^ 之，，Ό果可知，本實施例使用 鈀電鍍彼覆膜的引線框，可以在 肛不又间溫度熱經歷之情形 下’接合部係為穩定的，拙社里·^、， 此尨果可以明顯判斷出具有非常 好的焊料潤濕性。 如此在使用習知焊料中融點高且溶融時回流溫度也高 的自由料㈣’本實_接合料會發生剝離現象或接 D不良等問題。此外’具有本實施例鈀電鍍披覆膜的引線 框，因飽電㈣覆膜可以薄膜化，故可以降低成本。 最後，對實施例2把電鍵披覆膜而言，對此電銀披覆 膜組成進行調查的結果，可明確判斷出有4剛卿的錯共 析於母相的紐中。還有，分析方法係利用⑽（感應結合電 漿）分析，以測量得到既定量鈀披覆臈令所含的鈀量。 【圖式簡單說明】 第1圖係繪示焊料潤濕性評估用樣品的製造流程圖。 主要元件符號說明 無0 15 2169'8661~PP;AhddubComparative Example = saturating plating treatment (target film thickness is 0.03 μm di-p-diammine palladium (calculated in palladium metal) 4 g liters ammonia water vaporized ammonium pound pH value (pH) 20 ml / liter 100 g / liter 5 〇 Mg/L 8.5 Liquid Temperature and Current Density The solder wettability evaluation test was performed at 55 ° C 0.75 amps / m ^ 2 of the above evaluation samples. This solder 2169-8661-PF; Ahddub full humidity evaluation test system ^ ^ The test is immersed in the solder. # # 枓 枓 之 之 之 之 之 ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( (The so-called 盏 test). The specific conditions are as follows. ..., a time (ZCT) solder wettability evaluation test conditions. Flux: rosin flux. solder bath: 63% tin - 120% Degree ± 5 ° C. For the sample. Immersion speed of the sample: 2 mm / sec • Dip depth of the sample: 2 mm • Number of impregnations of the sample: 1 Next, in the above solder wettability evaluation ten, Each evaluation sample was kept at a heating temperature of 380 ° C ± 5 ° C for 1 minute, and the heating temperature was taken. The test was carried out under the condition that the temperature was maintained at 3 〇 (4) at 400 ° C. In addition, each of the evaluation samples was subjected to three measurements under the same conditions, and the results are shown in Table 2 (the heating temperature was 38 ° C ± 5 ° C) And Table 3 (the heating temperature is 400 degrees Celsius and 5 degrees Celsius). Table 2 No interleaving time (seconds) Minimum value Maximum value Average Example 1 0.46 0.53 0. 49 Example 2 0.49 0.54 0.50 Implementation Example 3 0.41 0.51 0.46 Conventional Example 2.09 4. 03 3.06 Comparative Example 1.43 1.46 1.44 (heating condition is 380 degrees Celsius ± 5 degrees Celsius for 1 minute) Table 3 2169-8661-PF; Ahddub 13 1351740 No interleaving time (seconds) __ Minimum value maximum value Example 1 0.31 0.40 Example 2 0.45 0.47 0.16~ Example 3 0.35 Γ 0.46 '0.38 Conventional Example 3.72 5. 00 4. 36 Comparative Example 1.41 1.54 1.47 In Tables 2 and 3 'The maximum time, the minimum time, and the average time of each of the three evaluation results of each evaluation sample are respectively determined. According to Table 2 and Table 3, the judgment is made. 'Examples! η Each evaluation sample is heated at 380 degrees Celsius or 400 degrees Celsius. Degree, no interlacing The time is very short, and each measurement changes less, and it can be determined that the solder wettability is stabilized. That is, even if a high temperature thermal experience is applied, the wettability of the solder can be judged to be extremely good. In the example, not only is there no long interleaving time, but each measurement changes greatly. Furthermore, in the comparative example, it was also confirmed that there was a tendency for the interleaving time to become longer after the application of the high-temperature heat experience. Next, in the solder wettability evaluation test described above, heat treatment was carried out for 30 seconds at a higher temperature of 430 ° C ± 5 ° C, and the results of the evaluation of the sample were examined. The evaluation samples used here are implemented using three of you, the conventional examples, and the comparative examples. Except for the heating conditions, they are all the same as the above conditions. The results are shown in Table 4. Table 4 No interleaving time (seconds) Minimum value Maximum value average 0.63 5.00 Example 2 0.62 0.67 Conventional example 5.00 5.00 Comparative example 5.00 5. 00 5.00 (heating condition is 430 degrees Celsius + 5 degrees Celsius for 30 seconds) 2169 -8661-PF; Ahddub 14 1351740 As shown in Table 4, the conventional example and the ratio are all in the range of 5 seconds or more, and the joint of the solder m-like mouth has a very poor wettability. The non-interlacing time of Example 2 is 〇 (7) on the other side, and the other party breaks out even at 430 degrees Celsius / with obvious judgment of wettability. From the results of the above-mentioned Table 2 to Table 4, it can be seen that, in this embodiment, the lead frame of the film is coated with palladium, and the joint portion can be stabilized in the case of temperature and heat in the anus. , 拙社里^,, this result can be clearly judged to have very good solder wettability. Thus, in the case of using a conventional solder, the free material (4) which has a high melting point and a high reflow temperature at the time of melting may cause problems such as peeling or poor connection. Further, the lead frame having the palladium plating film of the present embodiment can be thinned by the charged (four) film, so that the cost can be reduced. Finally, in the case of the electric button coating film of Example 2, the result of investigation of the composition of the electro-silver coating film clearly confirmed that 4 Gangqing's mis-analysis was in the mother phase. Further, the analysis method uses (10) (inductively coupled plasma) analysis to measure the amount of palladium contained in the quantitative palladium coating. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the manufacture of a sample for evaluating solder wettability. Main component symbol description No 0 15 2169'8661~PP; Ahddub
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| US4182781A (en) * | 1977-09-21 | 1980-01-08 | Texas Instruments Incorporated | Low cost method for forming elevated metal bumps on integrated circuit bodies employing an aluminum/palladium metallization base for electroless plating |
| JPS6033382A (en) * | 1983-08-03 | 1985-02-20 | Nippon Pureeteingu Kk | Electrodeposition of amorphous alloy by pulse electrolysis |
| JPS6137960A (en) * | 1984-07-28 | 1986-02-22 | Tadanobu Okubo | Metal surface processing method |
| JPS6178590A (en) * | 1984-09-25 | 1986-04-22 | Kyocera Corp | Silver solder material |
| JPS6178591A (en) * | 1984-09-25 | 1986-04-22 | Kyocera Corp | Silver solder material |
| JPS6178592A (en) * | 1984-09-25 | 1986-04-22 | Kyocera Corp | Silver solder material |
| EP0250146A1 (en) * | 1986-06-16 | 1987-12-23 | Texas Instruments Incorporated | Palladium plated lead frame for integrated circuit |
| US5225711A (en) * | 1988-12-23 | 1993-07-06 | International Business Machines Corporation | Palladium enhanced soldering and bonding of semiconductor device contacts |
| EP0537982A2 (en) * | 1991-10-14 | 1993-04-21 | Fujitsu Limited | Semiconductor device having improved leads |
| JP3560250B2 (en) * | 1993-02-02 | 2004-09-02 | 新光電気工業株式会社 | Lead frame for semiconductor device |
| US5455118A (en) | 1994-02-01 | 1995-10-03 | Pcc Composites, Inc. | Plating for metal matrix composites |
| JPH07263493A (en) * | 1994-03-18 | 1995-10-13 | World Metal:Kk | Chip mounting method |
| JP3345529B2 (en) * | 1995-06-20 | 2002-11-18 | 日立化成工業株式会社 | Wire bonding terminal, method of manufacturing the same, and method of manufacturing semiconductor mounting substrate using the wire bonding terminal |
| DE19631565A1 (en) * | 1996-07-24 | 1998-01-29 | Atotech Deutschland Gmbh | Uniform adherent palladium contact bump production |
| JP3226213B2 (en) * | 1996-10-17 | 2001-11-05 | 松下電器産業株式会社 | Solder material and electronic component using the same |
| SG74657A1 (en) * | 1998-09-15 | 2000-08-22 | Texas Instr Singapore Pte Ltd | Multichip semiconductor assembly |
| US6545344B2 (en) * | 2000-06-27 | 2003-04-08 | Texas Instruments Incorporated | Semiconductor leadframes plated with lead-free solder and minimum palladium |
| US6506314B1 (en) | 2000-07-27 | 2003-01-14 | Atotech Deutschland Gmbh | Adhesion of polymeric materials to metal surfaces |
| US6706561B2 (en) * | 2002-02-11 | 2004-03-16 | Texas Instruments Incorporated | Method for fabricating preplated nickel/palladium and tin leadframes |
| JP4689218B2 (en) * | 2003-09-12 | 2011-05-25 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| JP4719424B2 (en) * | 2004-03-15 | 2011-07-06 | ルネサスエレクトロニクス株式会社 | pad |
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