TWI337384B - Semiconductor fabrication process with asymmetrical conductive spacers - Google Patents

Semiconductor fabrication process with asymmetrical conductive spacers Download PDF

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Publication number
TWI337384B
TWI337384B TW093112324A TW93112324A TWI337384B TW I337384 B TWI337384 B TW I337384B TW 093112324 A TW093112324 A TW 093112324A TW 93112324 A TW93112324 A TW 93112324A TW I337384 B TWI337384 B TW I337384B
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Taiwan
Prior art keywords
diffusion
spacer
gate
substrate
implant
Prior art date
Application number
TW093112324A
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English (en)
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TW200504892A (en
Inventor
Leo Mathew
Muralidhar Ramachandran
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Freescale Semiconductor Inc
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Publication of TW200504892A publication Critical patent/TW200504892A/zh
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Publication of TWI337384B publication Critical patent/TWI337384B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

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1337384 九、發明說明： 本申請案已於2003年4月30曰在美國提出申請其專利申 請案號碼為10/427,141。 【發明所屬之技術領域】 本發明大體上係關於半導體製造領域，且更特定言之， 本發明係關於一種用於形成具有低泄漏及可接受之臨限電 壓的小電晶體之方法。 【先前技術】 在半導體f件領❺中，冑晶體必須同時顯現出高效能及 低功率特徵。通常此等兩個參數互相具有競爭性。當電晶 體通道長度減少（例如）以改良器件速度時，諸如亞臨限泄漏 及臨限電壓之其他參數會變得更加難以控制。習知地，採 用已摻雜之電晶體通道來將臨限電壓控制於所要的範圍 内。常常使用離子植入來達成此等已摻雜之通道。 近來，已使用了絕緣物上矽（S〇〖）技術來達成更低的功率 消耗。此外’正藉由每項新穎的方法技術來使閘極長度按 比例減少。藉由習知通道植入物一貫地難以達成s〇I及深亞 微米器件所需之淺通道。然而，沒有此等已摻雜之通道， 將難以製造能顯現足夠低的泄漏電流、充分的臨限電壓及 可接受之低臨限電壓變化之深亞微米器件。因此，吾人所 要的是建構一種方法及具有短通道長度、充分的臨限電壓 及低亞臨限泄漏之所得電晶體，而不會顯著增加成本或方 法的複雜性。 【發明内容】 93032.doc 1337384 電性間隙物連同習知之閘極結構形成了具有三個部分的電 晶體閘極。可單獨控制每個三閘極結構之極性，使得電晶 體可具有（例如）兩個呈—種極性的結構及—個呈另一種極 性的結構。以此方式來提供非對稱摻雜擴散物之能力有利 地改良了控制非常短的通道電晶體之臨限電壓、亞臨限泄 漏及通道長度之能力。 現參看圖1，閘極介電薄膜104形成於半導體晶圓1〇〇之半 導體基板102上。在一實施例中，閘極介電丨〇4係半導體基 板102之上表_面經熱氧化所形成之二氧化矽薄膜。基板1〇2 之熱氧化藉由將晶圓曝露於如為半導體製造方法領域中之 人員所熟知之超過90(TC的氧化環境（如〇2，Η2”下來達 成。在此實施例中’閘極介電1〇4之厚度為15至15〇埃中之 任一大小。在其他實施例中，閘極介電1〇4為介電常數大於 4,0之一"高K"介電。在閘極介電薄膜中適合使用高κ介電以 達成足夠電容及一更厚之薄膜。適合用於介電1〇4之高尺實 施例的材料包括諸如铪氧化物之各種金屬氧化化合物及其 它材料，諸如鋁氧化物、铪矽酸鹽、锆矽酸鹽、姶鋁酸鹽、 鋼I呂酸鹽、結結酸鹽及鋼氧化物》關於高κ介電之額外資訊 可於（例如）Samavedam 之·'Transistor having a high K dielectric and short gate length and method therefor’’的美國 專利第6,514,808號中找到。 半導體基板102之上部分通常包括諸如石夕之單晶體半導 體材料，閘極介電104形成於該材料上。在特別適於與諸如 行動器件及無線器件之低功率消耗應用一起使用之一實施 93032.doc 1337384 例中，半導體基板l〇2為一絕緣物上矽（s〇I)基板，其中單 體夕為开> 成於埋入氧化物上且厚度大約在1 〇〇〇至 2〇,000埃的範圍内之相對薄的薄膜（意即低於1 〇,〇〇〇埃）。 現參看圖2，閘極薄膜106形成於閘極介電1〇4上。在一實 施例中，閘極薄膜106為一層多晶矽薄臈，該薄膜藉由在溫 度保持於約550-650t範圍内之反應器腔室内來對矽烷進 行熱分解而形成◊可能將該多晶矽薄膜沈積為未摻雜矽， 且隨後使用離子植入方法使其摻雜n型（如磷，砷）或口型（如 爛）之摻雜劑。在其他實施例中，可就地來摻雜多晶矽或藉 由擴散來摻#該多晶石夕。在其他實施例中，除了多晶石夕之 外’閘極薄膜可包括一種材料或化合物或以該材料或化合 物來代替該多晶矽’其中該材料或化合物包括鍺、鈕、氮 化石夕、氮化鈦、氮化鉬或其組合物。 現參看圖3，對閘極薄膜ι〇6進行圖案化以形成一具有大 體上垂直之側邊112的閘極116。使用該領域中所熟知之光 微影處理技術及各向異性或乾式蝕刻技術來達成閘極u 6 之圖案化。光微影處理可包括使用抗反射層（ARC)及光阻圖 案化技術。 現參看圖4,擴散介電薄膜12〇形成於閘極116上。在一實 施例中，介電薄膜12〇為一介電常數低於約4.0之低K介電。 在其他實施例中，介電薄膜12〇包括化學氣相沈積（CVD)氮 化矽之薄膜。在此實施例中，CVD氮化矽可藉由在一溫度 保持於300-800。(：範圍内之反應器内來使二氣甲矽烷或矽 烧與氨反應而形成。可在沈積氮化矽之前將CVD氮化矽襯 塾層沈積於閘極116上以減輕當氮化矽接觸矽時所產生的 93032.doc 1337384 應力。以一大體上共形之方式來沈積CVD介電薄膜⑽使 得該構形之垂直部分巾的薄膜厚度A約在該構形之水平部 分中的薄膜厚度之至少80〇/〇内。 介電薄膜120可以各向異性之方式蝕刻或在進行沈積時 而留下。若對介電薄膜120進行蝕刻，則鄰近於閘極116之 侧壁的薄膜部分仍提供閘極116與隨後沈積之導電性擴散 結構之間的隔離。吾人亦期望將介電薄膜留在基板1〇2之未 被閘極116所覆蓋的部分上，以將導電性擴散結構與基板 102隔離。若—對薄膜120進行蝕刻，則可藉由該等在蝕刻薄 膜120之後所留下之閘極介電1〇4的部分來提供與基板間的 隔離。此外，若薄膜120包括位於矽氧化物襯墊層上之氮化 石夕，則薄膜12 0之姓刻較佳地移除氮化石夕而留下石夕氧化物。 可在形成介電薄膜120之後來執行一個或多個植入步 驟。在一實施例中’執行一個或多個擴散植入步驟，以將 源極/汲極擴散區118引入彼等基板1〇2之未被閘極116所覆 蓋的部分。將源極/汲極擴散區稱作輕微摻雜的汲極（ldd) 區118以避免與前面所提及並將在下文中對其作進一步描 述的導電性擴散相混淆。LDD植入區118適合用來控制所得 器件之臨限電壓及有效通道長度。然而，在基板1〇2之一 s〇I 實施例中，高劑量離子植入係非吾人所要的，因為難以在 極淺的石夕基板内來充分地保持劑量。為處理此問題，可在 該方法之特定實施例中徹底消除LDD植入物，在該等情況 下’臨限電壓的控制藉由改變該等擴散中之一擴散的植入 極性來達成（如下文中之更詳細描述）。 93032.doc -10- 1337384 現參看圖5，導電性·擴散間隙物薄膜124沈積於介電薄膜 12〇上。在一實施例中，擴散間隙物薄膜124為一CVD多晶 矽，其形成方式與閘極薄膜1〇6之多晶矽實施例大致相同 (參見圖2之描述”在此實施例中，將多晶矽沈積為未摻雜 薄膜，使得可隨後按需要來對薄膜之各部分進行摻雜。在 其他實施例中，擴散間隙物薄膜124為一諸如矽鍺或基於鈕 或鈦之金屬的替代導電性薄膜。 現參看圖6及圖7，執行了第一植入丨32及第二植入14〇。 以一通常在6—。至60。之間的第一植入角來執行第一植入132 以將第一摻雜物引入導電性擴散物薄膜124。在第一植入 132期間所使用之植入角會導致植入物種主要存在於導電 性擴散物124之被植入角曝露的一部分136。藉由使用一適 當植入角並將電晶體適當地定向於晶圓1〇〇上（例如相對於 晶圓平面）’第一植入132在導電性擴散薄膜124之第一部分 136中產生第一摻雜分佈，其中擴散薄膜124之第一部分us 代表閘極116第一側壁112上之薄膜124的部分。 同樣地，藉由使用第二植入角，第二植入14〇將第二摻雜 分佈主要引入擴散薄膜124之第二部分142。第二植入角可 能為第一植入132期間所使用之第一植入角之反相角。例 如，若第一植入132之角為1〇。，則第二植入14〇之角可能為 -ΗΓ。在一適合用於控制電晶體之臨限電壓及亞臨限泄漏 之實施例中，第一植入丨32及第二植入14〇期間所使用之植 入物種的極性相反。因此，第一植入132可使用諸如硼之p 型物種而第二植入140則使用諸如磷或砷之n型物種。例 93032.doc • 11 - 如’在一適合用於製造n通道電晶體之特殊實施例中，導電 性閘極116及擴散薄膜124之第二部分142為η型摻雜，而擴 散薄膜124之第一部分136則為ρ型摻雜。在此實施例中，當 將位於薄膜124之第一部分136下面的區域用作器件汲極區 時，較其中使整個閘極結構摻雜有一致極性的對應電晶 體’該所得電晶體將具有改良之（提高之）Vt及更低之亞臨限 泄漏。 第一植入132及第二植入140之植入劑量應足以分別達成 擴散薄膜124之高度摻雜的第一部分136及第二部分丨42。在 其中第一植入132為p型植入且第二植入140為η型植入的實 如例中’吾人所期望之用於植入的劑量為超過約 i〇ns/cm2。吾人期望植入能量足以達成擴散薄膜124中心附 近的峰值劑量❶用於P型（硼）植入之代表性摻雜能量的範圍 為約10至100 keV，而用於η型（磷）植入之代表性摻雜能量的 範圍為約30至100 keV。在其他實施例中，可使用諸如電毀 植入及阻塞層之額外或替代植入技術（以精確地調節現有 植入）〇 現轉向圖8，已對圖7之導電性擴散薄膜124進行了各向異 性姓刻以分別產生第一導電性擴散間隙物結構146及第二 導電性擴散間隙物結構150 »如圖8中所示，藉由介電i2〇 及104將導電性擴散間隙物146及150與閘極116及基板1〇2 進行電隔離。在一實施例中，擴散間隙物146及150之側向 厚度約為閘極116之側向尺寸（L)的1 /4至1 /2。例如，若閘極 116之L約為1〇〇 nm，則擴散間隙物146及150之單獨側向厚 93032.doc •12- 1337384 度或相加之側向厚度約在25至5〇11111的範圍内。在其他實施 例令，擴散間隙物146及1 50之側向尺寸可在此範圍之外。 現參看圖9及圖1〇，對介電層間隙物薄膜158進行沈積及 蝕刻以在擴散間隙物146及150之外側壁上形成介電間隙物 162。間隙物薄膜158可為CVD矽氧化物、氮化矽或二者之 組合物。間隙物結構162有利於防止所得電晶體之源極/汲 極區與閘極之間形成短路。更具體言之，本方法之一實施 例採用一石夕化物序列以將擴散間隙物146及15〇短路至閘極 116。在此實—施例中，間隙物結構162防止矽化物將源極/汲 極區短路至擴散物。 現參看圖11，將閘極116、擴散間隙物146與15〇及介電層 間隙物162用作摻雜遮罩來執行源極/汲極植入154以將源 極/汲極雜質分佈（區域）156引入基板1〇2，使得源極/汲極區 1 56自動對位於間隙物} 62且’由於間隙物1 62較佳地應相對 /專且均，所以可使源極及極區15 6有效地自動對位於擴 散間隙物146及150。在另一實施例中，在形成介電間隙物 1 62之前來執行植入154，使得源極/汲極區156能直接自動 對位於擴散間隙物146及150。在任一實施例中，使源極/汲 極區156對位於擴散間隙物146及150。在η通道電晶體之實 施例中’源極/没極植入使用諸如填或石申之η型物種，而在ρ 通道電晶體之實施例中，源極/没極植入丨54則使用硼或另 一 P型摻雜物。雜質分佈156較佳地超過約1〇i9 at〇ms/cm3。 現參看圖1 2及圖1 3 ’使用石夕化物的方法，將擴散間隙物 146及150電連接至閘極116。在圖12中，將諸如鈷之金屬166 93032.doc •13- 1337384 均一地沈積於晶圓100.上。在此沈積步驟之前，清除源極/ 沒極區1 56上之介電（包括介電薄膜120)及閘極116上表面之 任何殘留介電以曝露基板102内之已摻雜的半導體及問極 116之多晶石夕或其他材料。為達到將包括二氧化石夕在内的介 電清除掉的程度’可採用高頻（HF)浸漬或其他合適之濕化 方法’而氮化矽及其它介電則可需要使用習知之乾式姓刻 處理步驟。 在將金屬166沈積之後，將晶圓1〇〇及金屬166曝露於加熱 環境170下以_在金屬166與矽（或其他半導體）相接觸之任一 地方形成石夕化物。與諸如間隙物16 2之介電相接觸的金屬 166之部分在熱步驟之後仍處於未反應狀態，藉此能選擇性 地移除該等未反應部分，如圖1 3所示《此矽化物方法產生 了能將第一擴散間隙物146及第二擴散間隙物1 50電連接至 閘極116的電橋174 »除了或代替鈷之外，金屬166可包括諸 如鎳、鈦、氮化鈦及其組合物之材料。 如圖13所示之所得電晶體11 〇包括一個三部分偏壓結 構’其包括閘極116、第一導電性擴散間隙物146及第二導 電性擴散間隙物150，其中任一部分皆位於下面的基板1 〇2 上並藉由一***介電而與該基板】〇2隔離。介電！ 2〇***於 擴散間隙物146及15 0與閘極116的側壁之間。基板内之源極 /没極區156存在於一由擴散間隙物146及150所界定之通道 區域111的任一側上。施加至擴散間隙物146與1 50以及閘極 116的電壓能調變該通道區域1丨丨之傳導性。 在較佳實施例中，偏壓結構之組件的極性或摻雜類型可 93032.doc • 14· 1337384 獨立地變化。因此，該等偏壓結構之三組件中的每一組件 皆可為η型、p型或本征型。由於工作函數差異與不同的導 電性類型相關聯，因此施加至閘極結構之三部分中的每一 部分之共同電壓對下面的通道ln可具有不同的調變效應。 在一實施例中’將第一擴散間隙物146下面之區域156用 作電晶體汲極。在此實施例中，將第一擴散間隙物146摻雜 成Ρ型而將閘極116及第二擴散間隙物15〇皆摻雜成η型。此 、’且有利於在沒極附近產生一能帶隙峰值，其能有效地提 南電晶體之亭限電壓並減少包括亞臨限泄漏及Dibl(沒極 誘發障壁泄漏）在内的短通道效應。 現參看圖14 ’其描述了一用於接觸並偏壓擴散間隙物丨4(5 及1 50之替代方法。與使用矽化物方法將擴散間隙物146及 150橋接至閘極U6(如上文關於圖12及圖13之描述）不同的 是’分別使用接觸件1 80及184以分別將擴散間隙物146及 150連接至基板1〇2的p+部分及n+部分。在此實施例中，將 非臨界遮罩及蝕刻序列用來形成能將擴散結構”***，，為兩 個電隔離部分的空隙186。此實施例使得能夠對電晶體之偏 壓結構的組件進行獨立的偏壓，此有利於控制特殊應用中 之臨限電壓。 因此’對受益於本揭示案的熟習此項技術者而言應瞭 解，根據本發明’本文已提供了一種用於製造一能達成上 文所闡述之優點的積體電路的方法。雖然已參考了其特定 說明性實施例來描述並說明瞭本發明，但是並不意欲將本 發明限制於彼等說明性實施例。熟習此項技術者應認識 93032.doc 到，在不脫離本發明之精神 u τ π馆/兄下可作出改變或修正。 因此，意欲將如屬於附加申請 右^ m 月寻利範圍及其均等物内的所 有該4改良及修正包含於本發明内。 【圖式簡單說明】 圖1為一半導體晶圓之 形成 戳甶圖，其中一閘極介電 於半導體基板上； 圖2說明繼圖丨後之處理過程 極介電上； 圖3說明繼—圖2後之處理過程 形成閘極結構； 圖4說明繼圖3後之處理過程 閘極上； 圖5說明繼圖4後之處理過程 介電薄膜上； 圖6說明繼圖5後之處理過程 分被植入第一摻雜劑； 圖7說明繼圖6後之處理過程 分被植入第二#雜劑； 圖8說明繼圖7後之處理過程 以形成導電性擴散物； 圖9說明繼圖8後之處理過程： 散物及閘極上； 其中一閘極薄膜形成於 其中閘極薄膜被圖案化 閘 以 其令一介電形成於基板及 其令一導電性薄膜形成於 其中導電性薄臈之第一 Μ 其中導電性薄膜之第二部 其中導電性薄膜被圖案化 其中一介電薄膜形成於擴 刻以 圖10說明繼圖9後之處理過程，其中該介電薄膜被蝕 形成介電間隙物； 93032.doc • 16 - 囷U說明繼圖10後之處理過程，其中將閉極、擴散物及 介電用作植人遮罩來植人基板之源極/沒極區； 圖U說明繼圖η後之處理過程，其中—金屬薄膜沈積於 晶圓之上； 圖13s尤明繼圖12後之處理過程，其中藉由對矽化物進行 熱處理將閘極與擴散物連接在一起；及 圖14為一種用於將擴散物連接至電晶體其餘部分之替代 方法的俯視圖。 【主要元吃符號說明】 100 半導體晶圓 102 基板 104 閘極介電 106 閘極薄膜 110 電晶體 111 通道區域 112 側壁 116 閘極 118 輕微摻雜的汲極（LDD)區 120 介電薄膜 124 導電性擴散物 132 植入 136 部分 140 植入 142 部分 93032.doc •17- 1337384 146 擴散間隙物 150 擴散間隙物 154 植入 156 區域 158 介電間隙物薄膜 162 介電間隙物 166 金屬 170 周圍環境 174 一電橋 180 接觸件 184 接觸件 186 空隙 93032.doc -18-

Claims (1)

1337384 十、申請專利範圍： 1· 一種用於形成一電晶體之方法，其包括： 在一半導體基板上之一閘極介電上形成一閘極； 形成鄰近於該閘極之各自的第一及第二側壁之導電性 第一及第二擴散間隙物，其中在該等擴散間隙物中之每 個擴散間隙物與其各自之閘極側壁之間具有—介電中 物； a 藉由一第一物種來摻雜該第—擴散間隙物，且藉由一 第二物種來摻雜該第二擴散間隙物，其中該第一‘散間 隙物及該第二擴散間隙物之極性相反；及 、 在該基板中形成對位於該等擴散間隙物的源極/㈣ 區。 2· 如申請專利範圍第!項之方法，纟中摻雜該第一擴散間隙 物包括離子植人-第-摻雜劑’同時保持該基板處於一 在6。至60。範圍内的植入角，且其中摻雜該第二擴散間隙 物包括離子植人-第二摻雜劑’同時保持該基板處於一 在-6°至-60°範圍内的植入角。
3.如申請專利範圍第旧之方法，其中形成該等擴散間隙物 包括在該基板及閘極上沈積一導電性擴散間隙物薄膜並 各向異性地蝕刻該擴散間隙物薄臈。 4·如申請專利範圍第！項之方法，其中形成該問極之進一步 特徵為： 形成一 η型閘極； 形成該第-擴散間隙物之進—步特徵為形成—η型擴 93032.doc 1337384 散間隙物；及 步特徵為形成一 p型擴 形成該第二擴散間隙物之進 散間隙物。 -種位於-積體電路中之電晶體 -位於-基板上之—問極介電上：二：
鄰近於該問極之各自的側壁之第—及第二導電 間隙物’纟中在每個擴散間隙物與其各自之問極側壁之 間具有-擴散介電中間物’纟中該間極、第一擴散間隙 物及第一垮散間隙物中之至少一個具有一第一導電類型 且至少一個具有一第二導電類型；及 位於該基板中對位於該等擴散間隙物的源極/沒極雜質 區域，其用於界定-位於該閘極、該[擴散間隙物及 該第二擴散間隙物下方之通道區域。 6.
如申請專利範圍第5項之電晶體’其中該第一擴散間隙物 及該閘極具有一第一導電類型，且該第二電極具有一不 同於該第一導電類型之第二導電類型。 7·如申請專利範圍第5項之電晶體，其中該第一擴散間隙物 電接觸該基板之一n+部分，且該第二擴散間隙物接觸該 基板之一 p+部分’藉此能夠獨立地來偏壓該第一擴散間 隙物及該第二擴散間隙物。 8. —種半導體之製造方法，其包括： 形成鄰近於一半導體基板上所形成之一閘極之各自的 側壁之第一及第二導電性擴散間隙物，該閘極具有一第 一導電類型； 93032.doc •2· 來推·雜該第一導電性間 一雜質來摻雜該第二導 第一擴散間隙物及該第 專源極/汲極區界定了其 施加至該閘極、該第— 之電壓來調變該通道區 藉由該第一導電類型之一雜質 隙物，且藉由一第二導電類型之 電性間隙物； 在該基板中形成側向對位於該 二擴散間隙物之源極/汲極區，該 之間的一通道區域，其中藉由— 擴散間隙物或該第二擴散間隙物 域〇 9. 如申請專啊範圍第8項之方法 电其中摻雜該第一擴散間隙 物包括藉由一使用一第一植 植入角所執行之第一植入來植 入一擴散間隙物薄膜，且其中捻 — 兵中播雜該第二擴散間隙物包 括藉由一使用一第二植入自 > 植入角所執仃之第二植入來植入該 擴散間隙物薄膜。 10. 如申請專利範圍第8項之方法，其進—步包括藉由一導電 性石夕化物來橋接該第—擴散間隙物、該閘極及該第二擴 散間隙物。 93032.doc
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